US20110002084A1 - Chip-type electric double layer capacitor and method of manufacturing the same - Google Patents

Chip-type electric double layer capacitor and method of manufacturing the same Download PDF

Info

Publication number
US20110002084A1
US20110002084A1 US12/654,751 US65475109A US2011002084A1 US 20110002084 A1 US20110002084 A1 US 20110002084A1 US 65475109 A US65475109 A US 65475109A US 2011002084 A1 US2011002084 A1 US 2011002084A1
Authority
US
United States
Prior art keywords
double layer
electric double
layer capacitor
case
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/654,751
Inventor
Sang Kyun Lee
Chang Ryul JUNG
Sung Ho Lee
Dong Sup Park
Yeong Su Cho
Hyun Chul Jung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electro Mechanics Co Ltd
Original Assignee
Samsung Electro Mechanics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to KR10-2009-0061333 priority Critical
Priority to KR20090061333 priority
Priority to KR10-2009-0086085 priority
Priority to KR1020090086085A priority patent/KR101133374B1/en
Priority to KR10-2009-0086487 priority
Priority to KR10-2009-0086624 priority
Priority to KR1020090086487A priority patent/KR101067177B1/en
Priority to KR1020090086624A priority patent/KR101070084B1/en
Application filed by Samsung Electro Mechanics Co Ltd filed Critical Samsung Electro Mechanics Co Ltd
Assigned to SAMSUNG ELECTRO-MECHANICS CO., LTD. reassignment SAMSUNG ELECTRO-MECHANICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHO, YEONG SU, JUNG, HYUN CHUL, PARK, DONG SUP, JUNG, CHANG RYUL, LEE, SANG KYUN, LEE, SUNG HO
Publication of US20110002084A1 publication Critical patent/US20110002084A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G9/00Electrolytic capacitors, rectifiers, detectors, switching devices, light-sensitive or temperature-sensitive devices; Processes of their manufacture
    • H01G9/155Double-layer capacitors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G11/00Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors [EDLCs]; Processes specially adapted for the manufacture thereof or of parts thereof
    • H01G11/74Terminals, e.g. extensions of current collectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G11/00Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors [EDLCs]; Processes specially adapted for the manufacture thereof or of parts thereof
    • H01G11/78Cases; Housings; Encapsulations; Mountings
    • H01G11/80Gaskets; Sealings
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G11/00Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors [EDLCs]; Processes specially adapted for the manufacture thereof or of parts thereof
    • H01G11/78Cases; Housings; Encapsulations; Mountings
    • H01G11/82Fixing or assembling a capacitive element in a housing, e.g. mounting electrodes, current collectors or terminals in containers or encapsulations
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G11/00Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors [EDLCs]; Processes specially adapted for the manufacture thereof or of parts thereof
    • H01G11/84Processes for the manufacture of hybrid or EDL capacitors, or components thereof
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G9/00Electrolytic capacitors, rectifiers, detectors, switching devices, light-sensitive or temperature-sensitive devices; Processes of their manufacture
    • H01G9/004Details
    • H01G9/008Terminals
    • H01G9/016Terminals specially adapted for double-layer capacitors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G9/00Electrolytic capacitors, rectifiers, detectors, switching devices, light-sensitive or temperature-sensitive devices; Processes of their manufacture
    • H01G9/004Details
    • H01G9/08Housing; Encapsulation
    • H01G9/10Sealing, e.g. of lead-in wires
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/13Energy storage using capacitors
    • Y02T10/7022

Abstract

A chip-type electric double layer capacitor includes: an exterior case including a housing space formed therein and formed of insulation resin; a first external terminal buried in the exterior case and including a first surface exposed to the housing space and a second surface exposed to the outside of the exterior case; a second external terminal buried in the exterior case and including a first surface exposed to the housing space and a second surface exposed to the outside of the exterior case; and an electric double layer cell disposed in the housing space so as to be electrically connected to the first surfaces of the first and second external terminals.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application claims the priority of Korean Patent Application Nos. 10-2009-0086624 filed on Sep. 14, 2009, 10-2009-0061333 filed on Jul. 6, 2009, 10-2009-0086487 filed on Sep. 14, 2009, and 10-2009-0086085 filed on Sep. 11, 2009, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a chip-type electric double layer capacitor and a method of manufacturing the same, and more particularly, to a chip-type electric double layer capacitor which may be reduced in size and weight and a method of manufacturing the same.
  • 2. Description of the Related Art
  • In various electronic products such as information communication devices, a stable energy supply is considered to be an important element. In general, such a function is performed by a capacitor. That is, the capacitor serves to store electricity in a circuit provided in various electronic products such as information communication devices and then discharge the electricity, thereby stabilizing the flow of electricity with the circuit. A general capacitor has a short charge and discharge time, a long lifespan, and high output density. However, since the general capacitor has low energy density, there is a limitation in using the capacitor as a storage device.
  • To overcome such a limitation, a new category of capacitors such as electric double layer capacitors have recently been developed, which have a short charge and discharge time and high output density. A great deal of attention is being paid to such capacitors as next generation energy devices together with secondary cells.
  • The electric double layer capacitor is an energy storage device using a pair of charge layers (electrode layers) having a different polarity. The electric double layer capacitor may perform continuous electrical charge and discharge cycles and has higher energy efficiency and output and greater durability and stability than other, more general capacitors. Accordingly, the electric double layer capacitor which may be charged and discharged with high current is being recognized as a storage device which may be charged and discharged at a high frequency, such as an auxiliary power supply for mobile phones, an auxiliary power supply for electric vehicles, and an auxiliary power supply for solar cells.
  • A basic structure of the electric double layer capacitor includes an electrode, an electrolyte, a current collector, and a separator. The electrode has a relatively large surface area such as a porous electrode. The operational principle of the electric double layer capacitor is an electro-chemical mechanism in which electricity is generated when a voltage of several volts is applied to both ends of a unit cell electrode such that ions in the electrolyte move along an electric field to be adsorbed by an electrode surface.
  • In general, to surface mount such an electric double layer capacitor on a circuit board, a bracket is welded over and under the electric double layer capacitor, and the electric double layer capacitor is then mounted on the circuit board through the bracket.
  • However, the electric double layer capacitor having such a structure has a relatively large thickness. Due to the additional structures required for surface mounting, such as the brackets and so on, the thickness further increases. When such an electric double layer capacitor is used, there may be difficulties in manufacturing high-capacity products because of the increase in thickness. Furthermore, since an additional manufacturing process must be performed, the price of products inevitably increases.
  • SUMMARY OF THE INVENTION
  • An aspect of the present invention provides a chip-type electric double layer capacitor which may be reduced in size and weight and surface-mounted without an additional structure and a method of manufacturing the same.
  • According to an aspect of the present invention, there is provided a chip-type electric double layer capacitor including: an exterior case including a housing space formed therein and formed of insulation resin; a first external terminal buried in the exterior case and including a first surface exposed to the housing space and a second surface exposed to the outside of the exterior case; a second external terminal buried in the exterior case and including a first surface exposed to the housing space and a second surface exposed to the outside of the exterior case; and an electric double layer cell disposed in the housing space so as to be electrically connected to the first surfaces of the first and second external terminals.
  • The first and second external terminals may be buried in the external case by insert injection molding.
  • The first and second external terminals may have a buried region extension region.
  • The insulation resin may be polyphenylene sulfide (PPS) or liquid crystal polymer (LCP).
  • The chip-type electric double layer capacitor may further include adhesive layers which are formed to cover boundary surfaces between the exterior case and the first and second external terminals, respectively.
  • The adhesive layers may be formed to cover boundary surfaces between the exterior case and the second surfaces of the first and second external terminals, respectively.
  • The adhesive layers may be formed to cover boundary surfaces between the exterior case and the first surfaces of the first and second external terminals, respectively.
  • The adhesive layers may include epoxy resin.
  • The first and second external terminals may be formed on the same surface of the exterior case.
  • The first and second external terminals may be formed at both ends of the same surface of the exterior case.
  • The first and second external terminals may be formed on the same surface of the exterior case so as to be positioned toward the central portion of the surface.
  • The exterior case may further include sealing portions formed in the respective corners of the housing space.
  • The exterior case may include a lower case having the housing space of which the top surface is opened and the first and second external terminals buried therein, and an upper cap mounted on the lower case so as to cover the housing space.
  • The exterior case may include a lower case having the housing space of which the top surface is opened, sealing portions formed in the corner of the respective corners of the housing space, and the first and second external terminals buried therein, and an upper cap mounted on the lower case having the sealing portions so as to cover the housing space.
  • The lower case and the upper cap may be coupled to each other by welding or ultrasonic welding.
  • The sealing portions may be formed integrally with the lower case by insert injection molding.
  • The sealing portions may be formed separately from the lower case by double injection molding.
  • The sealing portions and the lower case may be formed of the same insulation resin or different insulation resins.
  • The electric double layer capacitor cell may include first and second current collectors, first and second electrodes connected to the first and second current collectors, respectively, and an ion-permeable separator formed between the first and second electrodes.
  • The first surfaces of the first and second external terminals and the electric double layer capacitor cell may be connected by welding or ultrasonic welding.
  • The electric double layer capacitor cell may include one or more pairs of first and second current collectors, one or more pairs of first and second electrodes, and one or more separators which are continuously stacked.
  • The electric double layer capacitor cell may be formed by winding first and second electrodes.
  • According to another aspect of the present invention, there is provided a method of manufacturing a chip-type electric double layer capacitor, including: forming a lower case having an opened housing space and first and second external terminals buried therein, the first and second external terminals having first surfaces exposed to the housing space, respectively, and second surfaces exposed to an outer region of the lower case, respectively; mounting an electric double layer capacitor cell in the housing space such that the electric double layer capacitor cell is electrically connected to the first surfaces of the first and second external terminals exposed to the housing space; and mounting an upper cap on the lower case so as to cover the housing space.
  • The method may further include forming adhesive layers to cover boundary surfaces between the exterior case and the first and second external terminals.
  • The forming of the lower case may be performed by insert injection molding.
  • The method may further include forming sealing portions in the respective corners of the housing space.
  • The sealing portions may be formed integrally with the lower case by insert injection molding.
  • The sealing portions may be formed separately from the lower case by double injection molding.
  • The connection between the first and second external terminals and the electric double layer capacitor cell may be performed by welding or ultrasonic welding.
  • The mounting of the upper cap on the lower case may be performed by welding or ultrasonic welding.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other aspects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
  • FIG. 1A is a schematic cross-sectional view of a chip-type electric double layer capacitor according to an embodiment of the present invention;
  • FIG. 1B is a schematic perspective view of a chip-type electric double layer capacitor according to another embodiment of the present invention;
  • FIG. 2A is a schematic cross-sectional view of the chip-type electric double layer capacitor of FIG. 1A, taken along a line I-I′;
  • FIG. 2B is a schematic cross-sectional view of a chip-type double layer capacitor according to another embodiment of the present invention, illustrating only a lower case;
  • FIG. 2C is a schematic cross-sectional view of a chip-type double layer capacitor according to another embodiment of the present invention, illustrating only a lower case;
  • FIG. 3A is a schematic cross-sectional view of a chip-type electric double layer capacitor according to another embodiment of the present invention;
  • FIG. 3B is a plan view of a lower case of the chip-type electric double layer capacitor according to the embodiment of the present invention;
  • FIG. 4 is a schematic cross-sectional view of a chip-type electric double layer capacitor according to another embodiment of the present invention;
  • FIG. 5A is a schematic perspective view of a chip-type electric double layer capacitor cell according to another embodiment of the present invention;
  • FIG. 5B is a schematic cross-sectional view of a chip-type electric double layer capacitor according to the embodiment of the present invention;
  • FIGS. 6A to 6C are cross-sectional views explaining a method of manufacturing a chip-type electric double layer chip capacitor according to another embodiment of the present invention; and
  • FIGS. 7A to 7C are cross-sectional views explaining a method of manufacturing a chip-type electric double layer capacitor according to another embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like reference numerals in the drawings denote like elements, and thus their description will be omitted.
  • FIG. 1A is a schematic cross-sectional view of a chip-type electric double layer capacitor according to an embodiment of the present invention. FIG. 2A is a schematic cross-sectional view of the chip-type electric double layer capacitor, taken along a line I-I′ of FIG. 1A.
  • Referring to FIGS. 1A and 2A, the chip-type electric double layer capacitor 100 according the embodiment of the present invention includes an exterior case 110 having a housing space 180 formed therein and formed of insulation resin and an electric double layer capacitor cell 160 disposed in the housing space of the exterior case 110.
  • The exterior case 110 includes first and second external terminals 120 a and 120 b buried therein. The first external terminal 120 a has a first surface 121 a exposed to the housing space 180 and a second surface 122 a exposed to the outside of the exterior case 110, and the second external terminal 120 b has a first surface 121 b exposed to the housing space 180 and a second surface 122 b exposed to the outside of the exterior case 110. That is, the first and second external terminals 120 a and 120 b are structures for connecting the outside of the exterior case 110 and the inside of the housing space 180.
  • The external case 110 may be formed integrally with the first and second external terminals 120 a and 120 b by insert injection molding. For example, a mold having a desired exterior-case shape may be prepared, the first and second external terminals maybe disposed in the mold, and insulation resin may be injected into the mold to manufacture the external case 110 integrated with the first and second external terminals 120 a and 120 b. At this time, the first and second external terminals may be disposed to have the first surface exposed to the housing space of the external case and the second surface exposed to the outside of the external case.
  • The electric double layer cell 160 is disposed in the housing space of the exterior case 110, and electrically connected to the first surfaces 121 a and 121 b of the first and second external terminals 120 a and 120 b exposed to the housing space 180. The second surfaces 122 a and 122 b of the first and second external terminals 120 a and 120 b may be units for electrically connecting the electric double layer cell 160 to an external power supply.
  • The chip-type electric double layer capacitor 100 according to this embodiment of the present invention may include adhesive layers 115 a and 115 b which are formed to cover boundary surfaces between the exterior case and the first and second external terminals 120 a and 120 b, respectively. More specifically, referring to FIGS. 1A and 2A, the adhesive layers 115 a and 115 b may be formed to cover the boundary surfaces between the exterior case and the second surfaces 122 a and 122 b of the first and second external terminals, respectively.
  • Although not shown, adhesive layers may be formed to cover boundary surfaces between the exterior case and the surfaces of the first and second external terminals exposed to the housing space.
  • Although the external terminals 120 a and 120 b are integrated with the external case 110, a minute gap may occur due to the heterogeneity between the two materials, and an electrolyte may escape through the minute gap. That is, when the electrolyte escapes while the chip-type electric double layer capacitor is manufactured or used, reliability may decrease, and the lifespan of the chip-type electric double layer capacitor may be reduced.
  • Therefore, when the adhesive layers 115 a and 115 b are formed at the boundary surfaces between the exterior case and the first and second external terminals, respectively, it is possible to prevent the electrolyte from escaping.
  • The adhesive layer may be formed using epoxy resin. The epoxy resin is not specifically limited. For example, multifunctional epoxy resin having two or more epoxy groups in a molecule, such as bisphenol A epoxy resin, bisphenol novolac resin and so on, may be used as the epoxy resin. The epoxy resin may include a cross-liking agent.
  • Referring to FIGS. 1A and 2A, the first and second external terminals 120 a and 120 b may be formed on the same surface 111 of the external case 111. Furthermore, although not shown, the first and second external terminals may be formed on different surfaces of the external case, respectively.
  • When the first and second external terminals are formed on the same surface 111, the chip-type electric double layer capacitor 100 may be surface-mounted (SMT) without an additional structure.
  • In order to implement such a structure, the first and second external 120 a and 120 b and the external case 110 may form one plane.
  • The formation positions of the first and second external terminals are not specifically limited, and the first and second external terminals 120 a and 120 b may be formed at both ends of the same surface 111 of the external case. The first and second external terminals may extend from both ends of the same surface 111 of the exterior case to both side surfaces connected to the same surface 111, respectively. When the chip-type electric double layer capacitor is surface-mounted, the regions of the first and second external terminals extending to the side surfaces may be utilized for a performance test of the chip-type electric layer double capacitor.
  • FIG. 1B is a schematic perspective view of a chip-type electric double layer capacitor 200 according to another embodiment of the present invention. Referring to FIG. 1B, the chip-type electric double layer capacitor 200 may include first and second external terminals 220 a and 220 b which are formed on the same surface 211 of an external case 210 so as to be positioned toward the central portion of the same surface 211.
  • The chip-type electric double layer capacitor 200 may include adhesive layers 215 a and 215 b which are formed to cover boundary surfaces between the exterior case 210 and the first and second external terminals 220 a and 220 b, respectively.
  • Referring to FIG. 2A, the electric double layer cell 160 disposed in the housing space 180 of the exterior case 110 is electrically connected to the first surfaces 121 a and 121 b of the first and second external terminals 120 a and 120 b exposed to the housing space. The electric double layer capacitor cell 160 may be connected to the first surfaces 121 a and 121 b of the first and second external terminals 120 a and 120 b exposed to the housing space 180 by welding or ultrasonic welding.
  • The electric double layer capacitor cell may include first and second current collectors 130 a and 130 b, first and second electrodes 140 a and 140 b connected to the first and second current collectors 130 a and 130 b, respectively, and an ion permeable separator 150 formed between the first and second electrodes 140 a and 140 b.
  • The first and second current collectors 130 a and 130 b are conductive sheets for transferring an electrical signal to the first and second electrodes 140 a and 140 b, respectively, and may be formed of a conductive polymer, a rubber sheet, or a metallic foil. In this embodiment, the electric double layer capacitor cell 160 may be electrically connected to the first and second external terminals 120 a and 120 b through the current collectors 130 a and 130 b. The shapes of the first and second current collectors 130 a and 130 b may be properly modified in such a manner that they are electrically connected to the first and second external electrodes 120 a and 120 b, respectively. Such a modification may be influenced by the shape or size of the electric double layer capacitor cell.
  • Referring to FIG. 2A, the first current collector 130 a may have a bent portion for the connection with the first external terminal 120 a, and the first and second current collectors 130 a and 130 b may be directly connected to the first and second external terminals 120 a and 120 b, respectively.
  • Although not shown, the first and second current collectors may be electrically connected to the first and second external terminals through proper connection members, respectively.
  • Furthermore, although not shown, an insulation layer may be formed between one surface of the exterior case, in which the first and second external terminals 120 a and 120 b are buried, and the second current collector 130 contacted with the surface, in order to prevent a short circuit.
  • When the electric double layer capacitor cell does not include the first and second current collectors 130 a and 130 b, the first and second electrodes 130 a and 130 b may be electrically connected to the first surfaces of the first and second external terminals 120 a and 120 b exposed to the housing space.
  • The first and second electrodes 140 a and 140 b may be formed of a polarizable electrode material. For example, activated carbon with a relatively high specific surface area may be used. The first and second electrodes 140 a and 140 b may be manufactured by making an electrode material mainly consisting of powdered activated carbon into a solid-state sheet or adhering electrode material slurry onto the first and second current collectors 130 a and 130 b.
  • The separator 150 may be formed of a porous material through which ions can permeate. For example, a porous material such as polypropylene, polyethylene, or glass fiber may be used.
  • In this embodiment, the exterior case 110 may include a lower case 110 a and an upper cap 110 b. The lower case 110 a has a housing space of which the top surface is opened and includes the first and second external terminals 120 a and 120 b buried therein. The upper cap 110 b is mounted on the lower case 110 a so as to cover the housing space.
  • The upper cap 110 a and the lower case 110 b may be coupled to each other by welding or ultrasonic welding. A symbol P of FIG. 2A indicates a coupling region between the lower case and the upper cap.
  • The exterior case 110 is formed of insulation resin. Examples of the insulation resin may include polyphenylene sulfide (PPS) and liquid crystal polymer (LCP). Accordingly, the chip-type electric double layer capacitor 100 may protect the internal structure during the surface mounting (SMT) process which is performed at a high temperature of about 240-270° C.
  • As described above, the chip-type electric double layer capacitor according to this embodiment of the present invention has such a structure that the first and second external terminals 120 a and 120 b are buried in the exterior case 110. Therefore, its space utilization efficiency increases. Accordingly, it is possible to increase the stacking degree of the electric double layer capacitor cell mounted in the chip-type electric double layer capacitor.
  • FIG. 2B is a schematic cross-sectional view of a chip-type double layer capacitor according to another embodiment of the present invention, illustrating only a lower case 110 b. The following descriptions will be focused on different components from those of the above-described embodiment, and the duplicated descriptions of the same components will be omitted.
  • In this embodiment of the present invention, the first and second external terminals 120 a and 120 b are buried in the exterior case 110. The first external terminal 120 a has the first surface 121 a exposed to the housing space 180 and the second surface 122 a exposed to the outside of the exterior case. The second external terminal 120 a has the first surface 121 b exposed to the housing space 180, and the second surface 122 b exposed to the outside of the exterior case.
  • The first and second external terminals 120 a and 120 b are formed integrally with the external case 110 so as to be buried in the external case 110. However, a minute gap may occur due to due to the heterogeneity between the two materials, and an electrolyte may escape through the minute gap.
  • When the electrolyte escapes while the chip-type electric double layer capacitor is manufactured or used, its reliability may decrease, and its lifespan may be reduced.
  • Therefore, the contact area between the first and second external terminals and the exterior case may be widened in such a manner that an electrolyte escape path can be extended.
  • Accordingly, the first and second external terminals may be formed to have a buried region extension portion D. The shape of the buried region extension portion D is not limited. Referring to FIG. 2B, the first and second external terminals are formed in a plate shape. In this case, the plate shape may be bent in such a manner that a part thereof is exposed to the housing space and another part thereof is exposed to the outside. Accordingly, the buried regions of the first and second external terminals in the exterior case may be extended.
  • The chip-type double layer capacitor according to this embodiment of the present invention may include adhesive layers which are formed to cover the boundary surface between each of the first and second external terminals and the exterior case. Referring to FIG. 2, the chip-type double layer capacitor may include first adhesive layers 115 a and 115 b which are formed to cover the boundary surfaces between the external case and the second surfaces 122 a and 122 b of the first and second external terminals 120 a and 120 b, respectively, and second adhesive layers 116 a and 116 b which are formed to cover the boundary surfaces between the external case and the first surfaces 121 a and 121 b of the first and second external terminals 120 a and 120 b, respectively.
  • Furthermore, the chip-type double layer capacitor may include a third adhesive layer 117 formed on a coupling region of the lower case 110 b which is to be coupled to the upper cap 110 a.
  • FIG. 2C is a schematic cross-sectional view of a chip-type double layer capacitor according to another embodiment of the present invention, illustrating only a lower case 110 b. The following descriptions will be focused on different components from those of the above-described embodiments, and the duplicated descriptions of the same components will be omitted.
  • Referring to FIG. 2C, the first external terminal has the first surface 121 a exposed to the housing space 180 and the second surface 122 a exposed to the outside, and the second external terminal has the first surface 122 a exposed to the housing space 180 and the second surface 122 b exposed to the outside. The first and second external terminals have a buried region extension portion D. The buried region extension portion D may be formed in various shapes such that a contact area with exterior case can be extended.
  • FIG. 3A is a schematic cross-sectional view of a chip-type electric double layer capacitor 100 according to another embodiment of the present invention. FIG. 3B is a plan view of a lower case 110 b of the chip-type electric double layer capacitor according to the embodiment of the present invention. The following descriptions will be focused on different components from those of the above-described embodiments, and the duplicated descriptions of the same components will be omitted.
  • Referring to FIGS. 3A and 3B, the chip-type electric double layer capacitor 100 according to this embodiment of the present invention includes an exterior case 110 and an electric double layer capacitor cell 160. The exterior case 110 has a housing space 180 formed therein, includes sealing portions 170 formed in the respective corners of the housing space 180, and is formed of insulation resin. The electrode double layer cell 160 is disposed in the housing space 180 of the exterior case 110.
  • The sealing portions 170 may be formed by injecting insulation resin such that the lower case 110 b having the first and second external terminals 120 a and 120 b buried therein are molded integrally with the sealing portions 170 by insert injection molding or the like. In this case, the sealing portions 170 may be formed of the same insulation resin as the lower case 110 b.
  • Instead of the above-described structure in which the sealing portions 170 and the lower case 110 b are integrally molded, the sealing portions 170 maybe formed in the respective corners of the housing space 180 inside the lower case 110 b by double injection molding, separately from the lower case 110 b. In this case, the sealing portions 170 may be formed of the same insulation resin as the lower case 110 b, but formed of a different insulation resin from the lower case 110 b.
  • The lower case 110 b including the sealing portions 170 may be coupled to the upper cap 110 a by welding or ultrasonic welding. A symbol P of FIG. 3A indicates a coupling region between the upper cap 110 a and the lower case 110 b including the sealing portions 170.
  • According to this embodiment of the present invention, as the sealing portions 170 are formed in the respective corners of the housing space 180 inside the lower case 110 b, it is possible to maximize the welded surface of the lower case 110 b coupled to the upper cap 110 a. Therefore, a probability in which the electrolyte inside the chip-type electric double layer capacitor 100 may escape to the outside may be minimized to strengthen the sealing property.
  • Furthermore, as the sealing portions 170 are formed in the above-described manner, the coupling region P between the lowercase 110 b and the upper cap 110 a, that is, the welded area therebetween may be widened. Then, a coupling force between the lower case 110 b and the upper cap 110 a may be maximized to increase the durability of a finalized product.
  • FIG. 4 is a schematic cross-sectional view of a chip-type electric double layer capacitor 300 according to another embodiment of the present invention. The following descriptions will be focused on different components from those of the above-described embodiments, and the duplicated descriptions of the same components will be omitted.
  • Referring to FIG. 4, the electric double layer capacitor according to this embodiment of the present invention has a structure in which one or more pairs of first and second current collectors, one or more pairs of first and second electrodes, and one or more separators are continuously stacked. Since the electric double layer capacitor has high space utilization efficiency, it may include a plurality of electric double layer cells stacked therein.
  • More specifically, primary first and second current collectors 331 a and 331 b are connected to first and second external terminals 320 a and 320 b, respectively. The primary first current collector 331 a is connected to a primary first electrode 341 a, the primary second current collector 331 b is connected to a primary second electrode 341 b, and a primary ion-permeable separator 351 is formed between the primary first and second electrodes 341 a and 341 b, thereby forming one unit cell.
  • The primary first current collector 331 a is connected to a secondary first electrode 342 a, a secondary second current collector 332 b is connected to a secondary second electrode 342 b, and a secondary ion-permeable separator 352 is formed between the secondary first and second electrodes 342 a and 342 b, thereby forming another unit cell. The secondary second current collector 332 b is bent to be electrically connected to the second external terminal 320 b.
  • The secondary second current collector 332 b is connected to a tertiary second electrode 343 b, a secondary first current collector 332 a is connected to a tertiary first electrode 343 a, and a tertiary ion-permeable separator 353 is formed between the tertiary first and second electrodes 343 a and 343 b, thereby forming another unit cell. The secondary first current collector 332 a is bent to be electrically connected to the second external terminal 320 b.
  • As in this embodiment, the plurality of unit cells may be stacked to obtain a high capacitance. Although not shown, an insulation material may be applied onto the outside of the unit-cell multilayer structure to prevent an unexpected short circuit.
  • In this embodiment of the present invention, the first and second external terminals 320 a and 320 b are buried into one surface 311 of the exterior case. However, since the first and second external terminals 320 a and 320 b have a larger thickness than the exterior case, they protrude to the outside of the exterior case.
  • Furthermore, the electric double layer capacitor according to the embodiment of the present invention may include adhesive layers 315 a and 315 b which are formed to cover boundary surfaces between the exterior case and the first and second external terminals, respectively.
  • FIG. 5A is a schematic perspective view of a chip-type electric double layer capacitor cell 460 according to another embodiment of the present invention, and FIG. 5B is a schematic cross-sectional view of a chip-type electric double layer capacitor 400 according to the embodiment of the present invention. The following descriptions will be focused on different components from those of the above-described embodiments, and the duplicated descriptions of the same components will be omitted.
  • Referring to FIGS. 5A and 53, the electric double layer cell 460 according to this embodiment of the present invention has a structure in which first and second electrodes are wound. More specifically, a first electrode 440 a, a first separator 450 a, a second electrode 440 b, and a second separator 450 b are sequentially stacked, and the multilayer structure is wound to form the electric double layer cell 460. The first and second electrodes 440 a and 440 b are connected to first and second current collectors 430 a and 430 b, respectively.
  • The electric double layer capacitor cell 460 is disposed in a housing space of an exterior case 410, and the first and second current collectors 430 a and 430 b are bent to be electrically connected to first and second external terminals 420 a and 420 b, respectively.
  • In this embodiment, the first and second external terminals 420 a and 420 b are buried into one surface 411 of the exterior case. However, the first and second external terminals 420 a and 420 b have a larger thickness than the exterior case so as to protrude to the housing space of the exterior case.
  • Furthermore, the electric double layer capacitor according to the embodiment of the present invention may include adhesive layers 415 a and 415 b which are formed to cover boundary surfaces between the exterior case and the first and second external terminals, respectively.
  • FIGS. 6A to 6C are cross-sectional views explaining a method of manufacturing a chip-type electric double layer chip capacitor according to another embodiment of the present invention.
  • Referring to FIG. 6A, a lower case 110 b having an opened housing space 180 and including first and second external terminals 120 a and 120 b buried therein is formed. The first external terminal 120 a has a first surface 121 a exposed to the housing space 180 and a second surface 122 a exposed to the outside of the lower case 110 b, and the second external terminal 120 b has a first surface 122 a exposed to the housing space 160 and a second surface 122 b exposed to the outside of the lower case 110 b.
  • The process of forming the lower case 110 b is not specifically limited, as long as insulation resin and the first and second external terminals may be integrally molded so that the first and second external terminals are buried in the insulation resin. For example, insert injection molding may be applied.
  • More specifically, the first and second external terminals are disposed in a mold having a desired lower-case shape, and insulation resin is injected into the mold. The insulation resin injected into the mold hardens with the first and second external terminals in the mold through cooling or cross-linking. The insulation resin and the first and second external terminals are integrated by the insert injection molding, even though the first and second external terminals are formed of a different material from the insulation resin.
  • Next, adhesive layers are formed to cover boundary surfaces between the external case and the first and second external terminals, respectively. Referring to FIG. 6A, the adhesive layers 115 a and 115 b may be formed to cover the boundary surfaces between the exterior case and the second surfaces 122 a and 122 b of the first and second external terminals, respectively. Although not shown, the adhesive layers may be formed to cover the boundary surfaces between the exterior case and the first surfaces 121 a and 122 b of the first and second external terminals.
  • Referring to FIG. 6B, an electric double layer capacitor cell 160 is mounted in the housing space so as to be electrically connected to the first surfaces 121 a and 121 b of the first and second external terminals 120 a and 120 b exposed to the housing space of the lower case 110 b.
  • As described above, the electric double layer capacitor cell may include first and second current collectors 130 a and 130 b, first and second electrodes 140 a and 140 b connected to the first and second current collectors 130 a and 130 b, respectively, and an ion-permeable separator 150 formed between the first and second electrodes 140 a and 140 b. The first and second current collectors 130 a and 130 b are electrically connected to the first surfaces of the first and second external terminals 120 a and 120 b exposed to the housing space, and the first current collector 130 a may have a bent shape.
  • The first and second external terminals 120 a and 120 b may be connected to the first and second current collectors 130 a and 130 b, respectively, by welding or ultrasonic welding. For example, resistance welding or arc welding may be applied.
  • Referring to FIG. 6C, an upper cap 110 a is mounted on the lower case 110 b so as to cover the housing space. Then, the lower case 110 b having the electric double layer capacitor cell mounted therein is filled with an electrolyte. In this case, an aqueous electrolyte or non-aqueous electrolyte may be used as the electrolyte.
  • The mounting of the upper cap 110 a on the lower case 110 b may be performed by forming an adhesive layer (not shown). That is, an adhesive layer is applied on a region P of the lower case 110 b, and the upper cap 110 a is mounted on the region P so as to be coupled to the lower case 110 b.
  • Alternatively, the mounting of the upper cap 110 a on the lower case 110 b may be performed by welding or ultrasonic welding. For example, resistance welding or arc welding may be applied.
  • Through such a process, the airtightness between the lower case and the upper cap may be improved to protect the internal elements of the exterior case.
  • FIGS. 7A to 7C are cross-sectional views explaining a method of manufacturing a chip-type electric double layer capacitor according to another embodiment of the present invention. The following descriptions will be focused on different components from those of the above-described embodiment, and the duplicated descriptions of the same components will be omitted.
  • Referring to FIG. 7A, a lower case 110 b is formed. The lower case 110 b includes first and second external terminals 120 a and 120 b buried therein, a housing space 180 of which the top surface is opened, and sealing portions 170 formed in the respective corners of the housing space 180.
  • The process of forming the first and second external terminals 120 a and 120 b and the lower case 110 b is not limited, as long as insulation resin and the first and second external terminals 120 a and 120 b may be integrally molded so that the first and second external terminals 120 a and 120 b are buried in the insulation resin. For example, insert injection molding may be used.
  • At this time, the sealing portions 170 formed in the respective corners of the housing space 180 of the lower case 110 b may be formed integrally with the lower case 10 b during the insert injection molding of the lower case 110 b.
  • Alternatively, the sealing portions 170 and the lower case 110 b may be separately formed by double injection molding, unlike the above-described process. In this case, the sealing portions 170 and the lower case 110 b may be formed of the same insulation resin or different insulation resins.
  • Referring to FIG. 7B, an electric double layer capacitor cell 160 is mounted in the housing space 180 so as to be electrically connected to the first surfaces 121 a and 121 b of the first and second external terminals 120 a and 120 b exposed to the housing space 180 of the lower case 110 b.
  • After the electric double layer capacitor cell 160 is mounted in the lower case 110 b, the housing space 180 is filled with an electrolyte. In this case, an aqueous electrolyte or non-aqueous electrolyte may be used as the electrolyte.
  • Referring to FIG. 7C, an upper cap 110 a is mounted on the lower case 110 b including the sealing portions 170 so as to cover the housing space 180.
  • The mounting of the upper cap 110 a on the lower case 110 b including the sealing portions 170 may be performed by welding or ultrasonic welding. For example, resistance welding or arc welding may be applied. Through such a process, the airtightness between the lower case 110 b and the upper cap 110 a may be improved to protect the internal elements of the exterior case 110.
  • According to this embodiment of the present invention, as the sealing portions 170 are formed in the lower case 110 b, it is possible to maximize the coupling area between the upper cap 110 a and the lower case 110 b. Therefore, since the electrolyte inside the lower case 110 b may be prevented from escaping to the outside, the sealing property may be improved to increase the durability of a finalized product.
  • In the chip-type electric capacitor type according to the embodiment of the present invention, since the exterior case and the external terminals are integrally formed, the space utilization efficiency is high. Accordingly, the electric double layer capacitor may be reduced in size and weight and increased in capacity. Furthermore, the chip-type electric double layer capacitor may be surface-mounted without an additional structure. A collective mounting technique using a solder method may be applied to simplify the surface mounting process.
  • Furthermore, since the contact area between the first and second external terminals and the exterior case may be extended, the electrolyte escape path may be enlarged. Further, the adhesive layers may be formed at the boundary surfaces between the first and second external terminals and the exterior case. Accordingly, it is possible to prevent the electrolyte form escaping.
  • Furthermore, as the sealing portions are formed in the respective corners of the housing space when the lower is molded, the welded surface of the lower case coupled to the upper cap may be maximized. Therefore, since the electrolyte inside the exterior case may be prevented from escaping to the outside, it is possible to strength the sealing property. Accordingly, it is possible to improve the durability of a finalized product.
  • While the present invention has been shown and described in connection with the exemplary embodiments, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (30)

1. A chip-type electric double layer capacitor comprising:
an exterior case comprising a housing space formed therein and formed of insulation resin;
a first external terminal buried in the exterior case and comprising a first surface exposed to the housing space and a second surface exposed to the outside of the exterior case;
a second external terminal buried in the exterior case and comprising a first surface exposed to the housing space and a second surface exposed to the outside of the exterior case; and
an electric double layer cell disposed in the housing space so as to be electrically connected to the first surfaces of the first and second external terminals.
2. The chip-type electric double layer capacitor of claim 1, wherein the first and second external terminals are buried in the external case by insert injection molding.
3. The chip-type electric double layer capacitor of claim 1, wherein the first and second external terminals have a buried region extension region.
4. The chip-type electric double layer capacitor of claim 1, wherein the insulation resin is polyphenylene sulfide (PPS) or liquid crystal polymer (LCP).
5. The chip-type electric double layer capacitor of claim 1, further comprising adhesive layers which are formed to cover boundary surfaces between the exterior case and the first and second external terminals, respectively.
6. The chip-type electric double layer capacitor of claim 5, wherein the adhesive layers are formed to cover boundary surfaces between the exterior case and the second surfaces of the first and second external terminals, respectively.
7. The chip-type electric double layer capacitor of claim 5, wherein the adhesive layers are formed to cover boundary surfaces between the exterior case and the first surfaces of the first and second external terminals, respectively.
8. The chip-type electric double layer capacitor of claim 5, wherein the adhesive layers comprise epoxy resin.
9. The chip-type electric double layer capacitor of claim 1, wherein the first and second external terminals are formed on the same surface of the exterior case.
10. The chip-type electric double layer capacitor of claim 1, wherein the first and second external terminals are formed at both ends of the same surface of the exterior case.
11. The chip-type electric double layer capacitor of claim 1, wherein the first and second external terminals are formed on the same surface of the exterior case so as to be positioned toward the central portion of the surface.
12. The chip-type electric double layer capacitor of claim 1, wherein the exterior case further comprises sealing portions formed in the respective corners of the housing space.
13. The chip-type electric double layer capacitor of claim 1, wherein the exterior case comprises:
a lower case having the housing space of which the top surface is opened and the first and second external terminals buried therein; and
an upper cap mounted on the lower case so as to cover the housing space.
14. The chip-type electric double layer capacitor of claim 1, wherein the exterior case comprises:
a lower case having the housing space of which the top surface is opened, sealing portions formed in the corner of the respective corners of the housing space, and the first and second external terminals buried therein; and
an upper cap mounted on the lower case having the sealing portions so as to cover the housing space.
15. The chip-type electric double layer capacitor of claim 13, wherein the lower case and the upper cap are coupled to each other by welding or ultrasonic welding.
16. The chip-type electric double layer capacitor of claim 14, wherein the sealing portions are formed integrally with the lower case by insert injection molding.
17. The chip-type electric double layer capacitor of claim 14, wherein the sealing portions are formed separately from the lower case by double injection molding.
18. The chip-type electric double layer capacitor of claim 14, wherein the sealing portions and the lower case are formed of the same insulation resin or different insulation resins.
19. The chip-type electric double layer capacitor of claim 1, wherein the electric double layer capacitor cell comprises first and second current collectors, first and second electrodes connected to the first and second current collectors, respectively, and an ion-permeable separator formed between the first and second electrodes.
20. The chip-type electric double layer capacitor of claim 1, wherein the first surfaces of the first and second external terminals and the electric double layer capacitor cell are connected by welding or ultrasonic welding.
21. The chip-type electric double layer capacitor of claim 1, wherein the electric double layer capacitor cell comprises one or more pairs of first and second current collectors, one or more pairs of first and second electrodes, and one or more separators which are continuously stacked.
22. The chip-type electric double layer capacitor of claim 1, wherein the electric double layer capacitor cell is formed by winding first and second electrodes.
23. A method of manufacturing a chip-type electric double layer capacitor, comprising:
forming a lower case having an opened housing space and first and second external terminals buried therein, the first and second external terminals having first surfaces exposed to the housing space, respectively, and second surfaces exposed to an outer region of the lower case, respectively;
mounting an electric double layer capacitor cell in the housing space such that the electric double layer capacitor cell is electrically connected to the first surfaces of the first and second external terminals exposed to the housing space; and
mounting an upper cap on the lower case so as to cover the housing space.
24. The method of claim 23, further comprising forming adhesive layers to cover boundary surfaces between the exterior case and the first and second external terminals.
25. The method of claim 23, wherein the forming of the lower case is performed by insert injection molding.
26. The method of claim 23, further comprising forming sealing portions in the respective corners of the housing space.
27. The method of claim 26, wherein the sealing portions are formed integrally with the lower case by insert injection molding.
28. The method of claim 26, wherein the sealing portions are formed separately from the lower case by double injection molding.
29. The method of claim 23, wherein the connection between the first and second external terminals and the electric double layer capacitor cell is performed by welding or ultrasonic welding.
30. The method of claim 23, wherein the mounting of the upper cap on the lower case is performed by welding or ultrasonic welding.
US12/654,751 2009-07-06 2009-12-30 Chip-type electric double layer capacitor and method of manufacturing the same Abandoned US20110002084A1 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
KR10-2009-0061333 2009-07-06
KR20090061333 2009-07-06
KR10-2009-0086085 2009-09-11
KR1020090086085A KR101133374B1 (en) 2009-09-11 2009-09-11 Chip-type electric double layer capacitor and method for manufacturing the same
KR10-2009-0086624 2009-09-14
KR10-2009-0086487 2009-09-14
KR1020090086487A KR101067177B1 (en) 2009-09-14 2009-09-14 Chip-type electric double layer capacitor and method for manufacturing the same
KR1020090086624A KR101070084B1 (en) 2009-07-06 2009-09-14 Chip-type electric double layer capacitor and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/568,483 US9070513B2 (en) 2009-07-06 2012-08-07 Method of manufacturing chip-type electric double layer capacitor

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/568,483 Division US9070513B2 (en) 2009-07-06 2012-08-07 Method of manufacturing chip-type electric double layer capacitor

Publications (1)

Publication Number Publication Date
US20110002084A1 true US20110002084A1 (en) 2011-01-06

Family

ID=43307932

Family Applications (2)

Application Number Title Priority Date Filing Date
US12/654,751 Abandoned US20110002084A1 (en) 2009-07-06 2009-12-30 Chip-type electric double layer capacitor and method of manufacturing the same
US13/568,483 Active 2030-10-29 US9070513B2 (en) 2009-07-06 2012-08-07 Method of manufacturing chip-type electric double layer capacitor

Family Applications After (1)

Application Number Title Priority Date Filing Date
US13/568,483 Active 2030-10-29 US9070513B2 (en) 2009-07-06 2012-08-07 Method of manufacturing chip-type electric double layer capacitor

Country Status (4)

Country Link
US (2) US20110002084A1 (en)
JP (1) JP4994464B2 (en)
CN (1) CN101944440A (en)
DE (1) DE102010001062A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150221448A1 (en) * 2012-11-29 2015-08-06 Murata Manufacturing Co., Ltd. Power storage device
US20160205769A1 (en) * 2015-01-08 2016-07-14 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component and board having the same

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014072464A (en) 2012-09-29 2014-04-21 Murata Mfg Co Ltd Power storage device
US9312072B2 (en) * 2013-03-18 2016-04-12 Apaq Technology Co., Ltd. Winding-type solid electrolytic capacitor package structure using a carrier board and method of manufacturing the same

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5041696A (en) * 1988-04-21 1991-08-20 Siemens Aktiengesellschaft Chip component for fastening to a circuit board, comprising an electrical or electronic function member
US20010012193A1 (en) * 2000-02-04 2001-08-09 Shunji Watanabe Non-aqueous electrolyte cells and electric double layer capacitors
US6459564B1 (en) * 1999-01-26 2002-10-01 Seiko Instruments Inc. Electrical double layer capacitor and portable electronic apparatus equipped with electrical double layer capacitor
US20040241542A1 (en) * 2003-05-30 2004-12-02 Yoshibumi Nakamura Electrochemical cell
US20050207095A1 (en) * 2003-12-03 2005-09-22 Sanyo Electric Co., Ltd. Electric double layer capacitor, electrolytic cell and process for fabricating same
US20050250010A1 (en) * 2002-12-05 2005-11-10 Tdk Corporation Coating liquid for electrode formation, electrode. electrochemical device, and process for producing these
US20060087795A1 (en) * 2004-10-27 2006-04-27 Nec Tokin Corporation Surface-mount capacitor and method of producing the same
US7095605B2 (en) * 2002-03-14 2006-08-22 Sanyo Electric Co., Ltd. Solid electrolytic capacitor
US20070014076A1 (en) * 2003-05-30 2007-01-18 Sanyo Electric Co., Ltd. Electric double layer capacitor and electrolytic cell
US20080206635A1 (en) * 2007-02-27 2008-08-28 Seiko Instruments Inc. Electrochemical Element
US20090011330A1 (en) * 2005-07-29 2009-01-08 Sii Micro Parts Ltd. Electrochemical Cell

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0732958B2 (en) 1989-07-14 1995-04-12 株式会社東芝 Laser processing method
JPH1154387A (en) * 1997-07-30 1999-02-26 Tdk Corp Chip-type electric double-layer capacitor
JP3151177B2 (en) 1997-12-02 2001-04-03 ハウス食品株式会社 Method for producing sterilized spice powder and curry powder containing curry powder produced by the method
FR2824663B1 (en) 2001-05-14 2004-10-01 Semco Sa Method and device for doping, diffusing and pyrolithic oxidation of reduced pressure silicon wafers
DE10312999A1 (en) 2003-03-24 2004-10-07 Daimlerchrysler Ag Preparation of an electrode for supercapacitors comprising deposition of a strongly adhering dendritic micro- or nanoporous metal layer useful for batteries, in automobile construction, and in the telecommunication industry
JP2004327887A (en) 2003-04-28 2004-11-18 Sanyo Electric Co Ltd Capacitor array or battery array
JP2004356461A (en) 2003-05-30 2004-12-16 Sanyo Electric Co Ltd Electric double layer chip capacitor and chip electrolyte battery
JP2006012792A (en) 2004-05-28 2006-01-12 Kyocera Corp Case for battery, battery, case for electric double layer capacitor, and electric double layer capacitor
JP2006049289A (en) * 2004-06-29 2006-02-16 Kyocera Corp Case for battery, battery, case for electric double layer capacitor, and electric double layer capacitor
JP4868797B2 (en) 2004-09-28 2012-02-01 京セラ株式会社 Battery case and battery, and electric double layer capacitor case and electric double layer capacitor
JP2007026945A (en) * 2005-07-19 2007-02-01 Toyota Motor Corp Battery and manufacturing method thereof
JP2007207920A (en) * 2006-01-31 2007-08-16 Sanyo Electric Co Ltd Capacitor
KR100774735B1 (en) 2006-02-14 2007-11-08 엘에스전선 주식회사 Connecting structure between electrode and lead, electric double layer capacitor having the same, and Manufacturing method for the capacitor
JP2008085084A (en) * 2006-09-27 2008-04-10 Sanyo Electric Co Ltd Electric double layer capacitor
CA2664954C (en) 2006-12-01 2015-02-17 Nelson E. Hurst, Iii Fold flat seat with rearward folding motion
JP2009200161A (en) 2008-02-20 2009-09-03 Nec Tokin Corp Electric double layer capacitor
KR100881854B1 (en) 2008-09-10 2009-02-09 박용성 Surface mount devices type super capacitor and its manufacturing process
KR101048216B1 (en) 2009-05-26 2011-07-08 김상태 Tree support

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5041696A (en) * 1988-04-21 1991-08-20 Siemens Aktiengesellschaft Chip component for fastening to a circuit board, comprising an electrical or electronic function member
US6459564B1 (en) * 1999-01-26 2002-10-01 Seiko Instruments Inc. Electrical double layer capacitor and portable electronic apparatus equipped with electrical double layer capacitor
US20010012193A1 (en) * 2000-02-04 2001-08-09 Shunji Watanabe Non-aqueous electrolyte cells and electric double layer capacitors
US7095605B2 (en) * 2002-03-14 2006-08-22 Sanyo Electric Co., Ltd. Solid electrolytic capacitor
US20050250010A1 (en) * 2002-12-05 2005-11-10 Tdk Corporation Coating liquid for electrode formation, electrode. electrochemical device, and process for producing these
US20040241542A1 (en) * 2003-05-30 2004-12-02 Yoshibumi Nakamura Electrochemical cell
US20070014076A1 (en) * 2003-05-30 2007-01-18 Sanyo Electric Co., Ltd. Electric double layer capacitor and electrolytic cell
US7248460B2 (en) * 2003-05-30 2007-07-24 Sanyo Electric Co., Ltd. Electric double layer capacitor and electrolytic cell
US20050207095A1 (en) * 2003-12-03 2005-09-22 Sanyo Electric Co., Ltd. Electric double layer capacitor, electrolytic cell and process for fabricating same
US20060087795A1 (en) * 2004-10-27 2006-04-27 Nec Tokin Corporation Surface-mount capacitor and method of producing the same
US20090011330A1 (en) * 2005-07-29 2009-01-08 Sii Micro Parts Ltd. Electrochemical Cell
US20080206635A1 (en) * 2007-02-27 2008-08-28 Seiko Instruments Inc. Electrochemical Element

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150221448A1 (en) * 2012-11-29 2015-08-06 Murata Manufacturing Co., Ltd. Power storage device
US9558893B2 (en) * 2012-11-29 2017-01-31 Murata Manufacturing Co., Ltd. Power storage device
US20160205769A1 (en) * 2015-01-08 2016-07-14 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component and board having the same
US9491847B2 (en) * 2015-01-08 2016-11-08 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component and board having the same

Also Published As

Publication number Publication date
US9070513B2 (en) 2015-06-30
JP4994464B2 (en) 2012-08-08
CN101944440A (en) 2011-01-12
DE102010001062A1 (en) 2011-01-13
US20120297594A1 (en) 2012-11-29
JP2011014864A (en) 2011-01-20

Similar Documents

Publication Publication Date Title
US8259013B2 (en) Protective circuit module and secondary battery pack including the same
JP5846932B2 (en) Method for manufacturing an electrochemical cell having an electrode assembly with the same electrode tab size at the joint
US6726732B2 (en) Electric energy storage device and method for manufacturing the same
JP4736580B2 (en) Bipolar battery, battery pack and vehicle equipped with these batteries
DE10085269B3 (en) Ultrathin electrochemical energy storage devices
JP5275271B2 (en) Secondary battery
JP4964350B2 (en) Electrochemical device and manufacturing method thereof
KR100873308B1 (en) High Capacity Battery Cell Employed with Two or More Unit Cells
US6621687B2 (en) Micro-supercapacitor
JP4436121B2 (en) Power storage device and method for manufacturing power storage device
CN101401229B (en) Middle or large-sized battery module employing impact-absorbing member
KR20180082491A (en) Lithium batteries utilizing nanoporous separator layers
JP4628682B2 (en) Battery unit and lithium secondary battery using the same
KR100428693B1 (en) Electric double layer capacitor and battery
EP1812979B1 (en) Lithium ion secondary batteries
US8797716B2 (en) Electrochemical cell
US7659014B2 (en) Electrode assembly having super-capacitor and lithium secondary battery having the same
US7248460B2 (en) Electric double layer capacitor and electrolytic cell
JP5269854B2 (en) Electrochemical capacitor
JP4502265B2 (en) Pouch type lithium polymer battery and manufacturing method thereof
CN101662038B (en) Battery pack
KR100905390B1 (en) Pouch-type Secondary Battery Having Improved Safety by Preventing Internal Moving of Electrode Assembly
CN102386349B (en) Battery pack
JP2012230916A (en) Method for manufacturing collector
KR20070099430A (en) Lithium secondary battery improved safety and capacity

Legal Events

Date Code Title Description
AS Assignment

Owner name: SAMSUNG ELECTRO-MECHANICS CO., LTD., KOREA, REPUBL

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, SANG KYUN;JUNG, CHANG RYUL;LEE, SUNG HO;AND OTHERS;SIGNING DATES FROM 20091124 TO 20091130;REEL/FRAME:023765/0732

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION