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US20100314748A1 - Chip packaging method and structure thereof - Google Patents

Chip packaging method and structure thereof Download PDF

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Publication number
US20100314748A1
US20100314748A1 US12585323 US58532309A US2010314748A1 US 20100314748 A1 US20100314748 A1 US 20100314748A1 US 12585323 US12585323 US 12585323 US 58532309 A US58532309 A US 58532309A US 2010314748 A1 US2010314748 A1 US 2010314748A1
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metal
plurality
chip
layer
packaging
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Abandoned
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US12585323
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Cheng-Ho Hsu
Kuei Pin WAN
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Kun Yuan Tech Co Ltd
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Kun Yuan Tech Co Ltd
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    • HELECTRICITY
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L24/42Wire connectors; Manufacturing methods related thereto
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    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
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    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/181Encapsulation

Abstract

The present invention relates to a chip packaging method and structure, in which bonding pads provided on the chip are connected by a plurality of metal wires via bonding, each of the metal wires is bending in the middle part to be higher than a predetermined height, and its ends are respectively electrically connected with two of the bonding pads. A molding layer is packaged on the chip and the molding layer is higher than the predetermined height. The molding layer is sliced at the predetermined height. Two upper breakpoints of each metal wire are exposed and a substrate is attached onto the molding layer. A plurality of circuit contacts of the substrate are respectively electrically coupled with the upper breakpoints. Whereby, the invention is capable of reducing the length of the metal wires in order to improve transmission speed, but also to reduce the volume of the packaging structure.

Description

    BACKGROUND OF THE INVENTION
  • [0001]
    1. Field of the Invention
  • [0002]
    The present invention relates to a chip packaging method and structure and, more particularly, to a packaging method and structure for use in inverting a chip in a semiconductor packaging process.
  • [0003]
    2. Description of Related Art
  • [0004]
    Please refer to FIG. 1. FIG. 1 is a cross-sectional diagram of a conventional chip packaging body 9. A commonly known conventional method for packaging a chip is as follows: firstly, attaching a chip 91 onto a substrate 93 disposed in advance with circuits and a plurality of connecting pads 931, then bonding golden wires 92 to electrically connect contacts 911 on the chip 91 with the plurality of connecting pads 931 on the substrate 93, finally packaging a molding layer 94.
  • [0005]
    However, the approach of bonding golden wires 92 in the packaging method of the existing technology is as follows: bonding out from the contacts 911 on the chip 91 and connecting downward with the connecting pads 931 on the substrate 93 when attaining a particular height. Such an approach results is too long in length of the connecting golden wires 92, rendering waste of cost of the golden wires 92. And more importantly, the longer the connecting golden wires 92, the larger the signal loss or the higher the noise produced, when requiring the chip packaging body 9 of high transmission speed, in particular the analog signal chip.
  • [0006]
    Therefore, it is desirable to provide an improved chip packaging method and structure so as to raise the transmission speed of the chip packaging body, save cost of the golden wires, reduce the volume of the chip packaging body and to allow the chip in the packaging body to be in a better protection state.
  • SUMMARY OF THE INVENTION
  • [0007]
    An object of the present invention is to provide a chip packaging method, comprising the following steps:
  • [0008]
    (A) providing a chip, a plurality of bonding pads being provided on an upper surface thereof; (B) connecting out a plurality of metal wires via bonding, in which a middle part of each of the plurality of metal wires is bent to be higher than a predetermined height, and two ends of each of the plurality of metal wires are respectively electrically connected to two of the plurality of bonding pads; (C) packing a molding layer on the chip to cover at least a part of the plurality of metal wires, the molding layer being higher than the predetermined height; (D) slicing the molding layer from the place of the predetermined height and cutting out the plurality of metal wires to expose two upper breakpoints of each of the plurality of metal wires; and (E) attaching a substrate, disposed in advance with a plurality of circuit contacts, onto the molding layer, wherein the plurality of circuit contacts are correspondingly electrically coupled to the upper breakpoints of the plurality of metal wires, respectively. Thus, according to the manufacturing method of the invention, it is capable of shortening the length of the metal wires in the internal part of the chip packaging structure so as to raise the transmission speed, save cost, and reduce the volume of the chip packaging body.
  • [0009]
    The manufacturing method of the invention further comprises a step (D1) after the step (D), i.e. forming a plurality of metal pads on the molding layer, the plurality of metal pads being respectively corresponding to the upper breakpoints of the plurality of metal wires, wherein in the step (E), the plurality of circuit contacts of the substrate are respectively electrically connected to the upper breakpoints of the plurality of metal wires through the plurality of metal pads. The metal pads of the invention not only can enlarge the electrically contacting size, but also can provide attaching the substrate to the molding layer. In addition, the step in (D1) of forming a plurality of metal pads on the molding layer includes formation by way of passing a tin slot.
  • [0010]
    Preferably, in the step (A) of the invention, a lower surface of the chip is mounted on a carrier board. Functionally, the carrier board is able to facilitate the proceeding of the packaging process, other than protecting the chip. Further, the step in (D) of slicing the molding layer is at least selected from a group formed by laser cutting, diamond knife cutting and grinding wheel cutting. Furthermore, the invention further comprises a step (F) after the step (E), i.e. forming a plurality of ball pads on the upper surface of the substrate, the plurality of ball pads being respectively electrically coupled to the plurality of circuit contacts. That is, the packaging structure of the invention may be a packaging structure of a ball grid array.
  • [0011]
    A further object of the present invention is to provide a chip packaging structure, comprising a chip, at least a metal wire, a molding layer and a substrate. The chip includes an upper surface and a lower surface, the upper surface being provided with at least a bonding pad The at least a metal wire includes a first end and a second end, the first end being electrically connected to the at least a bonding pad of the chip. The molding layer is packaged to cover the chip and the at least a metal wire, the second end of the at least a metal wire being exposed to an upper surface of the molding layer. The substrate is attached onto the upper surface of the molding layer, a lower surface of the substrate including at least a circuit contact, which is correspondingly electrically coupled to the second end of the at least a metal wire. Thus, the chip packaging structure of the invention is capable of shortening the length of the metal wires in the internal part of the chip packaging structure so as to raise the transmission speed, save cost of the metal wires, and reduce the volume of the chip packaging body.
  • [0012]
    In addition, the chip packaging structure of the invention further comprises a carrier board, the lower surface of the chip being mounted on the carrier board. Functionally, the carrier board is able to facilitate the proceeding of the packaging process, other than protecting the chip. The chip packaging structure of the invention further comprises a fastening layer for fastening between the lower surface of the chip and the carrier board. The fastening layer is mainly for use in attaching the chip onto the carrier board. Further, in the chip packaging structure of the invention, the upper surface of the molding layer further comprises at least a metal pad, and the at least a circuit contact of the substrate is electrically connected to the second end of the at least a metal wire through the at least a metal pad. The metal pad of the invention not only can enlarge the size of the electrical contacting, but also can provide attaching the substrate to the molding layer. The at least a metal pad includes a tin-plated pad.
  • [0013]
    Furthermore, in the chip packaging structure of the invention, the lower surface of the substrate is further convexly provided with at least a leg pad, and the at least a circuit contact is electrically connected to the second end of the at least a metal wire through the at least a leg pad. The leg pad of the invention is mainly for use in enlarging the electrically contacting size. In addition, the invention further comprises an attaching layer, which is attached between the upper surface of the molding layer and the lower surface of the substrate, while not overlaying the at least a leg pad. The attaching layer is mainly to attach the molding layer and the substrate. Preferably, the upper surface of the substrate further comprises at least a ball pad, which is electrically coupled to the at least a circuit contact. That is, the packaging structure of the invention may be a packaging structure of a ball grid array.
  • [0014]
    Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0015]
    FIG. 1 is a cross-sectional diagram of a conventional chip packaging structure;
  • [0016]
    FIGS. 2A-2F are cross-sectional diagrams of a preferred embodiment of the invention;
  • [0017]
    FIG. 3 is a flow chart of a preferred embodiment of the invention;
  • [0018]
    FIG. 4 is a cross-sectional diagram of a first preferred embodiment of the invention; and
  • [0019]
    FIG. 5 is a cross-sectional diagram of a second preferred embodiment of the invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • [0020]
    Please refer to FIGS. 2A to 2F together with FIG. 3. FIGS. 2A-2F are cross-sectional diagrams of each step for a chip packaging method of a preferred embodiment of the invention, and FIG. 3 is a flow chart of a preferred embodiment of the invention. Firstly, as shown in FIG. 2A, a chip 2 is provided, a plurality of bonding pads 211 are provided on an upper surface 21 thereof and a lower surface 22 of the chip 2 is mounted on a carrier board 3 (step A in FIG. 3). However, the carrier board 3 may be added in dependence of the condition or need and is mainly used for protecting the chip 2, while facilitating the proceeding of the packaging process.
  • [0021]
    Next, as shown in FIG. 2B, a plurality of metal wires 5 are connected out via bonding (step B in FIG. 3), and a middle part of each of the plurality of metal wires 5 is bent to be higher than a predetermined height H, in which two ends of each of the plurality of metal wires 5 are respectively electrically connected to two of the plurality of bonding pads 211. That is, each of the two of the plurality of bonding pads 211 provided on the upper surface 21 of the chip 2 is electrically connected via one of the plurality of metal wires 5 and each of the plurality of metal wires 5 is extending upward to be higher than a predetermined height H and bent in a middle part. After that, as shown in FIG. 2C, a molding layer 4 is packed on the chip 2 to cover at least a part of the plurality of metal wires 5, in which the molding layer 4 is higher than the predetermined height H (step C in FIG. 3).
  • [0022]
    Further, as shown in FIG. 2D, the molding layer 4 is sliced from the place of the predetermined height H and the plurality of metal wires 5 are cut out simultaneously to expose two upper breakpoints 53,54 of each of the plurality of metal wires 5 (step D in FIG. 3). In the embodiment, it is performed by diamond knife cutting. Of course, laser cutting or grinding wheel cutting may be used as well. Later, as shown in FIG. 2E, a plurality of metal pads 411 are formed on the molding layer 4 (step D1 in FIG. 3), in which the plurality of metal pads 411 are respectively corresponding to the upper breakpoints 53,54 of the plurality of metal wires 5. In the embodiment, forming a plurality of metal pads 411 may be processed by way of passing a tin slot.
  • [0023]
    And then, as shown in FIG. 2F, a substrate 6, disposed in advance with a plurality of circuit contacts 61, is attached onto the molding layer 4 (step E in FIG. 3), in which the plurality of circuit contacts 61 are respectively electrically coupled to the upper breakpoints 53,54 of the plurality of metal wires 5 through the plurality of metal pads 411. In the mean time, by way of overlaying the plurality of metal pads 411, just passing through a tin slot and being in a melted state, directly onto the substrate 6 and the molding layer 4, the effect of attaching is produced after cooling and curing.
  • [0024]
    Based on this, the metal pads 411 of the embodiment are mainly used not only to enlarge the electrically contacting size and avoid that the metal wires 5 are too thin to correspondingly electrical contact with the circuit contacts 61, but also to provide attaching the substrate 6 to the molding layer 4. Lastly, a plurality of ball pads 631 are formed on the upper surface 63 of the substrate 6, in which the plurality of ball pads 631 are respectively electrically coupled to the plurality of circuit contacts 61 (step F in FIG. 3). That is, the packaging structure of the embodiment is a packaging structure of a ball grid array.
  • [0025]
    Please refer to FIG. 4. FIG. 4 is a cross-sectional diagram of a first preferred embodiment of the invention. As shown, the invention comprises a chip 2, including an upper surface 21 and a lower surface 22, in which the upper surface 21 are provided with a plurality of bonding pads 211. The lower surface 22 are provided with a carrier board 3, in which the lower surface 22 of the chip 2 is mounted on the carrier board 3 through a fastening layer 31. The carrier board 3 is mainly used to protect the chip 2, while facilitating the proceeding of the whole packaging process. In addition, the drawing shows a plurality of metal wires 5 and each of the plurality of metal wires 5 includes a first end 51 and a second end 52, in which the first end 51 of each metal wire 5 is electrically connected to a bonding pad 211 of the chip 2.
  • [0026]
    Further, FIG. 4 shows a molding layer 4, which is packaged to cover the chip 2 and the plurality of metal wires 5. Moreover, the second end 52 of each metal wire 5 is exposed to an upper surface 41 of the molding layer 4. The upper surface 41 of the molding layer 4 further comprises a plurality of metal pads 411, and each of the plurality of metal pads 411 is electrically connected to the second end 52 of the metal wire 5. In this embodiment, each of the plurality of metal pads 411 is a tin-plated pad, which may be formed by passing through a tin slot. On the other hand, the substrate 6 is attached onto the upper surface 41 of the molding layer 4, which is processed through attaching of the Metal pads 411 in a melted state and then curing and fastening after cooling according to this embodiment.
  • [0027]
    In addition, a lower surface 62 of the substrate 6 includes a plurality of circuit contacts 61 and each of the plurality of circuit contacts 61 is correspondingly electrically coupled to the second end 52 of the metal wire 5. Thus, the metal pads 411 of the embodiment not only can enlarge the contacting size of the electrical coupling, but also can provide the attaching effect, i.e. fastening the substrate 6 onto the molding layer 4. Still further, the drawing shows that the upper surface 63 of the substrate 6 further comprises a plurality of ball pads 631 and each of the plurality of ball pads 631 is electrically coupled to one circuit contact 61. That is, the packaging structure of the embodiment may be a packaging structure of a ball grid array.
  • [0028]
    Please refer to FIG. 5. FIG. 5 is a cross-sectional diagram of a chip packaging structure a second preferred embodiment of the invention. This embodiment mainly differs from the first preferred embodiment in that in this embodiment, the lower surface 62 of the substrate 6 is convexly provided with a plurality of leg pads, and each circuit contact 61 is electrically connected to the second end 52 of one metal wire 5 through one leg pad 621. In addition, an attaching layer 64 is additionally painted to attach the substrate 6 onto the molding layer 4, in which the attaching layer 64 is attached between the upper surface of the molding layer 4 and the lower surface 62 of the substrate 6, while not overlaying the plurality of leg pads 621.
  • [0029]
    Although the present invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the scope of the invention as hereinafter claimed.

Claims (14)

  1. 1. A chip packaging method, comprising the following steps:
    (A) providing a chip, a plurality of bonding pads being provided on an upper surface thereof;
    (B) connecting out a plurality of metal wires via bonding, in which a middle part of each of the plurality of metal wires is bent to be higher than a predetermined height, and two ends of each of the plurality of metal wires are respectively electrically connected to two of the plurality of bonding pads;
    (C) packing a molding layer on the chip to cover at least a part of the plurality of metal wires, the molding layer being higher than the predetermined height;
    (D) slicing the molding layer from the place of the predetermined height and cutting out the plurality of metal wires to expose two upper breakpoints of each of the plurality of metal wires; and
    (E) attaching a substrate, disposed in advance with a plurality of circuit contacts, onto the molding layer, wherein the plurality of circuit contacts are correspondingly electrically coupled to the upper breakpoints of the plurality of metal wires, respectively.
  2. 2. The chip packaging method as claimed in claim 1, wherein in the step (A), a lower surface of the chip is mounted on a carrier board.
  3. 3. The chip packaging method as claimed in claim 1, further comprising a step after the step (D):
    (D1) forming a plurality of metal pads on the molding layer, the plurality of metal pads being respectively corresponding to the upper breakpoints of the plurality of metal wires;
    wherein in the step (E), the plurality of circuit contacts of the substrate are respectively electrically connected to the upper breakpoints of the plurality of metal wires through the plurality of metal pads.
  4. 4. The chip packaging method as claimed in claim 3, wherein the step in (D1) of forming a plurality of metal pads on the molding layer includes formation by way of passing a tin slot.
  5. 5. The chip packaging method as claimed in claim 1, wherein the step in (D) of slicing the molding layer is at least selected from a group formed by laser cutting, diamond knife cutting and grinding wheel cutting.
  6. 6. The chip packaging method as claimed in claim 1, further comprising a step after the step (E):
    (F) forming a plurality of ball pads on the upper surface of the substrate, the plurality of ball pads being respectively electrically coupled to the plurality of circuit contacts.
  7. 7. A chip packaging structure, comprising:
    a chip, including an upper surface and a lower surface, the upper surface being provided with at least a bonding pad;
    at least a metal wire, including a first end and a second end, the first end being electrically connected to the at least a bonding pad of the chip;
    a molding layer, being packaged to cover the chip and the at least a metal wire, the second end of the at least a metal wire being exposed to an upper surface of the molding layer; and
    a substrate, attaching onto the upper surface of the molding layer, a lower surface of the substrate including at least a circuit contact, which is correspondingly electrically coupled to the second end of the at least a metal wire.
  8. 8. The chip packaging structure as claimed in claim 7, further comprising a carrier board, the lower surface of the chip being mounted on the carrier board.
  9. 9. The chip packaging structure as claimed in claim 8, further comprising a fastening layer for fastening between the lower surface of the chip and the carrier board.
  10. 10. The chip packaging structure as claimed in claim 7, wherein the upper surface of the molding layer further comprises at least a metal pad, and the at least a circuit contact of the substrate is electrically connected to the second end of the at least a metal wire through the at least a metal pad.
  11. 11. The chip packaging structure as claimed in claim 10, wherein the at least a metal pad includes a tin-plated pad.
  12. 12. The chip packaging structure as claimed in claim 7, wherein the lower surface of the substrate is further convexly provided with a leg pad, and the at least a circuit contact is electrically connected to the second end of the at least a metal wire through the at least a leg pad.
  13. 13. The chip packaging structure as claimed in claim 12, further comprising an attaching layer, which is attached between the upper surface of the molding layer and the lower surface of the substrate, while not overlaying the at least a leg pad.
  14. 14. The chip packaging structure as claimed in claim 7, wherein the upper surface of the substrate further comprises a ball pad, which is electrically coupled to the at least a circuit contact.
US12585323 2009-06-15 2009-09-11 Chip packaging method and structure thereof Abandoned US20100314748A1 (en)

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