US20100298900A1 - Cardiac pacemaker with table-based pacing mode implementation - Google Patents

Cardiac pacemaker with table-based pacing mode implementation Download PDF

Info

Publication number
US20100298900A1
US20100298900A1 US12848894 US84889410A US2010298900A1 US 20100298900 A1 US20100298900 A1 US 20100298900A1 US 12848894 US12848894 US 12848894 US 84889410 A US84889410 A US 84889410A US 2010298900 A1 US2010298900 A1 US 2010298900A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
pacing
brady
device
ram
word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12848894
Inventor
David W. Yost
Doug M. Birkholz
James A. Esler
Original Assignee
Yost David W
Birkholz Doug M
Esler James A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • AHUMAN NECESSITIES
    • A61MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61NELECTROTHERAPY; MAGNETOTHERAPY; RADIATION THERAPY; ULTRASOUND THERAPY
    • A61N1/00Electrotherapy; Circuits therefor
    • A61N1/18Applying electric currents by contact electrodes
    • A61N1/32Applying electric currents by contact electrodes alternating or intermittent currents
    • A61N1/36Applying electric currents by contact electrodes alternating or intermittent currents for stimulation
    • A61N1/362Heart stimulators

Abstract

A device and method for implementing a bradycardia pacing mode are disclosed which is mostly hardware-based but still allows the flexibility for making major changes in brady behavior normally found only in firmware-based implementations. The brady behavior of the device is encapsulated by a table in an area of RAM referred to as brady RAM, and the brady behavior can be changed by re-loading the brady RAM with a different table.

Description

    CLAIM OF PRIORITY
  • [0001]
    This application is a divisional of and claims the benefit of priority under 35 U.S.C. §120 to U.S. patent application Ser. No. 11/116,596, filed on Apr. 28, 2005, which is hereby incorporated by reference herein in its entirety.
  • FIELD OF THE INVENTION
  • [0002]
    This invention pertains generally to the field of cardiac pacemakers and implantable cardioverter/defibrillators incorporating a pacing function. In particular, the invention relates to the hardware and software used to control the operation of such devices.
  • BACKGROUND
  • [0003]
    It is now common for patients having disorders of cardiac rhythm to be treated with implantable pacemakers that provide electrical stimulation to selected chambers of the heart in the form of timed pacing pulses. The most common condition for which pacemakers are used is in the treatment of bradycardia, where the ventricular rate is too slow. Atrio-ventricular conduction defects (i.e., AV block) that are permanent or intermittent and sick sinus syndrome represent the most common causes of bradycardia for which permanent pacing may be indicated. If functioning properly, the pacemaker makes up for the heart's inability to pace itself at an appropriate rhythm in order to meet metabolic demand by enforcing a minimum heart rate and/or artificially restoring AV conduction. Pacing therapy delivered in this manner is referred to as bradycardia or “brady” pacing. Particular bradycardia pacing modes determine how the pacing pulses are delivered in response to sensed cardiac events and lapsed time intervals. Pacing therapy may also be delivered using a bradycardia pacing mode for the purpose of restoring synchronous ventricular contractions in patients with inter-ventricular or intra-ventricular conduction disorders, termed cardiac resynchronization therapy.
  • [0004]
    The earliest pacemakers were hardware-based devices in which pacing decisions were made by logic circuits implemented in hardware. Most cardiac pacemakers today, however, (including implantable cardioverter/defibrillators with pacing capability) are microprocessor-based systems in which software (a.k.a. firmware, as the term is used here) run by a microprocessor commands the generation of pacing outputs, with various timers being used to alert the microprocessor as to when to pace. Such firmware-based systems exhibit great flexibility, as compared with a pacemaker implemented with dedicated hardware, since the behavior of the device can be changed simply by reprogramming the microprocessor. Controlling the delivery of paces with a firmware-based system, however, also has some disadvantages. If the microprocessor continually executes instructions during the cardiac cycle in order to process and respond to timing and sensing events, a large amount of battery power is consumed. Also, making pacing decisions with software inevitably introduces some variability into the timing of the paces, commonly referred to as pacing jitter.
  • SUMMARY
  • [0005]
    In the approach described herein, a bradycardia pacing mode is implemented using a brady table which maps particular device states, as defined by the occurrence of sensed events and the states of timers, to particular device actions such as the delivery of pacing pulses and the resetting or stopping of timers. Hardware-based circuitry compares the current state of the device to the device states contained in the brady table. If the current device state matches a table device state, the circuitry performs the actions to which the table device state is mapped. The brady table may be stored in an area of RAM, referred to as the brady RAM, which can be accessed by a microprocessor as well as the hardware-based circuitry. Device behavior may thus be easily changed by loading a different brady table into the brady RAM.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0006]
    FIG. 1 is a system diagram of an implantable pacemaker.
  • [0007]
    FIG. 2 illustrates hardware for implementing a pacing mode with a brady table.
  • [0008]
    FIG. 3 illustrates an exemplary bradycardia pacing mode.
  • [0009]
    FIG. 4 illustrates an example of action and condition word construction.
  • [0010]
    FIG. 5 illustrates exemplary action and condition word pairs for implementing a bradycardia pacing mode.
  • DETAILED DESCRIPTION
  • [0011]
    Described herein is a device and method for implementing a bradycardia pacing mode which allows for a low power implementation that is mostly hardware-based but still allows the flexibility for making major changes in brady behavior normally found only in firmware-based implementations. The brady behavior of the device is encapsulated by a RAM-based table in an area of RAM referred to as brady RAM, and the brady behavior can be changed by re-loading the brady RAM with a different table. Firmware executed by a microprocessor may load the table based on the brady mode desired. Hardware then reads the table only when pacing decisions need to be made, and uses the information in the table to make brady decisions. The design may be easily extended to more complicated pacing modes by making the RAM larger. Because hardware rather than firmware decides when to pace, there is no latency in pace delivery, and no jitter in the cycle length. The device may also utilize a FIFO queue in an area of the brady RAM or elsewhere in which either hardware or firmware may record particular events along with a timestamp for latter retrieval and analysis. The RAM based brady table may be used to define which brady events the hardware will put in a FIFO. Firmware can also place any event in the FIFO, where such events may be unrelated to brady events. The FIFO queue eases the task of keeping events in chronological order when both hardware and firmware are recording events.
  • [0012]
    Set forth below are descriptions of an exemplary implantable device and hardware for implementing a bradycardia pacing mode in the manner just described. An exemplary implementation of a pacing mode using a brady table is also given.
  • 1. Implantable Device Description
  • [0013]
    An implantable pacemaker includes a housing containing electronic circuitry and one or more electrodes in electrical contact with the myocardium used for sensing and pacing the heart. The housing is usually implanted subcutaneously on the patient's chest, and is connected to the electrodes by leads threaded through the vessels of the upper venous system into the heart. The electronic circuitry contained within the housing includes a battery, circuitry for generating pacing pulses, circuitry for interpreting electrogram signals representing cardiac electrical activity, and logic circuitry for operating the pacemaker in a number of programmed pacing modes where a pacing mode defines how pacing pulses are output in response to particular sensed events and the expiration of particular defined time intervals. Telemetry circuitry is usually also provided to enable communication with an external programmer that can interrogate the pacemaker and receive stored data as well as directly adjust the operating parameters of the pacemaker after implantation.
  • [0014]
    An electrode can be incorporated into a sensing channel that generates an electrogram signal representing cardiac electrical activity at the electrode site and/or incorporated into a pacing channel for delivering pacing pulses to the site. A pacing channel includes a pulse generator connected to an electrode while a sensing channel includes a sense amplifier connected to an electrode and a comparator circuit for comparing the electrogram signal to a specified threshold value. The sensing circuitry of the device generates atrial and ventricular electrogram signals from the voltages sensed by the electrodes of a particular channel. An electrogram is analogous to a surface EKG and indicates the time course and amplitude of cardiac depolarization and repolarization that occurs during either an intrinsic or paced beat. When an electrogram signal in an atrial or ventricular sensing channel exceeds a specified threshold (e.g., as determined by a comparator) the sensing circuitry detects an atrial or ventricular sense, respectively, which pacing algorithms may employ to trigger or inhibit pacing. Sensing and/or pacing channels may be configured as either atrial or ventricular channels allowing the device to deliver conventional ventricular single-site pacing with or without atrial tracking, biventricular pacing, or multi-site pacing of a single chamber.
  • 2. Bradycardia Pacing Modes
  • [0015]
    Bradycardia pacing modes refer to pacing algorithms which are used to pace the atria and/or ventricles in a manner that enforces a certain minimum heart rate or restores AV conduction. Because of the risk of inducing an arrhythmia with asynchronous pacing, most pacemakers for treating bradycardia are programmed to operate synchronously in a so-called demand mode where sensed cardiac events occurring within a defined interval either trigger or inhibit a pacing pulse. In a triggered mode, a sense occurring in one heart chamber triggers a pace to either the same or a different heart chamber Inhibited demand pacing modes utilize escape intervals to control pacing in accordance with sensed intrinsic activity. In an inhibited demand mode, a pacing pulse is delivered to a heart chamber during a cardiac cycle only after expiration of a defined escape interval during which no intrinsic beat by the chamber is detected. For example, a ventricular escape interval for pacing the ventricles can be defined between ventricular events, referred to as the cardiac cycle (CC) interval with its inverse being the lower rate limit or LRL. The CC interval is restarted with each ventricular sense or pace. An atrial escape interval can also be defined for pacing the atria either alone or in addition to pacing the ventricles which starts with a ventricular sense or pace and is referred to as the ventriculo-atrial interval or VAI. In atrial tracking and AV sequential pacing modes, another ventricular escape interval is defined between atrial and ventricular events, referred to as the atrio-ventricular pacing delay interval or AVI, where a ventricular pacing pulse is delivered upon expiration of the atrio-ventricular pacing delay interval if no ventricular sense occurs before. In an atrial tracking mode, the atrio-ventricular pacing delay interval is triggered by an atrial sense and stopped by a ventricular sense or pace. In an AV sequential pacing mode, the atrio-ventricular delay interval is triggered by an atrial pace and stopped by a ventricular sense or pace. Atrial tracking and AV sequential pacing are commonly combined so that an AVI starts with either an atrial pace or sense.
  • [0016]
    Cardiac resynchronization therapy is pacing stimulation applied to one or more heart chambers in a manner that compensates for conduction delays and is most conveniently delivered in conjunction with a bradycardia pacing mode. Ventricular resynchronization pacing is useful in treating heart failure in patients with interventricular or intraventricular conduction defects because, although not directly inotropic, resynchronization results in a more coordinated contraction of the ventricles with improved pumping efficiency and increased cardiac output. Ventricular resynchronization can be achieved in certain patients by pacing at a single unconventional site, such as the left ventricle instead of the right ventricle in patients with left ventricular conduction defects. Resynchronization pacing may also involve biventricular pacing with the paces to right and left ventricles delivered either simultaneously or sequentially, with the interval between the paces termed the biventricular delay (BVD) interval (also sometimes referred to as the VV delay). The BVD interval may be zero in order to pace both ventricles simultaneously, or non-zero in order to pace the left and right ventricles sequentially. In an example biventricular resynchronization pacing mode, right atrial paces and senses trigger an AVI which upon expiration results in a pace to one of the ventricles and which is stopped by a right ventricular sense. The contralateral ventricular pace is delivered at the specified BVD interval with respect to expiration of the AVI.
  • [0017]
    Another aspect of bradycardia pacing modes involves the use of timer-defined refractory periods for the sensing channels. In order to prevent cross-talk between sensing channels and other types of false sensing, certain events may cause a sensing channel to be rendered refractory for specified period time during which sensed events may be ignored for purposes of the pacing algorithm, interpreted as noise, or only used for other purposes such as tachyarrhythmia detection. A refractory period is initiated when a particular event starts a timer which defines the refractory period and is terminated upon expiration of the timer. Sensing channels are commonly rendered refractory for a period of time upon occurrence of a sense or pace in the same or different channel. One well-known example of a cross-chamber refractory period is the post-ventricular atrial refractory period or PVARP which renders the atrial sensing channel refractory for a period of time following a ventricular sense or pace in order to prevent pacemaker mediated tachycardia.
  • 3. Electronic Circuitry for Implementing Bradycardia Pacing
  • [0018]
    FIG. 1 is a system diagram of the electronic components contained within the pacemaker housing which are used to implement a pacing mode by causing the delivery of paces in response to sensed cardiac events and lapsed time intervals. A microprocessor 10 communicates with a system RAM 12 and a system ROM 13 for containing data and programmed instructions over a bidirectional system address and data bus 17. Telemetry circuitry 11 is also interfaced to the bus enabling communication between the microprocessor and an external programmer. The microprocessor 10 controls the overall operation of the device in accordance with programmed instructions stored in memory. In most pacemaker designs being used at the present time, instructions executed by a microprocessor are also responsible for implementing the pacing mode by making pacing decisions based the outputs of timers and sensing circuitry in what may be termed a firmware-based implementation. In the presently described approach, on the other hand, the pacing algorithm is encapsulated by a brady table which maps particular device states, as defined by the occurrence of sensed events and the states of timers, to particular device actions such as the delivery of pacing pulses and the resetting or stopping of timers. Hardware-based circuitry driven by a clock signal compares the current state of the device to the device states contained in the brady table. If the current device state matches a table device state, the circuitry performs the actions to which the table device state is mapped. The brady table may be stored in an area of RAM, referred to as the brady RAM, which can also be accessed by the microprocessor. Device behavior may thus be easily changed by loading a different brady table into the brady RAM. This approach thus obtains the advantages of hardware driven pacing, namely, low power and timing stability, but offers a flexibility similar to that of firmware-based pacing implementations. FIG. 1 illustrates a brady RAM 14 and brady RAM controller 15 interfaced to the bus 17. When enabled by the microprocessor, the brady RAM controller 14 sequentially accesses the table device states and associated actions contained in the brady RAM. The brady RAM 14 is interfaced to pacing and sensing hardware 16 which includes the sensing and pacing channels of the device and hardware timers for defining escape intervals and refractory periods. Logic circuitry associated with the brady RAM 14 includes circuitry for comparing the current state of the device with the table device states and for causing the device actions contained in the brady table to be performed by the hardware 16.
  • [0019]
    FIG. 2 illustrates the operation of the brady RAM-based pacing circuitry in more detail according to one particular embodiment. The brady RAM is shown as being divided into a brady RAM 14 a which contains a set of condition words and a brady RAM 14 b which contains an action word corresponding to each condition word. Each condition word represents a particular device state according to whether particular bits of the word are set or cleared, and each action word represents particular actions which can be performed by the device according to whether particular bits of the word are set or cleared. In other words, each bit of a condition word may represent the state of a particular timer or whether a particular sensed event has occurred, and each bit of an action word may represent a timer input or delivery of a pace through a particular pacing channel. When enabled by the microprocessor 10, the brady RAM controller 15 accesses the brady RAM by asserting the address of a condition word to the brady RAM 14 a and the address of the corresponding action word to brady RAM 14 b. When the brady RAM controller 15 is enabled, the microprocessor also actuates a plurality of solid state switches SW which isolate the brady RAM 14 a and 14 b from the system address and data bus 17. The switches SW block the system address bus and pass the address outputs of the brady RAM controller to the brady RAM when the brady RAM controller is operating, and vice-versa when the microprocessor 10 is accessing the brady RAM. Similarly, the data bits of both brady RAM 14 a and 14 b are also isolated from the system data bus 17 by switches SW when the brady RAM controller is operating, and vice-versa when the microprocessor is reading or writing to the brady RAM.
  • [0020]
    The current state of the device is represented by a set of timer outputs 21 (i.e., timer states such as running, stopped, or expired), a set of state register outputs 22 which may define certain behaviors, and a set of sensing comparator outputs 23. The state register outputs may define any type of detected condition or event which can be used to affect device behavior (e.g., detection of a noisy condition in a particular sensing channel). Together, these outputs may be thought of as a current status word. The condition words in the brady RAM 14 a are constructed with a bit-by-bit correspondence to the outputs of the current status word. The actions which may be taken by the device in implementing a bradycardia pacing mode are represented by a set of action inputs which may include timer inputs 24 (e.g., starting or resetting, stopping, or disabling a particular timer), a set of state register inputs 25 which cause the contents of the state registers to change, and a set of pacing pulse generator inputs 26 which cause delivery of paces to particular pacing electrodes. An action input may also be provided for causing a particular event represented in the current status word to be stored in a FIFO queue along with a time stamp. The FIFO queue may be located in the brady RAM or elsewhere. The action words in the brady RAM 14 b are constructed with a bit-by-bit correspondence to the set of available action inputs.
  • [0021]
    The operation of the brady hardware starts when the brady RAM controller 15 is enabled. In this embodiment, the operation of the brady RAM controller is triggered by a change in device status. When a bit of the current status word changes as detected by state change detector 27, the brady RAM controller begins to sequence through each condition word in the brady table by sequentially asserting the address of each condition word to the brady RAM 14 a and the address of the corresponding action word to brady RAM 14 b. A signal derived from the system clock CLK drives the brady RAM controller at an appropriate frequency to cause the addresses of the condition and actions words to be asserted in sequence. As the address of a condition word is asserted, the data bits of the condition word are output from the brady RAM 14 a. In this embodiment, a set bit (i.e., a one) in the condition word signifies a particular timer state or sensing comparator output which defines a particular device state, and a cleared bit (i.e., a zero) signifies that a particular timer state or sensing comparator output does not matter in defining the particular device state. In order to evaluate whether a device state defined by a condition word matches the current device state, the condition word is passed to a multi-bit AND gate AG1 where the condition word is ANDed with the current status word. The output of the gate AG1 is then compared with the condition word by a multi-bit comparator CMP. If the condition word represents the current state of the device, the output of comparator CMP is asserted which enables the multi-bit buffer B1. The data bits of the corresponding action word in the brady RAM 14 b which are addressed by the brady RAM controller are then passed to the set of action inputs to cause the actions specified by the action word. After all of the condition words are evaluated in this manner, the brady RAM controller waits for another change in the device state and then repeats the sequence.
  • 4. Example Pacing Mode Implementation
  • [0022]
    The brady RAM-based circuitry described above may be configured to implement any pacing mode where paces are delivered in accordance with defined timer states and sensed events. By way of example, what follows is a description of a simplified atrial and ventricular pacing mode and how that pacing mode is implemented in the brady RAM as condition words and corresponding action words.
  • [0023]
    FIG. 3 illustrates a particular DDD pacing algorithm as steps S1 through S7. Two escape intervals are defined: an AVI started by an atrial sense or pace which upon expiration results in a ventricular pace, and a VAI started by a ventricular sense or pace which upon expiration results in an atrial pace. Only one refractory period is defined, a PVARP, which is started by a ventricular sense or pace and which renders the atrial sensing channel refractory for its duration.
  • [0024]
    FIG. 4 shows how the timer states, sensed events, and device actions of the pacing algorithm illustrated by FIG. 3 are encoded as condition words and action words. A condition word has five bits numbered 1 through 5 which, if set, represent AVI expiration, VAI expiration, a ventricular sense, an atrial sense, and PVARP expiration, respectively. An action word also has five bits numbered 1 through 5 which, if set, represent a ventricular pace, an atrial pace, resetting (i.e., restarting) the AVI, resetting the VAI, and resetting the PVARP, respectively.
  • [0025]
    FIG. 5 shows how different condition words may be associated with different action words in a brady table in order to implement the pacing algorithm illustrated by FIG. 3. The implementation requires four condition/action word pairs which map different device states to different device actions. The first pair results in a ventricular pace being delivered if the AVI is expired regardless of what else is included in the current status word. The VAI and PVARP are also reset. The second pair causes resetting of the VAI and PVARP when a ventricular sense occurs. The third pair causes delivery of an atrial pace and resetting of the AVI when the VAI expires. The fourth pair shows that an atrial sense causes resetting of the AVI only if the PVARP is also expired. This latter behavior may alternatively be interpreted as not generating an atrial sense if the PVARP is unexpired.
  • [0026]
    Although the invention has been described in conjunction with the foregoing specific embodiments, many alternatives, variations, and modifications will be apparent to those of ordinary skill in the art. Such alternatives, variations, and modifications are intended to fall within the scope of the following appended claims.

Claims (20)

  1. 1. A method for operating a cardiac pacemaker, comprising:
    sensing cardiac events;
    detecting states of one or more timers;
    mapping particular device states defined by timer states and/or sensed events to associated device actions which include pacing pulse delivery in accordance with a bradycardia pacing mode and/or changes in timer states in a brady table contained in a brady RAM; and,
    comparing current timer states and sensed events to a device state contained in the brady table and, if found to match, causing performance of the associated device action.
  2. 2. The method of claim 1 further comprising accessing the brady RAM by means of a microprocessor and reloading the brady RAM with a different brady table to modify the pacing mode.
  3. 3. The method of claim 1 wherein the brady table is made up of condition words representing particular device states and corresponding action words representing particular device actions.
  4. 4. The method of claim 3 wherein each condition word represents a particular device state according to whether particular bits of the word are set or cleared, and each action word represents particular actions which can be performed by the device according to whether particular bits of the word are set or cleared.
  5. 5. The method of claim 4 wherein the current state of the pacemaker is represented by a set of timer outputs and a set of sensing comparator outputs which form a current status word, and further wherein the condition words in the brady table are constructed with a bit-by-bit correspondence to the current status word.
  6. 6. The method of claim 4 wherein the actions which may be taken by the pacemaker in implementing a bradycardia pacing mode are represented by a set of action inputs which may include timer inputs and a set of pacing pulse generator inputs which cause delivery of paces to particular pacing electrodes, and further wherein the action words in the brady table are constructed with a bit-by-bit correspondence to the set of available action inputs.
  7. 7. The method of claim 6 wherein an action input is provided for causing a particular event represented in the current status word to be stored in a FIFO queue along with a time stamp.
  8. 8. The method of claim 4 further comprising sequentially comparing condition words with the current status word when a bit of the current status word changes as detected by a state change detector.
  9. 9. The method of claim 5 wherein the current status word further comprises one or more state register outputs which are used to affect device behavior.
  10. 10. The method of claim 9 wherein a state register output signifies detection of a noisy condition in a particular sensing channel.
  11. 11. A cardiac pacing device, comprising:
    means for sensing cardiac events;
    means for detecting states of one or more timers;
    means for mapping particular device states defined by timer states and/or sensed events to associated device actions which include pacing pulse delivery in accordance with a bradycardia pacing mode and/or changes in timer states in a brady table contained in a brady RAM; and,
    means for comparing current timer states and sensed events to a device state contained in the brady table and, if found to match, causing performance of the associated device action.
  12. 12. The device of claim 11 further comprising means for accessing the brady RAM with a microprocessor and reloading the brady RAM with a different brady table to modify the pacing mode.
  13. 13. The device of claim 11 wherein the brady table is made up of condition words representing particular device states and corresponding action words representing particular device actions.
  14. 14. The device of claim 13 wherein each condition word represents a particular device state according to whether particular bits of the word are set or cleared, and each action word represents particular actions which can be performed by the device according to whether particular bits of the word are set or cleared.
  15. 15. The device of claim 14 wherein the current state of the device is represented by a set of timer outputs and a set of sensing comparator outputs which form a current status word, and further wherein the condition words in the brady table are constructed with a bit-by-bit correspondence to the current status word.
  16. 16. The device of claim 14 wherein the actions which may be taken by the device in implementing a bradycardia pacing mode are represented by a set of action inputs which may include timer inputs and a set of pacing pulse generator inputs which cause delivery of paces to particular pacing electrodes, and further wherein the action words in the brady table are constructed with a bit-by-bit correspondence to the set of available action inputs.
  17. 17. The device of claim 16 wherein an action input is provided for causing a particular event represented in the current status word to be stored in a FIFO queue along with a time stamp.
  18. 18. The device of claim 14 further comprising means for sequentially comparing condition words with the current status word when a bit of the current status word changes as detected by a state change detector.
  19. 19. The device of claim 15 wherein the current status word further comprises one or more state register outputs which are used to affect device behavior.
  20. 20. The device of claim 19 further comprising a state register output that signifies detection of a noisy condition in a particular sensing channel.
US12848894 2005-04-28 2010-08-02 Cardiac pacemaker with table-based pacing mode implementation Abandoned US20100298900A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US11116596 US7769447B2 (en) 2005-04-28 2005-04-28 Cardiac pacemaker with table-based pacing mode implementation
US12848894 US20100298900A1 (en) 2005-04-28 2010-08-02 Cardiac pacemaker with table-based pacing mode implementation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12848894 US20100298900A1 (en) 2005-04-28 2010-08-02 Cardiac pacemaker with table-based pacing mode implementation

Publications (1)

Publication Number Publication Date
US20100298900A1 true true US20100298900A1 (en) 2010-11-25

Family

ID=37235473

Family Applications (2)

Application Number Title Priority Date Filing Date
US11116596 Active 2026-05-12 US7769447B2 (en) 2005-04-28 2005-04-28 Cardiac pacemaker with table-based pacing mode implementation
US12848894 Abandoned US20100298900A1 (en) 2005-04-28 2010-08-02 Cardiac pacemaker with table-based pacing mode implementation

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US11116596 Active 2026-05-12 US7769447B2 (en) 2005-04-28 2005-04-28 Cardiac pacemaker with table-based pacing mode implementation

Country Status (1)

Country Link
US (2) US7769447B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100234912A1 (en) * 2005-04-28 2010-09-16 Ternes David J Flexible neural stimulation engine

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7769447B2 (en) * 2005-04-28 2010-08-03 Cardiac Pacemakers, Inc. Cardiac pacemaker with table-based pacing mode implementation
US9645882B2 (en) * 2007-07-24 2017-05-09 The Regents Of The University Of Michigan Field repairable logic
US8060204B2 (en) * 2008-02-28 2011-11-15 Cardiac Pacemakers, Inc. Low power digital design for deep submicron technology

Citations (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4378020A (en) * 1981-08-20 1983-03-29 Telectronics Pty. Ltd. Dual chamber pacer
US4407288A (en) * 1981-02-18 1983-10-04 Mieczyslaw Mirowski Implantable heart stimulator and stimulation method
US4503857A (en) * 1981-10-26 1985-03-12 Vitatron Medical B.V. Programmable cardiac pacemaker with microprocessor control of pacer rate
US4554920A (en) * 1982-11-22 1985-11-26 Intermedics, Inc. Microprocessor controlled cardiac pacemaker and method for avoiding pacer sustained tachycardia
US4577633A (en) * 1984-03-28 1986-03-25 Medtronic, Inc. Rate scanning demand pacemaker and method for treatment of tachycardia
US4779617A (en) * 1986-10-06 1988-10-25 Telectronics N.V. Pacemaker noise rejection system
US4928688A (en) * 1989-01-23 1990-05-29 Mieczyslaw Mirowski Method and apparatus for treating hemodynamic disfunction
US5022395A (en) * 1989-07-07 1991-06-11 Cardiac Pacemakers, Inc. Implantable cardiac device with dual clock control of microprocessor
US5081987A (en) * 1989-03-13 1992-01-21 Siemens Aktiengesellschaft Implantable medical device for stimulating a physiological event of a living being with stimulation intensity adaptable to physical activity of the living being
US5085215A (en) * 1990-03-20 1992-02-04 Telectronics Pacing Systems, Inc. Metabolic demand driven rate-responsive pacemaker
US5103820A (en) * 1990-08-14 1992-04-14 Medtronic, Inc. VDD pacemaker with selectable post-ventricular atrial refractory periods
US5247930A (en) * 1992-02-04 1993-09-28 Vitatron Medical, B.V. Dual chamber pacing system with dynamic physiological tracking and method of timing delivered stimulus for optimized synchronous pacing
US5312450A (en) * 1992-05-01 1994-05-17 Medtronic, Inc. Pacemaker for terminating pacemaker-mediated tachycardia
US5360437A (en) * 1991-10-31 1994-11-01 Medtronic, Inc. Implantable medical device with flexible hardware platform
US5431691A (en) * 1992-03-02 1995-07-11 Siemens Pacesetter, Inc. Method and system for recording and displaying a sequential series of pacing events
US5545186A (en) * 1995-03-30 1996-08-13 Medtronic, Inc. Prioritized rule based method and apparatus for diagnosis and treatment of arrhythmias
US5643326A (en) * 1994-05-27 1997-07-01 Weiner; Henry L. Dual chamber pacing with atrial and ventricular independence
US5692907A (en) * 1995-08-16 1997-12-02 Pacesetter, Inc. Interactive cardiac rhythm simulator
US5725561A (en) * 1995-06-09 1998-03-10 Medtronic, Inc. Method and apparatus for variable rate cardiac stimulation
US5776168A (en) * 1996-04-03 1998-07-07 Medtronic, Inc. EGM recording system for implantable medical device
US5792203A (en) * 1997-08-18 1998-08-11 Sulzer Intermedics Inc. Universal programmable cardiac stimulation device
US5991659A (en) * 1998-09-30 1999-11-23 Vitatron Medical, B.V. Pacing system with full range sudden rate drop detection and responsive pacing intervention
US6129659A (en) * 1999-03-02 2000-10-10 Wilk; Bruce R. Cold therapy pad with magnetotherapy insert
US6366810B1 (en) * 1998-09-14 2002-04-02 Angeion Corporation Deterministic and jitter-free dual-chamber cardiac pacemaker
US6427084B2 (en) * 1999-08-23 2002-07-30 Cardiac Pacemakers, Inc. Multi-site hybrid hardware-based cardiac pacemaker
USRE38119E1 (en) * 1989-01-23 2003-05-20 Mirowski Family Ventures, LLC Method and apparatus for treating hemodynamic disfunction
US6931282B2 (en) * 2002-05-23 2005-08-16 Cardiac Pacemakers, Inc. Method to create pacemaker timing cycles
US7006872B2 (en) * 2001-04-27 2006-02-28 Medtronic, Inc. Closed loop neuromodulation for suppression of epileptic activity
US7047066B2 (en) * 2000-12-26 2006-05-16 Cardiac Pacemakers, Inc. Method and system for display of cardiac event intervals in a resynchronization pacemaker
US20060247708A1 (en) * 2005-04-28 2006-11-02 Cardiac Pacemakers, Inc. Cardiac pacemaker with table-based pacing mode implementation
US20070043398A1 (en) * 2005-04-28 2007-02-22 David Ternes Flexible neural stimulation engine

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5292340A (en) * 1993-01-04 1994-03-08 Telectronics Pacing Systems, Inc. Physiologically-calibrated rate adaptive, dual chamber pacemaker
US6026324A (en) * 1998-10-13 2000-02-15 Cardiac Pacemakers, Inc. Extraction of hemodynamic pulse pressure from fluid and myocardial accelerations
US6129745A (en) * 1998-10-23 2000-10-10 Medtronic, Inc. Medical device for automatic diagnosis of undersensing by timing

Patent Citations (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4407288B1 (en) * 1981-02-18 2000-09-19 Mieczyslaw Mirowski Implantable heart stimulator and stimulation method
US4407288A (en) * 1981-02-18 1983-10-04 Mieczyslaw Mirowski Implantable heart stimulator and stimulation method
US4378020A (en) * 1981-08-20 1983-03-29 Telectronics Pty. Ltd. Dual chamber pacer
US4503857A (en) * 1981-10-26 1985-03-12 Vitatron Medical B.V. Programmable cardiac pacemaker with microprocessor control of pacer rate
US4554920A (en) * 1982-11-22 1985-11-26 Intermedics, Inc. Microprocessor controlled cardiac pacemaker and method for avoiding pacer sustained tachycardia
US4577633A (en) * 1984-03-28 1986-03-25 Medtronic, Inc. Rate scanning demand pacemaker and method for treatment of tachycardia
US4779617A (en) * 1986-10-06 1988-10-25 Telectronics N.V. Pacemaker noise rejection system
US4928688A (en) * 1989-01-23 1990-05-29 Mieczyslaw Mirowski Method and apparatus for treating hemodynamic disfunction
USRE39897E1 (en) * 1989-01-23 2007-10-23 Mirowski Family Ventures, L.L.C. Method and apparatus for treating hemodynamic disfunction
USRE38119E1 (en) * 1989-01-23 2003-05-20 Mirowski Family Ventures, LLC Method and apparatus for treating hemodynamic disfunction
US5081987A (en) * 1989-03-13 1992-01-21 Siemens Aktiengesellschaft Implantable medical device for stimulating a physiological event of a living being with stimulation intensity adaptable to physical activity of the living being
US5022395A (en) * 1989-07-07 1991-06-11 Cardiac Pacemakers, Inc. Implantable cardiac device with dual clock control of microprocessor
US5085215A (en) * 1990-03-20 1992-02-04 Telectronics Pacing Systems, Inc. Metabolic demand driven rate-responsive pacemaker
US5103820A (en) * 1990-08-14 1992-04-14 Medtronic, Inc. VDD pacemaker with selectable post-ventricular atrial refractory periods
US5360437A (en) * 1991-10-31 1994-11-01 Medtronic, Inc. Implantable medical device with flexible hardware platform
US5247930A (en) * 1992-02-04 1993-09-28 Vitatron Medical, B.V. Dual chamber pacing system with dynamic physiological tracking and method of timing delivered stimulus for optimized synchronous pacing
US5431691A (en) * 1992-03-02 1995-07-11 Siemens Pacesetter, Inc. Method and system for recording and displaying a sequential series of pacing events
US5312450A (en) * 1992-05-01 1994-05-17 Medtronic, Inc. Pacemaker for terminating pacemaker-mediated tachycardia
US5643326A (en) * 1994-05-27 1997-07-01 Weiner; Henry L. Dual chamber pacing with atrial and ventricular independence
US5545186A (en) * 1995-03-30 1996-08-13 Medtronic, Inc. Prioritized rule based method and apparatus for diagnosis and treatment of arrhythmias
US5725561A (en) * 1995-06-09 1998-03-10 Medtronic, Inc. Method and apparatus for variable rate cardiac stimulation
US5692907A (en) * 1995-08-16 1997-12-02 Pacesetter, Inc. Interactive cardiac rhythm simulator
US5776168A (en) * 1996-04-03 1998-07-07 Medtronic, Inc. EGM recording system for implantable medical device
US5792203A (en) * 1997-08-18 1998-08-11 Sulzer Intermedics Inc. Universal programmable cardiac stimulation device
US6366810B1 (en) * 1998-09-14 2002-04-02 Angeion Corporation Deterministic and jitter-free dual-chamber cardiac pacemaker
US5991659A (en) * 1998-09-30 1999-11-23 Vitatron Medical, B.V. Pacing system with full range sudden rate drop detection and responsive pacing intervention
US6129659A (en) * 1999-03-02 2000-10-10 Wilk; Bruce R. Cold therapy pad with magnetotherapy insert
US6920355B2 (en) * 1999-08-23 2005-07-19 Cardiac Pacemakers, Inc. Multi-site hybrid hardware-based cardiac pacemaker
US6427084B2 (en) * 1999-08-23 2002-07-30 Cardiac Pacemakers, Inc. Multi-site hybrid hardware-based cardiac pacemaker
US7047066B2 (en) * 2000-12-26 2006-05-16 Cardiac Pacemakers, Inc. Method and system for display of cardiac event intervals in a resynchronization pacemaker
US7006872B2 (en) * 2001-04-27 2006-02-28 Medtronic, Inc. Closed loop neuromodulation for suppression of epileptic activity
US6931282B2 (en) * 2002-05-23 2005-08-16 Cardiac Pacemakers, Inc. Method to create pacemaker timing cycles
US20060247708A1 (en) * 2005-04-28 2006-11-02 Cardiac Pacemakers, Inc. Cardiac pacemaker with table-based pacing mode implementation
US20070043398A1 (en) * 2005-04-28 2007-02-22 David Ternes Flexible neural stimulation engine
US7751884B2 (en) * 2005-04-28 2010-07-06 Cardiac Pacemakers, Inc. Flexible neural stimulation engine
US7769447B2 (en) * 2005-04-28 2010-08-03 Cardiac Pacemakers, Inc. Cardiac pacemaker with table-based pacing mode implementation
US20100234912A1 (en) * 2005-04-28 2010-09-16 Ternes David J Flexible neural stimulation engine

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100234912A1 (en) * 2005-04-28 2010-09-16 Ternes David J Flexible neural stimulation engine
US8352029B2 (en) 2005-04-28 2013-01-08 Cardiac Pacemakers, Inc. Flexible neural stimulation engine

Also Published As

Publication number Publication date Type
US7769447B2 (en) 2010-08-03 grant
US20060247708A1 (en) 2006-11-02 application

Similar Documents

Publication Publication Date Title
US5983138A (en) Device and method for ventricular tracking and pacing
US6434428B1 (en) System and method for optimizing far-field R-wave sensing by switching electrode polarity during atrial capture verification
US6615083B2 (en) Implantable medical device system with sensor for hemodynamic stability and method of use
US6711439B1 (en) Evoked response variability as an indicator of autonomic tone and surrogate for patient condition
US6058326A (en) Method and apparatus for cardiac pacing in accordance with multiple pacing therapy features
US7130683B2 (en) Preferred ADI/R: a permanent pacing mode to eliminate ventricular pacing while maintaining back support
US6721598B1 (en) Coronary sinus cardiac lead for stimulating and sensing in the right and left heart and system
US6091986A (en) Method and apparatus for storage of physiologic signals
US6473645B1 (en) System and method for programmably controlling electrode activation sequence in a multi-site cardiac stimulation device
EP1629863B1 (en) System and method for determining optimal atrioventricular delay based on intrinsic conduction delays
US6473647B1 (en) Implantable cardiac stimulation device for and method of monitoring progression or regression of heart disease by monitoring evoked response features
US6480742B2 (en) Pace counter isolation for cardiac resynchronization pacing
US6965797B2 (en) Method and apparatus for assessing and treating myocardial wall stress
US20030078624A1 (en) Maximum atrial tracking rate for cardiac rhythm management system
US7020523B1 (en) Methods and systems for automatically switching electrode configurations
US6553258B2 (en) System and method for managing refractory periods in a cardiac rhythm management device with biventricular sensing
US6950701B2 (en) Dual-chamber pacemaker system for simultaneous bi-chamber pacing and sensing
US7555341B2 (en) System to treat AV-conducted ventricular tachyarrhythmia
US6240313B1 (en) Cardiac rhythm management system with prevention of double counting of events
US6477420B1 (en) Control of pacing rate in mode switching implantable medical devices
US5103820A (en) VDD pacemaker with selectable post-ventricular atrial refractory periods
US7386342B1 (en) Subcutaneous cardiac stimulation device providing anti-tachycardia pacing therapy and method
US6490486B1 (en) Implantable cardiac stimulation device and method that monitors displacement of an implanted lead
US5653738A (en) DDI pacing with protection against induction of a pacemaker medicated retrograde rhythm
US20020082660A1 (en) Apparatus and method for pacing mode switching during atrial tachyarrhythmias