US20100238213A1 - Method for dead nozzle remapping - Google Patents

Method for dead nozzle remapping Download PDF

Info

Publication number
US20100238213A1
US20100238213A1 US12790945 US79094510A US20100238213A1 US 20100238213 A1 US20100238213 A1 US 20100238213A1 US 12790945 US12790945 US 12790945 US 79094510 A US79094510 A US 79094510A US 20100238213 A1 US20100238213 A1 US 20100238213A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
fig
shows
data
dot
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12790945
Inventor
Richard Thomas Plunkett
Simon Robert Walmsley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zamtec Ltd
Original Assignee
Silverbrook Research Pty Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/73Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, e.g. INK-JET PRINTERS, THERMAL PRINTERS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01Ink jet
    • B41J2/015Ink jet characterised by the jet generation process
    • B41J2/04Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/04505Control methods or devices therefor, e.g. driver circuits, control circuits aiming at correcting alignment
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, e.g. INK-JET PRINTERS, THERMAL PRINTERS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01Ink jet
    • B41J2/015Ink jet characterised by the jet generation process
    • B41J2/04Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/04508Control methods or devices therefor, e.g. driver circuits, control circuits aiming at correcting other parameters
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, e.g. INK-JET PRINTERS, THERMAL PRINTERS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01Ink jet
    • B41J2/015Ink jet characterised by the jet generation process
    • B41J2/04Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/0451Control methods or devices therefor, e.g. driver circuits, control circuits for detecting failure, e.g. clogging, malfunctioning actuator
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, e.g. INK-JET PRINTERS, THERMAL PRINTERS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01Ink jet
    • B41J2/015Ink jet characterised by the jet generation process
    • B41J2/04Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/04528Control methods or devices therefor, e.g. driver circuits, control circuits aiming at warming up the head
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, e.g. INK-JET PRINTERS, THERMAL PRINTERS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01Ink jet
    • B41J2/015Ink jet characterised by the jet generation process
    • B41J2/04Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/04541Specific driving circuit
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, e.g. INK-JET PRINTERS, THERMAL PRINTERS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01Ink jet
    • B41J2/015Ink jet characterised by the jet generation process
    • B41J2/04Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/04543Block driving
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, e.g. INK-JET PRINTERS, THERMAL PRINTERS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01Ink jet
    • B41J2/015Ink jet characterised by the jet generation process
    • B41J2/04Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/04563Control methods or devices therefor, e.g. driver circuits, control circuits detecting head temperature; Ink temperature
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, e.g. INK-JET PRINTERS, THERMAL PRINTERS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01Ink jet
    • B41J2/015Ink jet characterised by the jet generation process
    • B41J2/04Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/04573Timing; Delays
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, e.g. INK-JET PRINTERS, THERMAL PRINTERS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01Ink jet
    • B41J2/015Ink jet characterised by the jet generation process
    • B41J2/04Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/04586Control methods or devices therefor, e.g. driver circuits, control circuits controlling heads of a type not covered by groups B41J2/04575 - B41J2/04585, or of an undefined type
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/55Detecting local intrusion or implementing counter-measures
    • G06F21/554Detecting local intrusion or implementing counter-measures involving event detection and direct action
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/57Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/57Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
    • G06F21/575Secure boot
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60Protecting data
    • G06F21/64Protecting data integrity, e.g. using checksums, certificates or signatures
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/74Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information operating in dual or compartmented mode, i.e. at least one secure mode
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating pulses not covered by one of the other main groups in this subclass
    • H03K5/125Discriminating pulses
    • H03K5/1252Suppression or limitation of noise or interference
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/40Picture signal circuits
    • H04N1/405Halftoning, i.e. converting the picture signal of a continuous-tone original into a corresponding signal showing only two levels
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, e.g. INK-JET PRINTERS, THERMAL PRINTERS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2202/00Embodiments of or processes related to ink-jet or thermal heads
    • B41J2202/01Embodiments of or processes related to ink-jet heads
    • B41J2202/20Modules
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00Data processing: database and file management or data structures
    • Y10S707/99931Database or file accessing
    • Y10S707/99933Query processing, i.e. searching
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00Data processing: database and file management or data structures
    • Y10S707/99931Database or file accessing
    • Y10S707/99939Privileged access
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49401Fluid pattern dispersing device making, e.g., ink jet

Abstract

A method of accounting for dead nozzle remapping in a multi-nozzle printhead includes defining a first fixative plane and a second fixative plane; determining a first color plane requiring the fixative; determining if fixative is present in the first color plane; determining if the first color plane is dead; and adding fixative to a second color plane when it is determined that the first color plane is dead.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • [0001]
    The present application is a Continuation of U.S. application Ser. No. 10/727,181 filed Dec. 2, 2003, all of which are herein incorporated by reference.
  • FIELD OF INVENTION
  • [0002]
    The present invention relates to techniques for outputting one or more lines of a dither matrix from a memory containing the dither matrix.
  • BACKGROUND OF INVENTION
  • [0003]
    Manufacturing a printhead that has relatively high resolution and print-speed raises a number of problems.
  • [0004]
    Difficulties in manufacturing pagewidth printheads of any substantial size arise due to the relatively small dimensions of standard silicon wafers that are used in printhead (or printhead module) manufacture. For example, if it is desired to make an 8 inch wide pagewidth printhead, only one such printhead can be laid out on a standard 8-inch wafer, since such wafers are circular in plan. Manufacturing a pagewidth printhead from two or more smaller modules can reduce this limitation to some extent, but raises other problems related to providing a joint between adjacent printhead modules that is precise enough to avoid visible artefacts (which would typically take the form of noticeable lines) when the printhead is used. The problem is exacerbated in relatively high-resolution applications because of the tight tolerances dictated by the small spacing between nozzles.
  • [0005]
    The quality of a joint region between adjacent printhead modules relies on factors including a precision with which the abutting ends of each module can be manufactured, the accuracy with which they can be aligned when assembled into a single printhead, and other more practical factors such as management of ink channels behind the nozzles. It will be appreciated that the difficulties include relative vertical displacement of the printhead modules with respect to each other.
  • [0006]
    Whilst some of these issues may be dealt with by careful design and manufacture, the level of precision required renders it relatively expensive to manufacture printheads within the required tolerances. It would be desirable to provide a solution to one or more of the problems associated with precision manufacture and assembly of multiple printhead modules to form a printhead, and especially a pagewidth printhead.
  • [0007]
    In some cases, it is desirable to produce a number of different printhead module types or lengths on a substrate to maximise usage of the substrate's surface area. However, different sizes and types of modules will have different numbers and layouts of print nozzles, potentially including different horizontal and vertical offsets. Where two or more modules are to be joined to form a single printhead, there is also the problem of dealing with different seam shapes between abutting ends of joined modules, which again may incorporate vertical or horizontal offsets between the modules. Printhead controllers are usually dedicated application specific integrated circuits (ASICs) designed for specific use with a single type of printhead module, that is used by itself rather than with other modules. It would be desirable to provide a way in which different lengths and types of printhead modules could be accounted for using a single printer controller.
  • [0008]
    In any printing system that includes multiple nozzles on a printhead or printhead module, there is the possibility of one or more of the nozzles failing in the field, or being inoperative due to manufacturing defect. Given the relatively large size of a typical printhead module, it would be desirable to provide some form of compensation for one or more “dead” nozzles. Where the printhead also outputs fixative on a per-nozzle basis, it is also desirable that the fixative is provided in such a way that dead nozzles are compensated for.
  • SUMMARY OF INVENTION
  • [0009]
    According to an aspect of the present disclosure, a method of accounting for dead nozzle remapping in a multi-nozzle printhead includes defining a first fixative plane and a second fixative plane; determining a first color plane requiring the fixative; determining if fixative is present in the first color plane; determining if the first color plane is dead; and adding fixative to a second color plane when it is determined that the first color plane is dead.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0010]
    Preferred and other embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:
  • [0011]
    FIG. 1 is an example of state machine notation
  • [0012]
    FIG. 2 shows document data flow in a printer
  • [0013]
    FIG. 3 is an example of a single printer controller (hereinafter “SoPEC”) A4 simplex printer system
  • [0014]
    FIG. 4 is an example of a dual SoPEC A4 duplex printer system
  • [0015]
    FIG. 5 is an example of a dual SoPEC A3 simplex printer system
  • [0016]
    FIG. 6 is an example of a quad SoPEC A3 duplex printer system
  • [0017]
    FIG. 7 is an example of a SoPEC A4 simplex printing system with an extra SoPEC used as DRAM storage
  • [0018]
    FIG. 8 is an example of an A3 duplex printing system featuring four printing SoPECs
  • [0019]
    FIG. 9 shows pages containing different numbers of bands
  • [0020]
    FIG. 10 shows the contents of a page band
  • [0021]
    FIG. 11 illustrates a page data path from host to SoPEC
  • [0022]
    FIG. 12 shows a page structure
  • [0023]
    FIG. 13 shows a SoPEC system top level partition
  • [0024]
    FIG. 14 shows a SoPEC CPU memory map (not to scale)
  • [0025]
    FIG. 15 is a block diagram of CPU
  • [0026]
    FIG. 16 shows CPU bus transactions
  • [0027]
    FIG. 17 shows a state machine for a CPU subsystem slave
  • [0028]
    FIG. 18 shows a SoPEC CPU memory map (not to scale)
  • [0029]
    FIG. 19 shows an external signal view of a memory management unit (hereinafter “MMU”) sub-block partition
  • [0030]
    FIG. 20 shows an internal signal view of an MMU sub-block partition
  • [0031]
    FIG. 21 shows a DRAM write buffer
  • [0032]
    FIG. 22 shows DIU waveforms for multiple transactions
  • [0033]
    FIG. 23 shows a SoPEC LEON CPU core
  • [0034]
    FIG. 24 shows a cache data RAM wrapper
  • [0035]
    FIG. 25 shows a realtime debug unit block diagram
  • [0036]
    FIG. 26 shows interrupt acknowledge cycles for single and pending interrupts
  • [0037]
    FIG. 27 shows an A3 duplex system featuring four printing SoPECs with a single SoPEC DRAM device
  • [0038]
    FIG. 28 is an SCB block diagram
  • [0039]
    FIG. 29 is a logical view of the SCB of FIG. 28
  • [0040]
    FIG. 30 shows an ISI configuration with four SoPEC devices
  • [0041]
    FIG. 31 shows half-duplex interleaved transmission from ISIMaster to ISISlave
  • [0042]
    FIG. 32 shows ISI transactions
  • [0043]
    FIG. 33 shows an ISI long packet
  • [0044]
    FIG. 34 shows an ISI ping packet
  • [0045]
    FIG. 35 shows a short ISI packet
  • [0046]
    FIG. 36 shows successful transmission of two long packets with sequence bit toggling
  • [0047]
    FIG. 37 shows sequence bit operation with errored long packet
  • [0048]
    FIG. 38 shows sequence bit operation with ACK error
  • [0049]
    FIG. 39 shows an ISI sub-block partition
  • [0050]
    FIG. 40 shows an ISI serial interface engine functional block diagram
  • [0051]
    FIG. 41 is an SIE edge detection and data IO diagram
  • [0052]
    FIG. 42 is an SIE Rx/Tx state machine Tx cycle state diagram
  • [0053]
    FIG. 43 shows an SIE Rx/Tx state machine Tx bit stuff ‘0’ cycle state diagram
  • [0054]
    FIG. 44 shows an SIE Rx/Tx state machine Tx bit stuff ‘1’ cycle state diagram
  • [0055]
    FIG. 45 shows an SIE Rx/Tx state machine Rx cycle state diagram
  • [0056]
    FIG. 46 shows an SIE Tx functional timing example
  • [0057]
    FIG. 47 shows an SIE Rx functional timing example
  • [0058]
    FIG. 48 shows an SIE Rx/Tx FIFO block diagram
  • [0059]
    FIG. 49 shows SIE Rx/Tx FIFO control signal gating
  • [0060]
    FIG. 50 shows an SIE bit stuffing state machine Tx cycle state diagram
  • [0061]
    FIG. 51 shows an SIE bit stripping state machine Rx cycle state diagram
  • [0062]
    FIG. 52 shows a CRC 16 generation/checking shift register
  • [0063]
    FIG. 53 shows circular buffer operation
  • [0064]
    FIG. 54 shows duty cycle select
  • [0065]
    FIG. 55 shows a GPIO partition
  • [0066]
    FIG. 56 shows a motor control RTL diagram
  • [0067]
    FIG. 57 is an input de-glitch RTL diagram
  • [0068]
    FIG. 58 is a frequency analyser RTL diagram
  • [0069]
    FIG. 59 shows a brushless DC controller
  • [0070]
    FIG. 60 shows a period measure unit
  • [0071]
    FIG. 61 shows line synch generation logic
  • [0072]
    FIG. 62 shows an ICU partition
  • [0073]
    FIG. 63 is an interrupt clear state diagram
  • [0074]
    FIG. 63A Timers sub-block partition diagram
  • [0075]
    FIG. 64 is a watchdog timer RTL diagram
  • [0076]
    FIG. 65 is a generic timer RTL diagram
  • [0077]
    FIG. 66 is a schematic of a timing pulse generator
  • [0078]
    FIG. 67 is a Pulse generator RTL diagram
  • [0079]
    FIG. 68 shows a SoPEC clock relationship
  • [0080]
    FIG. 69 shows a CPR block partition
  • [0081]
    FIG. 70 shows reset deglitch logic
  • [0082]
    FIG. 71 shows reset synchronizer logic
  • [0083]
    FIG. 72 is a clock gate logic diagram
  • [0084]
    FIG. 73 shows a PLL and Clock divider logic
  • [0085]
    FIG. 74 shows a PLL control state machine diagram
  • [0086]
    FIG. 75 shows a LSS master system-level interface
  • [0087]
    FIG. 76 shows START and STOP conditions
  • [0088]
    FIG. 77 shows an LSS transfer of 2 data bytes
  • [0089]
    FIG. 78 is an example of an LSS write to a QA Chip
  • [0090]
    FIG. 79 is an example of an LSS read from QA Chip
  • [0091]
    FIG. 80 shows an LSS block diagram
  • [0092]
    FIG. 81 shows an LSS multi-command transaction
  • [0093]
    FIG. 82 shows start and stop generation based on previous bus state
  • [0094]
    FIG. 83 shows an LSS master state machine
  • [0095]
    FIG. 84 shows LSS master timing
  • [0096]
    FIG. 85 shows a SoPEC system top level partition
  • [0097]
    FIG. 86 shows an ead bus with 3 cycle random DRAM read accesses
  • [0098]
    FIG. 87 shows interleaving of CPU and non-CPU read accesses
  • [0099]
    FIG. 88 shows interleaving of read and write accesses with 3 cycle random DRAM accesses
  • [0100]
    FIG. 89 shows interleaving of write accesses with 3 cycle random DRAM accesses
  • [0101]
    FIG. 90 shows a read protocol for a SoPEC Unit making a single 256-bit access
  • [0102]
    FIG. 91 shows a read protocol for a SoPEC Unit making a single 256-bit access
  • [0103]
    FIG. 92 shows a write protocol for a SoPEC Unit making a single 256-bit access
  • [0104]
    FIG. 93 shows a protocol for a posted, masked, 128-bit write by the CPU
  • [0105]
    FIG. 94 shows a write protocol shown for CDU making four contiguous 64-bit accesses
  • [0106]
    FIG. 95 shows timeslot-based arbitration
  • [0107]
    FIG. 96 shows timeslot-based arbitration with separate pointers
  • [0108]
    FIG. 97 shows a first example (a) of separate read and write arbitration
  • [0109]
    FIG. 98 shows a second example (b) of separate read and write arbitration
  • [0110]
    FIG. 99 shows a third example (c) of separate read and write arbitration
  • [0111]
    FIG. 100 shows a DIU partition
  • [0112]
    FIG. 101 shows a DIU partition
  • [0113]
    FIG. 102 shows multiplexing and address translation logic for two memory instances
  • [0114]
    FIG. 103 shows a timing of dau dcu valid, dcu dau adv and dcu dau wady
  • [0115]
    FIG. 104 shows a DCU state machine
  • [0116]
    FIG. 105 shows random read timing
  • [0117]
    FIG. 106 shows random write timing
  • [0118]
    FIG. 107 shows refresh timing
  • [0119]
    FIG. 108 shows page mode write timing
  • [0120]
    FIG. 109 shows timing of non-CPU DIU read access
  • [0121]
    FIG. 110 shows timing of CPU DIU read access
  • [0122]
    FIG. 111 shows a CPU DIU read access
  • [0123]
    FIG. 112 shows timing of CPU DIU write access
  • [0124]
    FIG. 113 shows timing of a non-CDU/non-CPU DIU write access
  • [0125]
    FIG. 114 shows timing of CDU DIU write access
  • [0126]
    FIG. 115 shows command multiplexor sub-block partition
  • [0127]
    FIG. 116 shows command multiplexor timing at DIU requestors interface
  • [0128]
    FIG. 117 shows generation of re arbitrate and re arbitrate wady
  • [0129]
    FIG. 118 shows CPU interface and arbitration logic
  • [0130]
    FIG. 119 shows arbitration timing
  • [0131]
    FIG. 120 shows setting RotationSync to enable a new rotation.
  • [0132]
    FIG. 121 shows a timeslot based arbitration
  • [0133]
    FIG. 122 shows a timeslot based arbitration with separate pointers
  • [0134]
    FIG. 123 shows a CPU pre-access write lookahead pointer
  • [0135]
    FIG. 124 shows arbitration hierarchy
  • [0136]
    FIG. 125 shows hierarchical round-robin priority comparison
  • [0137]
    FIG. 126 shows a read multiplexor partition
  • [0138]
    FIG. 127 shows a read command queue (4 deep buffer)
  • [0139]
    FIG. 128 shows state-machines for shared read bus accesses
  • [0140]
    FIG. 129 shows a write multiplexor partition
  • [0141]
    FIG. 130 shows a read multiplexer timing for back-to-back shared read bus transfer
  • [0142]
    FIG. 131 shows a write multiplexer partition
  • [0143]
    FIG. 132 shows a block diagram of a PCU
  • [0144]
    FIG. 133 shows PCU accesses to PEP registers
  • [0145]
    FIG. 134 shows command arbitration and execution
  • [0146]
    FIG. 135 shows DRAM command access state machine
  • [0147]
    FIG. 136 shows an outline of contone data flow with respect to CDU
  • [0148]
    FIG. 137 shows a DRAM storage arrangement for a single line of JPEG 8×8 blocks in 4 colors
  • [0149]
    FIG. 138 shows a read control unit state machine
  • [0150]
    FIG. 139 shows a memory arrangement of JPEG blocks
  • [0151]
    FIG. 140 shows a contone data write state machine
  • [0152]
    FIG. 141 shows lead-in and lead-out clipping of contone data in multi-SoPEC environment
  • [0153]
    FIG. 142 shows a block diagram of CFU
  • [0154]
    FIG. 143 shows a DRAM storage arrangement for a single line of JPEG blocks in 4 colors
  • [0155]
    FIG. 144 shows a block diagram of color space converter
  • [0156]
    FIG. 145 shows a converter/invertor
  • [0157]
    FIG. 146 shows a high-level block diagram of LBD in context
  • [0158]
    FIG. 147 shows a schematic outline of the LBD and the SFU
  • [0159]
    FIG. 148 shows a block diagram of lossless bi-level decoder
  • [0160]
    FIG. 149 shows a stream decoder block diagram
  • [0161]
    FIG. 150 shows a command controller block diagram
  • [0162]
    FIG. 151 shows a state diagram for command controller (CC) state machine
  • [0163]
    FIG. 152 shows a next edge unit block diagram
  • [0164]
    FIG. 153 shows a next edge unit buffer diagram
  • [0165]
    FIG. 154 shows a next edge unit edge detect diagram
  • [0166]
    FIG. 155 shows a state diagram for the next edge unit state machine
  • [0167]
    FIG. 156 shows a line fill unit block diagram
  • [0168]
    FIG. 157 shows a state diagram for the Line Fill Unit (LFU) state machine
  • [0169]
    FIG. 158 shows a bi-level DRAM buffer
  • [0170]
    FIG. 159 shows interfaces between LBD/SFU/HCU
  • [0171]
    FIG. 160 shows an SFU sub-block partition
  • [0172]
    FIG. 161 shows an LBDPrevLineFifo sub-block
  • [0173]
    FIG. 162 shows timing of signals on the LBDPrevLineFIFO interface to DIU and address generator
  • [0174]
    FIG. 163 shows timing of signals on LBDPrevLineFIFO interface to DIU and address generator
  • [0175]
    FIG. 164 shows LBDNextLineFifo sub-block
  • [0176]
    FIG. 165 shows timing of signals on LBDNextLineFIFO interface to DIU and address generator
  • [0177]
    FIG. 166 shows LBDNextLineFIFO DIU interface state diagram
  • [0178]
    FIG. 167 shows an LDB to SFU write interface
  • [0179]
    FIG. 168 shows an LDB to SFU read interface (within a line)
  • [0180]
    FIG. 169 shows an HCUReadLineFifo Sub-block
  • [0181]
    FIG. 170 shows a DIU write Interface
  • [0182]
    FIG. 171 shows a DIU Read Interface multiplexing by select_hrfplf
  • [0183]
    FIG. 172 shows DIU read request arbitration logic
  • [0184]
    FIG. 173 shows address generation
  • [0185]
    FIG. 174 shows an X scaling control unit
  • [0186]
    FIG. 175 Y shows a scaling control unit
  • [0187]
    FIG. 176 shows an overview of X and Y scaling at HCU interface
  • [0188]
    FIG. 177 shows a high level block diagram of TE in context
  • [0189]
    FIG. 178 shows a QR Code
  • [0190]
    FIG. 179 shows Netpage tag structure
  • [0191]
    FIG. 180 shows a Netpage tag with data rendered at 1600 dpi (magnified view)
  • [0192]
    FIG. 181 shows an example of 2×2 dots for each block of QR code
  • [0193]
    FIG. 182 shows placement of tags for portrait & landscape printing
  • [0194]
    FIG. 183 shows agGeneral representation of tag placement
  • [0195]
    FIG. 184 shows composition of SoPEC's tag format structure
  • [0196]
    FIG. 185 shows a simple 3×3 tag structure
  • [0197]
    FIG. 186 shows 3×3 tag redesigned for 21×21 area (not simple replication)
  • [0198]
    FIG. 187 shows a TE Block Diagram
  • [0199]
    FIG. 188 shows a TE Hierarchy
  • [0200]
    FIG. 189 shows a block diagram of PCU accesses
  • [0201]
    FIG. 190 shows a tag encoder top-level FSM
  • [0202]
    FIG. 191 shows generated control signals
  • [0203]
    FIG. 192 shows logic to combine dot information and encoded data
  • [0204]
    FIG. 193 shows generation of Lastdotintag/1
  • [0205]
    FIG. 194 shows generation of Dot Position Valid
  • [0206]
    FIG. 195 shows generation of write enable to the TFU
  • [0207]
    FIG. 196 shows generation of Tag Dot Number
  • [0208]
    FIG. 197 shows TDI Architecture
  • [0209]
    FIG. 198 shows data flow through the TDI
  • [0210]
    FIG. 199 shows raw tag data interface block diagram
  • [0211]
    FIG. 200 shows an RTDI State Flow Diagram
  • [0212]
    FIG. 201 shows a relationship between TE_endoftagdata, cdu_startofbandstore and cdu_endofbandstore
  • [0213]
    FIG. 202 shows a TDi State Flow Diagram
  • [0214]
    FIG. 203 shows mapping of the tag data to codewords 0-7
  • [0215]
    FIG. 204 shows coding and mapping of uncoded fixed tag data for (15,5) RS encoder
  • [0216]
    FIG. 205 shows mapping of pre-coded fixed tag data
  • [0217]
    FIG. 206 shows coding and mapping of variable tag data for (15,7) RS encoder
  • [0218]
    FIG. 207 shows coding and mapping of uncoded fixed tag data for (15,7) RS encoder
  • [0219]
    FIG. 208 shows mapping of 2D decoded variable tag data
  • [0220]
    FIG. 209 shows a simple block diagram for an m=4 Reed Solomon encoder
  • [0221]
    FIG. 210 shows an RS encoder I/O diagram
  • [0222]
    FIG. 211 shows a (15,5) & (15,7) RS encoder block diagram
  • [0223]
    FIG. 212 shows a (15,5) RS encoder timing diagram
  • [0224]
    FIG. 213 shows a (15,7) RS encoder timing diagram
  • [0225]
    FIG. 214 shows a circuit for multiplying by alpha3
  • [0226]
    FIG. 215 shows adding two field elements
  • [0227]
    FIG. 216 shows an RS encoder implementation
  • [0228]
    FIG. 217 shows an encoded tag data interface
  • [0229]
    FIG. 218 shows an encoded fixed tag data interface
  • [0230]
    FIG. 219 shows an encoded variable tag data interface
  • [0231]
    FIG. 220 shows an encoded variable tag data sub-buffer
  • [0232]
    FIG. 221 shows a breakdown of the tag format structure
  • [0233]
    FIG. 222 shows a TFSI FSM state flow diagram
  • [0234]
    FIG. 223 shows a TFS block diagram
  • [0235]
    FIG. 224 shows a table A interface block diagram
  • [0236]
    FIG. 225 shows a table A address generator
  • [0237]
    FIG. 226 shows a table C interface block diagram
  • [0238]
    FIG. 227 shows a table B interface block diagram
  • [0239]
    FIG. 228 shows interfaces between TE, TFU and HCU
  • [0240]
    FIG. 229 shows a 16-byte FIFO in TFU
  • [0241]
    FIG. 230 shows a high level block diagram showing the HCU and its external interfaces
  • [0242]
    FIG. 231 shows a block diagram of the HCU
  • [0243]
    FIG. 232 shows a block diagram of the control unit
  • [0244]
    FIG. 233 shows a block diagram of determine advdot unit
  • [0245]
    FIG. 234 shows a page structure
  • [0246]
    FIG. 235 shows a block diagram of a margin unit
  • [0247]
    FIG. 236 shows a block diagram of a dither matrix table interface
  • [0248]
    FIG. 237 shows an example of reading lines of dither matrix from DRAM
  • [0249]
    FIG. 238 shows a state machine to read dither matrix table
  • [0250]
    FIG. 239 shows a contone dotgen unit
  • [0251]
    FIG. 240 shows a block diagram of dot reorg unit
  • [0252]
    FIG. 241 shows an HCU to DNC interface (also used in DNC to DWU, LLU to PHI)
  • [0253]
    FIG. 242 shows SFU to HCU interface (all feeders to HCU)
  • [0254]
    FIG. 243 shows representative logic of the SFU to HCU interface
  • [0255]
    FIG. 244 shows a high-level block diagram of DNC
  • [0256]
    FIG. 245 shows a dead nozzle table format
  • [0257]
    FIG. 246 shows set of dots operated on for error diffusion
  • [0258]
    FIG. 247 shows a block diagram of DNC
  • [0259]
    FIG. 248 shows a sub-block diagram of ink replacement unit
  • [0260]
    FIG. 249 shows a dead nozzle table state machine
  • [0261]
    FIG. 250 shows logic for dead nozzle removal and ink replacement
  • [0262]
    FIG. 251 shows a sub-block diagram of error diffusion unit
  • [0263]
    FIG. 252 shows a maximum length 32-bit LFSR used for random bit generation
  • [0264]
    FIG. 253 shows a high-level data flow diagram of DWU in context
  • [0265]
    FIG. 254 shows a printhead nozzle layout for 36-nozzle bi-lithic printhead
  • [0266]
    FIG. 255 shows a printhead nozzle layout for a 36-nozzle bi-lithic printhead
  • [0267]
    FIG. 256 shows a dot line store logical representation
  • [0268]
    FIG. 257 shows a conceptual view of printhead row alignment
  • [0269]
    FIG. 258 shows a conceptual view of printhead rows (as seen by the LLU and PHI)
  • [0270]
    FIG. 259 shows a comparison of 1.5×v 2× buffering
  • [0271]
    FIG. 260 shows an even dot order in DRAM (increasing sense, 13320 dot wide line)
  • [0272]
    FIG. 261 shows an even dot order in DRAM (decreasing sense, 13320 dot wide line)
  • [0273]
    FIG. 262 shows a dotline FIFO data structure in DRAM
  • [0274]
    FIG. 263 shows a DWU partition
  • [0275]
    FIG. 264 shows a buffer address generator sub-block
  • [0276]
    FIG. 265 shows a DIU Interface sub-block
  • [0277]
    FIG. 266 shows an interface controller state diagram
  • [0278]
    FIG. 267 shows a high level data flow diagram of LLU in context
  • [0279]
    FIG. 268 shows paper and printhead nozzles relationship (example with D1=D2=5)
  • [0280]
    FIG. 269 shows printhead structure and dot generate order
  • [0281]
    FIG. 270 shows an order of dot data generation and transmission
  • [0282]
    FIG. 271 shows a conceptual view of printhead rows
  • [0283]
    FIG. 272 shows a dotline FIFO data structure in DRAM (LLU specification)
  • [0284]
    FIG. 273 shows an LLU partition
  • [0285]
    FIG. 274 shows a dot generator RTL diagram
  • [0286]
    FIG. 275 shows a DIU interface
  • [0287]
    FIG. 276 shows an interface controller state diagram
  • [0288]
    FIG. 277 shows high-level data flow diagram of PHI in context
  • [0289]
    FIG. 278 shows power on reset
  • [0290]
    FIG. 279 shows printhead data rate equalization
  • [0291]
    FIG. 280 shows a printhead structure and dot generate order
  • [0292]
    FIG. 281 shows an order of dot data generation and transmission
  • [0293]
    FIG. 282 shows an order of dot data generation and transmission (single printhead case)
  • [0294]
    FIG. 283 shows printhead interface timing parameters
  • [0295]
    FIG. 284 shows printhead timing with margining
  • [0296]
    FIG. 285 shows a PHI block partition
  • [0297]
    FIG. 286 shows a sync generator state diagram
  • [0298]
    FIG. 287 shows a line sync de-glitch RTL diagram
  • [0299]
    FIG. 288 shows a fire generator state diagram
  • [0300]
    FIG. 289 shows a PHI controller state machine
  • [0301]
    FIG. 290 shows a datapath unit partition
  • [0302]
    FIG. 291 shows a dot order controller state diagram
  • [0303]
    FIG. 292 shows a data generator state diagram
  • [0304]
    FIG. 293 shows data serializer timing
  • [0305]
    FIG. 294 shows a data serializer RTL Diagram
  • [0306]
    FIG. 295 shows printhead types 0 to 7
  • [0307]
    FIG. 296 shows an ideal join between two dilithic printhead segments
  • [0308]
    FIG. 297 shows an example of a join between two bilithic printhead segments
  • [0309]
    FIG. 298 shows printable vs non-printable area under new definition (looking at colors as if 1 row only)
  • [0310]
    FIG. 299 shows identification of printhead nozzles and shift-register sequences for printheads in arrangement 1
  • [0311]
    FIG. 300 shows demultiplexing of data within the printheads in arrangement 1
  • [0312]
    FIG. 301 shows double data rate signalling for a type 0 printhead in arrangement 1
  • [0313]
    FIG. 302 shows double data rate signalling for a type 1 printhead in arrangement 1
  • [0314]
    FIG. 303 shows identification of printheads nozzles and shift-register sequences for printheads in arrangement 2
  • [0315]
    FIG. 304 shows demultiplexing of data within the printheads in arrangement 2
  • [0316]
    FIG. 305 shows double data rate signalling for a type 0 printhead in arrangement 2
  • [0317]
    FIG. 306 shows double data rate signalling for a type 1 printhead in arrangement 2
  • [0318]
    FIG. 307 shows all 8 printhead arrangements
  • [0319]
    FIG. 308 shows a printhead structure
  • [0320]
    FIG. 309 shows a column Structure
  • [0321]
    FIG. 310 shows a printhead dot shift register dot mapping to page
  • [0322]
    FIG. 311 shows data timing during printing
  • [0323]
    FIG. 312 shows print quality
  • [0324]
    FIG. 313 shows fire and select shift register setup for printing
  • [0325]
    FIG. 314 shows a fire pattern across butt end of printhead chips
  • [0326]
    FIG. 315 shows fire pattern generation
  • [0327]
    FIG. 316 shows determination of select shift register value
  • [0328]
    FIG. 317 shows timing for printing signals
  • [0329]
    FIG. 318 shows initialisation of printheads
  • [0330]
    FIG. 319 shows a nozzle test latching circuit
  • [0331]
    FIG. 320 shows nozzle testing
  • [0332]
    FIG. 321 shows a temperature reading
  • [0333]
    FIG. 322 shows CMOS testing
  • [0334]
    FIG. 323 shows a reticle layout
  • [0335]
    FIG. 324 shows a stepper pattern on Wafer
  • [0336]
    FIG. 325 shows relationship between datasets
  • [0337]
    FIG. 326 shows a validation hierarchy
  • [0338]
    FIG. 327 shows development of operating system code
  • [0339]
    FIG. 328 shows protocol for directly verifying reads from ChipR
  • [0340]
    FIG. 329 shows a protocol for signature translation protocol
  • [0341]
    FIG. 330 shows a protocol for a direct authenticated write
  • [0342]
    FIG. 331 shows an alternative protocol for a direct authenticated write
  • [0343]
    FIG. 332 shows a protocol for basic update of permissions
  • [0344]
    FIG. 333 shows a protocol for a multiple-key update
  • [0345]
    FIG. 334 shows a protocol for a single-key authenticated read
  • [0346]
    FIG. 335 shows a protocol for a single-key authenticated write
  • [0347]
    FIG. 336 shows a protocol for a single-key update of permissions
  • [0348]
    FIG. 337 shows a protocol for a single-key update
  • [0349]
    FIG. 338 shows a protocol for a multiple-key single-M authenticated read
  • [0350]
    FIG. 339 shows a protocol for a multiple-key authenticated write
  • [0351]
    FIG. 340 shows a protocol for a multiple-key update of permissions
  • [0352]
    FIG. 341 shows a protocol for a multiple-key update
  • [0353]
    FIG. 342 shows a protocol for a multiple-key multiple-M authenticated read
  • [0354]
    FIG. 343 shows a protocol for a multiple-key authenticated write
  • [0355]
    FIG. 344 shows a protocol for a multiple-key update of permissions
  • [0356]
    FIG. 345 shows a protocol for a multiple-key update
  • [0357]
    FIG. 346 shows relationship of permissions bits to M[n] access bits
  • [0358]
    FIG. 347 shows 160-bit maximal period LFSR
  • [0359]
    FIG. 348 shows clock filter
  • [0360]
    FIG. 349 shows tamper detection line
  • [0361]
    FIG. 350 shows an oversize nMOS transistor layout of Tamper Detection Line
  • [0362]
    FIG. 351 shows a Tamper Detection Line
  • [0363]
    FIG. 352 shows how Tamper Detection Lines cover the Noise Generator
  • [0364]
    FIG. 353 shows a prior art FET Implementation of CMOS inverter
  • [0365]
    FIG. 354 shows non-flashing CMOS
  • [0366]
    FIG. 355 shows components of a printer-based refill device
  • [0367]
    FIG. 356 shows refilling of printers by printer-based refill device
  • [0368]
    FIG. 357 shows components of a home refill station
  • [0369]
    FIG. 358 shows a three-ink reservoir unit
  • [0370]
    FIG. 359 shows refill of ink cartridges in a home refill station
  • [0371]
    FIG. 360 shows components of a commercial refill station
  • [0372]
    FIG. 361 shows an ink reservoir unit
  • [0373]
    FIG. 362 shows refill of ink cartridges in a commercial refill station (showing a single refill unit)
  • [0374]
    FIG. 363 shows equivalent signature generation
  • [0375]
    FIG. 364 shows a basic field definition
  • [0376]
    FIG. 365 shows an example of defining field sizes and positions
  • [0377]
    FIG. 366 shows permissions
  • [0378]
    FIG. 367 shows a first example of permissions for a field
  • [0379]
    FIG. 368 shows a second example of permissions for a field
  • [0380]
    FIG. 369 shows field attributes
  • [0381]
    FIG. 370 shows an output signature generation data format for Read
  • [0382]
    FIG. 371 shows an input signature verification data format for Test
  • [0383]
    FIG. 372 shows an output signature generation data format for Translate
  • [0384]
    FIG. 373 shows an input signature verification data format for WriteAuth
  • [0385]
    FIG. 374 shows input signature data format for ReplaceKey
  • [0386]
    FIG. 375 shows a key replacement map
  • [0387]
    FIG. 376 shows a key replacement map after K1 is replaced
  • [0388]
    FIG. 377 shows a key replacement process
  • [0389]
    FIG. 378 shows an output signature data format for GetProgramKey
  • [0390]
    FIG. 379 shows transfer and rollback process
  • [0391]
    FIG. 380 shows an upgrade flow
  • [0392]
    FIG. 381 shows authorised ink refill paths in the printing system
  • [0393]
    FIG. 382 shows an input signature verification data format for XferAmount
  • [0394]
    FIG. 383 shows a transfer and rollback process
  • [0395]
    FIG. 384 shows an upgrade flow
  • [0396]
    FIG. 385 shows authorised upgrade paths in the printing system
  • [0397]
    FIG. 386 shows a direct signature validation sequence
  • [0398]
    FIG. 387 shows signature validation using translation
  • [0399]
    FIG. 388 shows setup of preauth field attributes
  • [0400]
    FIG. 389 shows a high level block diagram of QA Chip
  • [0401]
    FIG. 390 shows an analogue unit
  • [0402]
    FIG. 391 shows a serial bus protocol for trimming
  • [0403]
    FIG. 392 shows a block diagram of a trim unit
  • [0404]
    FIG. 393 shows a block diagram of a CPU of the QA chip
  • [0405]
    FIG. 394 shows block diagram of an MIU
  • [0406]
    FIG. 395 shows a block diagram of memory components
  • [0407]
    FIG. 396 shows a first byte sent to an IOU
  • [0408]
    FIG. 397 shows a block diagram of the IOU
  • [0409]
    FIG. 398 shows a relationship between external SDa and SCIk and generation of internal signals
  • [0410]
    FIG. 399 shows block diagram of ALU
  • [0411]
    FIG. 400 shows a block diagram of DataSel
  • [0412]
    FIG. 401 shows a block diagram of ROR
  • [0413]
    FIG. 402 shows a block diagram of the ALU's IO block
  • [0414]
    FIG. 403 shows a block diagram of PCU
  • [0415]
    FIG. 404 shows a block diagram of an Address Generator Unit
  • [0416]
    FIG. 405 shows a block diagram for a Counter Unit
  • [0417]
    FIG. 406 shows a block diagram of PMU
  • [0418]
    FIG. 407 shows a state machine for PMU
  • [0419]
    FIG. 408 shows a block diagram of MRU
  • [0420]
    FIG. 409 shows simplified MAU state machine
  • [0421]
    FIG. 410 shows power-on reset behaviour
  • [0422]
    FIG. 411 shows a ring oscillator block diagram
  • [0423]
    FIG. 412 shows a system clock duty cycle
  • DETAILED DESCRIPTION 1 Print System Overview 1.1 Printing Considerations
  • [0424]
    A bi-lithic printhead produces 1600 dpi bi-level dots. On low-diffusion paper, each ejected drop forms a 22.5 μm diameter dot. Dots are easily produced in isolation, allowing dispersed-dot dithering to be exploited to its fullest. Since the bi-lithic printhead is the width of the page and operates with a constant paper velocity, color planes are printed in perfect registration, allowing ideal dot-on-dot printing. Dot-on-dot printing minimizes ‘muddying’ of midtones caused by inter-color bleed.
  • [0425]
    A page layout may contain a mixture of images, graphics and text. Continuous-tone (contone) images and graphics are reproduced using a stochastic dispersed-dot dither. Unlike a clustered-dot (or amplitude-modulated) dither, a dispersed-dot (or frequency-modulated) dither reproduces high spatial frequencies (i.e. image detail) almost to the limits of the dot resolution, while simultaneously reproducing lower spatial frequencies to their full color depth, when spatially integrated by the eye. A stochastic dither matrix is carefully designed to be free of objectionable low-frequency patterns when tiled across the image. As such its size typically exceeds the minimum size required to support a particular number of intensity levels (e.g. 16×16×8 bits for 257 intensity levels).
  • [0426]
    Human contrast sensitivity peaks at a spatial frequency of about 3 cycles per degree of visual field and then falls off logarithmically, decreasing by a factor of 100 beyond about 40 cycles per degree and becoming immeasurable beyond 60 cycles per degree. At a normal viewing distance of 12 inches (about 300 mm), this translates roughly to 200-300 cycles per inch (cpi) on the printed page, or 400-600 samples per inch according to Nyquist's theorem.
  • [0427]
    In practice, contone resolution above about 300 ppi is of limited utility outside special applications such as medical imaging. Offset printing of magazines, for example, uses contone resolutions in the range 150 to 300 ppi. Higher resolutions contribute slightly to color error through the dither.
  • [0428]
    Black text and graphics are reproduced directly using bi-level black dots, and are therefore not anti-aliased (i.e. low-pass filtered) before being printed. Text should therefore be supersampled beyond the perceptual limits discussed above, to produce smoother edges when spatially integrated by the eye. Text resolution up to about 1200 dpi continues to contribute to perceived text sharpness (assuming low-diffusion paper, of course).
  • [0429]
    A Netpage printer, for example, may use a contone resolution of 267 ppi (i.e. 1600 dpi 6), and a black text and graphics resolution of 800 dpi. A high end office or departmental printer may use a contone resolution of 320 ppi (1600 dpi/5) and a black text and graphics resolution of 1600 dpi. Both formats are capable of exceeding the quality of commercial (offset) printing and photographic reproduction.
  • 1.2 Document Data Flow
  • [0430]
    Because of the page-width nature of the bi-lithic printhead, each page must be printed at a constant speed to avoid creating visible artifacts. This means that the printing speed cannot be varied to match the input data rate. Document rasterization and document printing are therefore decoupled to ensure the printhead has a constant supply of data. A page is never printed until it is fully rasterized. This can be achieved by storing a compressed version of each rasterized page image in memory.
  • [0431]
    This decoupling also allows the RIP(s) to run ahead of the printer when rasterizing simple pages, buying time to rasterize more complex pages.
  • [0432]
    Because contone color images are reproduced by stochastic dithering, but black text and line graphics are reproduced directly using dots, the compressed page image format contains a separate foreground bi-level black layer and background contone color layer. The black layer is composited over the contone layer after the contone layer is dithered (although the contone layer has an optional black component). A final layer of Netpage tags (in infrared or black ink) is optionally added to the page for printout.
  • [0433]
    FIG. 2 shows the flow of a document from computer system to printed page.
  • [0434]
    At 267 ppi for example, a A4 page (8.26 inches×11.7 inches) of contone CMYK data has a size of 26.3 MB. At 320 ppi, an A4 page of contone data has a size of 37.8 MB. Using lossy contone compression algorithms such as JPEG, contone images compress with a ratio up to 10:1 without noticeable loss of quality, giving compressed page sizes of 2.63 MB at 267 ppi and 3.78 MB at 320 ppi.
  • [0435]
    At 800 dpi, a A4 page of bi-level data has a size of 7.4 MB. At 1600 dpi, a Letter page of bi-level data has a size of 29.5 MB. Coherent data such as text compresses very well. Using lossless bi-level compression algorithms such as SMG4 fax, ten-point plain text compresses with a ratio of about 50:1. Lossless bi-level compression across an average page is about 20:1 with 10:1 possible for pages which compress poorly. The requirement for SoPEC is to be able to print text at 10:1 compression. Assuming 10:1 compression gives compressed page sizes of 0.74 MB at 800 dpi, and 2.95 MB at 1600 dpi.
  • [0436]
    Once dithered, a page of CMYK contone image data consists of 116 MB of bi-level data. Using lossless bi-level compression algorithms on this data is pointless precisely because the optimal dither is stochastic—i.e. since it introduces hard-to-compress disorder.
  • [0437]
    Netpage tag data is optionally supplied with the page image. Rather than storing a compressed bi-level data layer for the Netpage tags, the tag data is stored in its raw form. Each tag is supplied up to 120 bits of raw variable data (combined with up to 56 bits of raw fixed data) and covers up to a 6 mm×6 mm area (at 1600 dpi). The absolute maximum number of tags on a A4 page is 15,540 when the tag is only 2 mm×2 mm (each tag is 126 dots×126 dots, for a total coverage of 148 tags×105 tags). 15,540 tags of 128 bits per tag gives a compressed tag page size of 0.24 MB.
  • [0438]
    The multi-layer compressed page image format therefore exploits the relative strengths of lossy JPEG contone image compression, lossless bi-level text compression, and tag encoding. The format is compact enough to be storage-efficient, and simple enough to allow straightforward real-time expansion during printing.
  • [0439]
    Since text and images normally don't overlap, the normal worst-case page image size is image only, while the normal best-case page image size is text only. The addition of worst case Netpage tags adds 0.24 MB to the page image size. The worst-case page image size is text over image plus tags. The average page size assumes a quarter of an average page contains images.
  • [0440]
    The Host PC rasterizes and compresses the incoming document on a page by page basis. The page is restructured into bands with one or more bands used to construct a page. The compressed data is then transferred to the SoPEC device via the USB link. A complete band is stored in SoPEC embedded memory. Once the band transfer is complete the SoPEC device reads the compressed data, expands the band, normalizes contone, bi-level and tag data to 1600 dpi and transfers the resultant calculated dots to the bi-lithic printhead.
  • [0441]
    The document data flow is:
      • The RIP software rasterizes each page description and compress the rasterized page image.
      • The infrared layer of the printed page optionally contains encoded Netpage tags at a programmable density.
      • The compressed page image is transferred to the SoPEC device via the USB normally on a band by band basis.
      • The print engine takes the compressed page image and starts the page expansion.
      • The first stage page expansion consists of 3 operations performed in parallel
        • expansion of the JPEG-compressed contone layer
        • expansion of the SMG4 fax compressed bi-level layer
        • encoding and rendering of the bi-level tag data.
      • The second stage dithers the contone layer using a programmable dither matrix, producing up to four bi-level layers at full-resolution.
      • The second stage then composites the bi-level tag data layer, the bi-level SMG4 fax de-compressed layer and up to four bi-level JPEG de-compressed layers into the full-resolution page image.
      • A fixative layer is also generated as required.
      • The last stage formats and prints the bi-level data through the bi-lithic printhead via the printhead interface.
  • [0454]
    The SoPEC device can print a full resolution page with 6 color planes. Each of the color planes can be generated from compressed data through any channel (either JPEG compressed, bi-level SMG4 fax compressed, tag data generated, or fixative channel created) with a maximum number of 6 data channels from page RIP to bi-lithic printhead color planes.
  • [0455]
    The mapping of data channels to color planes is programmable, this allows for multiple color planes in the printhead to map to the same data channel to provide for redundancy in the printhead to assist dead nozzle compensation.
  • [0456]
    Also a data channel could be used to gate data from another data channel. For example in stencil mode, data from the bilevel data channel at 1600 dpi can be used to filter the contone data channel at 320 dpi, giving the effect of 1600 dpi contone image.
  • 1.2.1 Page Considerations Due to SoPEC
  • [0457]
    The SoPEC device typically stores a complete page of document data on chip. The amount of storage available for compressed pages is limited to 2 Mbytes, imposing a fixed maximum on compressed page size. A comparison of the compressed image sizes in the following table indicates that SoPEC would not be capable of printing worst case pages unless they are split into bands and printing commences before all the bands for the page have been downloaded. The page sizes in the table are shown for comparison purposes and would be considered reasonable for a professional level printing system. The SoPEC device is aimed at the consumer level and would not be required to print pages of that complexity.
  • [0000]
    Size
    Page Content Description Calculation (MByte)
    Best Case picture Image, 8.26 × 11.7 × 267 × 1.97
    267 ppi with 3 colors, 267 × 3 @ 10:1
    A4 size
    Full page text, 800 dpi 8.26 × 11.7 × 800 × 0.74
    A4 size 800 @ 10:1
    Mixed Graphics and Text 6 × 4 × 267 × 267 × 1.55
    Image of 6 inches × 4 3 @ 5:1
    inches @ 267 ppi and 800 × 800 × 73 @ 10:1
    3 colors
    Remaining area text ~73
    inches2, 800 dpi
    Best Case Photo, 3 Colors, 6.6 Mpixel @ 10:1 2.00
    6.6 MegaPixel Image
  • [0458]
    If a document with more complex pages is required, the page RIP software in the host PC can determine that there is insufficient memory storage in the SoPEC for that document. In such cases the RIP software can take two courses of action. It can increase the compression ratio until the compressed page size will fit in the SoPEC device, at the expense of document quality, or divide the page into bands and allow SoPEC to begin printing a page band before all bands for that page are downloaded. Once SoPEC starts printing a page it cannot stop, if SoPEC consumes compressed data faster than the bands can be downloaded a buffer underrun error could occur causing the print to fail. A buffer underrun occurs if a line synchronisation pulse is received before a line of data has been transferred to the printhead.
  • [0459]
    Other options which can be considered if the page does not fit completely into the compressed page store are to slow the printing or to use multiple SoPECs to print parts of the page. A Storage SoPEC could be added to the system to provide guaranteed bandwidth data delivery. The print system could also be constructed using an ISI-Bridge chip to provide guaranteed data delivery.
  • 1.3 Page Format and Printflow
  • [0460]
    When rendering a page, the RIP produces a page header and a number of bands (a non-blank page requires at least one band) for a page. The page header contains high level rendering parameters, and each band contains compressed page data. The size of the band will depend on the memory available to the RIP, the speed of the RIP, and the amount of memory remaining in SoPEC while printing the previous band(s). FIG. 9 shows the high level data structure of a number of pages with different numbers of bands in the page.
  • [0461]
    Each compressed band contains a mandatory band header, an optional bi-level plane, optional sets of interleaved contone planes, and an optional tag data plane (for Netpage enabled applications). Since each of these planes is optional1, the band header specifies which planes are included with the band. FIG. 10 gives a high-level breakdown of the contents of a page band. 1Although a band must contain at least one plane
  • [0462]
    A single SoPEC has maximum rendering restrictions as follows:
      • 1 bi-level plane
      • 1 contone interleaved plane set containing a maximum of 4 contone planes
      • 1 tag data plane
      • a bi-lithic printhead with a maximum of 2 printhead ICs
  • [0467]
    The requirement for single-sided A4 single SoPEC printing is
      • average contone JPEG compression ratio of 10:1, with a local minimum compression ratio of 5:1 for a single line of interleaved JPEG blocks.
      • average bi-level compression ratio of 10:1, with a local minimum compression ratio of 1:1 for a single line.
  • [0470]
    If the page contains rendering parameters that exceed these specifications, then the RIP or the Host PC must split the page into a format that can be handled by a single SoPEC.
  • [0471]
    In the general case, the SoPEC CPU must analyze the page and band headers and generate an appropriate set of register write commands to configure the units in SoPEC for that page. The various bands are passed to the destination SoPEC(s) to locations in DRAM determined by the host.
  • [0472]
    The host keeps a memory map for the DRAM, and ensures that as a band is passed to a SoPEC, it is stored in a suitable free area in DRAM. Each SoPEC is connected to the ISI bus or USB bus via its Serial communication Block (SCB). The SoPEC CPU configures the SCB to allow compressed data bands to pass from the USB or ISI through the SCB to SoPEC DRAM. FIG. 11 shows an example data flow for a page destined to be printed by a single SoPEC. Band usage information is generated by the individual SoPECs and passed back to the host.
  • [0473]
    SoPEC has an addressing mechanism that permits circular band memory allocation, thus facilitating easy memory management. However it is not strictly necessary that all bands be stored together. As long as the appropriate registers in SoPEC are set up for each band, and a given band is contiguous2, the memory can be allocated in any way. 2Contiguous allocation also includes wrapping around in SoPEC's band store memory.
  • 1.4 SoPEC ASIC
  • [0474]
    The Small Office Home Office Print Engine Controller (SoPEC) is a page rendering engine ASIC that takes compressed page images as input, and produces decompressed page images at up to 6 channels of bi-level dot data as output. The bi-level dot data is generated for the Memjet bi-lithic printhead. The dot generation process takes account of printhead construction, dead nozzles, and allows for fixative generation.
  • [0475]
    A single SoPEC can control 2 bi-lithic printheads and up to 6 color channels at 10,000 lines/sec3, equating to 30 pages per minute. A single SoPEC can perform full-bleed printing of A3, A4 and Letter pages. The 6 channels of colored ink are the expected maximum in a consumer SOHO, or office Bi-lithic printing environment: 310,000 lines per second equates to 30 A4/Letter pages per minute at 1600 dpi
      • CMY, for regular color printing.
      • K, for black text, line graphics and gray-scale printing.
      • IR (infrared), for Netpage-enabled applications.
      • F (fixative), to enable printing at high speed. Because the bi-lithic printer is capable of printing so fast, a fixative may be required to enable the ink to dry before the page touches the page already printed. Otherwise the pages may bleed on each other. In low speed printing environments the fixative may not be required.
  • [0480]
    SoPEC is color space agnostic. Although it can accept contone data as CMYX or RGBX, where X is an optional 4th channel, it also can accept contone data in any print color space. Additionally, SoPEC provides a mechanism for arbitrary mapping of input channels to output channels, including combining dots for ink optimization, generation of channels based on any number of other channels etc. However, inputs are typically CMYK for contone input, K for the bi-level input, and the optional Netpage tag dots are typically rendered to an infra-red layer. A fixative channel is typically generated for fast printing applications.
  • [0481]
    SoPEC is resolution agnostic. It merely provides a mapping between input resolutions and output resolutions by means of scale factors. The expected output resolution is 1600 dpi, but SoPEC actually has no knowledge of the physical resolution of the Bi-lithic printhead.
  • [0482]
    SoPEC is page-length agnostic. Successive pages are typically split into bands and downloaded into the page store as each band of information is consumed and becomes free.
  • [0483]
    SoPEC provides an interface for synchronization with other SoPECs. This allows simple multi-SoPEC solutions for simultaneous A3/A4/Letter duplex printing. However, SoPEC is also capable of printing only a portion of a page image. Combining synchronization functionality with partial page rendering allows multiple SoPECs to be readily combined for alternative printing requirements including simultaneous duplex printing and wide format printing.
  • 1.4.1 Printing Rates
  • [0484]
    The required printing rate for SoPEC is 30 sheets per minute with an inter-sheet spacing of 4 cm. To achieve a 30 sheets per minute print rate, this requires:
      • 300 mm×63 (dot/mm)/2 sec=105.8 μseconds per line, with no inter-sheet gap.
      • 340 mm×63 (dot/mm)/2 sec=93.3 μseconds per line, with a 4 cm inter-sheet gap.
  • [0487]
    A printline for an A4 page consists of 13824 nozzles across the page. At a system clock rate of 160 MHz 13824 dots of data can be generated in 86.4 μseconds. Therefore data can be generated fast enough to meet the printing speed requirement. It is necessary to deliver this print data to the print-heads.
  • [0488]
    Printheads can be made up of 5:5, 6:4, 7:3 and 8:2 inch printhead combinations. Print data is transferred to both print heads in a pair simultaneously. This means the longest time to print a line is determined by the time to transfer print data to the longest print segment. There are 9744 nozzles across a 7 inch printhead. The print data is transferred to the printhead at a rate of 106 MHz (⅔ of the system clock rate) per color plane. This means that it will take 91.9 μs to transfer a single line for a 7:3 printhead configuration. So we can meet the requirement of 30 sheets per minute printing with a 4 cm gap with a 7:3 printhead combination. There are 11160 across an 8 inch printhead. To transfer the data to the printhead at 106 MHz will take 105.3 μs. So an 8:2 printhead combination printing with an inter-sheet gap will print slower than 30 sheets per minute.
  • 1.4.2 9.3 SoPEC Block Description
  • [0489]
    Looking at FIG. 13, the various units are described here in summary form:
  • [0000]
    Unit
    Subsystem Acronym Unit Name Description
    DRAM DIU DRAM interface unit Provides the interface for DRAM read and write
    access for the various SoPEC units, CPU and
    the SCB block. The DIU provides arbitration
    between competing units controls DRAM
    access.
    DRAM Embedded DRAM 20 Mbits of embedded DRAM,
    CPU CPU Central Processing CPU for system configuration and control
    Unit
    MMU Memory Management Limits access to certain memory address areas
    Unit in CPU user mode
    RDU Real-time Debug Unit Facilitates the observation of the contents of
    most of the CPU addressable registers in
    SoPEC in addition to some pseudo-registers in
    realtime.
    TIM General Timer Contains watchdog and general system timers
    LSS Low Speed Serial Low level controller for interfacing with the QA
    Interfaces chips
    GPIO General Purpose IOs General IO controller, with built-in Motor control
    unit, LED pulse units and de-glitch circuitry
    ROM Boot ROM 16 KBytes of System Boot ROM code
    ICU Interrupt Controller General Purpose interrupt controller with
    Unit configurable priority, and masking.
    CPR Clock, Power and Central Unit for controlling and generating the
    Reset block system clocks and resets and powerdown
    mechanisms
    PSS Power Save Storage Storage retained while system is powered down
    USB Universal Serial Bus USB device controller for interfacing with the
    Device host USB.
    ISI Inter-SoPEC Interface ISI controller for data and control
    communication with other SoPEC's in a multi-
    SoPEC system
    SCB Serial Communication Contains both the USB and ISI blocks.
    Block
    Print Engine PCU PEP controller Provides external CPU with the means to read
    Pipeline and write PEP Unit registers, and read and
    (PEP) write DRAM in single 32-bit chunks.
    CDU Contone decoder unit Expands JPEG compressed contone layer and
    writes decompressed contone to DRAM
    CFU Contone FIFO Unit Provides line buffering between CDU and HCU
    LBD Lossless Bi-level Expands compressed bi-level layer.
    Decoder
    SFU Spot FIFO Unit Provides line buffering between LBD and HCU
    TE Tag encoder Encodes tag data into line of tag dots.
    TFU Tag FIFO Unit Provides tag data storage between TE and HCU
    HCU Halftoner compositor Dithers contone layer and composites the bi-
    unit level spot 0 and position tag dots.
    DNC Dead Nozzle Compensates for dead nozzles by color
    Compensator redundancy and error diffusing dead nozzle
    data into surrounding dots.
    DWU Dotline Writer Unit Writes out the 6 channels of dot data for a
    given printline to the line store DRAM
    LLU Line Loader Unit Reads the expanded page image from line
    store, formatting the data appropriately for the
    bi-lithic printhead.
    PHI PrintHead Interface Is responsible for sending dot data to the bi-
    lithic printheads and for providing line
    synchronization between multiple SoPECs.
    Also provides test interface to printhead such
    as temperature monitoring and Dead Nozzle
    Identification.
  • 1.5 General Purpose IO (GPIO) 1.5.1 13.1 Overview
  • [0490]
    The General Purpose IO block (GPIO) is responsible for control and interfacing of GPIO pins to the rest of the SoPEC system. It provides easily programmable control logic to simplify control of GPIO functions. In all there are 32 GPIO pins of which any pin can assume any output or input function. Possible output functions are
      • 4 Stepper Motor control Outputs
      • 12 Brushless DC Motor Control Output (total of 2 different controllers each with 6 outputs)
      • 4 General purpose high drive pulsed outputs capable of driving LEDs.
      • 4 Open drain IOs used for LSS interfaces
      • 4 Normal drive low impedance IOs used for the ISI interface in Multi-SoPEC mode
  • [0496]
    Each of the pins can be configured in either input or output mode, each pin is independently controlled. A programmable de-glitching circuit exists for a fixed number of input pins. Each input is a schmidt trigger to increase noise immunity should the input be used without the de-glitch circuit.
  • 1.6 ROM Block 1.6.1 Overview
  • [0497]
    The ROM block interfaces to the CPU bus and contains the SoPEC boot code. The ROM block consists of the CPU bus interface, the ROM macro and the ChipID macro. The current ROM size is 16 KBytes implemented as a 4096×32 macro. Access to the ROM is not cached because the CPU enjoys fast (no more than one cycle slower than a cache access), unarbitrated access to the ROM.
  • [0498]
    Each SoPEC device is required to have a unique ChipID which is set by blowing fuses at manufacture. IBM's 300 mm ECID macro and a custom 112-bit ECID macro are used to implement the ChipID offering 224-bits of laser fuses. The exact number of fuse bits to be used for the ChipID will be determined later but all bits are made available to the CPU. The ECID macros allows all 224 bits to be read out in parallel and the ROM block will make all 224 bits available in the FuseChipID[N] registers which are readable by the CPU in supervisor mode only.
  • 1.7 Power Safe Storage (PSS) Block 1.7.1 Overview
  • [0499]
    The PSS block provides 128 bytes of storage space that will maintain its state when the rest of the SoPEC device is in sleep mode. The PSS is expected to be used primarily for the storage of decrypted signatures associated with downloaded programmed code but it can also be used to store any information that needs to survive sleep mode (e.g. configuration details). Note that the signature digest only needs to be stored in the PSS before entering sleep mode and the PSS can be used for temporary storage of any data at all other times.
  • [0500]
    Prior to entering sleep mode the CPU should store all of the information it will need on exiting sleep mode in the PSS. On emerging from sleep mode the boot code in ROM will read the ResetSrc register in the CPR block to determine which reset source caused the wakeup. The reset source information indicates whether or not the PSS contains valid stored data, and the PSS data determines the type of boot sequence to execute. If for any reason a full power-on boot sequence should be performed (e.g. the printer driver has been updated) then this is simply achieved by initiating a full software reset.
  • [0501]
    Note that a reset or a powerdown (powerdown is implemented by clock gating) of the PSS block will not clear the contents of the 128 bytes of storage. If clearing of the PSS storage is required, then the CPU must write to each location individually.
  • 1.8 Low Speed Serial Interface (LSS) 1.8.1 19.1 Overview
  • [0502]
    The Low Speed Serial Interface (LSS) provides a mechanism for the internal SoPEC CPU to communicate with external QA chips via two independent LSS buses. The LSS communicates through the GPIO block to the QA chips. This allows the QA chip pins to be reused in multi-SoPEC environments. The LSS Master system-level interface is illustrated in FIG. 75. Note that multiple QA chips are allowed on each LSS bus.
  • 1.9 PEP Controller Unit (PCU) 1.9.1 Overview
  • [0503]
    The PCU has three functions:
      • The first is to act as a bus bridge between the CPU-bus and the PCU-bus for reading and writing PEP configuration registers.
      • The second is to support page banding by allowing the PEP blocks to be reprogrammed between bands by retrieving commands from DRAM instead of being programmed directly by the CPU.
      • The third is to send register debug information to the RDU, within the CPU subsystem, when the PCU is in Debug Mode.
    1.10 Contone Decoder Unit (CDU) 1.10.1 Overview
  • [0507]
    The Contone Decoder Unit (CDU) is responsible for performing the optional decompression of the contone data layer.
  • [0508]
    The input to the CDU is up to 4 planes of compressed contone data in JPEG interleaved format. This will typically be 3 planes, representing a CMY contone image, or 4 planes representing a CMYK contone image. The CDU must support a page of A4 length (11.7 inches) and Letter width (8.5 inches) at a resolution of 267 ppi in 4 colors and a print speed of 1 side per 2 seconds.
  • [0509]
    The CDU and the other page expansion units support the notion of page banding. A compressed page is divided into one or more bands, with a number of bands stored in memory. As a band of the page is consumed for printing a new band can be downloaded. The new band may be for the current page or the next page. Band-finish interrupts have been provided to notify the CPU of free buffer space.
  • [0510]
    The compressed contone data is read from the on-chip DRAM. The output of the CDU is the decompressed contone data, separated into planes. The decompressed contone image is written to a circular buffer in DRAM with an expected minimum size of 12 lines and a configurable maximum. The decompressed contone image is subsequently read a line at a time by the CFU, optionally color converted, scaled up to 1600 ppi and then passed on to the HCU for the next stage in the printing pipeline. The CDU also outputs a cdu_finishedband control flag indicating that the CDU has finished reading a band of compressed contone data in DRAM and that area of DRAM is now free. This flag is used by the PCU and is available as an interrupt to the CPU.
  • 1.11 Contone FIFO Unit (CFU) 1.11.1 Overview
  • [0511]
    The Contone FIFO Unit (CFU) is responsible for reading the decompressed contone data layer from the circular buffer in DRAM, performing optional color conversion from YCrCb to RGB followed by optional color inversion in up to 4 color planes, and then feeding the data on to the HCU. Scaling of data is performed in the horizontal and vertical directions by the CFU so that the output to the HCU matches the printer resolution. Non-integer scaling is supported in both the horizontal and vertical directions. Typically, the scale factor will be the same in both directions but may be programmed to be different.
  • 1.12 Lossless Bi-level Decoder (LBD) 1.12.1 Overview
  • [0512]
    The Lossless Bi-level Decoder (LBD) is responsible for decompressing a single plane of bi-level data. In SoPEC bi-level data is limited to a single spot color (typically black for text and line graphics).
  • [0513]
    The input to the LBD is a single plane of bi-level data, read as a bitstream from DRAM. The LBD is programmed with the start address of the compressed data, the length of the output (decompressed) line, and the number of lines to decompress. Although the requirement for SoPEC is to be able to print text at 10:1 compression, the LBD can cope with any compression ratio if the requested DRAM access is available. A pass-through mode is provided for 1:1 compression. Ten-point plain text compresses with a ratio of about 50:1. Lossless bi-level compression across an average page is about 20:1 with 10:1 possible for pages which compress poorly.
  • [0514]
    The output of the LBD is a single plane of decompressed bi-level data. The decompressed bi-level data is output to the SFU (Spot FIFO Unit), and in turn becomes an input to the HCU (Halftoner/Compositor unit) for the next stage in the printing pipeline. The LBD also outputs a lbd_finishedband control flag that is used by the PCU and is available as an interrupt to the CPU.
  • 1.13 Halftoner Compositor Unit (HCU) 1.13.1 Overview
  • [0515]
    The Halftoner Compositor Unit (HCU) produces dots for each nozzle in the destination printhead taking account of the page dimensions (including margins). The spot data and tag data are received in bi-level form while the pixel contone data received from the CFU must be dithered to a bi-level representation. The resultant 6 bi-level planes for each dot position on the page are then remapped to 6 output planes and output dot at a time (6 bits) to the next stage in the printing pipeline, namely the dead nozzle compensator (DNC).
  • 1.13.2 Data flow
  • [0516]
    FIG. 230 shows a simple dot data flow high level block diagram of the HCU. The HCU reads contone data from the CFU, bi-level spot data from the SFU, and bi-level tag data from the TFU. Dither matrices are read from the DRAM via the DIU. The calculated output dot (6 bits) is read by the DNC.
  • [0517]
    The HCU is given the page dimensions (including margins), and is only started once for the page. It does not need to be programmed in between bands or restarted for each band. The HCU will stall appropriately if its input buffers are starved. At the end of the page the HCU will continue to produce 0 for all dots as long as data is requested by the units further down the pipeline (this allows later units to conveniently flush pipelined data).
  • [0518]
    The HCU performs a linear processing of dots calculating the 6-bit output of a dot in each cycle. The mapping of 6 calculated bits to 6 output bits for each dot allows for such example mappings as compositing of the spot0 layer over the appropriate contone layer (typically black), the merging of CMY into K (if K is present in the printhead), the splitting of K into CMY dots if there is no K in the printhead, and the generation of a fixative output bitstream.
  • 1.13.3 DRAM storage requirements
  • [0519]
    SoPEC allows for a number of different dither matrix configurations up to 256 bytes wide. The dither matrix is stored in DRAM. Using either a single or double-buffer scheme a line of the dither matrix must be read in by the HCU over a SoPEC line time. SoPEC must produce 13824 dots per line for A4/Letter printing which takes 13824 cycles.
  • [0520]
    The following give the storage and bandwidths requirements for some of the possible configurations of the dither matrix.
      • 4 Kbyte DRAM storage required for one 64×64 (preferred) byte dither matrix
      • 6.25 Kbyte DRAM storage required for one 80×80 byte dither matrix
      • 16 Kbyte DRAM storage required for four 64×64 byte dither matrices
      • 64 Kbyte DRAM storage required for one 256×256 byte dither matrix
  • [0525]
    It takes 4 or 8 read accesses to load a line of dither matrix into the dither matrix buffer, depending on whether we're using a single or double buffer (configured by DoubleLineBuff register).
  • 1.13.4 Implementation 1.13.4.1 Control Unit
  • [0526]
    The control unit is responsible for controlling the overall flow of the HCU. It is responsible for determining whether or not a dot will be generated in a given cycle, and what dot will actually be generated—including whether or not the dot is in a margin area, and what dither cell values should be used at the specific dot location. A block diagram of the control unit is shown in FIG. 232.
  • [0527]
    The inputs to the control unit are a number of avail flags specifying whether or not a given dotgen unit is capable of supplying ‘real’ data in this cycle. The term ‘real’ refers to data generated from external sources, such as contone line buffers, bi-level line buffers, and tag plane buffers. Each dotgen unit informs the control unit whether or not a dot can be generated this cycle from real data. It must also check that the DNC is ready to receive data.
  • [0528]
    The contone/spot margin unit is responsible for determining whether the current dot coordinate is within the target contone/spot margins, and the tag margin unit is responsible for determining whether the current dot coordinate is within the target tag margins.
  • [0529]
    The dither matrix table interface provides the interface to DRAM for the generation of dither cell values that are used in the halftoning process in the contone dotgen unit.
  • 1.13.4.1.1 Determine Advdot
  • [0530]
    The HCU does not always require contone planes, bi-level or tag planes in order to produce a page. For example, a given page may not have a bi-level layer, or a tag layer. In addition, the contone and bi-level parts of a page are only required within the contone and bi-level page margins, and the tag part of a page is only required within the tag page margins. Thus output dots can be generated without contone, bi-level or tag data before the respective top margins of a page has been reached, and 0s are generated for all color planes after the end of the page has been reached (to allow later stages of the printing pipeline to flush).
  • [0531]
    Consequently the HCU has an AvailMask register that determines which of the various input avail flags should be taken notice of during the production of a page from the first line of the target page, and a TMMask register that has the same behaviour, but is used in the lines before the target page has been reached (i.e. inside the target top margin area). The dither matrix mask bit TMask[0] is the exception, it applies to all margins areas not just the top margin. Each bit in the AvailMask refers to a particular avail bit: if the bit in the AvailMask register is set, then the corresponding avail bit must be 1 for the HCU to advance a dot. The bit to avail correspondence is shown in Table 194. Care should be taken with TMMask—if the particular data is not available after the top margin has been reached, then the HCU will stall. Note that the avail bits for contone and spot colors are ANDed with in_target_page after the target page area has been reached to allow dot production in the contone/spot margin areas without needing any data in the CFU and SFU. The avail bit for tag color is ANDed with in_tag_target_page after the target tag page area has been reached to allow dot production in the tag margin areas without needing any data in the TFU.
  • [0532]
    Each of the input avail bits is processed with its appropriate mask bit and the after_top_margin flag (note the dither matrix is the exception it is processed with in_target_page). The output bits are ANDed together along with Go and output_buff_full (which specifies whether the output buffer is ready to receive a dot in this cycle) to form the output bit advdot. We also generate wr_advdot. In this way, if the output buffer is full or any of the specified avail flags is clear, the HCU will stall. When the end of the page is reached, in_page will be deasserted and the HCU will continue to produce 0 for all dots as long as the DNC requests data. A block diagram of the determine advdot unit is shown in FIG. 233.
  • [0533]
    The advance dot block also determines if current page needs dither matrix, it indicates to the dither matrix table interface block via the dm_read_enable signal. If no dither is required in the margins or in the target page then dm_read_enable will be 0 and no dither will be read in for this page.
  • [0000]
    1.13.4.1.2 Position Unit The position unit is responsible for outputting the position of the current dot (curr_pos, curr_line) and whether or not this dot is the last dot of a line (advline). Both curr_pos and curr_line are set to 0 at reset or when Go transitions from 0 to 1. The position unit relies on the advdot input signal to advance through the dots on a page. Whenever an advdot pulse is received, curr_pos gets incremented. If curr_pos equals max_dot then an advline pulse is generated as this is the last dot in a line, curr_line gets incremented, and the curr_pos is reset to 0 to start counting the dots for the next line.
  • [0534]
    The position unit also generates a filtered version of advline called dm_advline to indicate to the dither matrix pointers to increment to the next line. The dm_advline is only incremented when dither is required for that line.
  • 1.13.4.1.3 Margin Unit
  • [0535]
    The responsibility of the margin unit is to determine whether the specific dot coordinate is within the page at all, within the target page or in a margin area (see FIG. 234). This unit is instantiated for both the contone/spot margin unit and the tag margin unit.
  • [0536]
    The margin unit takes the current dot and line position, and returns three flags.
      • the first, in_page is 1 if the current dot is within the page, and 0 if it is outside the page.
      • the second flag, in target_page, is 1 if the dot coordinate is within the target page area of the page, and 0 if it is within the target top/left/bottom/right margins.
      • the third flag, after_top_margin, is 1 if the current dot is below the target top margin, and 0 if it is within the target top margin.
  • [0540]
    A block diagram of the margin unit is shown in FIG. 235.
  • 1.13.4.1.4 Dither Matrix Table Interface
  • [0541]
    The dither matrix table interface provides the interface to DRAM for the generation of dither cell values that are used in the halftoning process in the contone dotgen unit. The control flag dm_read_enable enables the reading of the dither matrix table line structure from DRAM. If dm_read_enable is 0, the dither matrix is not specified in DRAM and no DRAM accesses are attempted. The dither matrix table interface has an output flag dm_avail which specifies if the current line of the specified matrix is available. The HCU can be directed to stall when dm_avail is 0 by setting the appropriate bit in the HCU's AvailMask or TMMask registers. When dm_avail is 0 the value in the DitherConstant register is used as the dither cell values that are output to the contone dotgen unit.
  • [0542]
    The dither matrix table interface consists of a state machine that interfaces to the DRAM interface, a dither matrix buffer that provides dither matrix values, and a unit to generate the addresses for reading the buffer. FIG. 236 shows a block diagram of the dither matrix table interface.
  • 1.13.4.1.5 Dither Data Structure in DRAM
  • [0543]
    The dither matrix is stored in DRAM in 256-bit words, transferred to the HCU in 64-bit words and consumed by the HCU in bytes. Table 195 shows the 64-bit words mapping to 256-bit word addresses, and Table 196 shows the 8-bits dither value mapping in the 64-bits word.
  • [0544]
    When the HCU first requests data from DRAM, the 64-bits word transfer order will be D0,D1,D2,D3. On the second request the transfer order will be D4,D5,D6,D7 and so on for other requests.
  • 1.13.4.1.5.1 Dither Matrix Buffer
  • [0545]
    The state machine loads dither matrix table data a line at a time from DRAM and stores it in a buffer. A single line of the dither matrix is either 256 or 128 8-bit entries, depending on the programmable bit DoubleLineBuf. If this bit is enabled, a double-buffer mechanism is employed such that while one buffer is read from for the current line's dither matrix data (8 bits representing a single dither matrix entry), the other buffer is being written to with the next line's dither matrix data (64-bits at a time). Alternatively, the single buffer scheme can be used, where the data must be loaded at the end of the line, thus incurring a delay.
  • [0546]
    The single/double buffer is implemented using a 256 byte 3-port register array, two reads, one write port, with the reads clocked at double the system clock rate (320 MHz) allowing 4 reads per clock cycle.
  • [0547]
    The dither matrix buffer unit also provides the mechanism for keeping track of the current read and write buffers, and providing the mechanism such that a buffer cannot be read from until it has been written to. In this case, each buffer is a line of the dither matrix, i.e. 256 or 128 bytes.
  • [0548]
    The dither matrix buffer maintains a read and write pointer for the dither matrix. The output value dm_avail is derived by comparing the read and write pointers to determine when the dither matrix is not empty. The write pointer wr_adr is incremented each time a 64-bit word is written to the dither matrix buffer and the read pointer rd_ptr is incremented each time dm_advline is received. If double_line_buf is 0 the rd_ptr will increment by 2, otherwise it will increment by 1. If the dither matrix buffer is full then no further writes will be allowed (buff_full=1), or if the buffer is empty no further buffer reads are allowed (buff_emp=1).
  • [0549]
    The read addresses are byte aligned and are generated by the read address generator. A single dither matrix entry is represented by 8 bits and an entry is read for each of the four contone planes in parallel. If double buffer is used (double_line_buf=1) the read address is derived from 7-bit address from the read address generator and 1-bit from the read pointer. If double_line_buf=0 then the read address is the full 8-bits from the read address generator.
  • 1.13.4.1.5.2 Read Address Generator
  • [0550]
    For each contone plane there is a initial, lower and upper index to be used when reading dither cell values from the dither matrix double buffer. The read address for each plane is used to select a byte from the current 256-byte read buffer. When Go gets set (0 to 1 transition), or at the end of a line, the read addresses are set to their corresponding initial index. Otherwise, the read address generator relies on advdot to advance the addresses within the inclusive range specified the lower and upper indices.
  • 1.13.4.1.5.3 State Machine
  • [0551]
    The dither matrix is read from DRAM in single 256-bit accesses, receiving the data from the DIU over 4 clock cycles (64-bits per cycle). Read accesses to DRAM are implemented by means of the state machine described in FIG. 238.
  • [0552]
    All counters and flags should be cleared after reset or when Go transitions from 0 to 1. While the Go bit is 1, the state machine relies on the dm_read_enable bit to tell it whether to attempt to read dither matrix data from DRAM. When dm_read_enable is clear, the state machine does nothing and remains in the idle state. When dm_read_enable is set, the state machine continues to load dither matrix data, 256-bits at a time (received over 4 clock cycles, 64 bits per cycle), while there is space available in the dither matrix buffer, (buff_full !=1).
  • [0553]
    The read address and line_start_adr are initially set to start_dm_adr. The read address gets incremented after each read access. It takes 4 or 8 read accesses to load a line of dither matrix into the dither matrix buffer, depending on whether we're using a single or double buffer. A count is kept of the accesses to DRAM. When a read access completes and access_count equals 3 or 7, a line of dither matrix has just been loaded from and the read address is updated to line_start_adr plus line_increment so it points to the start of the next line of dither matrix. (line_start_adr is also updated to this value). If the read address equals end_dm_adr then the next read address will be start_dm_adr, thus the read address wraps to point to the start of the area in DRAM where the dither matrix is stored.
  • [0554]
    The write address for the dither matrix buffer is implemented by means of a modulo-32 counter that is initially set to 0 and incremented when diu_hcu_rvalid is asserted.
  • 1.13.4.2 Contone Dotgen Unit
  • [0555]
    The contone dotgen unit is responsible for producing a dot in up to 4 color planes per cycle. The contone dotgen unit also produces a cp_avail flag which specifies whether or not contone pixels are currently available, and the output hcu_cfu_advdot to request the CFU to provide the next contone pixel in up to 4 color planes.
  • [0556]
    The block diagram for the contone dotgen unit is shown in FIG. 239.
  • [0557]
    A dither unit provides the functionality for dithering a single contone plane. The contone image is only defined within the contone/spot margin area. As a result, if the input flag in_target_page is 0, then a constant contone pixel value is used for the pixel instead of the contone plane.
  • [0558]
    The resultant contone pixel is then halftoned. The dither value to be used in the halftoning process is provided by the control data unit. The halftoning process involves a comparison between a pixel value and its corresponding dither value. If the 8-bit contone value is greater than or equal to the 8-bit dither matrix value a 1 is output. If not, then a 0 is output. This means each entry in the dither matrix is in the range 1-255 (0 is not used).
  • [0559]
    Note that constant use is dependant on the in_target_page signal only, if in_target_page is 1 then the cfu_hcu_c*_data should be allowed to pass through, regardless of the stalling behaviour or the avail_mask[1] setting. This allows a constant value to be setup on the CFU output data, and the use of different constants while inside and outside the target page. The hcu_cfu_advdot will always be zero if the avail_mask[1] is zero.
  • 1.13.4.3 Spot Dotgen Unit
  • [0560]
    The spot dotgen unit is responsible for producing a dot of bi-level data per cycle. It deals with bi-level data (and therefore does not need to halftone) that comes from the LBD via the SFU. Like the contone layer, the bi-level spot layer is only defined within the contone/spot margin area. As a result, if input flag in_target_page is 0, then a constant dot value (typically this would be 0) is used for the output dot.
  • [0561]
    The spot dotgen unit also produces a s_avail flag which specifies whether or not spot dots are currently available for this spot plane, and the output hcu_sfu_advdot to request the SFU to provide the next bi-level data value.
  • 1.13.4.4 Tag Dotgen Unit
  • [0562]
    This unit is very similar to the spot dotgen unit in that it deals with bi-level data, in this case from the TE via the TFU. The tag layer is only defined within the tag margin area. As a result, if input flag in_tag_target_page is 0, then a constant dot value, tp_constant (typically this would be 0), is used for the output dot. The tagplane dotgen unit also produces a tp_avail flag which specifies whether or not tag dots are currently available for the tagplane, and the output hcu_tfu_advdot to request the TFU to provide the next bi-level data value.
  • [0563]
    The hcu_tfu_advdot generation is similar to the SFU and CFU, except it depends only on in_target_page and advdot. It does not take into account the avail mask when inside the target page.
  • 1.13.4.5 Dot Reorg Unit
  • [0564]
    The dot reorg unit provides a means of mapping the bi-level dithered data, the spot0 color, and the tag data to output inks in the actual printhead. Each dot reorg unit takes a set of 6 1-bit inputs and produces a single bit output that represents the output dot for that color plane.
  • [0565]
    The output bit is a logical combination of any or all of the input bits. This allows the spot color to be placed in any output color plane (including infrared for testing purposes), black to be merged into cyan, magenta and yellow (in the case of no black ink in the Memjet printhead), and tag dot data to be placed in a visible plane. An output for fixative can readily be generated by simply combining desired input bits.
  • [0566]
    The dot reorg unit contains a 64-bit lookup to allow complete freedom with regards to mapping. Since all possible combinations of input bits are accounted for in the 64 bit lookup, a given dot reorg unit can take the mapping of other reorg units into account. For example, a black plane reorg unit may produce a 1 only if the contone plane 3 or spot color inputs are set (this effectively composites black bi-level over the contone). A fixative reorg unit may generate a 1 if any 2 of the output color planes is set (taking into account the mappings produced by the other reorg units).
  • [0567]
    If dead nozzle replacement is to be used, the dot reorg can be programmed to direct the dots of the specified color into the main plane, and 0 into the other. If a nozzle is then marked as dead in the DNC, swapping the bits between the planes will result in 0 in the dead nozzle, and the required data in the other plane.
  • [0568]
    If dead nozzle replacement is to be used, and there are no tags, the TE can be programmed with the position of dead nozzles and the resultant pattern used to direct dots into the specified nozzle row. If only fixed background TFS is to be used, a limited number of nozzles can be replaced. If variable tag data is to be used to specify dead nozzles, then large numbers of dead nozzles can be readily compensated for.
  • [0569]
    The dot reorg unit can be used to average out the nozzle usage when two rows of nozzles share the same ink and tag encoding is not being used. The TE can be programmed to produce a regular pattern (e.g. 0101 on one line, and 1010 on the next) and this pattern can be used as a directive as to direct dots into the specified nozzle row.
  • [0570]
    Each reorg unit contains a 64-bit IOMapping value programmable as two 32-bit HCU registers, and a set of selection logic based on the 6-bit dot input (26=64 bits), as shown in FIG. 240.
  • 1.13.4.6 Output Buffer
  • [0571]
    The output buffer de-couples the stalling behaviour of the feeder units from the stalling behaviour of the DNC. The larger the buffer the greater de-coupling. Currently the output buffer size is 2, but could be increased if needed at the cost of extra area.
  • [0572]
    If the Go bit is set to 0 no read or write of the output buffer is permitted. On a low to high transition of the Go bit the contents of the output buffer are cleared.
  • [0573]
    The output buffer also implements the interface logic to the DNC. If there is data in the output buffer the hcu_dnc_avail signal will be 1, otherwise is will be 0. If both hcu_dnc_avail and dnc_hcu_ready are 1 then data is read from the output buffer.
  • [0574]
    On the write side if there is space available in the output buffer the logic indicates to the control unit via the output_buff_full signal. The control unit will then allow writes to the output buffer via the wr_advdot signal. If the writes to the output buffer are after the end of a page (indicated by in_page equal to 0) then all dots written into the output buffer are set to zero.
  • 1.13.4.6.1 HCU to DNC Interface
  • [0575]
    FIG. 241 shows the timing diagram and representative logic of the HCU to DNC interface. The hcu_dnc_avail signal indicate to the DNC that the HCU has data available. The dnc_hcu_ready signal indicates to the HCU that the DNC is ready to accept data. When both signals are high data is transferred from the HCU to the DNC. Once the HCU indicates it has data available (setting the hcu_dnc_avail signal high) it can only set the hcu_dnc_avail low again after a dot is accepted by the DNC.
  • 1.13.4.7 Feeder to HCU interfaces
  • [0576]
    FIG. 242 shows the feeder unit to HCU interface timing diagram, and FIG. 243 shows representative logic of the interface with the register positions. sfu_hcu_data and sfu_hcu_avail are always registered while the sfu_hcu_advdot is not. The hcu_sfu_avail signal indicates to the HCU that the feeder unit has data available, and sfu_hcu_advdot indicates to the feeder unit that the HCU has captured the last dot. The HCU can never produce an advance dot pulse while the avail is low. The diagrams show the example of the SFU to HCU interface, but the same interface is used for the other feeder units TFU and CFU.
  • 1.14 Dead Nozzle Compensator (DNC) 1.14.1 Overview
  • [0577]
    The Dead Nozzle Compensator (DNC) is responsible for adjusting Memjet dot data to take account of non-functioning nozzles in the Memjet printhead. Input dot data is supplied from the HCU, and the corrected dot data is passed out to the DWU. The high level data path is shown by the block diagram in FIG. 244.
  • [0578]
    The DNC compensates for a dead nozzles by performing the following operations:
      • Dead nozzle removal, i.e. turn the nozzle off
      • Ink replacement by direct substitution i.e. K->K
      • Ink replacement by indirect substitution i.e. K->CMY
      • Error diffusion to adjacent nozzles
      • Fixative corrections
  • [0584]
    The DNC is required to efficiently support up to 5% dead nozzles, under the expected DRAM bandwidth allocation, with no restriction on where dead nozzles are located and handle any fixative correction due to nozzle compensations. Performance must degrade gracefully after 5% dead nozzles.
  • 1.14.2 Dead Nozzle Identification
  • [0585]
    Dead nozzles are identified by means of a position value and a mask value. Position information is represented by a 10-bit delta encoded format, where the 10-bit value defines the number of dots between dead nozzle columns4. With the delta information it also reads the 6-bit dead nozzle mask (dn_mask) for the defined dead nozzle position. Each bit in the dn_mask corresponds to an ink plane. A set bit indicates that the nozzle for the corresponding ink plane is dead. The dead nozzle table format is shown in FIG. 245. The DNC reads dead nozzle information from DRAM in single 256-bit accesses. A 10-bit delta encoding scheme is chosen so that each table entry is 16 bits wide, and 16 entries fit exactly in each 256-bit read. Using 10-bit delta encoding means that the maximum distance between dead nozzle columns is 1023 dots. It is possible that dead nozzles may be spaced further than 1023 dots from each other, so a null dead nozzle identifier is required. A null dead nozzle identifier is defined as a 6-bit do mask of all zeros. These null dead nozzle identifiers should also be used so that: 4for a 10-bit delta value of d, if the current column n is a dead nozzle column then the next dead nozzle column is given by n+(d+1).
      • the dead nozzle table is a multiple of 16 entries (so that it is aligned to the 256-bit DRAM locations)
      • the dead nozzle table spans the complete length of the line, i.e. the first entry dead nozzle table should have a delta from the first nozzle column in a line and the last entry in the dead nozzle table should correspond to the last nozzle column in a line.
  • [0588]
    Note that the DNC deals with the width of a page. This may or may not be the same as the width of the printhead (the PHI may introduce some margining to the page so that its dot output matches the width of the printhead). Care must be taken when programming the dead nozzle table so that dead nozzle positions are correctly specified with respect to the page and printhead.
  • 1.14.3 DRAM Storage and Bandwidth Requirement
  • [0589]
    The memory required is largely a factor of the number of dead nozzles present in the printhead (which in turn is a factor of the printhead size). The DNC is required to read a 16-bit entry from the dead nozzle table for every dead nozzle.
  • 1.14.4 Nozzle Compensation
  • [0590]
    The DNC receives 6 bits of dot information every cycle from the HCU, 1 bit per color plane. When the dot position corresponds to a dead nozzle column, the associated 6-bit dn_mask indicates which ink plane(s) contains a dead nozzle(s). The DNC first deletes dots destined for the dead nozzle. It then replaces those dead dots, either by placing the data destined for the dead nozzle into an adjacent ink plane (direct substitution) or into a number of ink planes (indirect substitution). After ink replacement, if a dead nozzle is made active again then the DNC performs error diffusion. Finally, following the dead nozzle compensation mechanisms the fixative, if present, may need to be adjusted due to new nozzles being activated, or dead nozzles being removed.
  • 1.14.4.1 Dead Nozzle Removal
  • [0591]
    If a nozzle is defined as dead, then the first action for the DNC is to turn off (zeroing) the dot data destined for that nozzle. This is done by a bit-wise ANDing of the inverse of the do mask with the dot value.
  • 1.14.4.2 Ink Replacement
  • [0592]
    Ink replacement is a mechanism where data destined for the dead nozzle is placed into an adjacent ink plane of the same color (direct substitution, i.e. K->Kalternative), or placed into a number of ink planes, the combination of which produces the desired color (indirect substitution, i.e. K->CMY). Ink replacement is performed by filtering out ink belonging to nozzles that are dead and then adding back in an appropriately calculated pattern. This two step process allows the optional re-inclusion of the ink data into the original dead nozzle position to be subsequently error diffused. In the general case, fixative data destined for a dead nozzle should not be left active intending it to be later diffused.
  • [0593]
    The ink replacement mechanism has 6 ink replacement patterns, one per ink plane, programmable by the CPU. The dead nozzle mask is ANDed with the dot data to see if there are any planes where the dot is active but the corresponding nozzle is dead. The resultant value forms an enable, on a per ink basis, for the ink replacement process. If replacement is enabled for a particular ink, the values from the corresponding replacement pattern register are ORed into the dot data. The output of the ink replacement process is then filtered so that error diffusion is only allowed for the planes in which error diffusion is enabled. The output of the ink replacement logic is ORed with the resultant dot after dead nozzle removal. See Figure n page565 on page 18 for implementation details.
  • [0594]
    For example if we consider the printhead color configuration C, M, Y, K1, K2, IR and the input dot data from the HCU is b101100. Assuming that the K1 ink plane and IR ink plane for this position are dead so the dead nozzle mask is b000101. The DNC first removes the dead nozzle by zeroing the K1 plane to produce b101000. Then the dead nozzle mask is ANDed with the dot data to give b000100 which selects the ink replacement pattern for K1 (in this case the ink replacement pattern for K1 is configured as b000010, i.e. ink replacement into the K2 plane). Providing error diffusion for K2 is enabled, the output from the ink replacement process is b000010. This is ORed with the output of dead nozzle removal to produce the resultant dot b101010. As can be seen the dot data in the defective K1 nozzle was removed and replaced by a dot in the adjacent K2 nozzle in the same dot position, i.e. direct substitution.
  • [0595]
    In the example above the K1 ink plane could be compensated for by indirect substitution, in which case ink replacement pattern for K1 would be configured as b111000 (substitution into the CMY color planes), and this is ORed with the output of dead nozzle removal to produce the resultant dot b111000. Here the dot data in the defective K1 ink plane was removed and placed into the CMY ink planes.
  • 1.14.4.3 Error Diffusion
  • [0596]
    Based on the programming of the lookup table the dead nozzle may be left active after ink replacement. In such cases the DNC can compensate using error diffusion. Error diffusion is a mechanism where dead nozzle dot data is diffused to adjacent dots.
  • [0597]
    When a dot is active and its destined nozzle is dead, the DNC will attempt to place the data into an adjacent dot position, if one is inactive. If both dots are inactive then the choice is arbitrary, and is determined by a pseudo random bit generator. If both neighbor dots are already active then the bit cannot be compensated by diffusion.
  • [0598]
    Since the DNC needs to look at neighboring dots to determine where to place the new bit (if required), the DNC works on a set of 3 dots at a time. For any given set of 3 dots, the first dot received from the HCU is referred to as dot A, and the second as dot B, and the third as dot C. The relationship is shown in FIG. 246.
  • [0599]
    For any given set of dots ABC, only B can be compensated for by error diffusion if B is defined as dead. A 1 in dot B will be diffused into either dot A or dot C if possible. If there is already a 1 in dot A or dot C then a 1 in dot B cannot be diffused into that dot.
  • [0600]
    The DNC must support adjacent dead nozzles. Thus if dot A is defined as dead and has previously been compensated for by error diffusion, then the dot data from dot B should not be diffused into dot A. Similarly, if dot C is defined as dead, then dot data from dot B should not be diffused into dot C.
  • [0601]
    Error diffusion should not cross line boundaries. If dot B contains a dead nozzle and is the first dot in a line then dot A represents the last dot from the previous line. In this case an active bit on a dead nozzle of dot B should not be diffused into dot A. Similarly, if dot B contains a dead nozzle and is the last dot in a line then dot C represents the first dot of the next line. In this case an active bit on a dead nozzle of dot B should not be diffused into dot C.
  • [0602]
    Thus, as a rule, a 1 in dot B cannot be diffused into dot A if
      • a 1 is already present in dot A,
      • dot A is defined as dead,
      • or dot A is the last dot in a line.
  • [0606]
    Similarly, a 1 in dot B cannot be diffused into dot C if
      • a 1 is already present in dot C,
      • dot C is defined as dead,
      • or dot C is the first dot in a line.
  • [0610]
    If B is defined to be dead and the dot value for B is 0, then no compensation needs to be done and dots A and C do not need to be changed.
  • [0611]
    If B is defined to be dead and the dot value for B is 1, then B is changed to 0 and the DNC attempts to place the 1 from B into either A or C:
      • If the dot can be placed into both A and C, then the DNC must choose between them. The preference is given by the current output from the random bit generator, 0 for “prefer left” (dot A) or 1 for “prefer right” (dot C).
      • If dot can be placed into only one of A and C, then the 1 from B is placed into that position.
      • If dot cannot be placed into either one of A or C, then the DNC cannot place the dot in either position.
    1.14.4.4 Fixative Correction
  • [0615]
    After the dead nozzle compensation methods have been applied to the dot data, the fixative, if present, may need to be adjusted due to new nozzles being activated, or dead nozzles being removed. For each output dot the DNC determines if fixative is required (using the FixativeRequiredMask register) for the new compensated dot data word and whether fixative is activated already for that dot. For the DNC to do so it needs to know the color plane that has fixative, this is specified by the FixativeMask1 configuration register.
  • [0616]
    The DNC also allows the specification of another fixative plane, specified by the FixativeMask2 configuration register, with FixativeMask1 having the higher priority over FixativeMask2. When attempting to add fixative the DNC first tries to add it into the planes defined by FixativeMask1. However, if any of these planes is dead then it tries to add fixative by placing it into the planes defined by FixativeMask2.
  • [0617]
    Note that the fixative defined by FixativeMask1 and FixativeMask2 could possibly be multi-part fixative, i.e. 2 bits could be set in FixativeMask1 with the fixative being a combination of both inks
  • 1.14.5 Implementation
  • [0618]
    A block diagram of the DNC is shown in FIG. 247.
  • 1.14.5.1 Ink Replacement Unit
  • [0619]
    FIG. 248 shows a sub-block diagram for the ink replacement unit.
  • 1.14.5.1.1 Control Unit
  • [0620]
    The control unit is responsible for reading the dead nozzle table from DRAM and making it available to the DNC via the dead nozzle FIFO. The dead nozzle table is read from DRAM in single 256-bit accesses, receiving the data from the DIU over 4 clock cycles (64-bits per cycle). Reading from DRAM is implemented by means of the state machine shown in FIG. 249.
  • [0621]
    All counters and flags should be cleared after reset. When Go transitions from 0 to 1 all counters and flags should take their initial value. While the Go bit is 1, the state machine requests a read access from the dead nozzle table in DRAM provided there is enough space in its FIFO.
  • [0622]
    A modulo-4 counter, rd_count, is used to count each of the 64-bits received in a 256-bit read access. It is incremented whenever diu_dnc_rvalid is asserted. When Go is 1, dn_table_radr is set to dn_table_start_adr. As each 64-bit value is returned, indicated by diu_dnc_rvalid being asserted, dn_table_radr is compared to dn_table_end_adr:
      • If rd_count equals 3 and dn_table_radr equals dn_table_end_adr, then dn_table_radr is updated to dn_table_start_adr.
      • If rd_count equals 3 and dn_table_radr does not equal dn_table_end_adr, then dn_table_radr is incremented by 1.
  • [0625]
    A count is kept of the number of 64-bit values in the FIFO. When diu_dnc_rvalid is 1 data is written to the FIFO by asserting wr_en, and fifo_contents and fifo_wr_adr are both incremented.
  • [0626]
    When fifo_contents[3:0] is greater than 0 and edu_ready is 1, dnc_hcu_ready is asserted to indicate that the DNC is ready to accept dots from the HCU. If hcu_dnc_avail is also 1 then a dotadv pulse is sent to the GenMask unit, indicating the DNC has accepted a dot from the HCU, and iru_avail is also asserted. After Go is set, a single preload pulse is sent to the GenMask unit once the FIFO contains data.
  • [0627]
    When a rd_adv pulse is received from the GenMask unit, fifo_rd_adr[4:0] is then incremented to select the next 16-bit value. If fifo_rd_adr[1:0]=11 then the next 64-bit value is read from the FIFO by asserting rd_en, and fifo_contents[3:0] is decremented.
  • 1.14.5.1.2 Dead Nozzle FIFO
  • [0628]
    The dead nozzle FIFO conceptually is a 64-bit input, and 16-bit output FIFO to account for the 64-bit data transfers from the DIU, and the individual 16-bit entries in the dead nozzle table that are used in the GenMask unit. In reality, the FIFO is actually 8 entries deep and 64-bits wide (to accommodate two 256-bit accesses).
  • [0629]
    On the DRAM side of the FIFO the write address is 64-bit aligned while on the GenMask side the read address is 16-bit aligned, i.e. the upper 3 bits are input as the read address for the FIFO and the lower 2 bits are used to select 16 bits from the 64 bits (1st 16 bits read corresponds to bits 15-0, second 16 bits to bits 31-16 etc.).
  • 1.14.5.1.3 GenMask Unit
  • [0630]
    The GenMask unit generates the 6-bit dn_mask that is sent to the replace unit. It consists of a 10-bit delta counter and a mask register.
  • [0631]
    After Go is set, the GenMask unit will receive a preload pulse from the control unit indicating the first dead nozzle table entry is available at the output of the dead nozzle FIFO and should be loaded into the delta counter and mask register. A rd_adv pulse is generated so that the next dead nozzle table entry is presented at the output of the dead nozzle FIFO. The delta counter is decremented every time a dotadv pulse is received. When the delta counter reaches 0, it gets loaded with the current delta value output from the dead nozzle FIFO, i.e. bits 15-6, and the mask register gets loaded with mask output from the dead nozzle FIFO, i.e. bits 5-0. A rd_adv pulse is then generated so that the next dead nozzle table entry is presented at the output of the dead nozzle FIFO.
  • [0632]
    When the delta counter is 0 the value in the mask register is output as the dn_mask, otherwise the dn_mask is all 0s.
  • [0633]
    The GenMask unit has no knowledge of the number of dots in a line, it simply loads a counter to count the delta from one dead nozzle column to the next. Thus the dead nozzle table should include null identifiers if necessary so that the dead nozzle table covers the first and last nozzle column in a line.
  • 1.14.5.1.4 Replace Unit
  • [0634]
    Dead nozzle removal and ink replacement are implemented by the combinatorial logic shown in FIG. 250. Dead nozzle removal is performed by bit-wise ANDing of the inverse of the dn_mask with the dot value.
  • [0635]
    The ink replacement mechanism has 6 ink replacement patterns, one per ink plane, programmable by the CPU. The dead nozzle mask is ANDed with the dot data to see if there are any planes where the dot is active but the corresponding nozzle is dead. The resultant value forms an enable, on a per ink basis, for the ink replacement process. If replacement is enabled for a particular ink, the values from the corresponding replacement pattern register are ORed into the dot data. The output of the ink replacement process is then filtered so that error diffusion is only allowed for the planes in which error diffusion is enabled.
  • [0636]
    The output of the ink replacement process is ORed with the resultant dot after dead nozzle removal. If the dot position does not contain a dead nozzle then the dn_mask will be all 0s and the dot, hcu_dnc_data, will be passed through unchanged.
  • 1.14.5.2 Error Diffusion Unit
  • [0637]
    FIG. 251 shows a sub-block diagram for the error diffusion unit.
  • 1.14.5.2.1 Random Bit Generator
  • [0638]
    The random bit value used to arbitrarily select the direction of diffusion is generated by a maximum length 32-bit LFSR. The tap points and feedback generation are shown in FIG. 252. The LFSR generates a new bit for each dot in a line regardless of whether the dot is dead or not, i.e shifting of the LFSR is enabled when advdot equals 1. The LFSR can be initialised with a 32-bit programmable seed value, random_seed. This seed value is loaded into the LFSR whenever a write occurs to the RandomSeed register. Note that the seed value must not be all 1s as this causes the LFSR to lock-up.
  • 1.14.5.2.2 Advance Dot Unit
  • [0639]
    The advance dot unit is responsible for determining in a given cycle whether or not the error diffuse unit will accept a dot from the ink replacement unit or make a dot available to the fixative correct unit and on to the DWU. It therefore receives the dwu_dnc_ready control signal from the DWU, the iru_avail flag from the ink replacement unit, and generates dnc_dwu_avail and edu_ready control flags.
  • [0640]
    Only the dwu_dnc_ready signal needs to be checked to see if a dot can be accepted and asserts edu_ready to indicate this. If the error diffuse unit is ready to accept a dot and the ink replacement unit has a dot available, then a advdot pulse is given to shift the dot into the pipeline in the diffuse unit. Note that since the error diffusion operates on 3 dots, the advance dot unit ignores dwu_dnc_ready initially until 3 dots have been accepted by the diffuse unit. Similarly dnc_dwu_avail is not asserted until the diffuse unit contains 3 dots and the ink replacement unit has a dot available.
  • 1.14.5.2.3 Diffuse Unit
  • [0641]
    The diffuse unit contains the combinatorial logic to implement the truth table from Table. The diffuse unit receives a dot consisting of 6 color planes (1 bit per plane) as well as an associated 6-bit dead nozzle mask value.
  • [0642]
    Error diffusion is applied to all 6 planes of the dot in parallel. Since error diffusion operates on 3 dots, the diffuse unit has a pipeline of 3 dots and their corresponding dead nozzle mask values. The first dot received is referred to as dot A, and the second as dot B, and the third as dot C. Dots are shifted along the pipeline whenever advdot is 1. A count is also kept of the number of dots received. It is incremented whenever advdot is 1, and wraps to 0 when it reaches max_dot. When the dot count is 0 dot C corresponds to the first dot in a line. When the dot count is 1 dot A corresponds to the last dot in a line.
  • [0643]
    In any given set of 3 dots only dot B can be defined as containing a dead nozzle(s). Dead nozzles are identified by bits set in iru_dn_mask. If dot B contains a dead nozzle(s), the corresponding bit(s) in dot A, dot C, the dead nozzle mask value for A, the dead nozzle mask value for C, the dot count, as well as the random bit value are input to the truth table logic and the dots A, B and C assigned accordingly. If dot B does not contain a dead nozzle then the dots are shifted along the pipeline unchanged.
  • 1.14.5.3 Fixative Correction Unit
  • [0644]
    The fixative correction unit consists of combinatorial logic to implement fixative correction as set forth in the following truth table. For each output dot the DNC determines if fixative is required for the new compensated dot data word and whether fixative is activated already for that dot.
  • [0000]
    Fixative Fixative
    Present required Action Output
    1 1 Output dot as is. dnc_dwu_data = edu_data
    1 0 Clear fixative plane. dnc_dwu_data = (edu_data)
    & ~(FixativeMask1 |
    FixativeMask2)
    0 1 Attempt to add fixative. if (FixativeMask1 & DnMask) != 0
    dnc_dwu_data = (edu_data) |
    (FixativeMask2 & ~DnMask)
    else
    dnc_dwu_data = (edu_data) |
    (FixativeMask1)
    0 0 Output dot as is. dnc_dwu_data = edu_data
    FixativePresent = ((FixativeMask1 | FixativeMask2) & edu_data) != 0
    FixativeRequired = (FixativeRequiredMask & edu_data) != 0
  • [0645]
    It then looks up the truth table to see what action, if any, needs to be taken.
  • [0646]
    When attempting to add fixative the DNC first tries to add it into the plane defined by FixativeMask1. However, if this plane is dead then it tries to add fixative by placing it into the plane defined by FixativeMask2. Note that if both FixativeMask1 and FixativeMask2 are both all 0s then the dot data will not be changed.
  • 1.15 Dotline Writer Unit (DWU) 1.15.1 Overview
  • [0647]
    The Dotline Writer Unit (DWU) receives 1 dot (6 bits) of color information per cycle from the DNC. Dot data received is bundled into 256-bit words and transferred to the DRAM. The DWU (in conjunction with the LLU) implements a dot line FIFO mechanism to compensate for the physical placement of nozzles in a printhead, and provides data rate smoothing to allow for local complexities in the dot data generate pipeline.
  • 1.16 Line Loader Unit (LLU) 1.16.1 Overview
  • [0648]
    The Line Loader Unit (LLU) reads dot data from the line buffers in DRAM and structures the data into even and odd dot channels destined for the same print time. The blocks of dot data are transferred to the PHI and then to the printhead. FIG. 267 shows a high level data flow diagram of the LLU in context.
  • 1.17 PrintHead Interface (PHI) 1.17.1 Overview
  • [0649]
    The Printhead interface (PHI) accepts dot data from the LLU and transmits the dot data to the printhead, using the printhead interface mechanism. The PHI generates the control and timing signals necessary to load and drive the bi-lithic printhead. The CPU determines the line update rate to the printhead and adjusts the line sync frequency to produce the maximum print speed to account for the printhead IC's size ratio and inherent latencies in the syncing system across multiple SoPECs.
  • [0650]
    The PHI also needs to consider the order in which dot data is loaded in the printhead. This is dependent on the construction of the printhead and the relative sizes of printhead ICs used to create the printhead. See Bi-lithic Printhead Reference document for a complete description of printhead types.
  • [0651]
    The printing process is a real-time process. Once the printing process has started, the next printline's data must be transferred to the printhead before the next line sync pulse is received by the printhead. Otherwise the printing process will terminate with a buffer underrun error.
  • [0652]
    The PHI can be configured to drive a single printhead IC with or without synchronization to other SoPECs. For example the PHI could drive a single IC printhead (i.e. a printhead constructed with one IC only), or dual IC printhead with one SoPEC device driving each printhead IC.
  • [0653]
    The PHI interface provides a mechanism for the CPU to directly control the PHI interface pins, allowing the CPU to access the bi-lithic printhead to:
      • determine printhead temperature
      • test for and determine dead nozzles for each printhead IC
      • initialize each printhead IC
      • pre-heat each printhead IC
  • [0658]
    FIG. 277 shows a high level data flow diagram of the PHI in context.

Claims (3)

  1. 1. A method of accounting for dead nozzle remapping in a multi-nozzle printhead, the method comprising:
    defining a first fixative plane and a second fixative plane;
    determining a first color plane requiring the fixative;
    determining if fixative is present in the first color plane;
    determining if the first color plane is dead; and
    adding fixative to a second color plane when it is determined that the first color plane is dead.
  2. 2. The method according to claim 1, wherein the first fixative plane has a higher priority than the second fixative plane.
  3. 3. The method according to claim 1, wherein the fixative defined by the first fixative plane and the second fixative plane is a multi-part fixative.
US12790945 2002-12-02 2010-05-31 Method for dead nozzle remapping Abandoned US20100238213A1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
AU2002953134 2002-12-02
AU2002953135 2002-12-02
AU2002953135 2002-12-02
AU2002953134 2002-12-02
US10727181 US20040174570A1 (en) 2002-12-02 2003-12-02 Variable size dither matrix usage
US12790945 US20100238213A1 (en) 2002-12-02 2010-05-31 Method for dead nozzle remapping

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12790945 US20100238213A1 (en) 2002-12-02 2010-05-31 Method for dead nozzle remapping

Publications (1)

Publication Number Publication Date
US20100238213A1 true true US20100238213A1 (en) 2010-09-23

Family

ID=32471018

Family Applications (49)

Application Number Title Priority Date Filing Date
US10727227 Abandoned US20040201647A1 (en) 2002-12-02 2003-12-02 Stitching of integrated circuit components
US10727162 Abandoned US20060082609A1 (en) 2002-12-02 2003-12-02 Compensation for horizontal skew between adjacent rows of nozzles on a printhead module
US10727164 Expired - Fee Related US7707621B2 (en) 2002-12-02 2003-12-02 Creation and usage of mutually exclusive messages
US10727251 Active 2025-06-26 US7188282B2 (en) 2002-12-02 2003-12-02 Tamper resistant shadow memory
US10727210 Active 2024-09-10 US7096137B2 (en) 2002-12-02 2003-12-02 Clock trim mechanism for onboard system clock
US10727257 Active 2025-04-10 US7302592B2 (en) 2002-12-02 2003-12-02 Integrated circuit which disables writing circuitry to memory when the power drops below a power threshold predetermined and controlled by the processor
US10727192 Abandoned US20040225881A1 (en) 2002-12-02 2003-12-02 Variant keys
US10727204 Active 2024-12-05 US7121639B2 (en) 2002-12-02 2003-12-02 Data rate equalisation to account for relatively different printhead widths
US10727274 Active 2027-03-21 US7770008B2 (en) 2002-12-02 2003-12-02 Embedding data and information related to function with which data is associated into a payload
US10727180 Abandoned US20040199786A1 (en) 2002-12-02 2003-12-02 Randomisation of the location of secret information on each of a series of integrated circuits
US10727245 Active 2024-05-21 US7399043B2 (en) 2002-12-02 2003-12-02 Compensation for uneven printhead module lengths in a multi-module printhead
US10727161 Active 2024-11-18 US7523111B2 (en) 2002-12-02 2003-12-02 Labelling of secret information
US10727179 Abandoned US20050213761A1 (en) 2002-12-02 2003-12-02 Storing number and a result of a function on an integrated circuit
US10727198 Active 2024-03-30 US7573301B2 (en) 2002-12-02 2003-12-02 Temperature based filter for an on-chip system clock
US10727159 Expired - Fee Related US7592829B2 (en) 2002-12-02 2003-12-02 On-chip storage of secret information as inverse pair
US10727157 Active 2027-05-02 US7818519B2 (en) 2002-12-02 2003-12-02 Timeslot arbitration scheme
US10727280 Expired - Fee Related US7152942B2 (en) 2002-12-02 2003-12-02 Fixative compensation
US10727233 Active 2025-03-26 US7165824B2 (en) 2002-12-02 2003-12-02 Dead nozzle compensation
US10727238 Active 2025-02-13 US7278034B2 (en) 2002-12-02 2003-12-02 Integrated circuit which disables writing circuitry to memory when the power drops below a power threshold predetermined and controlled by the processor
US10727178 Active 2025-01-16 US7181572B2 (en) 2002-12-02 2003-12-02 Cache updating method and apparatus
US10727163 Active 2025-07-10 US7377608B2 (en) 2002-12-02 2003-12-02 Compensation for vertical skew between adjacent rows of nozzles on a printhead module
US10727158 Expired - Fee Related US7660998B2 (en) 2002-12-02 2003-12-02 Relatively unique ID in integrated circuit
US10727160 Abandoned US20040249757A1 (en) 2002-12-02 2003-12-02 Authentication of resources usage in a multi-user environment
US10754938 Active 2027-01-05 US7831827B2 (en) 2002-12-02 2004-01-12 Authenticated communication between multiple entities
US10754536 Active 2027-07-10 US7783886B2 (en) 2002-12-02 2004-01-12 Multi-level boot hierarchy for software development on an integrated circuit
US11212702 Active 2024-01-11 US7171323B2 (en) 2002-12-02 2005-08-29 Integrated circuit having clock trim circuitry
US11272491 Expired - Fee Related US7278697B2 (en) 2002-12-02 2005-11-14 Data rate supply proportional to the ratio of different printhead lengths
US11442131 Expired - Fee Related US7465005B2 (en) 2002-12-02 2006-05-30 Printer controller with dead nozzle compensation
US11474278 Expired - Fee Related US7360131B2 (en) 2002-12-02 2006-06-26 Printer controller having tamper resistant shadow memory
US11488841 Expired - Fee Related US7328115B2 (en) 2002-12-02 2006-07-19 Quality assurance IC having clock trimmer
US11749750 Active 2024-10-26 US7747887B2 (en) 2002-12-02 2007-05-16 Print engine having authentication device for preventing multi-word memory writing upon power drop
US11749749 Active 2025-12-23 US7805626B2 (en) 2002-12-02 2007-05-16 Print engine having authentication device for disabling memory writing upon power drop
US11951213 Expired - Fee Related US7610163B2 (en) 2002-12-02 2007-12-05 Method of controlling quality for a print controller
US11955127 Active US7467839B2 (en) 2002-12-02 2007-12-12 Printer controller with equalised data supply rate to multi-color printhead ICS
US12043844 Abandoned US20080150997A1 (en) 2002-12-02 2008-03-06 Method Of Manufacturing Printhead ICS Incorporating Mems Inkjet Nozzles
US12047315 Abandoned US20080155826A1 (en) 2002-12-02 2008-03-12 Method of manufacturing mems ics
US12050941 Active US7540579B2 (en) 2002-12-02 2008-03-19 Controller for multi-color, multi-length printhead ICS
US12266479 Abandoned US20090058903A1 (en) 2002-12-02 2008-11-06 Printer controller configured to compensate for dead printhead nozzles
US12276368 Expired - Fee Related US7611215B2 (en) 2002-12-02 2008-11-23 Inkjet printer system having equalised control of multi-length printhead ICS
US12324889 Active 2023-12-29 US7747646B2 (en) 2002-12-02 2008-11-27 System having secure access between IC entities
US12436129 Expired - Fee Related US7722146B2 (en) 2002-12-02 2009-05-06 Printing system having controlled multi-length printhead ICS
US12500593 Active US7800410B2 (en) 2002-12-02 2009-07-09 Integrated circuit having temperature based clock filter
US12505513 Abandoned US20090284279A1 (en) 2002-12-02 2009-07-19 Integrated Circuit Having Inverse Bit Storage Test
US12564045 Expired - Fee Related US8005636B2 (en) 2002-12-02 2009-09-21 Method of controlling clock signal
US12582632 Active US7976116B2 (en) 2002-12-02 2009-10-20 Inkjet printer system having equalised control of different nozzle count printhead ICs
US12697272 Active US7996880B2 (en) 2002-12-02 2010-01-31 Secure updating of integrated circuits
US12778966 Abandoned US20100223453A1 (en) 2002-12-02 2010-05-12 Integrated circuit for validating and decrypting software data
US12790945 Abandoned US20100238213A1 (en) 2002-12-02 2010-05-31 Method for dead nozzle remapping
US12958968 Active US8038239B2 (en) 2002-12-02 2010-12-02 Controller for printhead having arbitrarily joined nozzle rows

Family Applications Before (47)

Application Number Title Priority Date Filing Date
US10727227 Abandoned US20040201647A1 (en) 2002-12-02 2003-12-02 Stitching of integrated circuit components
US10727162 Abandoned US20060082609A1 (en) 2002-12-02 2003-12-02 Compensation for horizontal skew between adjacent rows of nozzles on a printhead module
US10727164 Expired - Fee Related US7707621B2 (en) 2002-12-02 2003-12-02 Creation and usage of mutually exclusive messages
US10727251 Active 2025-06-26 US7188282B2 (en) 2002-12-02 2003-12-02 Tamper resistant shadow memory
US10727210 Active 2024-09-10 US7096137B2 (en) 2002-12-02 2003-12-02 Clock trim mechanism for onboard system clock
US10727257 Active 2025-04-10 US7302592B2 (en) 2002-12-02 2003-12-02 Integrated circuit which disables writing circuitry to memory when the power drops below a power threshold predetermined and controlled by the processor
US10727192 Abandoned US20040225881A1 (en) 2002-12-02 2003-12-02 Variant keys
US10727204 Active 2024-12-05 US7121639B2 (en) 2002-12-02 2003-12-02 Data rate equalisation to account for relatively different printhead widths
US10727274 Active 2027-03-21 US7770008B2 (en) 2002-12-02 2003-12-02 Embedding data and information related to function with which data is associated into a payload
US10727180 Abandoned US20040199786A1 (en) 2002-12-02 2003-12-02 Randomisation of the location of secret information on each of a series of integrated circuits
US10727245 Active 2024-05-21 US7399043B2 (en) 2002-12-02 2003-12-02 Compensation for uneven printhead module lengths in a multi-module printhead
US10727161 Active 2024-11-18 US7523111B2 (en) 2002-12-02 2003-12-02 Labelling of secret information
US10727179 Abandoned US20050213761A1 (en) 2002-12-02 2003-12-02 Storing number and a result of a function on an integrated circuit
US10727198 Active 2024-03-30 US7573301B2 (en) 2002-12-02 2003-12-02 Temperature based filter for an on-chip system clock
US10727159 Expired - Fee Related US7592829B2 (en) 2002-12-02 2003-12-02 On-chip storage of secret information as inverse pair
US10727157 Active 2027-05-02 US7818519B2 (en) 2002-12-02 2003-12-02 Timeslot arbitration scheme
US10727280 Expired - Fee Related US7152942B2 (en) 2002-12-02 2003-12-02 Fixative compensation
US10727233 Active 2025-03-26 US7165824B2 (en) 2002-12-02 2003-12-02 Dead nozzle compensation
US10727238 Active 2025-02-13 US7278034B2 (en) 2002-12-02 2003-12-02 Integrated circuit which disables writing circuitry to memory when the power drops below a power threshold predetermined and controlled by the processor
US10727178 Active 2025-01-16 US7181572B2 (en) 2002-12-02 2003-12-02 Cache updating method and apparatus
US10727163 Active 2025-07-10 US7377608B2 (en) 2002-12-02 2003-12-02 Compensation for vertical skew between adjacent rows of nozzles on a printhead module
US10727158 Expired - Fee Related US7660998B2 (en) 2002-12-02 2003-12-02 Relatively unique ID in integrated circuit
US10727160 Abandoned US20040249757A1 (en) 2002-12-02 2003-12-02 Authentication of resources usage in a multi-user environment
US10754938 Active 2027-01-05 US7831827B2 (en) 2002-12-02 2004-01-12 Authenticated communication between multiple entities
US10754536 Active 2027-07-10 US7783886B2 (en) 2002-12-02 2004-01-12 Multi-level boot hierarchy for software development on an integrated circuit
US11212702 Active 2024-01-11 US7171323B2 (en) 2002-12-02 2005-08-29 Integrated circuit having clock trim circuitry
US11272491 Expired - Fee Related US7278697B2 (en) 2002-12-02 2005-11-14 Data rate supply proportional to the ratio of different printhead lengths
US11442131 Expired - Fee Related US7465005B2 (en) 2002-12-02 2006-05-30 Printer controller with dead nozzle compensation
US11474278 Expired - Fee Related US7360131B2 (en) 2002-12-02 2006-06-26 Printer controller having tamper resistant shadow memory
US11488841 Expired - Fee Related US7328115B2 (en) 2002-12-02 2006-07-19 Quality assurance IC having clock trimmer
US11749750 Active 2024-10-26 US7747887B2 (en) 2002-12-02 2007-05-16 Print engine having authentication device for preventing multi-word memory writing upon power drop
US11749749 Active 2025-12-23 US7805626B2 (en) 2002-12-02 2007-05-16 Print engine having authentication device for disabling memory writing upon power drop
US11951213 Expired - Fee Related US7610163B2 (en) 2002-12-02 2007-12-05 Method of controlling quality for a print controller
US11955127 Active US7467839B2 (en) 2002-12-02 2007-12-12 Printer controller with equalised data supply rate to multi-color printhead ICS
US12043844 Abandoned US20080150997A1 (en) 2002-12-02 2008-03-06 Method Of Manufacturing Printhead ICS Incorporating Mems Inkjet Nozzles
US12047315 Abandoned US20080155826A1 (en) 2002-12-02 2008-03-12 Method of manufacturing mems ics
US12050941 Active US7540579B2 (en) 2002-12-02 2008-03-19 Controller for multi-color, multi-length printhead ICS
US12266479 Abandoned US20090058903A1 (en) 2002-12-02 2008-11-06 Printer controller configured to compensate for dead printhead nozzles
US12276368 Expired - Fee Related US7611215B2 (en) 2002-12-02 2008-11-23 Inkjet printer system having equalised control of multi-length printhead ICS
US12324889 Active 2023-12-29 US7747646B2 (en) 2002-12-02 2008-11-27 System having secure access between IC entities
US12436129 Expired - Fee Related US7722146B2 (en) 2002-12-02 2009-05-06 Printing system having controlled multi-length printhead ICS
US12500593 Active US7800410B2 (en) 2002-12-02 2009-07-09 Integrated circuit having temperature based clock filter
US12505513 Abandoned US20090284279A1 (en) 2002-12-02 2009-07-19 Integrated Circuit Having Inverse Bit Storage Test
US12564045 Expired - Fee Related US8005636B2 (en) 2002-12-02 2009-09-21 Method of controlling clock signal
US12582632 Active US7976116B2 (en) 2002-12-02 2009-10-20 Inkjet printer system having equalised control of different nozzle count printhead ICs
US12697272 Active US7996880B2 (en) 2002-12-02 2010-01-31 Secure updating of integrated circuits
US12778966 Abandoned US20100223453A1 (en) 2002-12-02 2010-05-12 Integrated circuit for validating and decrypting software data

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12958968 Active US8038239B2 (en) 2002-12-02 2010-12-02 Controller for printhead having arbitrarily joined nozzle rows

Country Status (6)

Country Link
US (49) US20040201647A1 (en)
EP (1) EP1572463B1 (en)
CA (1) CA2508141C (en)
DE (1) DE60336677D1 (en)
DK (1) DK1572463T3 (en)
WO (1) WO2004050369A9 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8824014B1 (en) 2013-02-11 2014-09-02 Xerox Corporation System and method for adjustment of coverage parameters for different colors in image data

Families Citing this family (820)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19950249C1 (en) * 1999-10-18 2001-02-01 Siemens Ag Electronic device with software protection for runtime software for automated systems
US7930531B2 (en) * 2000-01-06 2011-04-19 Super Talent Electronics, Inc. Multi-partition USB device that re-boots a PC to an alternate operating system for virus recovery
US6700590B1 (en) * 1999-11-01 2004-03-02 Indx Software Corporation System and method for retrieving and presenting data using class-based component and view model
US7062749B2 (en) * 2000-12-15 2006-06-13 Promenix, Inc. Measuring, monitoring and tracking enterprise communications and processes
EP1359550A1 (en) 2001-11-30 2003-11-05 STMicroelectronics S.A. Regeneration of a secret number by using an identifier of an integrated circuit
EP1391853A1 (en) * 2001-11-30 2004-02-25 STMicroelectronics S.A. Diversification of the unique identifier of an integrated circuit
US8385476B2 (en) * 2001-04-25 2013-02-26 Texas Instruments Incorporated Digital phase locked loop
US7552191B1 (en) * 2001-06-12 2009-06-23 F5 Networks, Inc. Method and apparatus to facilitate automatic sharing in a client server environment
US7613699B2 (en) * 2001-08-03 2009-11-03 Itt Manufacturing Enterprises, Inc. Apparatus and method for resolving security association database update coherency in high-speed systems having multiple security channels
FR2833119A1 (en) 2001-11-30 2003-06-06 St Microelectronics Sa Generation of quantities secret identification of a circuit integrated
FR2838210B1 (en) * 2002-04-03 2005-11-04 Gemplus Card Int Method cryptographic protects against such attacks hidden channel
EP1353259B1 (en) * 2002-04-08 2006-06-14 Aladdin Knowledge Systems (Deutschland) GmbH Method of upgrading and licensing computer programs and computer system therefor
GB0211812D0 (en) * 2002-05-23 2002-07-03 Koninkl Philips Electronics Nv S-box encryption in block cipher implementations
US20030229643A1 (en) * 2002-05-29 2003-12-11 Digimarc Corporation Creating a footprint of a computer file
US20040044508A1 (en) * 2002-08-29 2004-03-04 Hoffman Robert R. Method for generating commands for testing hardware device models
DE60308215T2 (en) * 2002-11-18 2007-08-23 Arm Ltd., Cherry Hinton Processor circuit between safe and unsafe modes
US20040201647A1 (en) * 2002-12-02 2004-10-14 Mark Jackson Pulver Stitching of integrated circuit components
US20090319802A1 (en) * 2002-12-02 2009-12-24 Silverbrook Research Pty Ltd Key Genaration In An Integrated Circuit
US7801120B2 (en) * 2003-01-13 2010-09-21 Emulex Design & Manufacturing Corporation Method and system for efficient queue management
US7010416B2 (en) * 2003-01-17 2006-03-07 Ph2 Solutions, Inc. Systems and methods for resetting vehicle emission system error indicators
JP3823925B2 (en) * 2003-02-05 2006-09-20 ソニー株式会社 The information processing apparatus, the license information recording medium, information processing method, and computer program
US7370212B2 (en) 2003-02-25 2008-05-06 Microsoft Corporation Issuing a publisher use license off-line in a digital rights management (DRM) system
EP1621035B1 (en) * 2003-03-10 2007-06-06 SmartTrust AB Method for secure downloading of applications
US8185812B2 (en) * 2003-03-20 2012-05-22 Arm Limited Single event upset error detection within an integrated circuit
WO2004084070A1 (en) * 2003-03-20 2004-09-30 Arm Limited Systematic and random error detection and recovery within processing stages of an integrated circuit
US8650470B2 (en) 2003-03-20 2014-02-11 Arm Limited Error recovery within integrated circuit
US7260001B2 (en) * 2003-03-20 2007-08-21 Arm Limited Memory system having fast and slow data reading mechanisms
US7278080B2 (en) * 2003-03-20 2007-10-02 Arm Limited Error detection and recovery within processing stages of an integrated circuit
US7409544B2 (en) 2003-03-27 2008-08-05 Microsoft Corporation Methods and systems for authenticating messages
US7610487B2 (en) * 2003-03-27 2009-10-27 Microsoft Corporation Human input security codes
US8261062B2 (en) 2003-03-27 2012-09-04 Microsoft Corporation Non-cryptographic addressing
US7624264B2 (en) 2003-03-27 2009-11-24 Microsoft Corporation Using time to determine a hash extension
JP2004341768A (en) * 2003-05-15 2004-12-02 Fujitsu Ltd Magnetic disk device, cipher processing method and program
US20050021544A1 (en) * 2003-06-18 2005-01-27 Robert Wilkins System and method for managing information
US8595394B1 (en) 2003-06-26 2013-11-26 Nvidia Corporation Method and system for dynamic buffering of disk I/O command chains
US8700808B2 (en) * 2003-12-01 2014-04-15 Nvidia Corporation Hardware support system for accelerated disk I/O
US7496715B1 (en) * 2003-07-16 2009-02-24 Unisys Corporation Programmable cache management system and method
JP4624732B2 (en) * 2003-07-16 2011-02-02 パナソニック株式会社 how to access
US6999887B2 (en) * 2003-08-06 2006-02-14 Infineon Technologies Ag Memory cell signal window testing apparatus
US8229108B2 (en) * 2003-08-15 2012-07-24 Broadcom Corporation Pseudo-random number generation based on periodic sampling of one or more linear feedback shift registers
JP2005100270A (en) * 2003-09-26 2005-04-14 Minolta Co Ltd Printing control program and printer
US8683132B1 (en) 2003-09-29 2014-03-25 Nvidia Corporation Memory controller for sequentially prefetching data for a processor of a computer system
US7395527B2 (en) 2003-09-30 2008-07-01 International Business Machines Corporation Method and apparatus for counting instruction execution and data accesses
US8381037B2 (en) 2003-10-09 2013-02-19 International Business Machines Corporation Method and system for autonomic execution path selection in an application
US7779212B2 (en) 2003-10-17 2010-08-17 Micron Technology, Inc. Method and apparatus for sending data from multiple sources over a communications bus
US20050254085A1 (en) * 2004-05-12 2005-11-17 Koji Oshikiri Image forming system
US8356142B1 (en) 2003-11-12 2013-01-15 Nvidia Corporation Memory controller for non-sequentially prefetching data for a processor of a computer system
US8156343B2 (en) * 2003-11-26 2012-04-10 Intel Corporation Accessing private data about the state of a data processing machine from storage that is publicly accessible
US8548170B2 (en) 2003-12-10 2013-10-01 Mcafee, Inc. Document de-registration
US7814327B2 (en) 2003-12-10 2010-10-12 Mcafee, Inc. Document registration
US7774604B2 (en) 2003-12-10 2010-08-10 Mcafee, Inc. Verifying captured objects before presentation
US7984175B2 (en) 2003-12-10 2011-07-19 Mcafee, Inc. Method and apparatus for data capture and analysis system
US8656039B2 (en) 2003-12-10 2014-02-18 Mcafee, Inc. Rule parser
US7899828B2 (en) 2003-12-10 2011-03-01 Mcafee, Inc. Tag data structure for maintaining relational data over captured objects
US20050132194A1 (en) * 2003-12-12 2005-06-16 Ward Jean R. Protection of identification documents using open cryptography
US7283944B2 (en) * 2003-12-15 2007-10-16 Springsoft, Inc. Circuit simulation bus transaction analysis
US7543142B2 (en) * 2003-12-19 2009-06-02 Intel Corporation Method and apparatus for performing an authentication after cipher operation in a network processor
US7512945B2 (en) * 2003-12-29 2009-03-31 Intel Corporation Method and apparatus for scheduling the processing of commands for execution by cryptographic algorithm cores in a programmable network processor
KR100631673B1 (en) * 2003-12-30 2006-10-09 엘지전자 주식회사 Mobile communication high-frequency module structure
US7831511B1 (en) 2004-01-07 2010-11-09 Intuit Inc. Automating setup of a user's financial management application account for electronic transfer of data with a financial institution
US7895382B2 (en) 2004-01-14 2011-02-22 International Business Machines Corporation Method and apparatus for qualifying collection of performance monitoring events by types of interrupt when interrupt occurs
US7415705B2 (en) 2004-01-14 2008-08-19 International Business Machines Corporation Autonomic method and apparatus for hardware assist for patching code
US7930540B2 (en) 2004-01-22 2011-04-19 Mcafee, Inc. Cryptographic policy enforcement
US7663915B2 (en) * 2004-02-10 2010-02-16 Semiconductor Energy Laboratory Co., Ltd. Nonvolatile memory
JP2005228123A (en) * 2004-02-13 2005-08-25 Sharp Corp Communication method, communication system and information reception-side device used in the communication system
US7260025B2 (en) * 2004-02-18 2007-08-21 Farinella & Associates, Llc Bookmark with integrated electronic timer and method therefor
WO2005081107A1 (en) * 2004-02-20 2005-09-01 Continental Teves Ag & Co. Ohg Method and integrated switching circuit for increasing the immunity to interference
US7607025B1 (en) * 2004-02-26 2009-10-20 Xilinx, Inc. Methods of intrusion detection and prevention in secure programmable logic devices
US7706782B1 (en) 2004-03-01 2010-04-27 Adobe Systems Incorporated System and method for developing information for a wireless information system
US7478158B1 (en) * 2004-03-01 2009-01-13 Adobe Systems Incorporated Bandwidth management system
US7822428B1 (en) 2004-03-01 2010-10-26 Adobe Systems Incorporated Mobile rich media information system
WO2005093759A1 (en) * 2004-03-15 2005-10-06 Thomson Licensing Technique for efficient video re-sampling
US7142478B2 (en) * 2004-03-19 2006-11-28 Infineon Technologies Ag Clock stop detector
US7738137B2 (en) * 2004-03-23 2010-06-15 Lexmark International, Inc. Inkjet print head synchronous serial output for data integrity
US20050216762A1 (en) * 2004-03-25 2005-09-29 Cyrus Peikari Protecting embedded devices with integrated reset detection
US7185301B2 (en) * 2004-04-06 2007-02-27 Lsi Logic Corporation Generic method and apparatus for implementing source synchronous interface in platform ASIC
US20050234986A1 (en) * 2004-04-09 2005-10-20 Microsoft Corporation Systems and methods for fragment-based serialization
JP4343867B2 (en) * 2004-04-13 2009-10-14 キヤノン株式会社 An ink jet recording apparatus
US8400645B2 (en) 2004-04-16 2013-03-19 Marvell International Technology Ltd. Printer with selectable capabilities
US20050246762A1 (en) * 2004-04-29 2005-11-03 International Business Machines Corporation Changing access permission based on usage of a computer resource
US20050257205A1 (en) * 2004-05-13 2005-11-17 Microsoft Corporation Method and system for dynamic software updates
US7735944B2 (en) 2004-05-27 2010-06-15 Silverbrook Research Pty Ltd Printer comprising two printhead modules and at least two printer controllers
US7757086B2 (en) * 2004-05-27 2010-07-13 Silverbrook Research Pty Ltd Key transportation
US7267417B2 (en) * 2004-05-27 2007-09-11 Silverbrook Research Pty Ltd Printer controller for supplying data to one or more printheads via serial links
US7328956B2 (en) * 2004-05-27 2008-02-12 Silverbrook Research Pty Ltd Printer comprising a printhead and at least two printer controllers connected to a common input of the printhead
US7549718B2 (en) * 2004-05-27 2009-06-23 Silverbrook Research Pty Ltd Printhead module having operation controllable on basis of thermal sensors
US7448707B2 (en) * 2004-05-27 2008-11-11 Silverbrook Research Pty Ltd Method of expelling ink from nozzels in groups, starting at outside nozzels of each group
US7252353B2 (en) * 2004-05-27 2007-08-07 Silverbrook Research Pty Ltd Printer controller for supplying data to a printhead module having one or more redundant nozzle rows
US7484831B2 (en) * 2004-05-27 2009-02-03 Silverbrook Research Pty Ltd Printhead module having horizontally grouped firing order
US7427117B2 (en) * 2004-05-27 2008-09-23 Silverbrook Research Pty Ltd Method of expelling ink from nozzles in groups, alternately, starting at outside nozzles of each group
US7551298B2 (en) * 2004-06-04 2009-06-23 Primax Electronics Ltd. Print control device with embedded engine simulation module and test method thereof
US7143221B2 (en) * 2004-06-08 2006-11-28 Arm Limited Method of arbitrating between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit of a data processing apparatus
JP4612461B2 (en) * 2004-06-24 2011-01-12 株式会社東芝 Microprocessor
JP4275583B2 (en) * 2004-06-24 2009-06-10 ユーディナデバイス株式会社 Electronic module
US7409315B2 (en) * 2004-06-28 2008-08-05 Broadcom Corporation On-board performance monitor and power control system
JP4874440B2 (en) * 2004-06-29 2012-02-15 株式会社デンソー Program generation program for generating a program based on the state and the corresponding information assigned an action event set, the program generating device, and a program generation method, and a program produced by these
US7929689B2 (en) 2004-06-30 2011-04-19 Microsoft Corporation Call signs
US7568102B2 (en) * 2004-07-15 2009-07-28 Sony Corporation System and method for authorizing the use of stored information in an operating system
US7716494B2 (en) * 2004-07-15 2010-05-11 Sony Corporation Establishing a trusted platform in a digital processing system
US7586904B2 (en) * 2004-07-15 2009-09-08 Broadcom Corp. Method and system for a gigabit Ethernet IP telephone chip with no DSP core, which uses a RISC core with instruction extensions to support voice processing
US7552326B2 (en) * 2004-07-15 2009-06-23 Sony Corporation Use of kernel authorization data to maintain security in a digital processing system
US20060015732A1 (en) * 2004-07-15 2006-01-19 Sony Corporation Processing system using internal digital signatures
US7840607B2 (en) * 2004-08-06 2010-11-23 Siemens Aktiengesellschaft Data mart generation and use in association with an operations intelligence platform
US7343496B1 (en) * 2004-08-13 2008-03-11 Zilog, Inc. Secure transaction microcontroller with secure boot loader
US20060037077A1 (en) * 2004-08-16 2006-02-16 Cisco Technology, Inc. Network intrusion detection system having application inspection and anomaly detection characteristics
US8700671B2 (en) * 2004-08-18 2014-04-15 Siemens Aktiengesellschaft System and methods for dynamic generation of point / tag configurations
US7182422B2 (en) * 2004-08-23 2007-02-27 Silverbrook Research Pty Ltd Printhead having first and second rows of print nozzles
US8560534B2 (en) 2004-08-23 2013-10-15 Mcafee, Inc. Database for a capture system
US7949849B2 (en) 2004-08-24 2011-05-24 Mcafee, Inc. File system for a capture system
WO2006026461A3 (en) * 2004-08-27 2007-12-21 Sanjeev Kumar Methods for memory assignment schemes and architecture for shareable parallel memory module based internet switches
US8032787B2 (en) * 2004-09-02 2011-10-04 Intel Corporation Volatile storage based power loss recovery mechanism
US20110071949A1 (en) * 2004-09-20 2011-03-24 Andrew Petrov Secure pin entry device for mobile phones
US8347078B2 (en) 2004-10-18 2013-01-01 Microsoft Corporation Device certificate individualization
US7644272B2 (en) 2004-10-22 2010-01-05 Broadcom Corporation Systems and methods for providing security to different functions
US8356143B1 (en) 2004-10-22 2013-01-15 NVIDIA Corporatin Prefetch mechanism for bus master memory access
US20060088160A1 (en) * 2004-10-27 2006-04-27 Lexmark International, Inc. Method and apparatus for generating and printing a security stamp with custom logo on an electrophotographic printer
US9032192B2 (en) * 2004-10-28 2015-05-12 Broadcom Corporation Method and system for policy based authentication
US7450723B2 (en) * 2004-11-12 2008-11-11 International Business Machines Corporation Method and system for providing for security in communication
US8176564B2 (en) 2004-11-15 2012-05-08 Microsoft Corporation Special PC mode entered upon detection of undesired state
US8464348B2 (en) * 2004-11-15 2013-06-11 Microsoft Corporation Isolated computing environment anchored into CPU and motherboard
US8336085B2 (en) 2004-11-15 2012-12-18 Microsoft Corporation Tuning product policy using observed evidence of customer behavior
DE102004055505A1 (en) * 2004-11-17 2006-05-24 Nec Europe Ltd. Procedures for the authorization of service requests to service hosts on a network
US7814123B2 (en) * 2004-12-02 2010-10-12 Siemens Aktiengesellschaft Management of component members using tag attributes
JP4570952B2 (en) * 2004-12-28 2010-10-27 富士通株式会社 Fast processing apparatus, high-speed information processing method and program
US20060146100A1 (en) * 2005-01-04 2006-07-06 Dull Daniel J Ink jet supply component including a secure memory serial device
US7778812B2 (en) * 2005-01-07 2010-08-17 Micron Technology, Inc. Selecting data to verify in hardware device model simulation test generation
US8442938B2 (en) 2005-01-14 2013-05-14 Siemens Aktiengesellschaft Child data structure update in data management system
US7966643B2 (en) * 2005-01-19 2011-06-21 Microsoft Corporation Method and system for securing a remote file system
US7770205B2 (en) * 2005-01-19 2010-08-03 Microsoft Corporation Binding a device to a computer
US7536542B2 (en) * 2005-01-19 2009-05-19 Microsoft Corporation Method and system for intercepting, analyzing, and modifying interactions between a transport client and a transport provider
US7315917B2 (en) * 2005-01-20 2008-01-01 Sandisk Corporation Scheduling of housekeeping operations in flash memory systems
US7132823B2 (en) * 2005-01-21 2006-11-07 Microsoft Corporation Design for test for a high speed serial interface
US7630781B2 (en) * 2005-01-27 2009-12-08 Lite-On Technology Corporation Media data reproduction methods and embedded systems utilizing the same
US7636911B2 (en) * 2005-01-28 2009-12-22 Microsoft Corporation System and methods for capturing structure of data models using entity patterns
US9300641B2 (en) * 2005-02-11 2016-03-29 Nokia Corporation Method and apparatus for providing bootstrapping procedures in a communication network
US7221878B2 (en) * 2005-02-18 2007-05-22 Hewlett-Packard Development Company, L.P. Allowing image formation using consumable item where code of consumable item is identical to code of image-formation device
EP1696321A1 (en) 2005-02-23 2006-08-30 Deutsche Thomson-Brandt Gmbh Method and apparatus for executing software applications
US7376809B2 (en) * 2005-03-09 2008-05-20 International Business Machines Corporation Systems and methods for multi-frame control blocks
US7620711B2 (en) * 2005-03-18 2009-11-17 Siemens Aktiengesellschaft Method of using configuration files for configuring technical devices
US20060218649A1 (en) * 2005-03-22 2006-09-28 Brickell Ernie F Method for conditional disclosure of identity information
JP4517907B2 (en) * 2005-03-23 2010-08-04 セイコーエプソン株式会社 Printing system, printing method and printing control apparatus
JP4389829B2 (en) * 2005-03-28 2009-12-24 セイコーエプソン株式会社 Client computer, a printer driver generating method, the printer driver search method
US20060215207A1 (en) * 2005-03-28 2006-09-28 Konica Minolta Systems Laboratory, Inc. Color and monochrome management printing system
US8095915B2 (en) * 2005-04-13 2012-01-10 Telefonaktiebolaget Lm Ericsson (Publ) Data value coherence in computer systems
US8725646B2 (en) 2005-04-15 2014-05-13 Microsoft Corporation Output protection levels
US7509250B2 (en) * 2005-04-20 2009-03-24 Honeywell International Inc. Hardware key control of debug interface
US9363481B2 (en) 2005-04-22 2016-06-07 Microsoft Technology Licensing, Llc Protected media pipeline
US9436804B2 (en) 2005-04-22 2016-09-06 Microsoft Technology Licensing, Llc Establishing a unique session key using a hardware functionality scan
US20060242406A1 (en) 2005-04-22 2006-10-26 Microsoft Corporation Protected computing environment
US8438645B2 (en) 2005-04-27 2013-05-07 Microsoft Corporation Secure clock with grace periods
JP4855710B2 (en) * 2005-04-28 2012-01-18 株式会社東芝 Plug-in instructions of the software, and application program
US8127147B2 (en) * 2005-05-10 2012-02-28 Seagate Technology Llc Method and apparatus for securing data storage while insuring control by logical roles
US20060265758A1 (en) 2005-05-20 2006-11-23 Microsoft Corporation Extensible media rights
DE102005024917A1 (en) * 2005-05-31 2006-12-07 Advanced Micro Devices, Inc., Sunnyvale Register transfer level simulation device for simulating bit or bus synchronization of digital electronic circuit in e.g. silicon chip, has delay unit selectively delaying digital signal of flip-flop register around variable delay time
JP5130646B2 (en) * 2005-06-06 2013-01-30 ソニー株式会社 Storage device
US8353046B2 (en) 2005-06-08 2013-01-08 Microsoft Corporation System and method for delivery of a modular operating system
JP2008542932A (en) * 2005-06-10 2008-11-27 フリースケール セミコンダクター インコーポレイテッド Medium access control device and method
US8223910B2 (en) * 2005-06-10 2012-07-17 Freescale Semiconductor, Inc. Method and device for frame synchronization
US20060285164A1 (en) * 2005-06-21 2006-12-21 Chun-Yi Wang Method for Processing Multi-layered Image Data
EP1894411A1 (en) * 2005-06-23 2008-03-05 Thomson Licensing Multi-media access device registration system and method
US8639946B2 (en) * 2005-06-24 2014-01-28 Sigmatel, Inc. System and method of using a protected non-volatile memory
US7337147B2 (en) * 2005-06-30 2008-02-26 Microsoft Corporation Dynamic digital content licensing
JP4410162B2 (en) * 2005-07-05 2010-02-03 富士通株式会社 Reconfigurable lsi
US7797291B1 (en) * 2005-07-11 2010-09-14 Sprint Communications Company L.P. Data retention auditing
JP4345721B2 (en) * 2005-07-14 2009-10-14 コニカミノルタビジネステクノロジーズ株式会社 Control system
KR100648658B1 (en) * 2005-07-19 2006-11-15 삼성전자주식회사 Printing system and printer capable of electronic signature and method using the same
US20070022250A1 (en) * 2005-07-19 2007-01-25 International Business Machines Corporation System and method of responding to a cache read error with a temporary cache directory column delete
EP1748343A1 (en) * 2005-07-29 2007-01-31 SGS-Thomson Microelectronics Limited Circuit personalisation
JP4412733B2 (en) * 2005-08-02 2010-02-10 キヤノン株式会社 Image processing apparatus and method, and a computer program and storage medium
US7907608B2 (en) 2005-08-12 2011-03-15 Mcafee, Inc. High speed packet capture
CN101243513A (en) * 2005-08-23 2008-08-13 皇家飞利浦电子股份有限公司 Information carrier authentication with a physical one-way function
JP2007058969A (en) * 2005-08-24 2007-03-08 Sanyo Electric Co Ltd memory
KR100833178B1 (en) * 2005-08-26 2008-05-28 삼성전자주식회사 System capable of controlling the number of block in a cache memory and method thereof
JP2007064762A (en) * 2005-08-30 2007-03-15 Matsushita Electric Ind Co Ltd Semiconductor device and test mode control circuit
US8255108B2 (en) * 2005-08-31 2012-08-28 Spx Corporation Dynamic file system creation for scan tools
US8183980B2 (en) * 2005-08-31 2012-05-22 Assa Abloy Ab Device authentication using a unidirectional protocol
JP2007066109A (en) * 2005-08-31 2007-03-15 Fujitsu Ltd Apparatus and method for controlling data transmission/reception
US7818326B2 (en) 2005-08-31 2010-10-19 Mcafee, Inc. System and method for word indexing in a capture system and querying thereof
JP4674513B2 (en) * 2005-09-14 2011-04-20 富士ゼロックス株式会社 Spatial arrangement reproduction method, reader, and program
US7979048B2 (en) * 2005-09-15 2011-07-12 Silicon Laboratories Inc. Quasi non-volatile memory for use in a receiver
US20070067445A1 (en) * 2005-09-16 2007-03-22 Smart Link Ltd. Remote computer wake-up for network applications
US8135741B2 (en) 2005-09-20 2012-03-13 Microsoft Corporation Modifying service provider context information to facilitate locating interceptor context information
EP1768028A1 (en) * 2005-09-22 2007-03-28 STMicroelectronics (Research & Development) Limited Addressing peripherals in an ic
US20100191959A1 (en) * 2005-09-23 2010-07-29 Space Micro Inc. Secure microprocessor and method
US20070074046A1 (en) * 2005-09-23 2007-03-29 Czajkowski David R Secure microprocessor and method
US9049243B2 (en) * 2005-09-28 2015-06-02 Photobucket Corporation System and method for allowing a user to opt for automatic or selectively sending of media
US9009265B2 (en) 2005-09-28 2015-04-14 Photobucket Corporation System and method for automatic transfer of data from one device to another
US7385491B2 (en) * 2005-09-28 2008-06-10 Itt Manufacturing Enterprises, Inc. Tamper monitor circuit
US8015253B1 (en) 2005-09-28 2011-09-06 Photobucket Corporation System and method for controlling inter-device media exchanges
WO2007038766A3 (en) * 2005-09-28 2009-04-23 Ontela Inc System for secure data transfer between electronic devices with a wide range of capabilities over multiple communications media
US9424270B1 (en) 2006-09-28 2016-08-23 Photobucket Corporation System and method for managing media files
US7870103B1 (en) * 2005-10-13 2011-01-11 Emc Corporation Tolerating and reporting collisions in content-derived identifiers of data segments using secondary identifiers
US7730011B1 (en) 2005-10-19 2010-06-01 Mcafee, Inc. Attributes of captured objects in a capture system
US7954037B2 (en) * 2005-10-25 2011-05-31 Sandisk Il Ltd Method for recovering from errors in flash memory
US8645712B1 (en) * 2005-10-27 2014-02-04 Altera Corporation Electronic circuit design copy protection
JP4513725B2 (en) * 2005-11-09 2010-07-28 ソニー株式会社 Packet transmitting apparatus, a communication system and a program
US7657104B2 (en) 2005-11-21 2010-02-02 Mcafee, Inc. Identifying image type in a capture system
US9176713B2 (en) * 2005-11-30 2015-11-03 International Business Machines Corporation Method, apparatus and program storage device that provides a user mode device interface
US7571368B1 (en) 2006-01-26 2009-08-04 Promethean Storage Llc Digital content protection systems and methods
US8832466B1 (en) 2006-01-27 2014-09-09 Trustwave Holdings, Inc. Methods for augmentation and interpretation of data objects
US9718268B1 (en) 2006-01-30 2017-08-01 Shahar Turgeman Ink printing system comprising groups of inks, each group having a unique ink base composition
US9352573B1 (en) 2006-01-30 2016-05-31 Shahar Turgeman Ink printing system comprising groups of inks, each group having a unique inkbase composition
US7421542B2 (en) * 2006-01-31 2008-09-02 Cisco Technology, Inc. Technique for data cache synchronization
US20070240126A1 (en) * 2006-02-01 2007-10-11 International Business Machines Corporation System and method for event based resource selection
US8386782B2 (en) * 2006-02-02 2013-02-26 Nokia Corporation Authenticated group key agreement in groups such as ad-hoc scenarios
US7421601B2 (en) * 2006-02-17 2008-09-02 International Business Machines Corporation Method and system for controlling power in a chip through a power-performance monitor and control unit
US7996899B1 (en) 2006-02-24 2011-08-09 Hitachi Global Storage Technologies Netherlands B.V. Communication systems and methods for digital content modification and protection
US8243922B1 (en) 2006-02-24 2012-08-14 Hitachi Global Storage Technologies Netherlands B.V. Digital content modification for content protection
US7441102B2 (en) * 2006-02-28 2008-10-21 Freescale Semiconductor, Inc. Integrated circuit with functional state configurable memory and method of configuring functional states of the integrated circuit memory
US8321691B2 (en) * 2006-03-06 2012-11-27 Stmicroelectronics S.A. EMA protection of a calculation by an electronic circuit
JP5060057B2 (en) * 2006-03-08 2012-10-31 富士通株式会社 Communication line monitoring system, a relay device, and the communication line monitoring method
KR20070094320A (en) * 2006-03-17 2007-09-20 엘지전자 주식회사 Apparatus for receiving broadcasting, method for transmitting and receiving application, method for transmitting information of status receiving broadcasting, and data structure in accordance with status receiving broadcasting
US8504537B2 (en) 2006-03-24 2013-08-06 Mcafee, Inc. Signature distribution in a document registration system
US8086842B2 (en) 2006-04-21 2011-12-27 Microsoft Corporation Peer-to-peer contact exchange
WO2007127188A3 (en) * 2006-04-24 2008-03-20 Encryptakey Inc Portable device and methods for performing secure transactions
JPWO2007125877A1 (en) * 2006-04-28 2009-09-10 パナソニック株式会社 Communication apparatus, and communication system
US7818740B2 (en) * 2006-05-05 2010-10-19 Microsoft Corporation Techniques to perform gradual upgrades
US8560829B2 (en) * 2006-05-09 2013-10-15 Broadcom Corporation Method and system for command interface protection to achieve a secure interface
US8285988B2 (en) * 2006-05-09 2012-10-09 Broadcom Corporation Method and system for command authentication to achieve a secure interface
US20070282318A1 (en) * 2006-05-16 2007-12-06 Spooner Gregory J Subcutaneous thermolipolysis using radiofrequency energy
US8205262B2 (en) * 2006-05-16 2012-06-19 Bird Peter L Hardware support for computer speciation
US7958227B2 (en) 2006-05-22 2011-06-07 Mcafee, Inc. Attributes of captured objects in a capture system
US7689614B2 (en) 2006-05-22 2010-03-30 Mcafee, Inc. Query generation for a capture system
US8141058B2 (en) 2006-06-05 2012-03-20 Rogue Wave Software, Inc. System for and method of capturing application characteristics data from a computer system and modeling target system
US7809997B2 (en) * 2006-06-05 2010-10-05 Renesas Electronics Corporation Semiconductor device, unique ID of semiconductor device and method for verifying unique ID
FR2902213B1 (en) * 2006-06-08 2008-10-17 Thomson Licensing Sas Electronic card endowed with safety features
US7774616B2 (en) * 2006-06-09 2010-08-10 International Business Machines Corporation Masking a boot sequence by providing a dummy processor
US7594104B2 (en) * 2006-06-09 2009-09-22 International Business Machines Corporation System and method for masking a hardware boot sequence
US20070288761A1 (en) * 2006-06-09 2007-12-13 Dale Jason N System and method for booting a multiprocessor device based on selection of encryption keys to be provided to processors
US20070288740A1 (en) * 2006-06-09 2007-12-13 Dale Jason N System and method for secure boot across a plurality of processors
US20070288738A1 (en) * 2006-06-09 2007-12-13 Dale Jason N System and method for selecting a random processor to boot on a multiprocessor system
EP2033315B1 (en) * 2006-06-21 2013-11-27 Element CXI, LLC Element controller for a resilient integrated circuit architecture
KR100804698B1 (en) * 2006-06-26 2008-02-18 삼성에스디아이 주식회사 The method of assuming the state of charge of the battery, battery management system using the method and the driving method of the battery management system using the method
US7934092B2 (en) * 2006-07-10 2011-04-26 Silverbrook Research Pty Ltd Electronic device having improved security
US20080028226A1 (en) * 2006-07-31 2008-01-31 Brocker Matthew W System-on-a-chip and method for securely transferring data on a system-on-a-chip
GB0615392D0 (en) * 2006-08-03 2006-09-13 Wivenhoe Technology Ltd Pseudo random number circuitry
US7769842B2 (en) * 2006-08-08 2010-08-03 Endl Texas, Llc Storage management unit to configure zoning, LUN masking, access controls, or other storage area network parameters
GB0616135D0 (en) * 2006-08-14 2006-09-20 British Telecomm Application controller
US8422673B2 (en) * 2006-08-31 2013-04-16 Red Hat, Inc. Method and system for protecting against unity keys
US8010995B2 (en) * 2006-09-08 2011-08-30 International Business Machines Corporation Methods, systems, and computer program products for implementing inter-process integrity serialization
US8065530B2 (en) * 2006-09-11 2011-11-22 Research In Motion Limited Apparatus, and associated method, for paging an access terminal in a radio communication system
DE102006045906A1 (en) * 2006-09-28 2008-04-17 Infineon Technologies Ag Module to a controller for a chip card
US20080080511A1 (en) * 2006-09-28 2008-04-03 Jian-Guo Chen Buffer cluster structure and arbiter scheme for multi-port upper-layer network processor
US8094685B2 (en) * 2006-10-04 2012-01-10 Siemens Medical Solutions Usa, Inc. Systems and methods for synchronizing multiple video streams
WO2008040377A1 (en) * 2006-10-06 2008-04-10 Agere Systems Inc. Protecting secret information in a programmed electronic device
US8452987B2 (en) * 2006-10-06 2013-05-28 Broadcom Corporation Method and system for disaster recovery in a secure reprogrammable system
US20080098380A1 (en) * 2006-10-18 2008-04-24 Toby Klusmeyer System, method, and device for updating programmable electronic equipment with a transport device from a deployment server via the internet or other communication medium
WO2008049235A1 (en) * 2006-10-27 2008-05-02 Storage Appliance Corporation Systems and methods for controlling production quantities
KR100831677B1 (en) * 2006-10-27 2008-05-22 주식회사 하이닉스반도체 Counter control signal generating circuit
US7656331B2 (en) * 2006-10-31 2010-02-02 Freescale Semiconductor, Inc. System on a chip with multiple independent outputs
DE102006052173A1 (en) * 2006-11-02 2008-05-08 Fast Lta Ag The write protection method and apparatus for at least one memory device having random access
US8443341B2 (en) 2006-11-09 2013-05-14 Rogue Wave Software, Inc. System for and method of capturing application characteristics data from a computer system and modeling target system
US7607752B2 (en) * 2006-11-17 2009-10-27 Hewlett-Packard Development Company, L.P. Misfiring print nozzle compensation
US8296337B2 (en) 2006-12-06 2012-10-23 Fusion-Io, Inc. Apparatus, system, and method for managing data from a requesting device with an empty data token directive
US8706968B2 (en) 2007-12-06 2014-04-22 Fusion-Io, Inc. Apparatus, system, and method for redundant write caching
US7836226B2 (en) 2007-12-06 2010-11-16 Fusion-Io, Inc. Apparatus, system, and method for coordinating storage requests in a multi-processor/multi-thread environment
US9116823B2 (en) 2006-12-06 2015-08-25 Intelligent Intellectual Property Holdings 2 Llc Systems and methods for adaptive error-correction coding
US8443134B2 (en) 2006-12-06 2013-05-14 Fusion-Io, Inc. Apparatus, system, and method for graceful cache device degradation
US9519540B2 (en) 2007-12-06 2016-12-13 Sandisk Technologies Llc Apparatus, system, and method for destaging cached data
CN101622595A (en) 2006-12-06 2010-01-06 弗森多系统公司(dba弗森-艾奥) Apparatus, system, and method for storage space recovery in solid-state storage
US9495241B2 (en) 2006-12-06 2016-11-15 Longitude Enterprise Flash S.A.R.L. Systems and methods for adaptive data storage
US8489817B2 (en) 2007-12-06 2013-07-16 Fusion-Io, Inc. Apparatus, system, and method for caching data
US8074011B2 (en) * 2006-12-06 2011-12-06 Fusion-Io, Inc. Apparatus, system, and method for storage space recovery after reaching a read count limit
US8316277B2 (en) 2007-12-06 2012-11-20 Fusion-Io, Inc. Apparatus, system, and method for ensuring data validity in a data storage process
US9104599B2 (en) 2007-12-06 2015-08-11 Intelligent Intellectual Property Holdings 2 Llc Apparatus, system, and method for destaging cached data
US8935302B2 (en) * 2006-12-06 2015-01-13 Intelligent Intellectual Property Holdings 2 Llc Apparatus, system, and method for data block usage information synchronization for a non-volatile storage volume
US8195912B2 (en) 2007-12-06 2012-06-05 Fusion-io, Inc Apparatus, system, and method for efficient mapping of virtual and physical addresses
WO2008076727B1 (en) * 2006-12-13 2008-08-21 Luminary Micro Inc Platform programming for mass customization
JP5043416B2 (en) * 2006-12-15 2012-10-10 キヤノン株式会社 The information processing apparatus, system and program, device, and a storage medium
WO2008075311A3 (en) * 2006-12-20 2008-08-21 Manoj Chandran Clock generation for memory access without a local oscillator
US7794036B2 (en) * 2006-12-22 2010-09-14 Pitney Bowes Inc. Ensuring print quality for postage meter systems
US7711684B2 (en) * 2006-12-28 2010-05-04 Ebay Inc. Collaborative content evaluation
US7877812B2 (en) * 2007-01-04 2011-01-25 International Business Machines Corporation Method, system and computer program product for enforcing privacy policies
US8472066B1 (en) * 2007-01-11 2013-06-25 Marvell International Ltd. Usage maps in image deposition devices
US8234624B2 (en) * 2007-01-25 2012-07-31 International Business Machines Corporation System and method for developing embedded software in-situ
WO2008094470A1 (en) * 2007-01-26 2008-08-07 Magtek, Inc. Card reader for use with web based transactions
US20080180470A1 (en) * 2007-01-31 2008-07-31 Seiichiro Oku Image forming apparatus and method of transferring print data
WO2008097202A1 (en) * 2007-02-09 2008-08-14 Agency For Science, Technology And Research A method and system for tamper proofing a system of interconnected electronic devices
EP2122466B1 (en) 2007-02-12 2015-04-29 Mentor Graphics Corporation Low power scan testing techniques and apparatus
US20080270661A1 (en) * 2007-02-19 2008-10-30 Plumpton Kevin I Interruption Management
US7703060B2 (en) * 2007-02-23 2010-04-20 International Business Machines Corporation Stitched IC layout methods, systems and program product
US7532993B2 (en) * 2007-02-26 2009-05-12 Infineon Technologies Ag Device providing trim values
US8260783B2 (en) 2007-02-27 2012-09-04 Siemens Aktiengesellschaft Storage of multiple, related time-series data streams
DE102007009909B4 (en) * 2007-02-28 2016-09-08 Globalfoundries Inc. A method for validating an atomic transaction in a multi-core microprocessor environment
US8484220B2 (en) 2007-03-06 2013-07-09 Mcafee, Inc. Clustered index with differentiated subfields
US20100198830A1 (en) * 2008-03-06 2010-08-05 Nitrosecurity, Inc. Dynamic data distribution aggregation
US7636875B2 (en) * 2007-03-08 2009-12-22 Texas Instruments Incorporated Low noise coding for digital data interface
US8125243B1 (en) 2007-03-12 2012-02-28 Cypress Semiconductor Corporation Integrity checking of configurable data of programmable device
DE102007029133A1 (en) * 2007-03-20 2008-09-25 Ludwig-Maximilians-Universität A method for computer-aided determining the dependencies of a plurality of modules of a technical system, in particular a software system
US8539455B2 (en) * 2007-03-26 2013-09-17 Rogue Wave Software, Inc. System for and method of capturing performance characteristics data from a computer system and modeling target system performance
US8060661B1 (en) 2007-03-27 2011-11-15 Cypress Semiconductor Corporation Interface circuit and method for programming or communicating with an integrated circuit via a power supply pin
JP5029101B2 (en) * 2007-04-04 2012-09-19 富士ゼロックス株式会社 Image processing apparatus, an image recording apparatus, image processing method and image processing program
EP1978468A1 (en) * 2007-04-04 2008-10-08 Sap Ag A method and a system for secure execution of workflow tasks in a distributed workflow management system within a decentralized network system
US7958432B2 (en) * 2007-04-11 2011-06-07 International Business Machines Corporation Verification of non volatile storage storing preserved unneeded data
KR101351019B1 (en) * 2007-04-13 2014-01-13 엘지전자 주식회사 apparatus for transmitting and receiving a broadcast signal and method of transmitting and receiving a broadcast signal
KR101351026B1 (en) * 2007-04-13 2014-01-13 엘지전자 주식회사 apparatus for transmitting and receiving a broadcast signal and method of transmitting and receiving a broadcast signal
EP2392253A1 (en) * 2007-04-18 2011-12-07 Weinmann Method and device for updating respirators
US20080263233A1 (en) * 2007-04-19 2008-10-23 Thomas Hein Integrated circuit and memory device
US20080266563A1 (en) * 2007-04-26 2008-10-30 Redman David J Measuring color using color filter arrays
US7743186B2 (en) * 2007-04-27 2010-06-22 Atmel Corporation Serialization of data for communication with different-protocol slave in multi-chip bus implementation
US7814250B2 (en) 2007-04-27 2010-10-12 Atmel Corporation Serialization of data for multi-chip bus implementation
US7769933B2 (en) * 2007-04-27 2010-08-03 Atmel Corporation Serialization of data for communication with master in multi-chip bus implementation
US7761632B2 (en) 2007-04-27 2010-07-20 Atmel Corporation Serialization of data for communication with slave in multi-chip bus implementation
US20080275662A1 (en) 2007-05-01 2008-11-06 Vladimir Dmitriev-Zdorov Generating transmission-code compliant test sequences
US7827455B1 (en) * 2007-05-01 2010-11-02 Unisys Corporation System and method for detecting glitches on a high-speed interface
US20080273584A1 (en) * 2007-05-01 2008-11-06 Vladimir Dmitriev-Zdorov Generating test sequences for circuit channels exhibiting duty-cycle distortion
WO2008137458A3 (en) * 2007-05-01 2009-01-08 Mentor Graphics Corp Generating test sequences for testing circuit channels
KR100970003B1 (en) * 2007-05-02 2010-07-16 삼성전자주식회사 Method and apparatus for transmitting signal
WO2009105055A1 (en) * 2007-05-10 2009-08-27 Micron Technology, Inc. Memory area protection system and methods
US20080288818A1 (en) * 2007-05-18 2008-11-20 Wen-Yueh Lai Method and System for Protecting Information between a Master Terminal and a Slave Terminal
US8040556B2 (en) * 2007-05-24 2011-10-18 Dainippon Screen Mfg. Co., Ltd. Image data generating method, printing method, image data generating apparatus, and printer
US7823006B2 (en) * 2007-05-29 2010-10-26 Microsoft Corporation Analyzing problem signatures
US20080301433A1 (en) * 2007-05-30 2008-12-04 Atmel Corporation Secure Communications
WO2008151339A3 (en) * 2007-06-11 2009-03-12 Fts Computertechnik Gmbh Method and architecture for securing real-time data
US9037750B2 (en) * 2007-07-10 2015-05-19 Qualcomm Incorporated Methods and apparatus for data exchange in peer to peer communications
JP2009027472A (en) * 2007-07-19 2009-02-05 Toshiba Corp Cipher calculation device
US20090022319A1 (en) * 2007-07-19 2009-01-22 Mark Shahaf Method and apparatus for securing data and communication
US8122322B2 (en) 2007-07-31 2012-02-21 Seagate Technology Llc System and method of storing reliability data
KR20090014034A (en) * 2007-08-03 2009-02-06 삼성전자주식회사 Inkjet image forming apparatus
CN101364210B (en) * 2007-08-06 2012-05-30 鸿富锦精密工业(深圳)有限公司 Portable computer with components expandable
JP2009053901A (en) * 2007-08-27 2009-03-12 Seiko Epson Corp Printer
US7505340B1 (en) * 2007-08-28 2009-03-17 International Business Machines Corporation Method for implementing SRAM cell write performance evaluation
US7917716B2 (en) * 2007-08-31 2011-03-29 Standard Microsystems Corporation Memory protection for embedded controllers
US8006095B2 (en) * 2007-08-31 2011-08-23 Standard Microsystems Corporation Configurable signature for authenticating data or program code
KR101429674B1 (en) * 2007-09-11 2014-08-13 삼성전자주식회사 Apparatus and method for reducing power consumption in system on chip
FR2921171B1 (en) * 2007-09-14 2015-10-23 Airbus France Process for minimizing the amount of information required for debugging an operating software of a system on board of an aircraft, and implementation of device
US8127233B2 (en) * 2007-09-24 2012-02-28 Microsoft Corporation Remote user interface updates using difference and motion encoding
US9201790B2 (en) * 2007-10-09 2015-12-01 Seagate Technology Llc System and method of matching data rates
JP5082737B2 (en) * 2007-10-09 2012-11-28 パナソニック株式会社 Information processing apparatus and information theft prevention method
US8619877B2 (en) * 2007-10-11 2013-12-31 Microsoft Corporation Optimized key frame caching for remote interface rendering
US8121423B2 (en) * 2007-10-12 2012-02-21 Microsoft Corporation Remote user interface raster segment motion detection and encoding
US8106909B2 (en) * 2007-10-13 2012-01-31 Microsoft Corporation Common key frame caching for a remote user interface
US8327191B2 (en) * 2007-10-19 2012-12-04 International Business Machines Corporation Automatically populating symptom databases for software applications
US20090113256A1 (en) * 2007-10-24 2009-04-30 Nokia Corporation Method, computer program product, apparatus and device providing scalable structured high throughput LDPC decoding
US7741659B2 (en) * 2007-10-25 2010-06-22 United Microelectronics Corp. Semiconductor device
US8135960B2 (en) * 2007-10-30 2012-03-13 International Business Machines Corporation Multiprocessor electronic circuit including a plurality of processors and electronic data processing system
US8260891B2 (en) * 2007-10-30 2012-09-04 Dell Products L.P. System and method for the provision of secure network boot services
CN102333100B (en) * 2007-11-08 2013-11-06 华为技术有限公司 Authentication method and terminal
JP4992678B2 (en) * 2007-11-13 2012-08-08 富士通株式会社 Image processing method, control program and image processing apparatus
US7866779B2 (en) * 2007-11-16 2011-01-11 Hewlett-Packard Development Company, L.P. Defective nozzle replacement in a printer
CN101441587B (en) * 2007-11-19 2011-05-18 辉达公司 Method and system for automatically analyzing GPU test result
JP5007663B2 (en) * 2007-11-30 2012-08-22 セイコーエプソン株式会社 Business management system and program
US7809980B2 (en) * 2007-12-06 2010-10-05 Jehoda Refaeli Error detector in a cache memory using configurable way redundancy
US8411665B2 (en) 2007-12-11 2013-04-02 At&T Intellectual Property I, L.P. System and method of routing voice communications via peering networks
US8786359B2 (en) * 2007-12-12 2014-07-22 Sandisk Technologies Inc. Current mirror device and method
CA2709327C (en) * 2007-12-13 2015-11-24 Certicom Corp. System and method for controlling features on a device
US7917806B2 (en) * 2007-12-18 2011-03-29 International Business Machines Corporation System and method for indicating status of an on-chip power supply system
KR100909067B1 (en) * 2007-12-18 2009-07-23 한국과학기술원 Wakeup receiver applying constant cycle power block techniques and wake-up method
US8028195B2 (en) * 2007-12-18 2011-09-27 International Business Machines Corporation Structure for indicating status of an on-chip power supply system
US8341751B2 (en) * 2007-12-26 2012-12-25 Wilson Kelce S Software license management
US7723153B2 (en) * 2007-12-26 2010-05-25 Organicid, Inc. Printed organic logic circuits using an organic semiconductor as a resistive load device
US8533384B2 (en) 2007-12-27 2013-09-10 Sandisk Enterprise Ip Llc Flash memory controller garbage collection operations performed independently in multiple flash memory groups
US7756659B2 (en) * 2008-01-11 2010-07-13 Fairchild Semiconductor Corporation Delay stabilization for skew tolerance
US8503679B2 (en) * 2008-01-23 2013-08-06 The Boeing Company Short message encryption
US8108831B2 (en) * 2008-02-07 2012-01-31 Microsoft Corporation Iterative component binding
US9069706B2 (en) * 2008-02-11 2015-06-30 Nvidia Corporation Confidential information protection system and method
US7886089B2 (en) * 2008-02-13 2011-02-08 International Business Machines Corporation Method, system and computer program product for enhanced shared store buffer management scheme for differing buffer sizes with limited resources for optimized performance
US8423993B2 (en) * 2008-02-29 2013-04-16 Red Hat, Inc. Systems and methods for managing software patches
JP4557021B2 (en) * 2008-02-29 2010-10-06 ブラザー工業株式会社 Droplet ejection device
KR100997879B1 (en) * 2008-03-03 2010-12-07 삼성전자주식회사 Crum unit, replaceable unit, image forming device comprising them, and method for performing a cryptographic data communication thereof
US8312534B2 (en) * 2008-03-03 2012-11-13 Lenovo (Singapore) Pte. Ltd. System and method for securely clearing secret data that remain in a computer system memory
US20090228875A1 (en) * 2008-03-04 2009-09-10 Devries Alex Method and System for Reducing Disk Allocation by Profiling Symbol Usage
DK2263146T3 (en) * 2008-03-14 2013-06-24 Hewlett Packard Development Co Secure access to memory in a fluidpatron
US8752038B1 (en) * 2008-03-17 2014-06-10 Symantec Corporation Reducing boot time by providing quantitative performance cost data within a boot management user interface
JP4990315B2 (en) * 2008-03-20 2012-08-01 アナパス・インコーポレーテッド Display device and method for transmitting a clock signal during the blank period
US8171386B2 (en) * 2008-03-27 2012-05-01 Arm Limited Single event upset error detection within sequential storage circuitry of an integrated circuit
US8434064B2 (en) * 2008-03-28 2013-04-30 Microsoft Corporation Detecting memory errors using write integrity testing
US8504980B1 (en) * 2008-04-14 2013-08-06 Sap Ag Constraining data changes during transaction processing by a computer system
US8031952B2 (en) * 2008-04-21 2011-10-04 Broadcom Corporation Method and apparatus for optimizing memory usage in image processing
US8200986B2 (en) * 2008-04-24 2012-06-12 Apple Inc. Computer enabled secure status return
JP5050985B2 (en) * 2008-04-30 2012-10-17 富士通株式会社 Verification support program, the verification support apparatus and the verification support method
WO2009136402A3 (en) * 2008-05-07 2010-03-11 Cosmologic Ltd. Register file system and method thereof for enabling a substantially direct memory access
US9058483B2 (en) 2008-05-08 2015-06-16 Google Inc. Method for validating an untrusted native code module
JP5056573B2 (en) * 2008-05-09 2012-10-24 富士通株式会社 Design support program, design support apparatus, and a design support method
US7882406B2 (en) * 2008-05-09 2011-02-01 Lsi Corporation Built in test controller with a downloadable testing program
JP5220185B2 (en) 2008-05-16 2013-06-26 フュージョン−アイオー・インコーポレーテッド Detecting a failed data storage mechanism, a device for replacing, the system and method
US7788433B2 (en) * 2008-05-24 2010-08-31 Via Technologies, Inc. Microprocessor apparatus providing for secure interrupts and exceptions
US8819839B2 (en) * 2008-05-24 2014-08-26 Via Technologies, Inc. Microprocessor having a secure execution mode with provisions for monitoring, indicating, and managing security levels
US8156391B2 (en) * 2008-05-27 2012-04-10 Lsi Corporation Data controlling in the MBIST chain architecture
US9707783B2 (en) * 2008-05-29 2017-07-18 Hewlett-Packard Development Company, L.P. Replaceable printer component including a memory storing a tag encryption mask
DK2294505T3 (en) * 2008-05-29 2018-04-09 Hewlett Packard Development Co Authentication of replaceable printer component
JP5217647B2 (en) * 2008-06-04 2013-06-19 富士通株式会社 Information processing apparatus and information processing method
US8175403B1 (en) * 2008-06-05 2012-05-08 Google Inc. Iterative backward reference selection with reduced entropy for image compression
US8046643B2 (en) * 2008-06-09 2011-10-25 Lsi Corporation Transport subsystem for an MBIST chain architecture
US20090319736A1 (en) * 2008-06-24 2009-12-24 Hitachi, Ltd. Method and apparatus for integrated nas and cas data backup
US8181230B2 (en) * 2008-06-30 2012-05-15 International Business Machines Corporation System and method for adaptive approximating of a user for role authorization in a hierarchical inter-organizational model
WO2010001324A3 (en) * 2008-06-30 2010-03-25 Mominis Ltd Method of generating and distributing a computer application
US8151008B2 (en) 2008-07-02 2012-04-03 Cradle Ip, Llc Method and system for performing DMA in a multi-core system-on-chip using deadline-based scheduling
US8325554B2 (en) * 2008-07-10 2012-12-04 Sanmina-Sci Corporation Battery-less cache memory module with integrated backup
US8205242B2 (en) 2008-07-10 2012-06-19 Mcafee, Inc. System and method for data mining and security policy management
US8954804B2 (en) * 2008-07-15 2015-02-10 Ati Technologies Ulc Secure boot circuit and method
US8706951B2 (en) 2008-07-18 2014-04-22 Marvell World Trade Ltd. Selectively accessing faster or slower multi-level cell memory
US20100014670A1 (en) * 2008-07-18 2010-01-21 Texas Instruments Incorporated One-Way Hash Extension for Encrypted Communication
US8151349B1 (en) * 2008-07-21 2012-04-03 Google Inc. Masking mechanism that facilitates safely executing untrusted native code
WO2010010163A1 (en) * 2008-07-25 2010-01-28 Em Microelectronic-Marin Sa Processor circuit with shared memory and buffer system
US7992065B2 (en) * 2008-07-29 2011-08-02 Texas Instruments Incorporated Automatic scan format selection based on scan topology selection
CN101329719B (en) * 2008-08-01 2010-11-10 西安西电捷通无线网络通信股份有限公司 Anonymous authentication method suitable for homogeneous electronic label
US20100033788A1 (en) * 2008-08-01 2010-02-11 University Of Florida Research Foundation, Inc. Micromirror and fabrication method for producing micromirror
US8358783B2 (en) 2008-08-11 2013-01-22 Assa Abloy Ab Secure wiegand communications
US9253154B2 (en) 2008-08-12 2016-02-02 Mcafee, Inc. Configuration management for a capture/registration system
FR2935078B1 (en) * 2008-08-12 2012-11-16 Groupe Des Ecoles De Telecommunications Get Ecole Nationale Superieure Des Telecommunications Enst Process for protection decryption of programmable logic configuration files and circuit implementing the PROCESS
US8582052B2 (en) * 2008-08-22 2013-11-12 Gentex Corporation Discrete LED backlight control for a reduced power LCD display system
US20100049658A1 (en) * 2008-08-22 2010-02-25 Javier Sanchez Secure electronic transaction system
US9324072B1 (en) * 2008-08-22 2016-04-26 Ixys Intl Limited Bit-flipping memory controller to prevent SRAM data remanence
US8051467B2 (en) * 2008-08-26 2011-11-01 Atmel Corporation Secure information processing
US8239567B1 (en) 2008-09-09 2012-08-07 Marvell International Ltd. Filtering superfluous data fragments on a computer network
US8356128B2 (en) * 2008-09-16 2013-01-15 Nvidia Corporation Method and system of reducing latencies associated with resource allocation by using multiple arbiters
US8132267B2 (en) 2008-09-30 2012-03-06 Intel Corporation Apparatus and method to harden computer system
US20100083365A1 (en) * 2008-09-30 2010-04-01 Naga Gurumoorthy Apparatus and method to harden computer system
US20100082846A1 (en) * 2008-10-01 2010-04-01 Kyung Hwan Kim Usb device and method for connecting the usb device with usb host
US20100085239A1 (en) * 2008-10-03 2010-04-08 Rosemount Aerospace Inc. Device and method for detecting a target using a high speed sampling device
US8161367B2 (en) * 2008-10-07 2012-04-17 Arm Limited Correction of single event upset error within sequential storage circuitry of an integrated circuit
US8370552B2 (en) * 2008-10-14 2013-02-05 Nvidia Corporation Priority based bus arbiters avoiding deadlock and starvation on buses that support retrying of transactions
US7825721B2 (en) * 2008-10-17 2010-11-02 United Technologies Corp. Systems and methods for filtering signals corresponding to sensed parameters
US8056044B2 (en) 2008-10-21 2011-11-08 Atmel Corporation Signal processing
US8020053B2 (en) * 2008-10-29 2011-09-13 Hewlett-Packard Development Company, L.P. On-line memory testing
US8510713B1 (en) 2008-10-31 2013-08-13 Google Inc. Method and system for validating a disassembler
US20100132047A1 (en) * 2008-11-24 2010-05-27 Honeywell International Inc. Systems and methods for tamper resistant memory devices
US8180730B2 (en) * 2008-11-25 2012-05-15 International Business Machines Corporation Arbitration token for managing data integrity and data accuracy of information services that utilize distributed data replicas
US20100132048A1 (en) * 2008-11-26 2010-05-27 International Business Machines Corporation Protecting Isolated Secret Data of Integrated Circuit Devices
JP5458556B2 (en) * 2008-11-27 2014-04-02 ソニー株式会社 Timing adjustment circuit, solid-state imaging device and a camera system,
US8266593B2 (en) * 2008-12-01 2012-09-11 Wipro Limited System and method for analyzing performance of a software testing system
JP5199392B2 (en) * 2008-12-08 2013-05-15 パナソニック株式会社 System clock monitoring device and a motor control system
US8417761B2 (en) * 2008-12-08 2013-04-09 International Business Machines Corporation Direct decimal number tripling in binary coded adders
US7895385B2 (en) * 2008-12-09 2011-02-22 Nvidia Corporation Establishing communication over serial buses in a slave device
US8194481B2 (en) 2008-12-18 2012-06-05 Mosaid Technologies Incorporated Semiconductor device with main memory unit and auxiliary memory unit requiring preset operation
US8037235B2 (en) * 2008-12-18 2011-10-11 Mosaid Technologies Incorporated Device and method for transferring data to a non-volatile memory device
JP2010149537A (en) * 2008-12-23 2010-07-08 Autonetworks Technologies Ltd Control apparatus, control method, and computer program
US8055936B2 (en) * 2008-12-31 2011-11-08 Pitney Bowes Inc. System and method for data recovery in a disabled integrated circuit
CN101772020B (en) * 2009-01-05 2011-12-28 华为技术有限公司 Authentication processing method and system, 3GPP AAA server and a user equipment
US8850591B2 (en) 2009-01-13 2014-09-30 Mcafee, Inc. System and method for concept building
US8706709B2 (en) 2009-01-15 2014-04-22 Mcafee, Inc. System and method for intelligent term grouping
US8125672B2 (en) * 2009-01-21 2012-02-28 Infoprint Solutions Company Llc Dual ink systems in a printer
US8788850B1 (en) * 2009-01-22 2014-07-22 Marvell International Ltd. Systems and methods for using a security circuit to monitor a voltage of an integrated circuit to counter security threats to the integrated circuit
US8063658B2 (en) * 2009-02-12 2011-11-22 Mosaid Technologies Incorporated Termination circuit for on-die termination
US8371669B1 (en) * 2009-02-18 2013-02-12 Marvell International Ltd. Fire timing control in printing devices
US8242790B2 (en) * 2009-02-23 2012-08-14 Lewis James M Method and system for detection of tampering related to reverse engineering
US8598890B2 (en) * 2009-02-23 2013-12-03 Lewis Innovative Technologies Method and system for protecting products and technology from integrated circuits which have been subject to tampering, stressing and replacement as well as detecting integrated circuits that have been subject to tampering
US8473442B1 (en) 2009-02-25 2013-06-25 Mcafee, Inc. System and method for intelligent state management
JP2010200090A (en) * 2009-02-26 2010-09-09 Toshiba Corp Phase compensation clock synchronizing circuit
US8314942B1 (en) 2009-02-27 2012-11-20 Marvell International Ltd. Positioning and printing of a handheld device
US8782025B2 (en) * 2009-03-10 2014-07-15 Ims Software Services Ltd. Systems and methods for address intelligence
US9245653B2 (en) 2010-03-15 2016-01-26 Intelligent Intellectual Property Holdings 2 Llc Reduced level cell mode for non-volatile memory
US8266503B2 (en) 2009-03-13 2012-09-11 Fusion-Io Apparatus, system, and method for using multi-level cell storage in a single-level cell mode
US8661184B2 (en) 2010-01-27 2014-02-25 Fusion-Io, Inc. Managing non-volatile media
US8854882B2 (en) 2010-01-27 2014-10-07 Intelligent Intellectual Property Holdings 2 Llc Configuring storage cells
US8380915B2 (en) 2010-01-27 2013-02-19 Fusion-Io, Inc. Apparatus, system, and method for managing solid-state storage media
WO2010106537A3 (en) * 2009-03-15 2010-11-18 Authix Tecnologies Srl. Remote product authentication
US8938717B1 (en) * 2009-03-16 2015-01-20 Xilinx, Inc. Updating an installed computer program
JP5366600B2 (en) * 2009-03-16 2013-12-11 キヤノン株式会社 Image forming apparatus
US9442846B2 (en) * 2009-03-17 2016-09-13 Cisco Technology, Inc. High speed memory systems and methods for designing hierarchical memory systems
US8433880B2 (en) 2009-03-17 2013-04-30 Memoir Systems, Inc. System and method for storing data in a virtualized high speed memory system
US8447722B1 (en) 2009-03-25 2013-05-21 Mcafee, Inc. System and method for data mining and security policy management
US8667121B2 (en) 2009-03-25 2014-03-04 Mcafee, Inc. System and method for managing data and policies
US8162433B2 (en) * 2009-03-30 2012-04-24 Xerox Corporation System and method for scheduling ink jet recovery in an ink jet printer
US8698823B2 (en) * 2009-04-08 2014-04-15 Nvidia Corporation System and method for deadlock-free pipelining
US9569282B2 (en) * 2009-04-24 2017-02-14 Microsoft Technology Licensing, Llc Concurrent mutation of isolated object graphs
US8726043B2 (en) * 2009-04-29 2014-05-13 Empire Technology Development Llc Securing backing storage data passed through a network
US8352679B2 (en) * 2009-04-29 2013-01-08 Empire Technology Development Llc Selectively securing data and/or erasing secure data caches responsive to security compromising conditions
US8924743B2 (en) 2009-05-06 2014-12-30 Empire Technology Development Llc Securing data caches through encryption
US8799671B2 (en) * 2009-05-06 2014-08-05 Empire Technology Development Llc Techniques for detecting encrypted data
US8417754B2 (en) * 2009-05-11 2013-04-09 Empire Technology Development, Llc Identification of integrated circuits
US8180981B2 (en) * 2009-05-15 2012-05-15 Oracle America, Inc. Cache coherent support for flash in a memory hierarchy
US8307258B2 (en) 2009-05-18 2012-11-06 Fusion-10, Inc Apparatus, system, and method for reconfiguring an array to operate with less storage elements
US8281227B2 (en) 2009-05-18 2012-10-02 Fusion-10, Inc. Apparatus, system, and method to increase data integrity in a redundant storage system
US20100298984A1 (en) * 2009-05-21 2010-11-25 Lennox Industries, Incorporated Usb hvac service verification
US20100303239A1 (en) * 2009-05-27 2010-12-02 Fujitsu Limited Method and apparatus for protecting root key in control system
US8918642B2 (en) 2009-06-10 2014-12-23 Cisco Technology Inc. Protection of secret value using hardware instability
US8819446B2 (en) 2009-06-26 2014-08-26 International Business Machines Corporation Support for secure objects in a computer system
US9954875B2 (en) 2009-06-26 2018-04-24 International Business Machines Corporation Protecting from unintentional malware download
US9298894B2 (en) * 2009-06-26 2016-03-29 International Business Machines Corporation Cache structure for a computer system providing support for secure objects
JP4772891B2 (en) * 2009-06-30 2011-09-14 株式会社東芝 Host controller, computer terminals and card access method
US8797337B1 (en) 2009-07-02 2014-08-05 Google Inc. Graphics scenegraph rendering for web applications using native code modules
KR101196410B1 (en) * 2009-07-07 2012-11-01 삼성전자주식회사 Method for auto setting configuration of television according to installation type of television and television using the same
US8631411B1 (en) 2009-07-21 2014-01-14 The Research Foundation For The State University Of New York Energy aware processing load distribution system and method
US8984198B2 (en) * 2009-07-21 2015-03-17 Microchip Technology Incorporated Data space arbiter
US20110258372A1 (en) * 2009-07-29 2011-10-20 Panasonic Corporation Memory device, host device, and memory system
US8176150B2 (en) * 2009-08-12 2012-05-08 Dell Products L.P. Automated services procurement through multi-stage process
US8375442B2 (en) * 2009-08-17 2013-02-12 Fatskunk, Inc. Auditing a device
US8949989B2 (en) 2009-08-17 2015-02-03 Qualcomm Incorporated Auditing a device
US8544089B2 (en) * 2009-08-17 2013-09-24 Fatskunk, Inc. Auditing a device
US8370935B1 (en) 2009-08-17 2013-02-05 Fatskunk, Inc. Auditing a device
WO2011031796A3 (en) 2009-09-08 2011-06-30 Fusion-Io, Inc. Apparatus, system, and method for caching data on a solid-state storage device
JP5518197B2 (en) * 2009-09-09 2014-06-11 フュージョン−アイオー・インコーポレーテッド Apparatus for allocating storage, system, and method
US8984216B2 (en) 2010-09-09 2015-03-17 Fusion-Io, Llc Apparatus, system, and method for managing lifetime of a storage device
US8601222B2 (en) 2010-05-13 2013-12-03 Fusion-Io, Inc. Apparatus, system, and method for conditional and atomic storage operations
WO2011031899A3 (en) 2009-09-09 2011-06-16 Fusion-Io, Inc. Apparatus, system, and method for power reduction in a storage device
US9223514B2 (en) 2009-09-09 2015-12-29 SanDisk Technologies, Inc. Erase suspend/resume for memory
US9122579B2 (en) 2010-01-06 2015-09-01 Intelligent Intellectual Property Holdings 2 Llc Apparatus, system, and method for a storage layer
US9084071B2 (en) * 2009-09-10 2015-07-14 Michael-Anthony Lisboa Simple mobile registration mechanism enabling automatic registration via mobile devices
JP5556405B2 (en) * 2009-10-19 2014-07-23 株式会社リコー Power supply control device, an image forming apparatus and power control method
CN102055887A (en) * 2009-10-29 2011-05-11 鸿富锦精密工业(深圳)有限公司 Network camera and data management and control method thereof
WO2011056868A3 (en) 2009-11-04 2011-10-13 New Jersey Institute Of Technology Differential frame based scheduling for input queued switches
US8131889B2 (en) 2009-11-10 2012-03-06 Apple Inc. Command queue for peripheral component
US9672109B2 (en) * 2009-11-25 2017-06-06 International Business Machines Corporation Adaptive dispersed storage network (DSN) and system
US8819452B2 (en) * 2009-11-25 2014-08-26 Cleversafe, Inc. Efficient storage of encrypted data in a dispersed storage network
DE102009047538B4 (en) * 2009-12-04 2018-02-22 Endress + Hauser Process Solutions Ag A method for optimizing the parameters setting from power supply parameters of a field device power supply module
US8452989B1 (en) * 2009-12-09 2013-05-28 Emc Corporation Providing security to an electronic device
WO2011075167A1 (en) * 2009-12-15 2011-06-23 Memoir Systems,Inc. System and method for reduced latency caching
DE102009055271A1 (en) * 2009-12-23 2011-06-30 Carl Zeiss NTS GmbH, 73447 A method for generating a representation of an object using a particle as well as particle beam device for carrying out the method
US20110161560A1 (en) * 2009-12-31 2011-06-30 Hutchison Neil D Erase command caching to improve erase performance on flash memory
US9514055B2 (en) * 2009-12-31 2016-12-06 Seagate Technology Llc Distributed media cache for data storage systems
US9134918B2 (en) * 2009-12-31 2015-09-15 Sandisk Technologies Inc. Physical compression of data with flat or systematic pattern
US8645930B2 (en) * 2010-01-04 2014-02-04 Apple Inc. System and method for obfuscation by common function and common function prototype
WO2011088074A3 (en) * 2010-01-12 2011-12-01 Stc. Unm System and methods for generating unclonable security keys in integrated circuits
WO2011094312A1 (en) * 2010-01-26 2011-08-04 Silver Tail Systems, Inc. System and method for network security including detection of man-in-the-browser attacks
US8315092B2 (en) * 2010-01-27 2012-11-20 Fusion-Io, Inc. Apparatus, system, and method for determining a read voltage threshold for solid-state storage media
JP5446943B2 (en) * 2010-01-29 2014-03-19 ソニー株式会社 Method for controlling the printing system and a printer device
WO2011097482A1 (en) 2010-02-05 2011-08-11 Maxlinear, Inc. Conditional access integration in a soc for mobile tv applications
US9177152B2 (en) 2010-03-26 2015-11-03 Maxlinear, Inc. Firmware authentication and deciphering for secure TV receiver
US8432981B1 (en) * 2010-03-10 2013-04-30 Smsc Holdings S.A.R.L. High frequency and idle communication signal state detection
US8370648B1 (en) * 2010-03-15 2013-02-05 Emc International Company Writing and reading encrypted data using time-based encryption keys
KR20110105153A (en) * 2010-03-18 2011-09-26 삼성전자주식회사 Flipflop circuit and scan flipflop circuit
JP5479177B2 (en) * 2010-03-19 2014-04-23 株式会社Pfu The information processing apparatus, consumables management method and program
US9141580B2 (en) 2010-03-23 2015-09-22 Citrix Systems, Inc. Systems and methods for monitoring and maintaining consistency of a configuration
US20120079279A1 (en) * 2010-03-29 2012-03-29 Maxlinear, Inc. Generation of SW Encryption Key During Silicon Manufacturing Process
WO2011123561A1 (en) 2010-03-30 2011-10-06 Maxlinear, Inc. Control word obfuscation in secure tv receiver
CA2799738A1 (en) * 2010-05-17 2011-11-24 Jon Parsons System and method for multi-dimensional secretion of digital data
JP5528209B2 (en) * 2010-05-20 2014-06-25 キヤノン株式会社 Image processing apparatus and image processing method
US9311664B2 (en) * 2010-05-25 2016-04-12 Salesforce.Com, Inc. Systems and methods for automatically collection of performance data in a multi-tenant database system environment
US20110302551A1 (en) * 2010-06-02 2011-12-08 Hummel Jr David Martin System and method for analytic process design
WO2011156745A3 (en) * 2010-06-10 2012-03-08 The Regents Of The University Of California Strong single and multiple error correcting wom codes, coding methods and devices
US8433727B2 (en) * 2010-06-22 2013-04-30 Red Hat Israel, Ltd. Method and apparatus for restricting access to writable properties at runtime
US8514630B2 (en) 2010-07-09 2013-08-20 Sandisk Technologies Inc. Detection of word-line leakage in memory arrays: current based approach
US8432732B2 (en) 2010-07-09 2013-04-30 Sandisk Technologies Inc. Detection of word-line leakage in memory arrays
US8305807B2 (en) 2010-07-09 2012-11-06 Sandisk Technologies Inc. Detection of broken word-lines in memory arrays
US8782434B1 (en) 2010-07-15 2014-07-15 The Research Foundation For The State University Of New York System and method for validating program execution at run-time
US8904189B1 (en) 2010-07-15 2014-12-02 The Research Foundation For The State University Of New York System and method for validating program execution at run-time using control flow signatures
EP2598996A4 (en) 2010-07-28 2013-12-18 Fusion Io Inc Apparatus, system, and method for conditional and atomic storage operations
US9213522B2 (en) 2010-07-29 2015-12-15 Ford Global Technologies, Llc Systems and methods for scheduling driver interface tasks based on driver workload
GB2496765B (en) 2010-07-29 2014-04-16 Ford Global Tech Llc Systems and methods for scheduling driver interface tasks based on driver workload
US8972106B2 (en) 2010-07-29 2015-03-03 Ford Global Technologies, Llc Systems and methods for scheduling driver interface tasks based on driver workload
US8892855B2 (en) 2010-08-10 2014-11-18 Maxlinear, Inc. Encryption keys distribution for conditional access software in TV receiver SOC
JP2012043071A (en) * 2010-08-16 2012-03-01 Canon Inc Adjusting system, adjusting device, adjusting method and program for the same
US8867682B2 (en) * 2010-08-30 2014-10-21 Exar Corporation Dejitter (desynchronize) technique to smooth gapped clock with jitter/wander attenuation using all digital logic
US8819672B2 (en) * 2010-09-20 2014-08-26 International Business Machines Corporation Multi-image migration system and method
JP5159849B2 (en) * 2010-09-24 2013-03-13 株式会社東芝 Memory management unit and memory management method
US9454504B2 (en) * 2010-09-30 2016-09-27 Hewlett-Packard Development Company, L.P. Slave device bit sequence zero driver
US8976691B2 (en) 2010-10-06 2015-03-10 Blackbird Technology Holdings, Inc. Method and apparatus for adaptive searching of distributed datasets
US9042353B2 (en) 2010-10-06 2015-05-26 Blackbird Technology Holdings, Inc. Method and apparatus for low-power, long-range networking
US8718551B2 (en) 2010-10-12 2014-05-06 Blackbird Technology Holdings, Inc. Method and apparatus for a multi-band, multi-mode smartcard
US8532100B2 (en) * 2010-10-19 2013-09-10 Cisco Technology, Inc. System and method for data exchange in a heterogeneous multiprocessor system
US8904356B2 (en) 2010-10-20 2014-12-02 International Business Machines Corporation Collaborative software debugging in a distributed system with multi-member variable expansion
US8972945B2 (en) 2010-10-21 2015-03-03 International Business Machines Corporation Collaborative software debugging in a distributed system with client-specific access control
US9009673B2 (en) 2010-10-21 2015-04-14 International Business Machines Corporation Collaborative software debugging in a distributed system with collaborative step over operation
US8671393B2 (en) 2010-10-21 2014-03-11 International Business Machines Corporation Collaborative software debugging in a distributed system with client-specific dynamic breakpoints
US8687004B2 (en) * 2010-11-01 2014-04-01 Apple Inc. Font file with graphic images
US8806615B2 (en) 2010-11-04 2014-08-12 Mcafee, Inc. System and method for protecting specified data combinations
US8850397B2 (en) 2010-11-10 2014-09-30 International Business Machines Corporation Collaborative software debugging in a distributed system with client-specific display of local variables
US8990775B2 (en) 2010-11-10 2015-03-24 International Business Machines Corporation Collaborative software debugging in a distributed system with dynamically displayed chat sessions
US9411709B2 (en) 2010-11-10 2016-08-09 International Business Machines Corporation Collaborative software debugging in a distributed system with client-specific event alerts
US8622312B2 (en) 2010-11-16 2014-01-07 Blackbird Technology Holdings, Inc. Method and apparatus for interfacing with a smartcard
US9208071B2 (en) 2010-12-13 2015-12-08 SanDisk Technologies, Inc. Apparatus, system, and method for accessing memory
US9047178B2 (en) 2010-12-13 2015-06-02 SanDisk Technologies, Inc. Auto-commit memory synchronization
US8527693B2 (en) 2010-12-13 2013-09-03 Fusion IO, Inc. Apparatus, system, and method for auto-commit memory
US9218278B2 (en) 2010-12-13 2015-12-22 SanDisk Technologies, Inc. Auto-commit memory
US8559927B2 (en) 2010-12-21 2013-10-15 Empire Technology Development, Llc Dummy information for location privacy in location based services
FR2970133B1 (en) * 2010-12-30 2013-01-18 Thales Sa Method and system for testing a cryptographic integrity of a given tolerant to errors
US8589509B2 (en) 2011-01-05 2013-11-19 Cloudium Systems Limited Controlling and optimizing system latency
US20120179943A1 (en) * 2011-01-06 2012-07-12 International Business Machines Corporation Method for information transfer in a voltage-driven intelligent characterization bench for semiconductor
JP5598337B2 (en) * 2011-01-12 2014-10-01 ソニー株式会社 Memory access control circuit, a prefetch circuit, a memory device and an information processing system
WO2012100087A3 (en) 2011-01-19 2012-09-20 Fusion-Io, Inc. Apparatus, system, and method for managing out-of-service conditions
WO2012100145A1 (en) * 2011-01-21 2012-07-26 Blackbird Technology Holdings, Inc. Method and apparatus for memory management
WO2012102736A1 (en) 2011-01-28 2012-08-02 Hewlett-Packard Development Company, L.P. Document management system and method
US8484477B2 (en) 2011-01-30 2013-07-09 Hewlett-Packard Development Company, L.P. Document management system and method
US8966184B2 (en) 2011-01-31 2015-02-24 Intelligent Intellectual Property Holdings 2, LLC. Apparatus, system, and method for managing eviction of data
WO2012109139A1 (en) * 2011-02-08 2012-08-16 Telcordia Technologies, Inc. Method and apparatus for secure data representation allowing efficient collection, search and retrieval
JP5842335B2 (en) * 2011-02-08 2016-01-13 セイコーエプソン株式会社 Image recording apparatus, a control method for an image recording apparatus, and a program
WO2012112650A1 (en) 2011-02-15 2012-08-23 Blackbird Technology Holdings, Inc. Method and apparatus for plug and play, networkable iso 18000-7 connectivity
US9003104B2 (en) 2011-02-15 2015-04-07 Intelligent Intellectual Property Holdings 2 Llc Systems and methods for a file-level cache
US8874823B2 (en) 2011-02-15 2014-10-28 Intellectual Property Holdings 2 Llc Systems and methods for managing data input/output operations
US8954752B2 (en) 2011-02-23 2015-02-10 International Business Machines Corporation Building and distributing secure object software
US8578175B2 (en) 2011-02-23 2013-11-05 International Business Machines Corporation Secure object having protected region, integrity tree, and unprotected region
JP2012174184A (en) * 2011-02-24 2012-09-10 Canon Inc Information processing device and control method of information processing device
WO2012116369A3 (en) 2011-02-25 2013-03-14 Fusion-Io, Inc. Apparatus, system, and method for managing contents of a cache
US20120221767A1 (en) 2011-02-28 2012-08-30 Apple Inc. Efficient buffering for a system having non-volatile memory
US9497715B2 (en) 2011-03-02 2016-11-15 Blackbird Technology Holdings, Inc. Method and apparatus for addressing in a resource-constrained network
US8763075B2 (en) * 2011-03-07 2014-06-24 Adtran, Inc. Method and apparatus for network access control
US8493120B2 (en) 2011-03-10 2013-07-23 Arm Limited Storage circuitry and method with increased resilience to single event upsets
CN102180022B (en) * 2011-03-11 2013-08-14 珠海艾派克微电子有限公司 Imaging box, imaging device and imaging control method
US8364729B2 (en) 2011-03-17 2013-01-29 Hewlett-Packard Development Company, L.P. Document management system and method
US9563555B2 (en) 2011-03-18 2017-02-07 Sandisk Technologies Llc Systems and methods for storage allocation
WO2012129191A3 (en) 2011-03-18 2012-12-27 Fusion-Io, Inc. Logical interfaces for contextual storage
US8649609B1 (en) 2011-03-24 2014-02-11 The United States Of America As Represented By The Adminstrator Of The National Aeronautics And Space Administration Field programmable gate array apparatus, method, and computer program
US8605346B2 (en) * 2011-04-06 2013-12-10 Hon Hai Precision Industry Co., Ltd. Image processing apparatus and method for controlling same
US8667321B2 (en) * 2011-04-14 2014-03-04 Mstar Semiconductor, Inc. Controlling method and controller for memory
US8739127B2 (en) * 2011-04-20 2014-05-27 International Business Machines Corporation Collaborative software debugging in a distributed system with symbol locking
US8656360B2 (en) 2011-04-20 2014-02-18 International Business Machines Corporation Collaborative software debugging in a distributed system with execution resumption on consensus
US8806438B2 (en) 2011-04-20 2014-08-12 International Business Machines Corporation Collaborative software debugging in a distributed system with variable-specific messages
WO2011113377A3 (en) * 2011-04-26 2012-04-19 华为技术有限公司 Method and apparatus for calibrating low frequency clock
US8719957B2 (en) * 2011-04-29 2014-05-06 Altera Corporation Systems and methods for detecting and mitigating programmable logic device tampering
US8379454B2 (en) 2011-05-05 2013-02-19 Sandisk Technologies Inc. Detection of broken word-lines in memory arrays
US9063862B2 (en) 2011-05-17 2015-06-23 Sandisk Technologies Inc. Expandable data cache
US9201677B2 (en) 2011-05-23 2015-12-01 Intelligent Intellectual Property Holdings 2 Llc Managing data input/output operations
US20120302212A1 (en) * 2011-05-25 2012-11-29 Critical Medical Solutions, Inc. Secure mobile radiology communication system
US8977930B1 (en) * 2011-06-02 2015-03-10 Drc Computer Corporation Memory architecture optimized for random access
US9077499B2 (en) * 2011-06-15 2015-07-07 Metanoia Communications Inc. Automatic power saving for communication systems
US8817976B2 (en) * 2011-06-24 2014-08-26 Gregory Scott Callen Reversible cipher
US8756577B2 (en) 2011-06-28 2014-06-17 International Business Machines Corporation Collaborative software debugging in a distributed system with private debug sessions
US20130002315A1 (en) * 2011-07-01 2013-01-03 Philippe Boucard Asynchronous clock adapter
US8929961B2 (en) 2011-07-15 2015-01-06 Blackbird Technology Holdings, Inc. Protective case for adding wireless functionality to a handheld electronic device
US8850284B2 (en) * 2011-07-21 2014-09-30 Silicon Motion Inc. Flash memory controller and data reading method
US8601276B2 (en) 2011-07-27 2013-12-03 Hewlett-Packard Development Company, L.P. Managing access to a secure content-part of a PPCD following introduction of the PPCD into a workflow
US8984298B2 (en) 2011-07-27 2015-03-17 Hewlett-Packard Development Company, L.P. Managing access to a secure content-part of a PPCD using a key reset point
US8750042B2 (en) 2011-07-28 2014-06-10 Sandisk Technologies Inc. Combined simultaneous sensing of multiple wordlines in a post-write read (PWR) and detection of NAND failures
US8726104B2 (en) 2011-07-28 2014-05-13 Sandisk Technologies Inc. Non-volatile memory and method with accelerated post-write read using combined verification of multiple pages
US8775901B2 (en) 2011-07-28 2014-07-08 SanDisk Technologies, Inc. Data recovery for defective word lines during programming of non-volatile memory arrays
US8880713B2 (en) * 2011-07-29 2014-11-04 General Electric Company System and methods for use in communicating with an energy management device in an energy device network
JP2013031961A (en) * 2011-08-02 2013-02-14 Ricoh Co Ltd Power supply control device and image forming apparatus
US9021146B2 (en) 2011-08-30 2015-04-28 Apple Inc. High priority command queue for peripheral component
US8810267B2 (en) 2011-08-31 2014-08-19 Truesense Imaging, Inc. Device identification and temperature sensor circuit
US8821012B2 (en) 2011-08-31 2014-09-02 Semiconductor Components Industries, Llc Combined device identification and temperature measurement
US9846789B2 (en) 2011-09-06 2017-12-19 International Business Machines Corporation Protecting application programs from malicious software or malware
US9231926B2 (en) * 2011-09-08 2016-01-05 Lexmark International, Inc. System and method for secured host-slave communication
US8872635B2 (en) * 2011-10-25 2014-10-28 Static Control Components, Inc. Systems and methods for verifying a chip
US8635467B2 (en) 2011-10-27 2014-01-21 Certicom Corp. Integrated circuit with logic circuitry and multiple concealing circuits
US8334705B1 (en) 2011-10-27 2012-12-18 Certicom Corp. Analog circuitry to conceal activity of logic circuitry
US9069494B2 (en) * 2011-10-31 2015-06-30 Xerox Corporation Evaluating and managing image quality performance and improving service effectiveness of groups of production printers
US8793543B2 (en) 2011-11-07 2014-07-29 Sandisk Enterprise Ip Llc Adaptive read comparison signal generation for memory systems
US9288161B2 (en) * 2011-12-05 2016-03-15 International Business Machines Corporation Verifying the functionality of an integrated circuit
US9330031B2 (en) 2011-12-09 2016-05-03 Nvidia Corporation System and method for calibration of serial links using a serial-to-parallel loopback
US9262250B2 (en) 2011-12-12 2016-02-16 Crashlytics, Inc. System and method for data collection and analysis of information relating to mobile applications
US9703680B1 (en) 2011-12-12 2017-07-11 Google Inc. System and method for automatic software development kit configuration and distribution
US9087154B1 (en) 2011-12-12 2015-07-21 Crashlytics, Inc. System and method for providing additional functionality to developer side application in an integrated development environment
JP6039579B2 (en) * 2011-12-13 2016-12-07 キヤノン株式会社 Method of manufacturing a nozzle tip
US8725934B2 (en) 2011-12-22 2014-05-13 Fusion-Io, Inc. Methods and appratuses for atomic storage operations
US9274937B2 (en) 2011-12-22 2016-03-01 Longitude Enterprise Flash S.A.R.L. Systems, methods, and interfaces for vector input/output operations
US20130163034A1 (en) * 2011-12-27 2013-06-27 Xerox Corporation Vendor selection method and system for wide format printing
US20130246336A1 (en) 2011-12-27 2013-09-19 Mcafee, Inc. System and method for providing data protection workflows in a network environment
US9213645B2 (en) 2011-12-29 2015-12-15 Sandisk Technologies Inc. Command aware partial page programming
US8458804B1 (en) 2011-12-29 2013-06-04 Elwha Llc Systems and methods for preventing data remanence in memory
US9727511B2 (en) 2011-12-30 2017-08-08 Bedrock Automation Platforms Inc. Input/output module with multi-channel switching capability
EP3121013A3 (en) 2012-01-05 2017-03-01 ZIH Corp. Method and apparatus for printhead control
US9370939B2 (en) 2012-01-05 2016-06-21 Zih Corp. Method and apparatus for printer control
US20130179614A1 (en) * 2012-01-10 2013-07-11 Diarmuid P. Ross Command Abort to Reduce Latency in Flash Memory Access
US9570124B2 (en) * 2012-01-11 2017-02-14 Viavi Solutions Inc. High speed logging system
US9251052B2 (en) 2012-01-12 2016-02-02 Intelligent Intellectual Property Holdings 2 Llc Systems and methods for profiling a non-volatile cache having a logical-to-physical translation layer
US9767032B2 (en) 2012-01-12 2017-09-19 Sandisk Technologies Llc Systems and methods for cache endurance
US9299451B2 (en) 2012-01-20 2016-03-29 International Business Machines Corporation Tamper resistant electronic system utilizing acceptable tamper threshold count
US8918680B2 (en) 2012-01-23 2014-12-23 Apple Inc. Trace queue for peripheral component
US9251086B2 (en) 2012-01-24 2016-02-02 SanDisk Technologies, Inc. Apparatus, system, and method for managing a cache
US9116812B2 (en) 2012-01-27 2015-08-25 Intelligent Intellectual Property Holdings 2 Llc Systems and methods for a de-duplication cache
US9059168B2 (en) 2012-02-02 2015-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Adjustable meander line resistor
US8890222B2 (en) 2012-02-03 2014-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Meander line resistor structure
US9418247B2 (en) * 2012-02-07 2016-08-16 MCube Inc. Security system and methods for integrated devices
US8918885B2 (en) * 2012-02-09 2014-12-23 International Business Machines Corporation Automatic discovery of system integrity exposures in system code
US8812466B2 (en) * 2012-02-10 2014-08-19 International Business Machines Corporation Detecting and combating attack in protection system of an industrial control system
JP2015515770A (en) 2012-02-29 2015-05-28 アルトネット、インコーポレイテッド Stream recognition and filtering
US8914767B2 (en) * 2012-03-12 2014-12-16 Symantec Corporation Systems and methods for using quick response codes to activate software applications
US8699715B1 (en) * 2012-03-27 2014-04-15 Emc Corporation On-demand proactive epoch control for cryptographic devices
US8776195B1 (en) * 2012-03-30 2014-07-08 Emc Corporation Common data format in knowledge-based authentication
US9764561B2 (en) 2012-04-04 2017-09-19 Xerox Corporation System and method for clearing weak and missing inkjets in an inkjet printer
US9218477B2 (en) 2012-04-13 2015-12-22 Lewis Innovative Technologies Electronic physical unclonable functions
DE102012103466B4 (en) * 2012-04-20 2015-08-27 Océ Printing Systems GmbH & Co. KG Printing method and device
US8985723B2 (en) 2012-04-20 2015-03-24 Xerox Corporation System and method of compensating for defective inkjets
US9215590B2 (en) 2012-04-20 2015-12-15 Bank Of America Corporation Authentication using vehicle data pairing
JP5918004B2 (en) * 2012-04-27 2016-05-18 株式会社東海理化電機製作所 Electronic key registration system
EP2859679A1 (en) * 2012-05-23 2015-04-15 The University Of Leeds Secure communication
US8854413B2 (en) 2012-06-01 2014-10-07 Cisco Technology, Inc. Communicating with an endpoint using matrix barcodes
WO2013186889A1 (en) * 2012-06-14 2013-12-19 三菱電機株式会社 I/o device, programmable logic controller, and arithmetic processing method
FR2992083B1 (en) * 2012-06-19 2014-07-04 Alstom Transport Sa Computer, communication assembly comprising such a computer, railway management system comprising such an assembly, and reliability of data process in a computer
US8804415B2 (en) 2012-06-19 2014-08-12 Fusion-Io, Inc. Adaptive voltage range management in non-volatile memory
US9618635B2 (en) 2012-06-21 2017-04-11 Honeywell International Inc. Integrated radiation sensitive circuit
US8575560B1 (en) 2012-06-21 2013-11-05 Honeywell International Inc. Integrated circuit cumulative dose radiation sensor
US8933412B2 (en) 2012-06-21 2015-01-13 Honeywell International Inc. Integrated comparative radiation sensitive circuit
US9612966B2 (en) 2012-07-03 2017-04-04 Sandisk Technologies Llc Systems, methods and apparatus for a virtual machine cache
US8667141B2 (en) * 2012-07-03 2014-03-04 Xerox Corporation Method and system for handling load on a service component in a network
WO2014011454A3 (en) * 2012-07-09 2014-04-17 Jvl Ventures, Llc Systems, methods, and computer program products for integrating third party services with a mobile wallet
US8955937B2 (en) 2012-07-23 2015-02-17 Xerox Corporation System and method for inoperable inkjet compensation
US9258907B2 (en) 2012-08-09 2016-02-09 Lockheed Martin Corporation Conformal 3D non-planar multi-layer circuitry
US9699263B1 (en) 2012-08-17 2017-07-04 Sandisk Technologies Llc. Automatic read and write acceleration of data accessed by virtual machines
JP5750414B2 (en) * 2012-08-27 2015-07-22 東芝テック株式会社 The ink jet head driving device
US8786889B2 (en) * 2012-08-29 2014-07-22 Eastman Kodak Company Method for computing scale for tag insertion
US8928929B2 (en) * 2012-08-29 2015-01-06 Eastman Kodak Company System for generating tag layouts
US20140068183A1 (en) 2012-08-31 2014-03-06 Fusion-Io, Inc. Systems, methods, and interfaces for adaptive persistence
US9319878B2 (en) 2012-09-14 2016-04-19 Qualcomm Incorporated Streaming alignment of key stream to unaligned data stream
US9122873B2 (en) 2012-09-14 2015-09-01 The Research Foundation For The State University Of New York Continuous run-time validation of program execution: a practical approach
US8938796B2 (en) 2012-09-20 2015-01-20 Paul Case, SR. Case secure computer architecture
KR20140067180A (en) * 2012-10-19 2014-06-05 삼성전자주식회사 Security management unit, host controller interface including the same, method for operating the host controller interface, and devices including the host controller interface
CN102929674B (en) * 2012-11-02 2016-02-10 威盛电子股份有限公司 And a booting method of the electronic device
US9595350B2 (en) * 2012-11-05 2017-03-14 Nxp Usa, Inc. Hardware-based memory initialization
US9098709B2 (en) * 2012-11-13 2015-08-04 International Business Machines Corporation Protection of user data in hosted application environments
US8714692B1 (en) 2012-12-04 2014-05-06 Xerox Corporation System and method of compensating for defective inkjets with context dependent image data
GB2508631A (en) * 2012-12-06 2014-06-11 Ibm Propagating a query in a network by applying a delay at a node
KR20140076840A (en) * 2012-12-13 2014-06-23 에스케이하이닉스 주식회사 Integrated circuit and semiconductor device using the same
US9501398B2 (en) 2012-12-26 2016-11-22 Sandisk Technologies Llc Persistent storage device with NVRAM for staging writes
US9612948B2 (en) 2012-12-27 2017-04-04 Sandisk Technologies Llc Reads and writes between a contiguous data block and noncontiguous sets of logical address blocks in a persistent storage device
US9239751B1 (en) 2012-12-27 2016-01-19 Sandisk Enterprise Ip Llc Compressing data from multiple reads for error control management in memory systems
US20140188261A1 (en) * 2012-12-28 2014-07-03 Sunedison, Inc. Methods and systems for preventing unsafe operations
US9454420B1 (en) 2012-12-31 2016-09-27 Sandisk Technologies Llc Method and system of reading threshold voltage equalization
US20140197865A1 (en) 2013-01-11 2014-07-17 International Business Machines Corporation On-chip randomness generation
JP6071565B2 (en) * 2013-01-11 2017-02-01 キヤノン株式会社 Method for manufacturing a liquid discharge head
EP2759405A3 (en) * 2013-01-25 2016-06-01 Müller Martini Holding AG Method for the capture and transmission of process control data prior to and/or within a print process for the production of printed products in a printing machine
EP2954415A4 (en) 2013-02-08 2016-11-09 Everspin Technologies Inc Tamper detection and response in a memory device
US9218509B2 (en) 2013-02-08 2015-12-22 Everspin Technologies, Inc. Response to tamper detection in a memory device
US9065632B2 (en) * 2013-02-20 2015-06-23 Qualcomm Incorporated Message authentication using a universal hash function computed with carryless multiplication
US9088459B1 (en) * 2013-02-22 2015-07-21 Jpmorgan Chase Bank, N.A. Breadth-first resource allocation system and methods
US9753487B2 (en) 2013-03-14 2017-09-05 Micron Technology, Inc. Serial peripheral interface and methods of operating same
US8772745B1 (en) 2013-03-14 2014-07-08 Lockheed Martin Corporation X-ray obscuration film and related techniques
US9870830B1 (en) 2013-03-14 2018-01-16 Sandisk Technologies Llc Optimal multilevel sensing for reading data from a storage medium
US9842053B2 (en) 2013-03-15 2017-12-12 Sandisk Technologies Llc Systems and methods for persistent cache logging
US9244763B1 (en) 2013-03-15 2016-01-26 Sandisk Enterprise Ip Llc System and method for updating a reading threshold voltage based on symbol transition information
US9136877B1 (en) 2013-03-15 2015-09-15 Sandisk Enterprise Ip Llc Syndrome layered decoding for LDPC codes
US9236886B1 (en) 2013-03-15 2016-01-12 Sandisk Enterprise Ip Llc Universal and reconfigurable QC-LDPC encoder
US9215075B1 (en) 2013-03-15 2015-12-15 Poltorak Technologies Llc System and method for secure relayed communications from an implantable medical device
US9367246B2 (en) 2013-03-15 2016-06-14 Sandisk Technologies Inc. Performance optimization of data transfer for soft information generation
US9059742B1 (en) * 2013-03-15 2015-06-16 Western Digital Technologies, Inc. System and method for dynamic scaling of LDPC decoder in a solid state drive
US9235468B2 (en) * 2013-04-12 2016-01-12 Qualcomm Incorporated Systems and methods to improve the reliability and lifespan of flash memory
RU2518950C9 (en) * 2013-05-06 2014-09-10 Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Санкт-Петербургский государственный электротехнический университет "ЛЭТИ" им. В.И. Ульянова (Ленина)" Method of encrypting n-bit unit m
US20140358792A1 (en) * 2013-05-30 2014-12-04 Dell Products L.P. Verifying oem components within an information handling system using original equipment manufacturer (oem) identifier
US8896086B1 (en) * 2013-05-30 2014-11-25 Freescale Semiconductor, Inc. System for preventing tampering with integrated circuit
US9230137B2 (en) * 2013-05-30 2016-01-05 Dell Products, L.P. Secure original equipment manufacturer (OEM) identifier for OEM devices
US9159437B2 (en) 2013-06-11 2015-10-13 Sandisk Enterprise IP LLC. Device and method for resolving an LM flag issue
DE102013212525A1 (en) * 2013-06-27 2014-12-31 Siemens Aktiengesellschaft Data storage device for secure data exchange between different security zones
US9898782B1 (en) 2013-06-28 2018-02-20 Winklevoss Ip, Llc Systems, methods, and program products for operating exchange traded products holding digital math-based assets
US9397500B2 (en) * 2013-06-28 2016-07-19 Solantro Semiconductor Corp. Inverter with extended endurance memory
WO2015001657A1 (en) * 2013-07-04 2015-01-08 富士通株式会社 Data network management system, data network management device, data processing device, and data network management method
CN103915119B (en) 2013-07-11 2017-02-15 威盛电子股份有限公司 Data storage device and a control method of a flash memory
US9131578B2 (en) 2013-07-16 2015-09-08 General Electric Company Programmable light emitting diode (LED) driver technique based upon an input voltage signal
US9194914B2 (en) * 2013-07-16 2015-11-24 Advanced Micro Devices, Inc. Power supply monitor for detecting faults during scan testing
US9179527B2 (en) * 2013-07-16 2015-11-03 General Electric Company Programmable light emitting diode (LED) driver technique based upon a prefix signal
US9384126B1 (en) 2013-07-25 2016-07-05 Sandisk Technologies Inc. Methods and systems to avoid false negative results in bloom filters implemented in non-volatile data storage systems
US9524235B1 (en) 2013-07-25 2016-12-20 Sandisk Technologies Llc Local hash value generation in non-volatile data storage systems
US9842128B2 (en) 2013-08-01 2017-12-12 Sandisk Technologies Llc Systems and methods for atomic storage operations
US9467297B2 (en) 2013-08-06 2016-10-11 Bedrock Automation Platforms Inc. Industrial control system redundant communications/control modules authentication
US9191203B2 (en) 2013-08-06 2015-11-17 Bedrock Automation Platforms Inc. Secure industrial control system
US9639463B1 (en) 2013-08-26 2017-05-02 Sandisk Technologies Llc Heuristic aware garbage collection scheme in storage systems
US9361221B1 (en) 2013-08-26 2016-06-07 Sandisk Technologies Inc. Write amplification reduction through reliable writes during garbage collection
US9466236B2 (en) * 2013-09-03 2016-10-11 Synaptics Incorporated Dithering to avoid pixel value conversion errors
US20150074374A1 (en) * 2013-09-06 2015-03-12 Futurewei Technologies Inc. Method and apparatus for asynchronous processor with auxiliary asynchronous vector processor
US9569385B2 (en) 2013-09-09 2017-02-14 Nvidia Corporation Memory transaction ordering
EP2849024A1 (en) 2013-09-16 2015-03-18 ST-Ericsson SA Power consumption management system and method
JP6146570B2 (en) * 2013-09-20 2017-06-14 東芝ライテック株式会社 Dimming control system
US9189617B2 (en) * 2013-09-27 2015-11-17 Intel Corporation Apparatus and method for implementing zero-knowledge proof security techniques on a computing platform
US9195857B2 (en) * 2013-09-30 2015-11-24 Infineon Technologies Ag Computational system
US20150095222A1 (en) * 2013-10-02 2015-04-02 Tyfone, Inc. Dynamic identity representation in mobile devices
US20150097839A1 (en) * 2013-10-07 2015-04-09 Tektronix, Inc. Stochastic rasterization of waveform trace displays
US9442662B2 (en) 2013-10-18 2016-09-13 Sandisk Technologies Llc Device and method for managing die groups
US9298608B2 (en) 2013-10-18 2016-03-29 Sandisk Enterprise Ip Llc Biasing for wear leveling in storage systems
US20160234530A1 (en) * 2013-10-25 2016-08-11 Microsoft Technology Licensing, Llc Hash-based block matching in video and image coding
EP3061233A4 (en) * 2013-10-25 2016-10-12 Microsoft Technology Licensing Llc Representing blocks with hash values in video and image coding and decoding
US9436831B2 (en) * 2013-10-30 2016-09-06 Sandisk Technologies Llc Secure erase in a memory device
US9263156B2 (en) 2013-11-07 2016-02-16 Sandisk Enterprise Ip Llc System and method for adjusting trip points within a storage device
KR20160085325A (en) 2013-11-12 2016-07-15 프린트릴리프 인크. Automated computer controlled system for measuring the consumption of printer resources and transacting environmental offsets
US9244785B2 (en) 2013-11-13 2016-01-26 Sandisk Enterprise Ip Llc Simulated power failure and data hardening
US9703816B2 (en) 2013-11-19 2017-07-11 Sandisk Technologies Llc Method and system for forward reference logging in a persistent datastore
US20150149024A1 (en) * 2013-11-22 2015-05-28 Sikorsky Aircraft Corporation Latency tolerant fault isolation
US9520197B2 (en) 2013-11-22 2016-12-13 Sandisk Technologies Llc Adaptive erase of a storage device
US9520162B2 (en) 2013-11-27 2016-12-13 Sandisk Technologies Llc DIMM device controller supervisor
US9582058B2 (en) 2013-11-29 2017-02-28 Sandisk Technologies Llc Power inrush management of storage devices
US9235245B2 (en) 2013-12-04 2016-01-12 Sandisk Enterprise Ip Llc Startup performance and power isolation
US9223965B2 (en) 2013-12-10 2015-12-29 International Business Machines Corporation Secure generation and management of a virtual card on a mobile device
US9235692B2 (en) 2013-12-13 2016-01-12 International Business Machines Corporation Secure application debugging
US9497178B2 (en) 2013-12-31 2016-11-15 International Business Machines Corporation Generating challenge response sets utilizing semantic web technology
US9659137B2 (en) * 2014-02-18 2017-05-23 Samsung Electronics Co., Ltd. Method of verifying layout of mask ROM
US9703314B2 (en) * 2014-02-26 2017-07-11 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus for a variable frequency and phase clock generation circuit
RU2564243C1 (en) * 2014-02-28 2015-09-27 Открытое Акционерное Общество "Информационные Технологии И Коммуникационные Системы" Cryptographic transformation method
US9703636B2 (en) 2014-03-01 2017-07-11 Sandisk Technologies Llc Firmware reversion trigger and control
US20160277761A1 (en) * 2014-03-04 2016-09-22 Microsoft Technology Licensing, Llc Encoder-side decisions for block flipping and skip mode in intra block copy prediction
US9542558B2 (en) 2014-03-12 2017-01-10 Apple Inc. Secure factory data generation and restoration
US9390814B2 (en) 2014-03-19 2016-07-12 Sandisk Technologies Llc Fault detection and prediction for data storage elements
US9448876B2 (en) 2014-03-19 2016-09-20 Sandisk Technologies Llc Fault detection and prediction in storage devices
US9454448B2 (en) 2014-03-19 2016-09-27 Sandisk Technologies Llc Fault testing in storage devices
US9324448B2 (en) 2014-03-25 2016-04-26 Semiconductor Components Industries, Llc Fuse element programming circuit and method
US9641809B2 (en) * 2014-03-25 2017-05-02 Nxp Usa, Inc. Circuit arrangement and method for processing a digital video stream and for detecting a fault in a digital video stream, digital video system and computer readable program product
RU2542880C1 (en) * 2014-03-31 2015-02-27 Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Санкт-Петербургский государственный электротехнический университет"ЛЭТИ" им. В.И. Ульянова (Ленина)" Method of encrypting binary data unit
US9626399B2 (en) 2014-03-31 2017-04-18 Sandisk Technologies Llc Conditional updates for reducing frequency of data modification operations
US9626400B2 (en) 2014-03-31 2017-04-18 Sandisk Technologies Llc Compaction of information in tiered data structure
US9390021B2 (en) 2014-03-31 2016-07-12 Sandisk Technologies Llc Efficient cache utilization in a tiered data structure
US20150277927A1 (en) * 2014-04-01 2015-10-01 National Chung Cheng University Speculative lookahead processing device and method
US9697267B2 (en) 2014-04-03 2017-07-04 Sandisk Technologies Llc Methods and systems for performing efficient snapshots in tiered data structures
RU2542929C1 (en) * 2014-04-14 2015-02-27 Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Санкт-Петербургский государственный электротехнический университет "ЛЭТИ" им. В.И. Ульянова (Ленина)" Method to code data unit represented as bit string
RU2542926C1 (en) * 2014-04-14 2015-02-27 Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Санкт-Петербургский государственный электротехнический университет "ЛЭТИ" им. В.И. Ульянова (Ленина)" Method to code message represented as multidigit binary number
DE102014207479A1 (en) * 2014-04-17 2015-10-22 Robert Bosch Gmbh A method for classifying a data segment with respect to its further processing
US9768957B2 (en) * 2014-04-23 2017-09-19 Cryptography Research, Inc. Generation and management of multiple base keys based on a device generated key
US9246501B2 (en) 2014-04-29 2016-01-26 Honeywell International Inc. Converter for analog inputs
EP2940869B1 (en) * 2014-04-30 2017-09-06 Nxp B.V. Synchronised logic circuit
WO2015174979A1 (en) * 2014-05-15 2015-11-19 Ge Intelligent Platforms, Inc. Intrinsically safe universal i/o device using programmable asic
US9343116B2 (en) 2014-05-28 2016-05-17 Micron Technology, Inc. Providing power availability information to memory
US9703491B2 (en) 2014-05-30 2017-07-11 Sandisk Technologies Llc Using history of unaligned writes to cache data and avoid read-modify-writes in a non-volatile storage device
US9652381B2 (en) 2014-06-19 2017-05-16 Sandisk Technologies Llc Sub-block garbage collection
EP3158751A4 (en) * 2014-06-23 2017-07-12 Microsoft Technology Licensing Llc Encoder decisions based on results of hash-based block matching
US9258117B1 (en) 2014-06-26 2016-02-09 Amazon Technologies, Inc. Mutual authentication with symmetric secrets and signatures
US9819488B2 (en) * 2014-07-10 2017-11-14 Ohio State Innovation Foundation Generation of encryption keys based on location
US9826252B2 (en) 2014-07-29 2017-11-21 Nxp Usa, Inc. Method and video system for freeze-frame detection
US9434165B2 (en) 2014-08-28 2016-09-06 Funai Electric Co., Ltd. Chip layout to enable multiple heater chip vertical resolutions
US9443601B2 (en) 2014-09-08 2016-09-13 Sandisk Technologies Llc Holdup capacitor energy harvesting
KR20160030701A (en) * 2014-09-11 2016-03-21 삼성전자주식회사 Host divice transmitting print data to printer and method for rendering print data by host device
JP2016063399A (en) * 2014-09-18 2016-04-25 富士ゼロックス株式会社 Image forming apparatus and image data processing apparatus
US20160098162A1 (en) * 2014-10-06 2016-04-07 Lenovo (Singapore) Pte. Ltd. Pen based locking mechanism
US9552192B2 (en) * 2014-11-05 2017-01-24 Oracle International Corporation Context-based generation of memory layouts in software programs
US20160140049A1 (en) * 2014-11-18 2016-05-19 Micron Technology, Inc. Wireless memory interface
KR101582168B1 (en) * 2014-11-19 2016-01-05 서울대학교산학협력단 Clock Recovery Scheme at DisplayPort Receiver
US9780952B1 (en) * 2014-12-12 2017-10-03 Amazon Technologies, Inc. Binding digitally signed requests to sessions
US9639425B1 (en) * 2015-01-13 2017-05-02 Marvell International Ltd. Signature-based sleep recovery operation flow
CN105891651A (en) 2015-01-16 2016-08-24 飞思卡尔半导体公司 Low power open circuit detection system
US9606851B2 (en) 2015-02-02 2017-03-28 International Business Machines Corporation Error monitoring of a memory device containing embedded error correction
US9825621B2 (en) * 2015-02-05 2017-11-21 Canon Kabushiki Kaisha Information processing apparatus capable of reducing amount of radiation noise and control method therefor
US9946677B2 (en) * 2015-02-12 2018-04-17 Atmel Corporation Managing single-wire communications
US9940457B2 (en) * 2015-02-13 2018-04-10 International Business Machines Corporation Detecting a cryogenic attack on a memory device with embedded error correction
US9946607B2 (en) 2015-03-04 2018-04-17 Sandisk Technologies Llc Systems and methods for storage error management
US9979782B2 (en) 2015-03-24 2018-05-22 Qualcomm Incorporated Low-power and low-latency device enumeration with cartesian addressing
JP2016198967A (en) 2015-04-10 2016-12-01 キヤノン株式会社 Image recording device and control method for the same
RU2580060C1 (en) * 2015-05-20