US20100187651A1 - Integrated circuit package and method of forming the same - Google Patents

Integrated circuit package and method of forming the same Download PDF

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Publication number
US20100187651A1
US20100187651A1 US12/578,382 US57838209A US2010187651A1 US 20100187651 A1 US20100187651 A1 US 20100187651A1 US 57838209 A US57838209 A US 57838209A US 2010187651 A1 US2010187651 A1 US 2010187651A1
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Prior art keywords
integrated circuit
portion
forming
lead frame
material
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Abandoned
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US12/578,382
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Yonggang Jin
Kiyoshi Kuwabara
Xavier Baraton
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STMicroelectronics Asia Pacific Pte Ltd
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STMicroelectronics Asia Pacific Pte Ltd
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Priority to US14743009P priority Critical
Application filed by STMicroelectronics Asia Pacific Pte Ltd filed Critical STMicroelectronics Asia Pacific Pte Ltd
Priority to US12/578,382 priority patent/US20100187651A1/en
Assigned to STMICROELECTRONICS ASIA PACIFIC PTE LTD. reassignment STMICROELECTRONICS ASIA PACIFIC PTE LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BARATON, XAVIER, KUWABARA, KIYOSHI, JIN, YONGGANG
Publication of US20100187651A1 publication Critical patent/US20100187651A1/en
Assigned to STMICROELECTRONICS PTE LTD. reassignment STMICROELECTRONICS PTE LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: STMICROELECTRONICS ASIA PACIFIC PTE LTD.
Assigned to STMICROELECTRONICS PTE LTD reassignment STMICROELECTRONICS PTE LTD CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE PREVIOUSLY RECORDED ON REEL 023365 FRAME 0789. ASSIGNOR(S) HEREBY CONFIRMS THE STMICROELECTRONICS ASIA PACIFIC PTE LTD SHOULD BE STMICROELECTRONICS PTE LTD. Assignors: KUWABARA, KIYOSHI, BARATON, XAVIER, JIN, YONGGANG
Application status is Abandoned legal-status Critical

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    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19042Component type being an inductor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19043Component type being a resistor

Abstract

Aspects of the invention are directed towards an integrated circuit package and method of forming the same, and more particularly to a redistributed chip packaging for an integrated circuit. The integrated circuit package includes an integrated circuit having a protective material on at least a portion of the integrated circuit. A lead frame is coupled to the integrated circuit and a conductive layer is also coupled to the interconnect. A solder ball is coupled to the conductive layer and a passivation layer is on the conductive layer. Active and passive components are electrically coupled to the integrated circuit.

Description

  • This application claims the benefit of U.S. Provisional Patent Application No. 61/147,430, filed on Jan. 26, 2009, which is hereby incorporated by reference for all purposes as if fully set forth herein.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The invention relates to an integrated circuit package and method of forming the same, and more particularly to a redistributed chip packaging for an integrated circuit.
  • 2. Discussion of the Related Art
  • With continuously decreasing semiconductor device dimensions and increasing device packaging densities, the packaging of semiconductor devices has continued to gain in importance. In the electronics industry, the continuing goal has been to reduce the size of electronic devices such as in digital cameras and camcorders. Metal interconnects, thereby including points of metal contact solder bumps that connect a semiconductor to surrounding circuits, increasingly become important.
  • SUMMARY OF THE INVENTION
  • Accordingly, the present invention is directed to an integrated circuit package and method of forming the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
  • An advantage of an embodiment of the invention is to provide reduced processing steps for foaming a chip packing.
  • Another advantage of an embodiment of the invention is to provide a reduced cost of forming a chip packing.
  • Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
  • To achieve these and other advantages and in accordance with the purpose of the invention, an embodiment of the invention is directed towards an integrated circuit package. The integrated circuit package includes an integrated circuit having a protective material on at least a portion of the integrated circuit. A lead frame is coupled to the integrated circuit and a conductive layer is also coupled to the interconnect. A solder ball is coupled to the conductive layer and a passivation layer is on the conductive layer. Active and passive components are electrically coupled to the integrated circuit.
  • In another aspect, an embodiment of the invention is directed towards a method of forming an integrated circuit package. The method includes forming a lead frame including a first portion and a second portion. The first portion and the second portion of the lead frame intersect at an angle ranging from about 45 degrees to about 135 degrees. An adhesive material is formed on the first portion of the lead frame and a carrier is attached to the lead frame with the adhesive material. An integrated circuit is also attached to the adhesive material. Interconnects are formed on the integrated circuit and protective material is formed on the integrated circuit.
  • In another aspect, an embodiment of the invention is directed towards a method of making an integrated circuit package. The method includes forming a lead frame including a first portion and a second portion. The first portion and the second portion of the lead frame intersect at an angle ranging from about 45 degrees to about 135 degrees. A double sided thermal tape is adhered to a bottom surface of the first portion of the lead frame; attaching a carrier to the lead frame with the thermal double-sided thermal tape is also part of the method. The method further includes attaching an integrated circuit to the thermal double-sided adhesive tape adjacent to the first portion of the lead frame and forming at least one pillar interconnect on the integrated circuit. A compressive compound is formed over the integrated circuit as well as over the first and second portions of the lead frame. The compressive compound is hardened by heating the compressive compound to a temperature in the range of about 120° C. to about 150° C.
  • It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.
  • In the drawings:
  • FIG. 1A illustrates a cross-sectional view of manufacturing a lead frame of the integrated circuit package of FIG. 1 according to an embodiment of the invention;
  • FIG. 1B illustrates a top-down view of the lead frame in FIG. 1A;
  • FIG. 2 illustrates a cross-sectional view of an intermediate stage of manufacturing the integrated circuit package of FIG. 1;
  • FIG. 3 illustrates a cross-sectional view of an intermediate stage of manufacturing the integrated circuit package of FIG. 1;
  • FIG. 4 illustrates a cross-sectional view of an intermediate stage of manufacturing the integrated circuit package of FIG. 1;
  • FIG. 5 illustrates a cross-sectional view of an intermediate stage of manufacturing the integrated circuit package of FIG. 1; and
  • FIG. 6 illustrates a completed integrated circuit package.
  • DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS
  • Reference will now be made in detail to an embodiment of the present invention, an example of which is illustrated in the accompanying drawings.
  • FIG. 1A illustrates a cross-sectional view of manufacturing an integrated circuit package according to an embodiment of the invention.
  • FIG. 1A illustrates forming a lead frame 100 having a first portion 102 and a second portion 104. The first portion 102 and the second portion 104 intersect forming an angle 106 ranging from about 45 degrees to about 135 degrees. In a preferred embodiment, the angle ranges from about 85 degrees to about 95 degrees. In a more preferred embodiment, the angle is about 90 degrees. The lead frame 100 comprises a conductive material. The conductive material may be a single material or an alloy material such as aluminum, gold, copper, combinations thereof, and the like. Now referring to FIG. 1B, it shows a top-down view of the lead frame 100. The lead frame is manufactured by forming the conductive material via stamping or etching as known in the art. In a preferred embodiment, the conductive material is stamped to form a plurality of open spaces 108 and bent into the desired angle 106 as shown in FIG. 1A.
  • FIG. 2 illustrates a cross-sectional view of an intermediate stage of manufacturing the integrated circuit package after forming the lead frame.
  • Referring to FIG. 2, an adhesive material 202 is formed on the bottom portion of the lead frame 100. In a preferred embodiment, the adhesive material 202 is double-sided thermal release tape such as 3195V by Nitto Denko, Japan. The double-sided thermal release tape is capable of being removed after thermo process at a high temperature ranging from about 175° C. to about 260° C. The adhesive material 202 is attached to a bottom surface of the lead frame and/or a carrier 204; next the carrier 204 is attached to an opposite surface of the adhesive material 202. The carrier 204 is for transportation of the apparatus and may include materials such as plastics, glass (e.g., low temperature CT glass), ceramics, steel, combinations thereof, and the like.
  • An integrated circuit chip 206 is attached to the adhesive material 202. The integrated circuit chip 206 is arranged between second portions 104 of the lead frame 100. At least one interconnect 208 is formed on the integrated circuit chip 206. In a preferred embodiment, the interconnect 208 includes a conductive material, e.g., copper, gold, pewter, combinations thereof, and the like, formed by plating as known in the art. In a preferred embodiment, the interconnect is a copper pillar bump. Of course, other conductive materials may also be used, such as alloys and the like.
  • FIG. 3 illustrates a cross-sectional view of an intermediate stage of manufacturing the integrated circuit package after attaching a carrier.
  • Referring to FIG. 3, a protective material 302 is formed over the structure in FIG. 2. The protective material is an encapsulant of material such as epoxy, plastic, polymers, combinations thereof, and the like. In a preferred embodiment, the protective material is an epoxy compressive molding compound. The protective material may either come in powder or liquid form. If in powder form, the powder needs to be processed before applying. The compressive molding compound is capable of being hardened during a molding process. In this embodiment, a mold (not shown) is affixed from the top and bottom and heated for the desired time and to the desired temperature to harden the protective material. After which, the mold is released, thereby forming a hardened protective material 302.
  • In a preferred embodiment, the hardening process includes heating the compound to a temperature ranging from about 120° C. to about 150° C. for a time ranging from about 2 to about 10 minutes. Also, in the preferred embodiment, the epoxy part is R4212 epoxy molding compound from Nagase Corp. of Japan.
  • FIG. 4 illustrates a cross-sectional view of an intermediate stage of manufacturing the integrated circuit package after forming the compressive molding compound.
  • Referring to FIG. 4, the adhesive material 202 and carrier 204 are removed by heating the apparatus to a thermal release temperature, e.g., a temperature ranging from about 175° C. to about 260° C. In a preferred embodiment, the apparatus is heated to a temperature of about 260° C.
  • FIG. 5 illustrates a cross-sectional view of an intermediate stage of manufacturing the integrated circuit package after forming the compressive molding compound.
  • Referring to FIG. 5, an upper and lower portion of the compressive molding compound 302 is removed. Removing these portions may be accomplished with grinding and/or polishing procedures as known in the art such as wheel silicon grinding. In a preferred embodiment, the compressive molding on the lower surface is grinded to remove the second portion 104 of the lead frame 100, e.g., about 115 μm of the second portion 104. The upper surface of the compressive molding compound 302 is removed to expose a surface of the interconnect 208 and the first portion 102 of the lead frame 100.
  • FIG. 6 illustrates a completed integrated circuit package.
  • Referring to FIG. 6, a first metallization layer is formed on a first surface of the compressive molding 302. A second metallization layer is formed on a second surface of the compressive molding 302. The first and second metallization layers are formed of conductive material to a thickness ranging from about 3 μm to about 10 μM via chemical vapor deposition, physical vapor deposition, and the like. The first metallization layer is etched to form interconnect traces 602. The second metallization layer is etched to form interconnect traces 604. The first and second metallization layers may be faulted of different materials. In a preferred embodiment, the first and second metallization layers consist of copper, aluminum, gold, or alloys thereof.
  • A first passivation layer 606 is formed on the interconnect traces 602 and a second passivation layer 608 is formed on the interconnect traces 604. The first passivation layer 606 is etched to form a contact hole 610. The first and second passivation layers are formed of insulative material via polymers, e.g., photosensitive liquid polymers. The insulating materials may include parylene, polyimide, benzocyclobutene (BCB), polybenzoxazole. (PBO), combinations thereof, and the like. The first and second passivation layers may be formed of different materials. A solder ball 612 is formed in the contact hole 610. The solder ball 612 is formed from conventional processes and may include a conductive material, such as silver, copper, tin, combinations thereof, and the like. Components 614, such as passive or active components including, for example, capacitors, resistors, transistors, inductors, combinations thereof, and the like, are attached to the interconnect traces 604.
  • It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims (20)

1. An integrated circuit package, comprising:
an integrated circuit;
a protective material on at least a portion of the integrated circuit;
a lead frame coupled to the integrated circuit;
a conductive layer coupled to the interconnect;
a solder ball coupled the conductive layer; and
a passivation layer on the conductive layer.
2. The integrated circuit package of claim 1, wherein the protective material comprises a compressive molding compound.
3. The integrated circuit package of claim 2, wherein the compressive molding compound comprises epoxy.
4. The integrated circuit package of claim 1, wherein the lead frame comprises a material selected from the group consisting of Al, Au, Cu, and combinations thereof.
5. The integrated circuit package of claim 1, wherein the passivation layer comprises an insulating polymer selected from the group consisting of parylene, polyimide, benzocyclobutene (BCB), and polybenzoxazole (PBO).
6. The integrated circuit package of claim 1, wherein the lead frame comprises a conductive material selected from the group consisting of Au, Al, Cu, Ti, and alloys of the same.
7. The integrated circuit package of claim 1, further comprising at least one of active and passive components electrically coupled to the integrated circuit.
8. A method of forming an integrated circuit package, comprising the steps of:
forming a lead frame comprising a first portion and a second portion, wherein the first portion and the second portion intersect at an angle ranging from about 45 degrees to about 135 degrees;
forming an adhesive material on the first portion of the lead frame;
attaching a carrier to the lead frame with the adhesive material;
attaching an integrated circuit to the adhesive material;
forming an interconnect on the integrated circuit; and
forming a protective material on the integrated circuit.
9. The method of claim 8, wherein the angle is in the range from about 85 degrees to about 95 degrees.
10. The method of claim 8, wherein forming the protective layer comprises the step of:
heating an epoxy material to a temperature in the range from about 120° C. to about 150° C. to harden the epoxy material.
11. The method of claim 8, further comprising removing the carrier and the adhesive material by heating an epoxy material to a temperature from about 175° C. to about 260° C. to thermally release the adhesive material and carrier.
12. The method of claim 11, further comprising the steps:
removing a portion of the hardened epoxy material to expose the interconnect and the first portion of the lead frame; and
removing the second portion of the lead frame.
13. The method of claim 12, wherein removing the portion of hardened epoxy material comprises grinding an upper surface of the hardened compound.
14. The method of claim 12, further comprising the steps of:
forming a conductive material on the hardened compound;
forming a passivation layer on the conductive material; and
faulting a solder ball on the passivation layer, wherein the solder ball is electrically coupled to the conductive material.
15. A method of making an integrated circuit package, comprising the steps of:
forming a lead frame comprising a first portion and a second portion, wherein the first portion and the second portion intersect at an angle ranging from about 45 degrees to about 135 degrees;
adhering a double-sided thermal tape to a bottom surface of the first portion of the lead frame;
attaching a carrier to the lead frame with the double-sided thermal tape;
attaching an integrated circuit to the double-sided thermal adhesive tape adjacent to the first portion of the lead frame;
forming at least one pillar interconnect on the integrated circuit;
forming a compressive compound over the integrated circuit and the first and second portions of the lead frame; and
hardening the compressive compound by heating the compressive compound to a temperature in the range from about 120° C. to about 150° C.
16. The method of claim 15, further comprising the steps:
removing a portion of the hardened molding to expose the pillar interconnect and the second portion of the lead frame; and
removing the first portion of the lead frame.
17. The method of claim 16, wherein the removing the portion of compressive molding step comprises grinding an upper surface of the compressive molding.
18. The method of claim 17, further comprising the steps of:
forming a conductive material on the hardened molding;
forming a first passivation layer on an upper surface of the conductive material;
forming a second passivation layer on a lower surface of the compressive molding material; and
forming a solder ball on the first passivation layer, wherein the solder ball is electrically coupled to the conductive material.
19. The method of claim 15, wherein the compressive molding material comprises an epoxy material.
20. The method of claim 18, further comprising the steps of attaching a component to the lower surface of the compressive molding.
US12/578,382 2009-01-26 2009-10-13 Integrated circuit package and method of forming the same Abandoned US20100187651A1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130249068A1 (en) * 2012-03-20 2013-09-26 Byung Tai Do Integrated circuit packaging system with external interconnect and method of manufacture thereof
CN103745938A (en) * 2014-02-08 2014-04-23 华进半导体封装先导技术研发中心有限公司 Manufacture method of fan-out wafer level package

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9543262B1 (en) * 2009-08-18 2017-01-10 Cypress Semiconductor Corporation Self aligned bump passivation

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5556810A (en) * 1990-06-01 1996-09-17 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device wherein a semiconductor chip is connected to a lead frame by metal plating
US20020019073A1 (en) * 2000-08-14 2002-02-14 Samsung Electronics Co. Ltd Method for manufacturing a dual chip package
US7294920B2 (en) * 2004-07-23 2007-11-13 Industrial Technology Research Institute Wafer-leveled chip packaging structure and method thereof
US20100176905A1 (en) * 2005-10-05 2010-07-15 Lotfi Ashraf W Magnetic Device Having a Conductive Clip
US8067821B1 (en) * 2008-04-10 2011-11-29 Amkor Technology, Inc. Flat semiconductor package with half package molding
US8525314B2 (en) * 2004-11-03 2013-09-03 Tessera, Inc. Stacked packaging improvements

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5480503A (en) * 1993-12-30 1996-01-02 International Business Machines Corporation Process for producing circuitized layers and multilayer ceramic sub-laminates and composites thereof
MY154596A (en) * 2007-07-25 2015-06-30 Carsem M Sdn Bhd Thin plastic leadless package with exposed metal die paddle

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5556810A (en) * 1990-06-01 1996-09-17 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device wherein a semiconductor chip is connected to a lead frame by metal plating
US20020019073A1 (en) * 2000-08-14 2002-02-14 Samsung Electronics Co. Ltd Method for manufacturing a dual chip package
US7294920B2 (en) * 2004-07-23 2007-11-13 Industrial Technology Research Institute Wafer-leveled chip packaging structure and method thereof
US8525314B2 (en) * 2004-11-03 2013-09-03 Tessera, Inc. Stacked packaging improvements
US20100176905A1 (en) * 2005-10-05 2010-07-15 Lotfi Ashraf W Magnetic Device Having a Conductive Clip
US8067821B1 (en) * 2008-04-10 2011-11-29 Amkor Technology, Inc. Flat semiconductor package with half package molding

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130249068A1 (en) * 2012-03-20 2013-09-26 Byung Tai Do Integrated circuit packaging system with external interconnect and method of manufacture thereof
US9324641B2 (en) * 2012-03-20 2016-04-26 Stats Chippac Ltd. Integrated circuit packaging system with external interconnect and method of manufacture thereof
CN103745938A (en) * 2014-02-08 2014-04-23 华进半导体封装先导技术研发中心有限公司 Manufacture method of fan-out wafer level package

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