US20100172116A1 - Shielded electronic components and method of manufacturing the same - Google Patents

Shielded electronic components and method of manufacturing the same Download PDF

Info

Publication number
US20100172116A1
US20100172116A1 US12/612,699 US61269909A US2010172116A1 US 20100172116 A1 US20100172116 A1 US 20100172116A1 US 61269909 A US61269909 A US 61269909A US 2010172116 A1 US2010172116 A1 US 2010172116A1
Authority
US
United States
Prior art keywords
board
electronic component
shielded electronic
sealant
plating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/612,699
Inventor
Chiko Yorita
Yoshihide Yamaguchi
Yuji Shirai
Yu Hasegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2008-286254 priority Critical
Priority to JP2008286254A priority patent/JP5324191B2/en
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Assigned to RENESAS TECHNOLOGY CORP. reassignment RENESAS TECHNOLOGY CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HASEGAWA, YU, SHIRAI, YUJI, YAMAGUCHI, YOSHIHIDE, YORITA, CHIKO
Publication of US20100172116A1 publication Critical patent/US20100172116A1/en
Assigned to NEC ELECTRRONICS CORPORATION reassignment NEC ELECTRRONICS CORPORATION MERGER (SEE DOCUMENT FOR DETAILS). Assignors: RENESAS TECHNOLOGY CORP.
Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: NEC ELECTRONICS CORPORATION
Application status is Abandoned legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565Moulds
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836Wafer tapes, e.g. grinding or dicing support tapes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/284Applying non-metallic protective coatings for encapsulating mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00Screening of apparatus or components against electric or magnetic fields
    • H05K9/0073Shielding materials
    • H05K9/0081Electromagnetic shielding materials, e.g. EMI, RFI shielding
    • H05K9/0084Electromagnetic shielding materials, e.g. EMI, RFI shielding comprising a single continuous metallic layer on an electrically insulating supporting structure, e.g. metal foil, film, plating coating, electro-deposition, vapour-deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/0651Wire or wire-like electrical connections from device to substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of H01L27/00 - H01L49/00 and H01L51/00, e.g. forming hybrid circuits
    • H01L25/165Containers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01027Cobalt [Co]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01045Rhodium [Rh]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01051Antimony [Sb]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • H01L2924/143Digital devices
    • H01L2924/1433Application-specific integrated circuit [ASIC]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0044Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/181Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126Assembling bases

Abstract

A shielded electronic component including a wiring board, at least one semiconductor chip mounted on a main surface of the wiring board, a sealant which seals the whole of an upper surface of the wiring board, and a nickel (Ni) plating film formed on an upper surface of the sealant is provided. The Ni plating film is formed on a palladium (Pd) pretreatment layer formed on the upper surface of the sealant with using high-pressure CO2 in a state of protecting a back surface of the wiring board, and is electrically connected with an end portion of a ground wiring layer of the wiring board or a ground (GND) connection through-hole connected with the end portion of the ground wiring layer.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • The present application claims priority from Japanese Patent Application No. JP 2008-286254 filed on Nov. 7, 2008, the content of which is hereby incorporated by reference into this application.
  • TECHNICAL FIELD OF THE INVENTION
  • The present invention relates to a shielded electronic component and a method of manufacturing the same. More particularly, the present invention relates to mounting of electric components including semiconductors such as a semiconductor-mounting electronic component which requires a shielding structure for avoiding adverse effects of ambient radio waves and electromagnetic noise from semiconductors, and a semiconductor mounting electronic component which requires shielding of noise generated from itself.
  • BACKGROUND OF THE INVENTION
  • A mobile phone will be exemplified to describe a mounting structure of electronic components including semiconductors.
  • Various electronic components are mounted on a mounting board inside a mobile phone. Functions of the board are largely classified into the following configurations.
  • That is, an RF (radio frequency) unit which receives high-frequency waves from a cell site (base station) by an antenna and reduces the frequency to make it low enough to be processed and/or amplifies the high-frequency waves to radio waves transmittable to the cell site, and a baseband unit including: a CPU (central processing unit) which processes received signals; various application processors which process images, audio etc.; and/or a memory device (memory). Frequencies of the transceived radio waves processed by the RF unit are as follows.
  • First, frequencies used in respective communication standards in Japan are: 800 MHz band for PDC (personal digital cellular); 1.5 MHz band for cdmaOne (code division multiple access one); 1.7 GHz band for CDMA200, and 2100 MHz band for W-CDMA (wideband code division multiple access).
  • Also, frequencies used in the global communication system GSM (global system for mobile communications) systems being mainly used in Europe are 900 MHz band and 1800 to 1900 MHz band. Frequencies used in the communication system D-AMPS (digital advanced mobile phone system) being used in United States and Canada are in 800 MHz band and 900 MHz band.
  • A component which amplifies transmitted waves so that the waves have respective frequencies of the above for transmitting radio waves from a phone to a cell site is power amplifier. There are various communication systems/frequency compatible types by way of selecting and combining frequencies from those mentioned above depending on the ways of use and regions. Since the output characteristics of a transistor(s) which amplifies radio waves in the power amplifier are nonlinear, noise of second harmonic and third harmonic is generated in the output of the part desired to have ensured efficiency.
  • While the circuit is designed to remove the noise on the transmitted waves by a filter, noise is generated from the power amplifier component itself, and it may negatively affect peripheral electronic components including semiconductors.
  • To describe high-frequency devices having a wireless function, mobile phones in Japan will be exemplified. Except for the power amplifier, there are near field wireless communication by infrared communication and/or Bluetooth, a TV tuner for the one-segment broadcasting in 400 MHz band, an FM/AM radio tuner, etc. In the future, various wireless communications such as WiFi (wireless fidelity) wireless LAN are expected to be mounted. Therefore, it is necessary to concern interactive influence of electromagnetic noise generated from these electronic components.
  • Second, a CPU that achieves main function in a phone, a main memory device, various application processors handling images, video, music, security etc., various memories, and/or passive components are mounted in the baseband unit. Clock frequencies of these application processors have been increased year by year. When they are mounted separately from an external memory, instruction error is easily generated due to disturbance noise.
  • In view of preventing the error, design load reduction, power consumption reduction, and mounting area reduction, a structure of stacking and packaging a processor and a memory has been increasingly employed. While current flows in a bonding wire when transmitting/receiving high-speed signals between an application processor and a memory, the wire part becomes an antenna to generate electromagnetic waves, so that a magnetic field and an electric field (noise) are generated in the line path of the current.
  • As to a countermeasure for noise of a mounting board in a mobile phone, when there is relatively a margin in the arrangement of semiconductor components and so the components which are feared to have noise interference can be separately mounted, normally, a metal cap is mounted in a large area size per function block unit so that a shielding effect can be obtained.
  • However, in the trend of high functionality and ultra-thin frame of recent mobile phones, the design is made to eliminate dead space as making a sterically mounting arrangement by packing components into available space. In such a design, it is difficult to ensure a mounting area for large components, even for the indispensable shielding cap. However, there has been a problem of posing erroneous operation due to influence of noise in removing the metal cap and neighboring a semiconductor for high-speed communication, a semiconductor for high-speed image processing and a power amplifier of an RF circuit as a single package without a shield.
  • For example, as to an electronic component aiming for individual shielding, as described in Japanese Patent Application Laid-Open Publication No. 2005-322752 (Patent Document 1), a structure in which a metal cap is put on a mounting board with respect to a module in which an IC and/or passive components are mounted on a board is generally used to solve the above problem.
  • However, in this structure, the inside of the cap is not resin-molded, and thus there is a difficulty in mass production when the resin molding process of large semiconductor packages to be formed with resin molding is changed to a metal cap structure, because the cost of the metal cap is expensive.
  • In addition, as an area of a substrate for ensuring a thickness of the metal cap and/or a mounting area is necessary, the electronic parts cannot be down-sized. Also, while the electronic components are mounted on a board of a product by solder reflow after shipment, one of typical lead-free solders to be used in the reflow is Sn3Ag0.5Cu solder paste.
  • A temperature of a reflow process in which a SnAgCu-based Pb-free solder paste is printed and the solder is heated to be melted is set such that a temperature higher than or equal to 217° C. which is a melting point of the Sn3Ag0.5Cu solder is ensured for about 40 to 60 seconds, for example.
  • In this time, the peak temperature is set to about 260° C. It is predicted that the electronic components will be subjected to the heating process at least once and three times at the most for connection of the components themselves. Incidentally, the three-time heating process is effects of connection of the components themselves, repair heating of adjacent components, and heating for mounting new components.
  • The electronic components may absorb water on the way of transfer. On that assumption, the JEDEC (joint electron device engineering council) standard sets a reliability guarantee standard of sensitivity level with respect to humidity to which the product is exposed in order to guarantee that there is no problem in the connecting points by performing heating complying with reflow after a water absorption test for a fixed period.
  • For example, JEDEC LEVEL 2 preconditions a reflow test of “subjecting the component in a relatively humid environment of 85° C./85% for 168 hours followed by reflow at 260° C. for three times.” If the component meets JEDEC LEVEL 2, a solder reflow connection of the component is guaranteed after leaving the product in a relatively humid atmosphere at 30° C. or lower and in 85% relative humidity of actual environment. If the electronic component does not meet JEDEC LEVEL 2, volume of water sneaked into the electronic component is expanded when the electronic component is assembled and mounted by reflow, resulting in a defect of exfoliation of an adhering surface and/or a connection portion inside the component.
  • Accordingly, there have been conventional methods which satisfy downsizing and high reliability in electronic components by forming a metal plating film, which can substitute the metal cap, on a mold resin.
  • Japanese Patent Application Laid-Open Publication No. 2004-297054 (Patent Document 2) and Japanese Patent Application Laid-Open Publication No. 2005-109306 (Patent Document 3) describe such methods of forming an electromagnetic shield to a semiconductor package.
  • Patent Document 2 discloses an example of an electromagnetic shield structure in which a shielding film is formed to cover the surface of a semiconductor device including semiconductor ICs mounted on a multilayer wiring board and subjected to resin molding, and the shielding film is electrically connected to a cut wiring portion(s) protruding at an edge portion(s) of the multilayer board. It is described that the shielding film is formed of a conductive paste by plating, sputtering, or CVD.
  • Also, Patent Document 3 discloses a method for achieving improvement of package shielding and reduction in size, height and weight of electronic components, and providing a sufficient shielding effect even to high frequencies, the method providing: a circuit board having a ground pattern; an electronic component mounted on a top surface of the circuit board; a sealant of an epoxy resin containing inorganic filler molding the mounted components; and a metal shield layer formed of a nonelectrolytic Cu (copper) plating layer, an electrolytic Cu plating layer, and an anti-oxidation layer for copper of these layers, the metal shield layer being formed on the sealant and connected with the ground pattern.
  • SUMMARY OF THE INVENTION
  • As to such a mounting configuration formed with a shield plating, the formed package was made to absorb moisture in an 85° C./85% RH (relative humidity) atmosphere and a reflow test was performed to make the maximum temperature to 260° C. After the test, a failure occurs such that the plating film for shielding formed on the package surface was expanded and exfoliated. This exfoliation occurred between the surface of the mold resin and the plating film.
  • Also, in a temperature cycle test (e.g., −30° C./125° C. in 30 min. cycle) after a reflow test in order to proving reliability, a failure occurs such that the shielding film formed by applying a paste has a deteriorated shielding property as the adhesiveness with the layer connected with the ground is decreased.
  • It is supposed that a ratio of metal bonding surface area and a ratio of contact surface area of the shielding metal that is electrically connected with the electrode and the ground wiring connected with a side and/or a surface of the module board are decreased due to deterioration by the temperature cycle test.
  • Micro breaking inside the material due to local strain caused by a difference in linear expansion coefficient of the material due to temperature rising/falling in the temperature cycle test starts to occur between the ground metal and the shielding metal such as: a metal connection by a board wiring material/plating, a contact bonding of the metal in the paste; a partial coupled portion between metal oxides, between a metal oxide and a metal portion, or between metals; and/or an adhered portion of metal and/or metal oxide and an organic polymer composite.
  • When electromagnetic waves pass through the broken length, electromagnetic waves cannot be shielded. When a hole of 300 diameter is opening in a film or a metal cap having a sufficient shielding effect, the wavelength for the communication wave of 900 MHz for mobile phones is 33.3 cm and so the diameter 300 μm is about 1/100 of the wavelength, and thus there is no influence on the shielding effect even if a hole at such a level is opening.
  • Meanwhile, empirically, a hole in, e.g., a slit-like shape in a shield allows electromagnetic noise to pass through. A slit-like crack generated by deterioration depending on usage environment causes reduction of the shielding effect even when it is short.
  • As described above, there is a problem of generating connection deterioration between the shielding metal or metal-containing material and the ground electrode.
  • Here, while the plating used for the shielding material can be electrolytic plating or non-electrolytic plating, electrolytic plating requires electrodes and formation of a seed electrode is indispensable with respect to a non-conductive plated material.
  • Generally, seed electrode formation to plastic is performed by non-electrolytic plating. Thus, a process of the formation will be described. To perform non-electrolytic Ni (nickel) plating to a plastic material, first, degreasing/cleaning of a plated surface is performed and roughening is performed if needed, and a processing of Pd (palladium) seed electrode formation is performed as a pretreatment of the plating process. A metal complex absorbed on the plated surface is reduced to deposit metal Pd.
  • Next, non-electrolytic Ni plating is grown using that Pd as core. For example, in the process of performing non-electrolytic plating, plating is carried out by subjecting the to-be-plated member to the steps of degreasing, cleaning, soft etching, cleaning, acid cleaning, rinsing, non-electrolytic Ni plating, and rinsing. The formed non-electrolytic plating film itself may be used for the shielding film, and, if necessary, an electrolytic plating can be formed on the non-electrolytic plating film using the Ni plating film as a seed electrode.
  • Meanwhile, when the non-electrolytic plating is formed on a mold resin, the mechanical strength relating to adhesiveness between the non-electrolytic plating film and the mold resin depends on the anchor effect of the plating film and an unevenness of the plastic surface at the micro level. Therefore, the expansion of the plating film generated when a moisture absorption reflow reliability test on the electronic component as described above is performed causes exfoliation at the interface of the mold resin and the plating film having weak adhesiveness.
  • To solve the problem of deterioration of the shield metal film (plating expansion/exfoliation and/or deterioration of the connection portion) of the electronic component as described above, for example, Pd metal particles are formed to the mold resin surface with a fixed diffusion depth from the surface, which is a pretreatment of the shield plating film. The formation of Pd metal particles is performed in a pressured state in the presence of high-pressure CO2.
  • For example, Japanese Patent Application Laid-Open Publication No. 2006-131769 (Patent Document 4) discloses a method of forming a plastic structure and the structure in which a Pd metal complex is dissolved in a supercritical fluid to contact with a plastic surface, a metal element as a plating seed electrode exists in the plastic at a 5 nm or smaller depth from the surface and at 5 atomic % or higher.
  • By forming the layer, the anchor effect of the non-electrolytic Ni plating to the resin thereafter can be further stronger. The non-electrolytic Ni plating may be done by a normal method or a non-electrolytic Ni plating method having Ni dissolved in high-pressure CO2 in the same manner with the Pd treatment. The latter method forms a film which forms more diffusion layer because the plating solution itself permeates inside the mold resin.
  • When actually performing the Pd pretreatment and the non-electrolytic Ni plating treatment both using the high-pressure CO2 in a supercritical state, the electronic component having components and an IC(s) mounted on a printed board and formed with mold resin is put under high pressure. At this time, infiltration of the high-pressure CO2 into an adhesive layer of the printed board and/or the glass cloth layer at a side edge portion of the cut board, and dissolution of the resin around the glass cloth to decompose the board into pieces etc. have been concerned.
  • If the solution permeates into the depth of the board through these paths, that is, if Pd metal is deposited and non-electrolytic Ni plating is deposited, short-circuiting occurs inside the board. Similarly, if the solution permeates at the interface of the mold resin and the board, short-circuiting occurs between the electrodes on the board surface. It is feared to decompose the structure of the module due to infiltration of the CO2 solution into the bonding portion of the board and the mold resin and/or the cut portions of the sides of the board.
  • Also, migration upon using the product due to metal ions infiltrated into the board is concerned.
  • Since a chamber to use the high-pressure CO2 solution is for a batch processing system, the electronic component is necessary to be wholly dipped in the solution. Therefore, the back surface of the component is unwillingly plated, resulting in a problem of short-circuiting between signal terminal electrodes and/or ground terminal electrodes.
  • An adhesive sheet generally in a sheet-like shape used as a protective film of the back surface of the plated body is dissolved in the CO2 in a supercritical state to be unable to protect the back surface, and thus there has been a problem of insufficient covering effect.
  • As described above, as to structure, reliability, and a manufacturing method of a shielding metal film and/or a shielding metal-containing film having reliability in reflow resistance of an electronic component, there have been problems of weakness in adhesiveness of a generally used non-electrolytic plating film to a mold resin, infiltration of a solution from side surfaces and/or cut plane of the plating, and impossibility of protection of a back surface of the plating by simply adhering a sheet.
  • Accordingly, a preferred aim of the present invention is to provide an electronic component having a shield with a high reliability in reflow resistance on one side thereof by forming a plating film having no infiltration of CO2 from side surfaces of a board, a high migration reliability, and significantly improved adhesiveness by forming a plating base under high-pressure CO2.
  • The above and other preferred aims and novel characteristics of the present invention will be apparent from the description of the present specification and the accompanying drawings.
  • The typical ones of the inventions disclosed in the present application will be briefly described as follows.
  • That is, a typical one of the inventions is such that a metal plating film is formed on a pretreatment layer using high-pressure CO2 formed only on a top surface of a sealant with protecting a back surface of a wiring board, the metal plating film being electrically connected with a ground-connection through-hole connected to an edge portion of a ground wiring layer on a side surface of the wiring board or an edge portion of the ground wiring layer.
  • The effects obtained by typical aspects of the present invention will be briefly described below.
  • That is, an advantage obtained by the typical one of the inventions is to manufacture an electronic component having a shield with a high reliability in reflow resistance on one side thereof by forming a plating film having no infiltration of CO2 from side surfaces of a board, a high migration reliability, and significantly improved adhesiveness by forming a plating base under high-pressure CO2.
  • BRIEF DESCRIPTIONS OF THE DRAWINGS
  • FIG. 1 is a cross-sectional view illustrating a structure of a shielded electronic component according to a first embodiment of the present invention;
  • FIG. 2 is an explanatory diagram for describing a method of manufacturing the shielded electronic component according to the first embodiment of the present invention;
  • FIG. 3 is an explanatory diagram for describing the method of manufacturing the shielded electronic component according to the first embodiment of the present invention;
  • FIG. 4 is an explanatory diagram for describing the method of manufacturing the shielded electronic component according to the first embodiment of the present invention;
  • FIG. 5 is an explanatory diagram for describing the method of manufacturing the shielded electronic component according to the first embodiment of the present invention;
  • FIG. 6 is an explanatory diagram for describing the method of manufacturing the shielded electronic component according to the first embodiment of the present invention;
  • FIG. 7 is an explanatory diagram for describing the method of manufacturing the shielded electronic component according to the first embodiment of the present invention;
  • FIG. 8 is an explanatory diagram for describing the method of manufacturing the shielded electronic component according to the first embodiment of the present invention;
  • FIG. 9 is an explanatory diagram for describing the method of manufacturing the shielded electronic component according to the first embodiment of the present invention;
  • FIG. 10 is a cross-sectional view illustrating a structure of a shielded electronic component according to a second embodiment of the present invention;
  • FIG. 11 is a cross-sectional view illustrating a structure of a shielded electronic component according to a third embodiment of the present invention;
  • FIG. 12 is an explanatory diagram for describing a method of manufacturing a shielded electronic component according to a fourth embodiment of the present invention;
  • FIG. 13 is an explanatory diagram for describing the method of manufacturing the shielded electronic component according to the fourth embodiment of the present invention;
  • FIG. 14 is an explanatory diagram for describing the method of manufacturing the shielded electronic component according to the fourth embodiment of the present invention; and
  • FIG. 15 is an explanatory diagram for describing the method of manufacturing the shielded electronic component according to the fourth embodiment of the present invention.
  • DESCRIPTIONS OF THE PREFERRED EMBODIMENTS
  • Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.
  • Also, in the embodiments described below, when referring to the number of elements (including number of pieces, values, amount, range, and the like), the number of the elements is not limited to a specific number unless otherwise stated or except the case where the number is apparently limited to a specific number in principle. The number larger or smaller than the specified number is also applicable.
  • First Embodiment
  • With reference to FIG. 1, a structure of a shielded electronic component according to a first embodiment of the present invention will be described. FIG. 1 is a cross-sectional view illustrating the structure of the shielded electronic component according to the first embodiment of the present invention and illustrating a structure of a power amplifier module.
  • In FIG. 1, a power amplifier module which is the shielded electronic component includes, when the external structure is viewed, a rectangular wiring board 10, a sealant 23 formed with overlapping on a surface (main surface) of the wiring board 10, a plurality of wirings 11 provided to a back surface of the wiring board 10, and a GND (ground) external wiring 12.
  • In addition, the sealant 23 is shielded by a Pd pretreatment layer 117 of a Pd complex and a Ni plating film 118. To edge portions of the wiring board 10, GND connection through-holes 101 for a GND wiring layer (not illustrated) or a shield connected to the GND wiring layer are formed.
  • Also, a wiring 13 is formed on the surface of the wiring board 10 in the power amplifier module, and a chip component is formed to the wiring 13. The chip component 14 is configured by a passive component such as a resister or a capacitor, and an electrode 14 a of the chip component 14 is electrically connected with the wiring 13. Further, a wiring 16 is connected to the GND external wiring 12 formed to the back surface of the wiring board 10 through a via 18 formed inside the wiring board 10. Moreover, a semiconductor chip 21 is formed on the surface of the wiring board 10.
  • In the power amplifier module, in assembling thereof, electronic components including the semiconductor chip 21 are mounted on a multichip board on which a plurality of the wiring boards 10 are aligned, and thereafter, the sealant 23 is formed with a resin having a fixed height so as to cover the mounted electronic components.
  • And, the multichip board to which the sealant 23 is formed is cut in a matrix into pieces so that a plurality of power amplifier modules are formed at once.
  • In this manner, side surfaces of the wiring board and side surfaces of the sealant 23 coincide, and edge portions of the sealant 23 are not positioned outside the edge portions of the wiring board 10 in the structure.
  • The wiring board 10 is configured by, for example, a printed wiring board, and it has a structure of attaching a plurality of dielectric layers (insulating layers) together. Predetermined wirings are formed to the surface (main surface), back surface, and the inside of the wiring board, and a part of the wiring formed to the surface of the wiring board 10 and a part of the wiring formed to the back surface of the wiring board 10 are electrically connected through the via 18 extending in a thickness direction of the wiring board 10.
  • Incidentally, while the number of the dielectric layers is three in the present embodiment, it is needless to say that the number is not limited to this.
  • Next, with reference to FIGS. 2 to 9, a method of manufacturing the shielded electronic component according to the first embodiment of the present invention will be described. FIGS. 2 to 9 are explanatory diagrams for describing the method of manufacturing the shielded electronic component according to the first embodiment of the present invention.
  • First, as illustrated in FIG. 2, the sealant 23 by mold resin is cut in by a dicing blade 2 until reaching the GND wiring layer (not illustrated) of the wiring board 10 or the GND connection through-hole 101 electrically connected with the GND wiring layer.
  • A top view upon half-cut dicing singulated pieces on the shield in this manner is illustrated in FIG. 3.
  • In FIG. 3, a mold resin, half-cut dicing grooves 114 which are formed by the half-cut dicing until they reach the through-hole of the board, and peripheral adhesive portion 115 adhering the periphery of the wiring board 10 are formed on the wiring board 10.
  • It is sufficient as long as the half-cut dicing groove 114 reaches a ground layer among some ground layers of the wiring board 10, i.e., reaching a ground layer to make the best configuration in consideration of performance of the module.
  • FIG. 4 illustrates a cross-sectional view of the wiring boards 10 attached to each other by their back surfaces to protect the back surfaces and fixed by an epoxy-based adhesive (or curable adhesive) as the peripheral adhesive portion 115 being cured around the complete periphery.
  • Also, as illustrated in FIG. 5, instead of half dicing, it can be a chocolate-bar like sealing as the sealant 23 such as mold resin is formed into a block per individual PKG (package).
  • Then, edge portions of the two boards formed by half dicing or two boards formed by individual molding are adhered by an adhesive and cured followed by a base treatment as being introduced into a chamber 116 in which a Pd complex (plating base) exists as being dissolved in high-pressure CO2 as illustrated in FIG. 6.
  • A Pd complex subjected to a reduction treatment permeates a surface of the sealant 23 to several nanometers or more in a depth direction of the sealant 23. Alternately, the surface of the sealant 23 has holes caused by vacancy of SiO2 particles included in the sealant 23 and/or space of an interface of the resin and SiO2 particle, and thus the Pd complex permeates deeply into a depth direction of the hole and space.
  • Therefore, Pd particles to be the seed electrode of plating permeate deeper than those in a normal Pd treatment. The Pd pretreatment layer having a depth to some extent becomes a base for giving the anchor effect to the Ni plating film 118.
  • In addition, a plating treatment thereafter can be performed by the normal non-electrolytic Ni plating in the atmosphere (the air) or high-pressure CO2 dissolving non-electrolytic Ni plating. In the actual usage, forming the non-electrolytic plating 118 by a plating solution dissolved in high pressure CO2 makes the Pd complex permeate the sealant 23 deeper, and thus forming the non-electrolytic Ni plating film 118 by non-electrolytic Ni plating solution dissolved in high-pressure CO2 can form a package more excellent in humidity-resistance reflow reliability as the shield plating.
  • After the plating treatment illustrated in FIG. 7, the adhered portion of the periphery are cut off as illustrated in FIG. 8, and the each sheet is cut into singulated pieces by full-cut dicing as illustrated in FIG. 9.
  • The electronic component manufactured in the manner as described above to be a package with a electromagnetic noise shield which is not affected by noise from other semiconductors and does not let own noise out to the outside, the electric component having a plating film having a dramatically improved adhesiveness formed by forming the plating base under high-pressure CO2, and having a shield with a high reflow resistance reliability on one surface can be provided.
  • Second Embodiment
  • A shielded electronic component according to a second embodiment has the semiconductor chip 21 of the first embodiment mounted by face-up mounting.
  • With reference to FIG. 10, a structure of a shielded electronic component according to the second embodiment of the present invention will be described. FIG. 10 is a cross-sectional view illustrating a structure of the shielded electronic component according to the second embodiment of the present invention, and illustrates a structure of a power amplifier module.
  • In FIG. 10, a wiring 13 is formed to a surface of a wiring board 10 in the power amplifier module, and a chip component 14 is formed to be connected to the wiring 13. The chip component 14 is configured by a passive component such as a resistor or capacitor, and an electrode 14 a of the chip component 14 and the wiring 13 formed to the wiring board 10 are electrically connected by a solder 15.
  • Also, a wiring 16 is connected to a GND external wiring 12 formed to a back surface of the wiring board 10 through a via 18 formed inside the wiring board 10. Further, the semiconductor chip 21 is mounted on the surface of the wiring board 10.
  • As illustrated in FIG. 10, the semiconductor chip 21 is mounted having a device-forming surface thereof facing upwards (face-up) on the wiring board 10. Further, the power amplifier module in the present embodiment is formed with a sealant 23 formed of a resin or the like to cover the chip component 14 and the semiconductor chip 21 mounted on the wiring board 10.
  • The components mounted on the module illustrated in FIG. 10 include an IC mounted face up and are connected to the wiring 13 of the wiring board 10 by a wire bonding 191.
  • Other than that, the manufacturing method and shielding method are the same with those of the first embodiment.
  • Also in the present embodiment, in the same manner with the first embodiment, the electronic component manufactured in the manner as described above to be a package with a electromagnetic noise shield which is not affected by noise from other semiconductors and does not let own noise out to the outside, the electric component having a plating film having a dramatically improved adhesiveness formed by forming the plating base under high-pressure CO2, and having a shield with a high reflow resistance reliability on one surface can be provided.
  • Third Embodiment
  • A shielded electronic component according to a third embodiment has the semiconductor chip 21 formed with a plurality of stacked semiconductors and mounted by face-up mounting.
  • With reference to FIG. 11, a structure of the shielded electronic component according to the third embodiment of the present invention will be described. FIG. 11 is a cross-sectional view illustrating the structure of the shielded electronic component according to the third embodiment of the present invention, and illustrating a generally used package. The package is a package of only for a memory, and/or a semiconductor package composed of an ASIC and a memory etc., for example.
  • In FIG. 11, the semiconductor chip 21 composed of a plurality of stacked semiconductors attached by a die-attach film 233 having its device forming surface facing upwards (face-up) is stacked on a wiring board 10.
  • The semiconductor chip 21 and the wiring board 10 are electrically connected to a wiring 13 on a surface of the wiring board 10 by a wire bonding 191. The top of the wiring board 10 is sealed by a sealant 23 of a mold resin or the like, and a Pd pretreatment layer 117 of a Pd complex permeated in an ultrahigh-pressure CO2 solvent and a Ni plating film 118 are formed on the sealant 23, and the plating is connected to GND connection through-holes 101 formed at side surfaces of the wiring board 10. This structure is a BGA (ball grid array) type package in which a solder 20 is mounted to terminal electrodes 19 on the back surface.
  • Other than that, the manufacturing method and shielding method are the same with those of the first embodiment.
  • Also in the present embodiment, in the same manner with the first embodiment, the electronic component manufactured in the manner as described above to be a package with a electromagnetic noise shield which is not affected by noise from other semiconductors and does not let own noise out to the outside, the electric component having a plating film having a dramatically improved adhesiveness formed by forming the plating base under high-pressure CO2, and having a shield with a high reflow resistance reliability on one surface can be provided.
  • Fourth Embodiment
  • A shielded electronic component according to a fourth embodiment has a protective film for protecting the back surface of the wiring board 10 as being applied to the back of the wiring board 10 instead of attaching back surfaces of the wiring boards 10 for protecting the back like the first embodiment.
  • With reference to FIGS. 12 to 15, a method of manufacturing the shielded electronic component according to the fourth embodiment of the present invention will be described. FIGS. 12 to 15 are explanatory diagrams for describing the method of manufacturing the shielded electronic component according to the fourth embodiment of the present invention.
  • First, in the same manner with the first and second embodiments, the sealant 23 of a mold resin or the like is cut in until reaching the GND wiring of the wiring board 10 or an electrode connected with the GND wiring by dicing. A top view of the electronic component after the half-cut dicing into singulated pieces on the shield in this method is the same with that in FIG. 5 of the first embodiment.
  • A cross-sectional view of the electronic component having a protective film 111 of an UV film or the like being applied to protect the back surface of the wiring board 10 formed in the manner as described above and having the whole periphery fixed by curing an epoxy-based adhesive (or curing adhesive) as the periphery adhesive portion 115 is illustrated in FIG. 12.
  • Note that there is no problem when the steps illustrated in FIG. 2 and FIG. 3 are carried out first or the application step of the protective film 111 illustrated in FIG. 12 is carried out first.
  • And, as illustrated in FIG. 13, after adhering and curing the epoxy-based adhesive or the like, the component is introduced into a chamber 116 in which a Pd complex (plating base) dissolved in high-pressure CO2 exists, and the base treatment is performed.
  • Pd complex subjected to a reduction treatment permeates the surface of the sealant 23 by several nanometers or more in the depth direction. Alternately, the surface of the sealant 23 has holes caused by vacancy of SiO2 particles contained in the sealant 23 and space of the interface of the resin and the SiO2 particle, and thus the Pd complex permeates deeply into the holes and space in the depth direction of the hole and space.
  • Therefore, the Pd particles to be the seed electrode of plating permeate deeper than a normal Pd treatment. The Pd pretreatment layer 117 having a depth to some extent becomes the base for giving the anchor effect to the Ni plating film 118.
  • And, a plating treatment thereafter can be performed by normal non-electrolytic Ni plating in the atmosphere (the air), and also can be performed by high-pressure CO2 dissolving non-electrolytic Ni plating. In actual usage, forming the non-electrolytic Ni plating film 118 by a plating solution dissolved in high-pressure CO2 can form a package more excellent in humidity resistance reflow reliability as shield plating because the plating solution permeates deeper to the sealant 23.
  • After the plating treatment illustrated in FIG. 14, the adhered portion of the periphery is cut off as illustrated in FIG. 15 and the protective film 111 is exfoliated by UV radiation.
  • After that, in the same manner with FIG. 9 of the first embodiment, the each sheet is cut into singulated pieces by full-cut dicing.
  • Also in the present embodiment, as the same manner with the first embodiment, the electronic component manufactured in the manner as described above to be a package with a electromagnetic noise shield which is not affected by noise from other semiconductors and does not let own noise out to the outside, the electric component having a plating film having a dramatically improved adhesiveness formed by forming the plating base under high-pressure CO2, and having a shield with a high reflow resistance reliability on one surface can be provided.
  • In the foregoing, the invention made by the inventors of the present invention has been concretely described based on the embodiments. However, it is needless to say that the present invention is not limited to the foregoing embodiments and various modifications and alterations can be made within the scope of the present invention.
  • The present invention relates to a shielded electronic component and a method of manufacturing the same, and as to mounting of an electronic component including semiconductor, the present invention can be widely applied to a semiconductor-mounting electronic component which requires a shield structure to avoid adverse effects of radio waves from the surrounding and the electromagnetic noise from the semiconductor, a semiconductor-mounting electronic component which requires a shielding of noise generated from itself, and so forth.

Claims (6)

1. A shielded electronic component comprising:
a wiring board;
a semiconductor integrated circuit device mounted on a main surface of the wiring board;
a sealant which seals the whole of an upper surface of the wiring board; and
a metal plating film formed on an upper surface of the sealant, wherein
the metal plating film is formed on a pretreatment layer formed only on the upper surface of the sealant with using high-pressure CO2 in a state of protecting a back surface of the wiring board, and electrically connected with an end portion of a ground wiring layer on a side surface of the wiring board or a ground connection through-hole connected to the end portion of the ground wiring layer.
2. The shielded electronic component according to claim 1, wherein
the metal plating film is formed with mixing high-pressure CO2 and a plating solution.
3. The shielded electronic component according to claim 1, wherein
the pretreatment layer contains palladium.
4. The shielded electronic component according to claim 1, wherein
the metal plating film is formed of a copper plating film or a nickel plating film.
5. A method of manufacturing a shielded electronic component comprising the steps of:
mounting a semiconductor integrated circuit device configuring the shielded electronic component on a board for forming a plurality of the shielded electronic components;
forming a sealant on the whole of an upper surface of the board;
performing half-cut dicing on the board at a cutting portion of the individual shielded electronic component until reaching a ground wiring layer of the board or a ground connection through-hole connected with the ground wiring layer;
attaching back surfaces of two of the half-cut diced boards to each other and fixing end portions of the two boards by an adhesive;
forming a pretreatment layer on an upper surface of the sealant with using high-pressure CO2;
forming a metal plating film on the pretreatment layer to be electrically connected with the ground wiring layer of the board or the ground connection through-hole connected with the ground wiring layer;
cutting off the adhering portion by the adhesive; and
performing full-cut dicing on the half-cut diced portion to cut out the individual shielded electronic component.
6. A method of manufacturing a shielded electronic component comprising the steps of:
mounting a semiconductor integrated circuit device configuring the shielded electronic component on a board for forming a plurality of the shielded electronic components;
forming a sealant on the whole of an upper surface of the board;
performing half-cut dicing on the board at a cutting portion of the individual shielded electronic component until reaching a ground wiring layer of the board or a ground connection through-hole connected with the ground wiring layer;
applying a protective film on a back surface of the half-cut diced board;
fixing end portions of the board and the protective film by an adhesive;
forming a pretreatment layer on an upper surface of the sealant with using high-pressure CO2;
forming a metal plating film on the pretreatment layer to be electrically connected with the ground wiring layer of the board or the ground connection through-hole connected with the ground wiring layer;
cutting off the adhering portion by the adhesive and exfoliating the protective film; and
performing full-cut dicing on the half-cut diced portion to cut out the individual shielded electronic component.
US12/612,699 2008-11-07 2009-11-05 Shielded electronic components and method of manufacturing the same Abandoned US20100172116A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008-286254 2008-11-07
JP2008286254A JP5324191B2 (en) 2008-11-07 2008-11-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/561,302 US9001528B2 (en) 2008-11-07 2012-07-30 Shielded electronic components and method of manufacturing the same

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/561,302 Continuation US9001528B2 (en) 2008-11-07 2012-07-30 Shielded electronic components and method of manufacturing the same

Publications (1)

Publication Number Publication Date
US20100172116A1 true US20100172116A1 (en) 2010-07-08

Family

ID=42302625

Family Applications (2)

Application Number Title Priority Date Filing Date
US12/612,699 Abandoned US20100172116A1 (en) 2008-11-07 2009-11-05 Shielded electronic components and method of manufacturing the same
US13/561,302 Active 2030-01-07 US9001528B2 (en) 2008-11-07 2012-07-30 Shielded electronic components and method of manufacturing the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
US13/561,302 Active 2030-01-07 US9001528B2 (en) 2008-11-07 2012-07-30 Shielded electronic components and method of manufacturing the same

Country Status (3)

Country Link
US (2) US20100172116A1 (en)
JP (1) JP5324191B2 (en)
CN (1) CN101740550B (en)

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102010033551A1 (en) * 2010-08-05 2012-02-09 Epcos Ag Method for producing a plurality of electromagnetic shielded electronic components and electromagnetic shielded electronic component
US20130003333A1 (en) * 2010-03-08 2013-01-03 Hiroshi Toyao Electronic device, wiring board, and method of shielding noise
US8772088B2 (en) 2011-02-09 2014-07-08 Murata Manufacturing Co., Ltd. Method of manufacturing high frequency module and high frequency module
US20140308907A1 (en) * 2013-04-16 2014-10-16 Skyworks Solutions, Inc. Apparatus and methods related to ground paths implemented with surface mount devices
US9166298B2 (en) 2012-08-24 2015-10-20 Kabushiki Kaisha Toshiba Wireless device, and information processing apparatus and storage device including the wireless device
US20150303075A1 (en) * 2014-04-18 2015-10-22 Samsung Electronics Co., Ltd. Method of fabricating a semiconductor package
US20150340248A1 (en) * 2010-11-26 2015-11-26 Siliconware Precision Industries Co., Ltd. Fabrication method of package having esd and emi preventing functions
CN105307848A (en) * 2013-07-05 2016-02-03 宝马股份公司 Method for producing a housing having shielding against electric and/or magnetic radiation, and housing having shielding against electric and/or magnetic radiation
US9362196B2 (en) 2010-07-15 2016-06-07 Kabushiki Kaisha Toshiba Semiconductor package and mobile device using the same
US9386734B2 (en) 2010-08-05 2016-07-05 Epcos Ag Method for producing a plurality of electronic devices
US9627327B2 (en) 2014-10-06 2017-04-18 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same
US20170133326A1 (en) * 2015-06-01 2017-05-11 Qorvo Us, Inc. Wafer level fan-out with electromagnetic shielding
US20170235861A1 (en) * 2016-02-12 2017-08-17 Fujitsu Limited Method of calculating thermal path and information processing device
US20170271270A1 (en) * 2016-03-18 2017-09-21 Intel Corporation Systems and methods for eloectromagnetic interference shielding
US20180108618A1 (en) * 2015-06-19 2018-04-19 Murata Manufacturing Co., Ltd Module and method for manufacturing same
US20180286817A1 (en) * 2017-03-30 2018-10-04 Taiyo Yuden Co., Ltd. Method of manufacturing electronic component module
US10192827B2 (en) * 2016-12-14 2019-01-29 Murata Manufacturing Co., Ltd. Transmit-and-receive module
US10249572B2 (en) 2014-12-22 2019-04-02 Atotech Deutschland Gmbh Method for electromagnetic shielding and thermal management of active components
US10375867B2 (en) 2016-04-27 2019-08-06 Omron Corporation Electronic device and method for producing same

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101855294B1 (en) * 2010-06-10 2018-05-08 삼성전자주식회사 Semiconductor package
TWI491009B (en) * 2010-10-08 2015-07-01 Chip level emi shielding structure and manufacture method thereof
US9484313B2 (en) 2013-02-27 2016-11-01 Advanced Semiconductor Engineering, Inc. Semiconductor packages with thermal-enhanced conformal shielding and related methods
US9881875B2 (en) 2013-07-31 2018-01-30 Universal Scientific Industrial (Shanghai) Co., Ltd. Electronic module and method of making the same
US9814166B2 (en) 2013-07-31 2017-11-07 Universal Scientific Industrial (Shanghai) Co., Ltd. Method of manufacturing electronic package module
JP6637896B2 (en) * 2014-03-04 2020-01-29 エムシー10 インコーポレイテッドMc10,Inc. Conformal IC device with flexible multi-part encapsulated housing for electronic devices
US9601464B2 (en) 2014-07-10 2017-03-21 Apple Inc. Thermally enhanced package-on-package structure
JP6443458B2 (en) * 2015-01-30 2018-12-26 株式会社村田製作所 Electronic circuit module
DE102015209191A1 (en) * 2015-02-10 2016-08-11 Conti Temic Microelectronic Gmbh Mechatronic component and method for its production
US10109593B2 (en) 2015-07-23 2018-10-23 Apple Inc. Self shielded system in package (SiP) modules
US10163871B2 (en) * 2015-10-02 2018-12-25 Qualcomm Incorporated Integrated device comprising embedded package on package (PoP) device
US9721903B2 (en) 2015-12-21 2017-08-01 Apple Inc. Vertical interconnects for self shielded system in package (SiP) modules
US9836095B1 (en) * 2016-09-30 2017-12-05 Intel Corporation Microelectronic device package electromagnetic shield
US10068854B2 (en) * 2016-10-24 2018-09-04 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070175763A1 (en) * 2004-02-12 2007-08-02 Takabumi Nagai Electroplating in presence of co2

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3455685B2 (en) * 1998-11-05 2003-10-14 新光電気工業株式会社 Method for manufacturing semiconductor device
JP3999784B2 (en) * 2003-01-16 2007-10-31 富士通株式会社 Manufacturing method of electronic component mounting board
JP4020874B2 (en) 2003-03-13 2007-12-12 三洋電機株式会社 Semiconductor device and manufacturing method thereof
JP2005109306A (en) * 2003-10-01 2005-04-21 Matsushita Electric Ind Co Ltd Electronic component package and its manufacturing method
JP4655465B2 (en) * 2003-10-06 2011-03-23 カシオ計算機株式会社 Surface light source and liquid crystal display device
JP4301071B2 (en) 2004-05-07 2009-07-22 株式会社村田製作所 Electronic component with shield case and method of manufacturing the same
JP2006131769A (en) 2004-11-05 2006-05-25 Hitachi Maxell Ltd Plastic structure and method for producing plastic structure
JP2006165109A (en) * 2004-12-03 2006-06-22 Shinko Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP3926835B1 (en) * 2006-09-28 2007-06-06 日立マクセル株式会社 Formation method of plating film

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070175763A1 (en) * 2004-02-12 2007-08-02 Takabumi Nagai Electroplating in presence of co2

Cited By (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130003333A1 (en) * 2010-03-08 2013-01-03 Hiroshi Toyao Electronic device, wiring board, and method of shielding noise
US8873246B2 (en) * 2010-03-08 2014-10-28 Nec Corporation Electronic device, wiring board, and method of shielding noise
US9721905B2 (en) 2010-07-15 2017-08-01 Kabushiki Kaisha Toshiba Semiconductor package and mobile device using the same
US9362196B2 (en) 2010-07-15 2016-06-07 Kabushiki Kaisha Toshiba Semiconductor package and mobile device using the same
US9386734B2 (en) 2010-08-05 2016-07-05 Epcos Ag Method for producing a plurality of electronic devices
DE102010033551A1 (en) * 2010-08-05 2012-02-09 Epcos Ag Method for producing a plurality of electromagnetic shielded electronic components and electromagnetic shielded electronic component
US20150340248A1 (en) * 2010-11-26 2015-11-26 Siliconware Precision Industries Co., Ltd. Fabrication method of package having esd and emi preventing functions
US10062582B2 (en) * 2010-11-26 2018-08-28 Siliconware Precision Industries Co., Ltd. Fabrication method of package having ESD and EMI preventing functions
US8772088B2 (en) 2011-02-09 2014-07-08 Murata Manufacturing Co., Ltd. Method of manufacturing high frequency module and high frequency module
US9166298B2 (en) 2012-08-24 2015-10-20 Kabushiki Kaisha Toshiba Wireless device, and information processing apparatus and storage device including the wireless device
US9788466B2 (en) * 2013-04-16 2017-10-10 Skyworks Solutions, Inc. Apparatus and methods related to ground paths implemented with surface mount devices
US20140308907A1 (en) * 2013-04-16 2014-10-16 Skyworks Solutions, Inc. Apparatus and methods related to ground paths implemented with surface mount devices
US10524350B2 (en) 2013-04-16 2019-12-31 Skyworks Solutions, Inc. Apparatus and methods related to conformal coating implemented with surface mount devices
US10561012B2 (en) 2013-04-16 2020-02-11 Skyworks Solutions, Inc. Methods related to implementing surface mount devices with ground paths
CN105307848A (en) * 2013-07-05 2016-02-03 宝马股份公司 Method for producing a housing having shielding against electric and/or magnetic radiation, and housing having shielding against electric and/or magnetic radiation
US20160044840A1 (en) * 2013-07-05 2016-02-11 Bayerische Motoren Werke Aktiengesellschaft Method for Producing a Housing Having Shielding Against Electric and/or Magnetic Radiation, and Housing Having the Shielding
US10492347B2 (en) * 2013-07-05 2019-11-26 Bayerische Motoren Werke Aktiengesellschaft Method for producing a housing having shielding against electric and/or magnetic radiation, and housing having the shielding
US9524884B2 (en) * 2014-04-18 2016-12-20 Samsung Electronics Co., Ltd. Method of fabricating a semiconductor package
US20150303075A1 (en) * 2014-04-18 2015-10-22 Samsung Electronics Co., Ltd. Method of fabricating a semiconductor package
US9627327B2 (en) 2014-10-06 2017-04-18 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing the same
US10249572B2 (en) 2014-12-22 2019-04-02 Atotech Deutschland Gmbh Method for electromagnetic shielding and thermal management of active components
US10103106B2 (en) * 2015-06-01 2018-10-16 Qorvo Us, Inc. Wafer level fan-out with electromagnetic shielding
US20170133326A1 (en) * 2015-06-01 2017-05-11 Qorvo Us, Inc. Wafer level fan-out with electromagnetic shielding
US10256195B2 (en) * 2015-06-19 2019-04-09 Murata Manufacturing Co., Ltd. Module and method for manufacturing same
US20180108618A1 (en) * 2015-06-19 2018-04-19 Murata Manufacturing Co., Ltd Module and method for manufacturing same
US20170235861A1 (en) * 2016-02-12 2017-08-17 Fujitsu Limited Method of calculating thermal path and information processing device
US20170271270A1 (en) * 2016-03-18 2017-09-21 Intel Corporation Systems and methods for eloectromagnetic interference shielding
US9953929B2 (en) * 2016-03-18 2018-04-24 Intel Corporation Systems and methods for electromagnetic interference shielding
US10375867B2 (en) 2016-04-27 2019-08-06 Omron Corporation Electronic device and method for producing same
US10192827B2 (en) * 2016-12-14 2019-01-29 Murata Manufacturing Co., Ltd. Transmit-and-receive module
US20180286817A1 (en) * 2017-03-30 2018-10-04 Taiyo Yuden Co., Ltd. Method of manufacturing electronic component module
US10529668B2 (en) * 2017-03-30 2020-01-07 Taiyo Yuden Co., Ltd. Method of manufacturing electronic component module

Also Published As

Publication number Publication date
JP5324191B2 (en) 2013-10-23
US9001528B2 (en) 2015-04-07
JP2010114291A (en) 2010-05-20
US20120292772A1 (en) 2012-11-22
CN101740550A (en) 2010-06-16
CN101740550B (en) 2011-12-21

Similar Documents

Publication Publication Date Title
TWI421904B (en) Semiconductor memory device and manufacturing method thereof
US20180083341A1 (en) Semiconductor package including antenna substrate and manufacturing method thereof
US8362597B1 (en) Shielded package having shield lid
US8368185B2 (en) Semiconductor device packages with electromagnetic interference shielding
US9425152B2 (en) Method for fabricating EMI shielding package structure
TWI471985B (en) Chip package and manufacturing method thereof
US8826527B2 (en) Electronic component-embedded printed circuit board and method of manufacturing the same
US8362598B2 (en) Semiconductor device with electromagnetic interference shielding
KR101769995B1 (en) semiconductor device and method of forming shielding layer after encapsulation and grounded through interconnect structure
US7745910B1 (en) Semiconductor device having RF shielding and method therefor
TWI654731B (en) Including a semiconductor element and an electromagnetic shielding of the absorbent
US8012868B1 (en) Semiconductor device having EMI shielding and method therefor
US7868443B2 (en) Vertical stack type multi-chip package having improved grounding performance and lower semiconductor chip reliability
US7268426B2 (en) High-frequency chip packages
US20140252613A1 (en) Semiconductor device
US8178956B2 (en) Integrated circuit package system for shielding electromagnetic interference
KR101805114B1 (en) Integrated circuit packaging system with dual side connection and method of manufacture thereof
US20110260301A1 (en) Semiconductor device packages with electromagnetic interference shielding
US7495319B2 (en) Resin-encapsulated semiconductor device and lead frame, and method for manufacturing the same
EP1764834B1 (en) Electromagnetic shielding of packages with a laminate substrate
US7876572B2 (en) Wiring board and semiconductor apparatus
US5436203A (en) Shielded liquid encapsulated semiconductor device and method for making the same
KR100714917B1 (en) Chip stack structure interposing shield plate and system in package comprising the same
US7480153B2 (en) EMI shielding package and method for making the same
CN100485921C (en) Overmolded semiconductor package with an integrated EMI and RFI shield

Legal Events

Date Code Title Description
AS Assignment

Owner name: RENESAS TECHNOLOGY CORP., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YORITA, CHIKO;YAMAGUCHI, YOSHIHIDE;SHIRAI, YUJI;AND OTHERS;SIGNING DATES FROM 20091208 TO 20091213;REEL/FRAME:024062/0377

AS Assignment

Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN

Free format text: CHANGE OF NAME;ASSIGNOR:NEC ELECTRONICS CORPORATION;REEL/FRAME:024953/0404

Effective date: 20100401

Owner name: NEC ELECTRRONICS CORPORATION, JAPAN

Free format text: MERGER;ASSIGNOR:RENESAS TECHNOLOGY CORP.;REEL/FRAME:024933/0869

Effective date: 20100401

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION