US20100155966A1 - Grid array packages - Google Patents

Grid array packages Download PDF

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Publication number
US20100155966A1
US20100155966A1 US12714130 US71413010A US2010155966A1 US 20100155966 A1 US20100155966 A1 US 20100155966A1 US 12714130 US12714130 US 12714130 US 71413010 A US71413010 A US 71413010A US 2010155966 A1 US2010155966 A1 US 2010155966A1
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Prior art keywords
substrate
surface
die
pads
semiconductor device
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US12714130
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US8049317B2 (en )
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Walter L. Moden
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Round Rock Research LLC
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Micron Technology Inc
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Abstract

A semiconductor device assembly includes a substrate and a semiconductor die adjacent to a first surface of the substrate. The substrate also includes a second surface opposite from the first surface, an opening extending from the first surface and the second surface, contact pads on the second surface, and substrate pads on the second surface, adjacent to the opening. Bond pads of the semiconductor die are aligned with the opening through the substrate. Intermediate conductive elements, such as bond wires, extend from bond pads of the semiconductor die, through the opening, to substrate pads on the opposite, second surface of the substrate. An encapsulant, which fills the opening and covers the intermediate conductive elements, protrudes beyond a plane in which the second surface of the substrate is located. Discrete conductive elements, such as solder balls, may protrude from the contact pads of the substrate.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation of U.S. patent application Ser. No. 11/866,065, filed Oct. 2, 2007, pending, which is a continuation of U.S. patent application Ser. No. 11/437,550, filed May 19, 2006, now U.S. Pat. No. 7,381,591, issued Jun. 3, 2008, which is a continuation of U.S. patent application Ser. No. 11/070,364, filed Mar. 1, 2005, now U.S. Pat. No. 7,329,945, issued Feb. 12, 2008, which is a continuation of U.S. patent application Ser. No. 09/699,537, filed Oct. 30, 2000, now U.S. Pat. No. 6,861,290, issued Mar. 1, 2005, which is a divisional of U.S. patent application Ser. No. 09/483,483, filed Jan. 14, 2000, now U.S. Pat. No. 6,265,766, issued Jul. 24, 2001, which is a continuation of U.S. patent application Ser. No. 08/948,936, filed Oct. 10, 1997, now U.S. Pat. No. 6,201,304, issued Mar. 13, 2001, which is a continuation of U.S. patent application Ser. No. 08/574,662, filed Dec. 19, 1995, now U.S. Pat. No. 5,719,440, issued Feb. 17, 1998. The disclosure of each of the previously referenced U.S. patent applications and patents is hereby incorporated herein by this reference in its entirety.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to an apparatus for connecting a bare semiconductor die having a size and bond pad arrangement, either solder ball arrangement, or pin arrangement (hereinafter referred to generally as a “terminal arrangement”), which does not conform to a printed circuit board with a specific or standardized pin out, connector pad, or lead placement (hereinafter referred to generally as a “connection arrangement”). More particularly, the present invention relates to an intermediate conductor-carrying substrate (hereinafter referred to generally as an “adaptor board”) for connecting a non-conforming bare die to another printed circuit board having a given connection arrangement (hereinafter referred to generally as a “master board”).
  • 2. State of the Art
  • Definitions: The following terms and acronyms will be used throughout the application and are defined as follows:
  • BGA—Ball Grid Array: An array of minute solder balls disposed on an attachment surface of a semiconductor die wherein the solder balls are refluxed for simultaneous attachment and electrical communication of the semiconductor die to a printed circuit board.
  • COB—Chip On Board: The techniques used to attach-semiconductor dice to a printed circuit board, including flip-chip attachment, wire bonding, and tape automated bonding (“TAB”).
  • Flip-Chip: A chip or die that has bumped terminations spaced around the active surface of the die and is intended for facedown mounting.
  • Flip-Chip Attachment: A method of attaching a semiconductor die to a substrate in which the die is flipped so that the connecting conductor pads on the face of the die are set on mirror-image pads on the substrate (i.e., printed circuit board) and bonded by refluxing the solder.
  • Glob Top: A glob of encapsulant material (usually epoxy or silicone or a combination thereof) surrounding a semiconductor die in the COB assembly process.
  • PGA—Pin Grid Array: An array of small pins extending substantially perpendicularly from the major plane of a semiconductor die, wherein the pins conform to a specific arrangement on a printed circuit board for attachment thereto.
  • SLICC—Slightly Larger than Integrated Circuit Carrier: An array of minute solder balls disposed on an attachment surface of a semiconductor die similar to a BGA, but having a smaller solder ball pitch and diameter than a BGA.
  • State-of-the-art COB technology generally consists of three semiconductor die to printed circuit board attachment techniques: flip-chip attachment, wire bonding, and TAB.
  • Flip-chip attachment consists of attaching a semiconductor die, generally having a BGA, a SLICC or a PGA, to a printed circuit board. With the BGA or SLICC, the solder ball arrangement on the semiconductor die must be a mirror-image of the connecting bond pads on the printed circuit board such that precise connection is made. The semiconductor die is bonded to the printed circuit board by refluxing the solder balls. With the PGA, the pin arrangement of the semiconductor die must be a mirror-image of the pin recesses on the printed circuit board. After insertion, the semiconductor die is generally bonded by soldering the pins into place. An under-fill encapsulant is generally disposed between the semiconductor die and the printed circuit board to prevent contamination. A variation of the pin-in-recess PGA is a J-lead PGA, wherein the loops of the Js are soldered to pads on the surface of the circuit board. Nonetheless, the lead and pad locations must coincide, as with the other referenced flip-chip techniques.
  • Wire bonding and TAB attachment generally begins with attaching a semiconductor die to the surface of a printed circuit board with an appropriate adhesive. In wire bonding, a plurality of bond wires are attached, one at a time, from each bond pad on the semiconductor die and to a corresponding lead on the printed circuit board. The bond wires are generally attached through one of three industry-standard wire bonding techniques: ultrasonic bonding, using a combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld; thermocompression bonding, using a combination of pressure and elevated temperature to form a weld; and thermosonic bonding, using a combination of pressure, elevated temperature, and ultrasonic vibration bursts. The die may be oriented either face up or face down (with its active surface and bond pads either up or down with respect to the circuit board) for wire bonding, although face up orientation is more common. With TAB, metal tape leads are attached between the bond pads on the semiconductor die and the leads on the printed circuit board. An encapsulant is generally used to cover the bond wires and metal tape leads to prevent contamination.
  • Although the foregoing methods are effective for bonding semiconductor dice to printed circuit boards, the terminal arrangements of the dice and the connection arrangements of the boards must be designed to accommodate one another. Thus, it may be impossible to electrically connect a particular semiconductor die to a printed circuit board for which the semiconductor die terminal arrangement was not designed to match the board's connection arrangement. With either wire bond or TAB attachment, the semiconductor die bond pad may not correspond to the lead ends on the circuit board, and thus attachment is either impossible or extremely difficult due to the need for overlong wires and the potential for inter-wire contact and shorting. With flip-chip attachment, if the printed circuit board connection arrangement is not a mirror-image of the solder ball or pin arrangement (terminal arrangement) on the semiconductor die, electrically connecting the flip-chip to the printed circuit board is impossible.
  • Therefore, it would be advantageous to develop an apparatus for connecting a semiconductor die having a size and bond pad arrangement, solder ball arrangement, or pin arrangement (“I/O pattern”) which does not conform to a printed circuit board with a specific or standardized pin out, connection pad location, or lead placement (“I/O pattern”).
  • SUMMARY OF THE INVENTION
  • The present invention relates to an intermediate printed circuit board or other conductor-carrying substrate that functions as an adaptor board for electrically connecting one or more bare semiconductor dice of a variety of sizes and bond pad locations, solder ball arrangement, or pin arrangement, to a master printed circuit board with a specific or standardized pin out, connector pad location, or lead placement.
  • An adaptor printed circuit board or substrate (“adaptor board”) is sized and configured with an I/O pattern to accommodate its attachment to the master printed circuit board (“master board”). If the master board is configured to receive a specific pin out or specific connector pad locations, the adaptor board is configured on its master board attachment surface with pins or solder balls in mirror-image to the master board connection arrangement to make electrical contact with the specific pin out or connector pads on the printed circuit board. If the master board is configured to receive a bond wire, the adaptor board is configured and sized to provide wire bond pads on its upper surface closely adjacent the bond pads of the master board leads. The adaptor board can, of course, be configured to accommodate other attachment and electrical connection means known in the industry, as well as other components in addition to the semiconductor die or dice carried thereon.
  • On the semiconductor die side of the adaptor board, one or more semiconductor dice are attached. If a “flip-chip” die is attached to the adaptor board, the adaptor board will, of course, be configured with an I/O pattern to receive the flip-chip with a specific pin out or connector pad locations. The pin out or connector pads on the adaptor board are connected to circuit traces on or through the adaptor board. The circuit traces form the electrical communication path from the pin recesses or connector pads on the adaptor board to the connection points to the master board.
  • If a “leads over” die is used with the adaptor board, the bond pads on the die are wire bonded to the adaptor board. Preferably, the leads over die is attached to the adaptor board with the bond pads facing the adaptor board. The bond wires are attached to the leads over die bond pads and extend into a via or vias in the adaptor board. The bond wires are attached to an I/O pattern of adaptor board bond pads within the via from which circuit traces extend, or to leads on the master board side of the adaptor board.
  • It is, of course, understood that the leads over die can be attached to the adaptor board with the bond pads facing away from the adaptor board. Thus, the bond wires are simply attached to the bond pads on the leads over die and to a corresponding I/O pattern of adaptor board pad on the semiconductor die side of the adaptor board.
  • Preferably, the exposed circuitry of the die and the die-to-adaptor board interconnection is sealed from contamination by a glob top after wire bonding or an underflow compound in the case of a flip-chip attachment.
  • Furthermore, it is understood that with the use of wire bonds, the adaptor boards can be stacked on top of each other and connected to the adaptor board as by wire bonding.
  • BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
  • While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which:
  • FIG. 1 is a side view of one embodiment of the present invention;
  • FIG. 2 is a side view of a second embodiment of the present invention;
  • FIG. 2A is a top view of the second embodiment of the present invention shown in FIG. 2;
  • FIG. 3 is a side view of a third embodiment of the present invention;
  • FIG. 3A is an upside-down exploded perspective view of selected portions of the third embodiment; and
  • FIG. 4 is a side view of a fourth embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE INVENTION
  • FIG. 1 illustrates a first embodiment of the present invention designated as a flip-chip style/flip-chip attachment assembly 100. Assembly 100 comprises a semiconductor die 12 having an inverted active surface 14 with at least one flip-chip electric connection 16 (such as a C4 solder bump connection, a pin connection, or a surface mount J-lead connection, by way of example) extending substantially perpendicularly from a bond pad 15 on the semiconductor die active surface 14. The flip-chip electric connections 16 are attached to an upper surface 20 of an adaptor board 18 in such a manner that the flip-chip electric connections 16 make electrical contact with electrical contact elements 21 in or on the surface of adaptor board 18. The electrical contact elements 21 make electrical communication between each flip-chip electric connection 16, through circuit traces 23 (exemplary traces shown in broken lines) in the adaptor board 18, to at least one master board connector 22 extending substantially perpendicularly from a lower surface 24 of the adaptor board 18 to connect adaptor board 18 to an aligned terminal 31 on master board 30. Preferably, a sealing compound 26 is disposed between the semiconductor die 12 and the adaptor board 18 to prevent contamination of the flip-chip electric connections 16 and to more firmly secure semiconductor die 12 to adaptor board 18.
  • In actual practice, there will be a plurality of terminals 31 arranged in a specific, perhaps industry-standard pattern, on master board 30, and master board connectors 22 will be arranged in a mirror-image pattern to terminals 31 for mating connection therewith. Master board connectors 22 and terminals 31 may comprise any electrical connection mechanism known in the art, in addition to those previously described herein.
  • FIGS. 2 and 2A illustrate a second embodiment of the present invention designated as a flip-chip style/wire bond attachment assembly 200. Components common to both FIG. 1 and FIG. 2 retain the same numeric designation. The assembly 200 comprises the semiconductor die 12 having active surface 14 with at least one flip-chip electric connection 16, as known in the art, extending substantially perpendicularly from a bond pad 15 on the semiconductor die active surface 14. The flip-chip electric connections 16 are attached to the adaptor board upper surface 20 in such a manner that the flip-chip electric connections 16 make electrical contact with electrical contact elements 21 on the adaptor board 18. The electrical contact elements 21 communicate between each flip-chip electric connection 16 to bond pads 28 on the adaptor board upper surface 20 through circuit traces 23. The adaptor board lower surface 24 is bonded to an upper surface 36 of a master board 30 with an adhesive 32, which may comprise a liquid or gel adhesive, or an adhesive tape, all as known in the art. If desired, adhesive 32 may be a heat-conductive adhesive. A wire bond 34 extends from each adaptor board bond pad 28 to a corresponding bond pad or lead end 35 on the upper surface 36 of master board 30, bond pad or lead end 35 communicating with other components mounted to master board 30 or with other components on other boards or other assemblies through circuit traces or other conductors known in the art.
  • FIGS. 3 and 3A illustrate a third embodiment of the present invention designated as a wire bond style/flip-chip attachment assembly 300. Components which are common to the previous figures retain the same numeric designation. The assembly 300 comprises an inverted semiconductor die 12 having active surface 14 with at least one bond pad 38 on the semiconductor die active surface 14. As illustrated, the bond pads 38 are arranged in two rows extending down the longitudinal axis of semiconductor die 12 being located transverse to the plane of the page, such an arrangement commonly being used for a “leads over” connection to frame leads extending over the die in its normal, upright position. The semiconductor die active surface 14 is bonded to the adaptor board upper surface 20 with an insulating, sealing adhesive 40. The adaptor board 18 includes at least one or more wire bond vias 42 which is located in a position or positions aligned with the semiconductor die bond pads 38. Each individual wire bond 134 is connected to each corresponding individual semiconductor die bond pad 38. Each wire bond 134 extends from the semiconductor die bond pad 38 to a corresponding bond pad or lead 39 on the adaptor board lower surface 24, which communicates with master board connectors 22 through circuit traces 23. The master board terminals 31 are in electrical communication with at least one master board connector 22 extending substantially perpendicularly from the adaptor board lower surface 24. Preferably, a sealant 44 encases the bond wires 134 and seals the wire bond via 42 to prevent contamination and damage to the wire bonds.
  • FIG. 4 illustrates a fourth embodiment of the present invention designated as a wire bond style/wire bond attachment assembly 400. Components which are common to the previous figures retain the same numeric designation. The assembly 400 comprises the semiconductor die 12 having active surface 14 with at least one bond pad 38 on the semiconductor die active surface 14. As with the embodiment of FIG. 3, semiconductor die 12 in this instance employs bond pads 38 in a “leads over” configuration. The semiconductor die active surface 14 is bonded to the adaptor board upper surface 20 with an insulating, sealing adhesive 40. The adaptor board 18 includes at least one or more wire bond vias 42 which are located in a position or positions aligned with the semiconductor die bond pads 38. Each individual wire bond 134 is connected to each corresponding semiconductor die bond pad 38. Each wire bond 134 extends from the semiconductor die bond pad 38 to a corresponding bond pad 46 within the wire bond via 42. The via bond pads 46 are in electrical communication through circuit traces 23 with at least one corresponding adaptor board bond pad 28. The adaptor board lower surface 24 is bonded to the master board upper surface 36 with the adhesive 32. Wire bonds 34 extend from the adapter board upper surface 20 to a corresponding bond pad or lead end 35 on the master board upper surface 36. Preferably, the wire bond via sealant 44 encases the bond wires 134 and seals the wire bond via 42 to prevent contamination.
  • Having thus described in detail preferred embodiments of the present invention, it is to be understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description as many apparent variations thereof are possible without departing from the spirit or scope thereof.

Claims (81)

  1. 1. A semiconductor device, comprising:
    a substrate with no more than one opening therethrough, the opening elongated along a center axis of the substrate, the substrate otherwise being substantially uniform in thickness and further comprising a first surface, a second surface opposite the first surface, a first row of substrate pads adjacent to a first side of the opening on the second surface, and a second row of substrate pads adjacent to a second side of the opening on the second surface;
    a semiconductor die comprising die pads on an active surface;
    an adhesive material securing the semiconductor die to the first surface of the substrate with the active surface of the semiconductor die facing the first surface of the substrate;
    bond wires extending between the die pads, through the opening, and to the first and second rows of substrate pads;
    an encapsulant substantially filling the opening, the encapsulant covering the bond wires and protruding a first distance beyond a plane of the second surface of the substrate forming a protrusion beneath the opening, wherein the protrusion protrudes a first profile distance from the second surface; and
    solder balls locating on the second surface, in electrical communication with the first and second rows of substrate pads, and protruding from the second surface a second profile distance, with the second profile distance exceeding the first profile distance.
  2. 2. The semiconductor device of claim 1, wherein the die pads of the semiconductor die include:
    a first row of die pads in electrical communication with the first row of substrate pads; and
    a second row of die pads in electrical communication with the second row of substrate pads.
  3. 3. The semiconductor device of claim 2, wherein the first and second sides of the opening of the substrate are parallel to each other.
  4. 4. The semiconductor device of claim 3, wherein the substrate lacks substrate pads adjacent to ends of the opening.
  5. 5. The semiconductor device of claim 1, wherein the adhesive extends beyond an outer periphery of the semiconductor die.
  6. 6. The semiconductor device of claim 5, wherein the adhesive does not extend beyond a periphery of the opening of the substrate.
  7. 7. The semiconductor device of claim 1, wherein the adhesive does not extend beyond a periphery of the opening of the substrate.
  8. 8. The semiconductor device of claim 1, wherein at least some of the solder balls are located in positions on the second surface of the substrate with which the semiconductor die adjacent to the first surface of the substrate is not superimposed.
  9. 9. The semiconductor device of claim 8, wherein at least some of the solder balls are located at positions on the second surface of the substrate with which the semiconductor die adjacent to the first surface of the substrate is superimposed.
  10. 10. The semiconductor device of claim 9, wherein a majority of the solder balls are located at positions on the second surface of the substrate with which the semiconductor die adjacent to the first surface of the substrate is superimposed.
  11. 11. The semiconductor device of claim 1, wherein at least some of the solder balls are located at positions on the second surface of the substrate with which the semiconductor die adjacent to the first surface of the substrate is superimposed.
  12. 12. The semiconductor device of claim 1, further comprising:
    a master printed circuit board including connector pads to which the solder balls are soldered, the master printed circuit board including conductive traces for establishing electrical communication between the connector pads and electrical components mounted to the master printed circuit board.
  13. 13. The semiconductor device of claim 12, wherein:
    the die pads of the semiconductor die are arranged in a non-industry-standard pattern; and
    the connector pads of the master printed circuit board are arranged in an industry-standard pattern.
  14. 14. The semiconductor device of claim 1, wherein:
    the die pads of the semiconductor die are arranged in a non-industry-standard pattern; and
    the solder balls are arranged in an industry-standard pattern.
  15. 15. The semiconductor device of claim 1, wherein the substrate has a substantially planar first surface and at least one lateral dimension that exceeds a corresponding lateral dimension of the semiconductor die.
  16. 16. The semiconductor device of claim 15, wherein a portion of the substrate extends laterally beyond an outer periphery of the semiconductor die.
  17. 17. The semiconductor device of claim 1, wherein the opening of the substrate has a length at least as long as a corresponding dimension of the semiconductor die.
  18. 18. The semiconductor device of claim 17, wherein the opening of the substrate extends at least from one outer peripheral edge of the semiconductor die to an opposite outer peripheral edge of the semiconductor die.
  19. 19. The semiconductor device of claim 1, wherein the solder balls include:
    a first three rows of solder balls arranged parallel to the center axis of the substrate, in a first region of the second surface of the substrate, the first region being located between the encapsulant and a first edge of the substrate; and
    a second three rows of solder balls arranged parallel to the center axis of the substrate, in a second region of the second surface of the substrate, the second region being located between the encapsulant and a second edge of the substrate, the second edge being opposite from the first edge.
  20. 20. The semiconductor device of claim 19, wherein the solder balls include no more than three rows of solder balls in the first region of the second surface of the substrate and no more than three rows of solder balls in the second region of the second surface of the substrate.
  21. 21. The semiconductor device of claim 19, wherein at least some of the solder balls are located at positions on the second surface of the substrate with which the semiconductor die adjacent to the first surface of the substrate is not superimposed.
  22. 22. The semiconductor device of claim 1, wherein the encapsulant is substantially laterally confined within a boundary over the second surface of the substrate surrounding the opening, and located between the substrate pads and the solder balls.
  23. 23. The semiconductor device of claim 1, wherein the encapsulant is substantially absent from regions of the second surface in a vicinity of the solder balls.
  24. 24. The semiconductor device of claim 1, wherein the substrate comprises a substantially planar substrate of sufficient rigidity to maintain planarity in an outer peripheral region located laterally beyond an outer periphery of the semiconductor die.
  25. 25. The semiconductor device of claim 24, wherein the peripheral region of the substrate is at least as wide as a pitch between the solder balls.
  26. 26. The semiconductor device of claim 1, further comprising:
    an encapsulating material on the first surface of the substrate and surrounding an outer periphery of the semiconductor die.
  27. 27. A semiconductor device, comprising:
    a semiconductor die comprising die pads along a center region of an active surface;
    a substrate comprising a single slot aligned with the die pads, a substantially planar first surface, a substantially planar second surface parallel to the first surface, and first and second rows of substrate pads on the substantially planar second surface, proximate first and second sides of the single slot, respectively;
    adhesive between the active surface of the die and the first surface of the substrate;
    bond wires that pass through the single slot, with first ends of the bond wires bonded to the die pads and second ends of the bond wires bonded to the first and second rows of substrate pads;
    encapsulant filling the single slot and protruding a first distance beyond a plane in which the second surface of the substrate is located; and
    solder balls protruding a second distance from the second surface of the substrate, the second distance being greater than the first distance, the solder balls being configured to establish electrical communication between the semiconductor die and at least one other electronic component.
  28. 28. The semiconductor device of claim 27, wherein the die pads of the semiconductor die are arranged in:
    a first row in electrical communication with the first row of substrate pads; and
    a second row in electrical communication with the second row of substrate pads.
  29. 29. The semiconductor device of claim 27, wherein all of the substrate pads of the substrate are located proximate to a first side of the single slot or a second side of the single slot.
  30. 30. The semiconductor device of claim 27, wherein the adhesive extends laterally beyond an outer periphery of the semiconductor die.
  31. 31. The semiconductor device of claim 30, further comprising:
    another encapsulant on the first surface of the substrate and surrounding an outer periphery of the semiconductor die.
  32. 32. The semiconductor device of claim 30, wherein the adhesive is substantially laterally confined outside of an interior periphery of the substrate that defines the single slot.
  33. 33. The semiconductor device of claim 27, wherein the adhesive is substantially laterally confined outside of an interior periphery of the substrate that defines the single slot.
  34. 34. The semiconductor device of claim 27, wherein at least some of the solder balls are located at positions on the second surface of the substrate with which the semiconductor adjacent to the first surface of the substrate is not superimposed.
  35. 35. The semiconductor device of claim 34, wherein a majority of the solder balls are located at positions on the second surface of the substrate with which the semiconductor die adjacent to the first surface of the substrate is superimposed.
  36. 36. The semiconductor device of claim 27, wherein a majority of the solder balls are located at positions on the second surface of the substrate with which the semiconductor die adjacent to the first surface of the substrate is superimposed.
  37. 37. The semiconductor device of claim 27, further comprising:
    a printed circuit board including connector pads to which the solder balls are soldered, the printed circuit board including conductive traces for establishing electrical communication between the connector pads and electrical components mounted to the printed circuit board.
  38. 38. The semiconductor device of claim 37, wherein:
    the die pads of the semiconductor die are arranged in a non-industry-standard pattern; and
    the connector pads of the printed circuit board are arranged in an industry-standard pattern.
  39. 39. The semiconductor device of claim 27, wherein:
    the die pads of the semiconductor die are arranged in a non-industry-standard pattern; and
    the solder balls are arranged in an industry-standard pattern.
  40. 40. The semiconductor device of claim 27, wherein the substrate is of sufficient rigidity to maintain planarity in an outer peripheral region located laterally beyond an outer periphery of the semiconductor die.
  41. 41. The semiconductor device of claim 40, wherein the peripheral region of the substrate is at least as wide as a pitch between the solder balls.
  42. 42. The semiconductor device of claim 27, wherein the single slot of the substrate has a length at least as long as a corresponding dimension of the semiconductor die.
  43. 43. The semiconductor device of claim 42, wherein the single slot of the substrate extends at least from one outer peripheral edge of the semiconductor die to an opposite outer peripheral edge of the semiconductor die.
  44. 44. The semiconductor device of claim 43, wherein the substrate is of sufficient rigidity to maintain planarity in outer peripheral region located laterally beyond an outer periphery of the semiconductor die.
  45. 45. The semiconductor device of claim 27, wherein the solder balls are arranged in:
    a first three rows parallel to the single slot of the substrate, in a first region of the second surface of the substrate, the first region being located between the encapsulant and a first edge of the substrate; and
    a second three rows parallel to the single slot of the substrate, in a second region of the second surface of the substrate, the second region being located between the encapsulant and a second edge of the substrate, the second edge being opposite from the first edge.
  46. 46. The semiconductor device of claim 45, wherein no more than three rows of solder balls are located in the first region of the second surface of the substrate and no more than three rows of solder balls are located in the second region of the second surface of the substrate.
  47. 47. The semiconductor device of claim 45, wherein at least some of the solder balls are located at positions on the second surface of the substrate with which the semiconductor die adjacent to the first surface of the substrate is not superimposed.
  48. 48. The semiconductor device of claim 27, wherein the encapsulant is substantially laterally confined within a boundary over the second surface of the substrate surrounding the single slot, and located between the substrate pads and the solder balls.
  49. 49. The semiconductor device of claim 27, wherein the encapsulant does not encroach into the first or second region of the second surface of the substrate.
  50. 50. The semiconductor device of claim 27, wherein the substrate comprises a printed circuit board.
  51. 51. A semiconductor device assembly, comprising:
    a substrate with an opening therethrough, the opening being substantially centrally located;
    a semiconductor die secured to a first surface of the substrate, the semiconductor die including bond pads aligned with the opening;
    bond wires extending from the bond pads of the semiconductor die to corresponding contacts on a second surface of the substrate, the corresponding contacts being located adjacent to the opening;
    an encapsulant filling the opening and covering the bond wires and the corresponding contacts of the substrate, the encapsulant protruding beyond a plane in which the second surface of the substrate is located.
  52. 52. The semiconductor device assembly of claim 51, further comprising:
    discrete conductive elements secure to substrate pads of the substrate, the substrate pads in electrical communication with the corresponding contacts, the discrete conductive elements protruding beyond the plane in which the second surface of the substrate is located.
  53. 53. The semiconductor device assembly of claim 52, wherein the discrete conductive elements comprise solder balls.
  54. 54. The semiconductor device assembly of claim 52, wherein the discrete conductive elements protrude a same distance beyond the plane in which the second surface of the substrate is located as a distance the encapsulant protrudes beyond the plane.
  55. 55. The semiconductor device assembly of claim 52, wherein the discrete conductive elements protrude a greater distance beyond the plane in which the second surface of the substrate is located than a distance the encapsulant protrudes beyond the plane.
  56. 56. The semiconductor device assembly of claim 52, further comprising:
    a carrier including terminals to which the discrete conductive elements are secured.
  57. 57. A device, comprising:
    a semiconductor die comprising die pads along a center region of the die;
    a substantially planar package substrate of substantially uniform thickness comprising a through-hole aligned with the die pads;
    adhesive to adhere the die to a top side of the substrate;
    conductive wires that pass from a bottom side of the substrate through the through-hole and are bonded to the die pads;
    encapsulant that fills the through-hole and forms a protrusion, wherein the protrusion extends a first distance below a plane defined by the bottom side of the substrate; and
    solder balls disposed under the bottom side of the substrate and electrically coupled to the conductive wires, wherein the solder balls extend below the bottom side by a second distance that is greater than the first distance.
  58. 58. The device of claim 57, wherein the conductive wires are bond wires.
  59. 59. The device of claim 58, wherein the die pads comprise first and second rows of die pads electrically coupled by the bond wires to first and second rows of substrate pads, respectively, adjacent to first and second sides of the through-hole, respectively.
  60. 60. The device of claim 59, wherein the first and second sides of the through-hole are the only sides of the through-hole having substrate pads proximate thereto, the substrate comprises only one through-hole, and the through-hole exposes the die to the encapsulant from approximately one edge of the die to another.
  61. 61. The device of claim 57, wherein the first distance is at least a majority of the second distance.
  62. 62. The device of claim 57, wherein the adhesive extends beyond a periphery of the die, and further comprising an encapsulant disposed on the top side of the substrate and surrounding a periphery of the die.
  63. 63. The device of claim 62, wherein the adhesive does not encroach above the through-hole.
  64. 64. The device of claim 57, wherein the protrusion tapers from a center of the protrusion towards outer edges of the protrusion.
  65. 65. The device of claim 57, wherein at least some of the solder balls are at least partially disposed outside of any location underneath the die.
  66. 66. The device of claim 65, wherein most of the solder balls are disposed underneath the die.
  67. 67. The device of claim 57, wherein a majority of the solder balls are disposed underneath the die.
  68. 68. The device of claim 57, further comprising a PCB comprising connector pads to which the solder balls are soldered, wherein the connector pads are electrically coupled via conductive traces to other electrical components mounted to the PCB.
  69. 69. The device of claim 68, wherein the connector pads are arranged in accordance with an industry-standard pattern and the die pads are arranged in a non-industry-standard pattern.
  70. 70. The device of claim 69, wherein the through-hole exposes a region of the die to the encapsulant that extends from one edge of the die to an opposite edge of the die.
  71. 71. The device of claim 70, wherein the first distance is at least a majority of the second distance.
  72. 72. The device of claim 57, wherein the solder balls are arranged in accordance with an industry-standard pattern and the die pads are arranged in a non-industry-standard pattern.
  73. 73. The device of claim 57, wherein the substrate is sufficiently rigid to maintain planarity in a region between outer edges of the die and outer edges of the substrate.
  74. 74. The device of claim 73, wherein the solder balls have a minimum pitch and at least one side of the peripheral region is at least as wide as the pitch.
  75. 75. The device of claim 57, wherein the through-hole exposes a region of the die to the encapsulant that extends from one edge of the die to an opposite edge of the die.
  76. 76. The device of claim 75, wherein the substrate is of sufficient rigidity to maintain planarity in a peripheral region that extends out from a periphery of the die to a periphery of the substrate.
  77. 77. The device of claim 57, wherein a first three rows of the solder balls, parallel to the through-hole, are disposed beneath a first region of the lower surface that extends between the through-hole and a first edge of the substrate, and a second three rows of the solder balls, parallel to the through-hole, are disposed beneath a second region of the lower surface that extends between the through-hole and a second edge, opposite the first edge, of the substrate.
  78. 78. The device of claim 77, wherein the encapsulant is substantially absent from beneath the first and second regions of the lower surface other than proximate the through-hole.
  79. 79. The device of claim 78, further comprising a PCB comprising connector pads, to which the solder balls are soldered, electrically coupled via conductive traces to other electrical components mounted to the PCB, wherein the through-hole exposes a region of the die to the encapsulant that extends from one edge of the die to an opposite edge of the die, the connector pads are arranged in accordance with an industry-standard pattern, and the die pads are arranged in a non-industry-standard pattern.
  80. 80. The device of claim 57, further comprising encapsulating material disposed on the top side of the substrate and surrounding a periphery of the die.
  81. 81. The device of claim 57, wherein the package substrate is a printed circuit board.
US12714130 1995-12-19 2010-02-26 Grid array packages Expired - Fee Related US8049317B2 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
US08574662 US5719440A (en) 1995-12-19 1995-12-19 Flip chip adaptor package for bare die
US08948936 US6201304B1 (en) 1995-12-19 1997-10-10 Flip chip adaptor package for bare die
US09483483 US6265766B1 (en) 1995-12-19 2000-01-14 Flip chip adaptor package for bare die
US09699537 US6861290B1 (en) 1995-12-19 2000-10-30 Flip-chip adaptor package for bare die
US11070364 US7329945B2 (en) 1995-12-19 2005-03-01 Flip-chip adaptor package for bare die
US11437550 US7381591B2 (en) 1995-12-19 2006-05-19 Flip-chip adaptor package for bare die
US11866065 US8198138B2 (en) 1995-12-19 2007-10-02 Methods for providing and using grid array packages
US12714130 US8049317B2 (en) 1995-12-19 2010-02-26 Grid array packages

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US12714130 US8049317B2 (en) 1995-12-19 2010-02-26 Grid array packages

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US11866065 Continuation US8198138B2 (en) 1995-12-19 2007-10-02 Methods for providing and using grid array packages

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US20100155966A1 true true US20100155966A1 (en) 2010-06-24
US8049317B2 US8049317B2 (en) 2011-11-01

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US09699537 Expired - Fee Related US6861290B1 (en) 1995-12-19 2000-10-30 Flip-chip adaptor package for bare die
US11070364 Expired - Fee Related US7329945B2 (en) 1995-12-19 2005-03-01 Flip-chip adaptor package for bare die
US11437550 Expired - Fee Related US7381591B2 (en) 1995-12-19 2006-05-19 Flip-chip adaptor package for bare die
US11866065 Expired - Fee Related US8198138B2 (en) 1995-12-19 2007-10-02 Methods for providing and using grid array packages
US12714193 Expired - Fee Related US8164175B2 (en) 1995-12-19 2010-02-26 Stackable semiconductor device assemblies
US12714130 Expired - Fee Related US8049317B2 (en) 1995-12-19 2010-02-26 Grid array packages
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US11070364 Expired - Fee Related US7329945B2 (en) 1995-12-19 2005-03-01 Flip-chip adaptor package for bare die
US11437550 Expired - Fee Related US7381591B2 (en) 1995-12-19 2006-05-19 Flip-chip adaptor package for bare die
US11866065 Expired - Fee Related US8198138B2 (en) 1995-12-19 2007-10-02 Methods for providing and using grid array packages
US12714193 Expired - Fee Related US8164175B2 (en) 1995-12-19 2010-02-26 Stackable semiconductor device assemblies

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US8164175B2 (en) 2012-04-24 grant
US20050167850A1 (en) 2005-08-04 application
US20100155930A1 (en) 2010-06-24 application
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US8049317B2 (en) 2011-11-01 grant
US7329945B2 (en) 2008-02-12 grant
US20100148352A1 (en) 2010-06-17 application
US8299598B2 (en) 2012-10-30 grant
US6861290B1 (en) 2005-03-01 grant
US20060211174A1 (en) 2006-09-21 application
US20080023853A1 (en) 2008-01-31 application
US7381591B2 (en) 2008-06-03 grant

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