US20100095094A1 - Method for processing data - Google Patents

Method for processing data Download PDF

Info

Publication number
US20100095094A1
US20100095094A1 US12640201 US64020109A US2010095094A1 US 20100095094 A1 US20100095094 A1 US 20100095094A1 US 12640201 US12640201 US 12640201 US 64020109 A US64020109 A US 64020109A US 2010095094 A1 US2010095094 A1 US 2010095094A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
processor
vpu
code
data
method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12640201
Inventor
Martin Vorbach
Armin Nückel
Frank May
Markus Weinhardt
Joao Manuel Paiva Cardoso
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PACT XPP Tech AG
Original Assignee
Martin Vorbach
Nueckel Armin
Frank May
Markus Weinhardt
Joao Manuel Paiva Cardoso
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/40Transformation of program code
    • G06F8/41Compilation
    • G06F8/45Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Abstract

A method and device for translating a program to a system including at least one first processor and a reconfigurable unit. Code portions of the program which are suitable for the reconfigurable unit are determined. The remaining code of the program is extracted and/or separated for processing by the first processor.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation of U.S. patent application Ser. No. 10/480,003, filed on Jun. 18, 2004, which is a national phase of International Application No. PCT/EP02/06865, filed on Jun. 20, 2002, which claims priority to German Patent Application No. DE 101 29 237.6, filed on Jun. 20, 2001, the entire contents of each of which are expressly incorporated herein by reference thereto.
  • FIELD OF THE INVENTION
  • The present invention relates to data processing. In particular, the present invention relates to traditional, i.e., conventional and reconfigurable processor architectures as well as methods therefor, which permit translation of a classical high-level language (PROGRAM) such as Pascal, C, C++, Java, etc., in particular onto a reconfigurable architecture. The present invention relates in particular to integration and/or close coupling of reconfigurable processors with standard processors, data exchange, and synchronization of data processing.
  • BACKGROUND INFORMATION
  • A conventional processor architecture (PROCESSOR) is understood in the present case to refer to sequential processors having a von Neumann architecture or a Harvard architecture, such as controllers or CISC processors, RISC processors, VLIW processors, DSP processors, etc.
  • The term “reconfigurable target architecture” is understood in the present case to refer to modules (VPUs) having a function and/or interconnection that is repeatedly configurable, in particular configurable without interruption during run time, in particular integrated modules having a plurality of one-dimensionally or multidimensionally arranged arithmetic and/or logic and/or analog and/or memory modules, in particular also coarse-grained modules (PAEs) which are interlinked directly or via a bus system.
  • The generic class of such modules includes in particular systolic arrays, neural networks, multiprocessor systems, processors having a plurality of arithmetic units and/or logic cells, interlinking and network modules such as crossbar switches as well as known modules of the generic types FPGA, DPGA and XPUTER, etc. In this connection, reference is made in particular to the following patents and patent applications: P 44 16 881.0-53, DE 197 81 412.3, DE 197 81 483.2, DE 196 54 846.2-53, DE 196 54 593.5-53, DE 197 04 044.6-53, DE 198 80 129.7, DE 198 61 088.2-53, DE 199 80 312.9, PCT/DE 00/01869, DE 100 36 627.9-33, DE 100 28 397.7, DE 101 10 530.4, DE 101 11 014.6, PCT/EP 00/10516, EP 01 102 674.7, DE 196 51 075.9-53, DE 196 54 846.2-53, DE 196 54 593.5-53, DE 197 04 728.9, DE 197 07 872.2, DE 101 39 170.6, DE 199 26 538.0, DE 101 42 904.5, DE 101 10 530.4. These are herewith incorporated to the full extent for disclosure purposes.
  • This system may be designed in particular as a (standard) processor or module and/or may be integrated into a semiconductor (system on chip, SoC).
  • Reconfigurable modules (VPUs) of different generic types (such as PACT XPP technology, Morphics, Morphosys, Chameleon) are largely incompatible with existing technical environments and programming methods.
  • Programs for these modules are typically incompatible with existing programs of CPUs. A considerable development expense is thus necessary for programming, e.g., in particular for modules of the generic types Morphics, Morphosys. Chameleon already integrates a standard processor (ARC) on more or less reconfigurable modules. This makes approaches for programming tools available. However, not all technical environments are suitable for the use of ARC processors; in particular there are often existing programs, code libraries, etc. for any indeterminate other CPUs.
  • In internal experiments it has been found that there are certain methods and program sequences which may be processed better using a reconfigurable architecture rather than a conventional processor architecture. Conversely, there are also such methods and program sequences which are better executed using a conventional processor architecture. It would be desirable to provide a sequence partitioning to permit appropriate optimization.
  • Conventional translation methods for reconfigurable architectures do not support any forwarding of codes to any standard compilers for generating object codes for any desired PROCESSOR. Ordinarily, the PROCESSOR is fixedly defined within the compiler.
  • In addition, there are no scheduling mechanisms for reconfiguring the individual configurations generated for VPUs. In particular there are no scheduling mechanisms for configuration of independently extracted portions or for individual partitions of extracted portions. Conventional corresponding translation methods are described in the dissertation Übersetzungsmethoden f{umlaut over (r)} strukturprogrammierbare Rechner [Translation Methods for Structure Programmable Computers], by Dr. Markus Weinhardt, 1997, for example.
  • Several conventional methods are known for partitioning array CODE e.g., João M. P. Cardoso, Compilation of Java™ Algorithms onto Reconfigurable Computing Systems with Exploitation of Operation-Level Parallelism, Ph.D. dissertation, Universidade Técnica de Lisboa (UTL), 2000.
  • However, these methods are not embedded into any complete compiler systems. Furthermore, these methods presuppose complete control of the reconfiguration by a host processor, which involves considerable complexity. The partitioning strategies are designed for FPGA-based systems and therefore do not correspond to any actual processor model.
  • SUMMARY
  • An object of the present invention is to provide a method for a commercial application.
  • A reconfigurable processor (VPU) is thus designed into a technical environment which has a standard processor (CPU) such as a DSP, RISC, CISC processor or a (micro)controller. The design may be accomplished according to an embodiment of the present invention in such a way that there is a simple and efficient connection. One resulting aspect is the simple programmability of the resulting system. Further use of existing programs of the CPU as well as the code compatibility and simple integration of the VPU into existing programs are taken into account.
  • A VPU (or a plurality of VPUs, although this need not be mentioned specifically each time) is coupled to a preferred CPU (or a plurality of CPUs, although this need not be mentioned specifically each time) so that it assumes the position and function of a coprocessor (or a plurality of coprocessors that respond optionally). This function permits a simple tie-in into existing program codes according to the pre-existing methods for working with coprocessors according to the related art.
  • The data exchange between the CPU and VPU according to the present invention may be accomplished by memory coupling and/or IO coupling. The CPU and VPU may share all resources; in particular embodiments, it is also possible for the CPU and VPU to jointly use only a portion of the resources and to make other resources available explicitly and/or exclusively for a CPU or VPU.
  • To perform a data exchange, data records and/or configurations may be copied and/or written/read in memory areas particularly provided for those purposes and/or corresponding basic addresses may be set in such a way that these point to the particular data areas.
  • To control the coprocessor, preferably a data record which contains the basic settings of a VPU, e.g., certain basic addresses are provided, for example. In addition, status variables may also be provided for triggering and for function control of a VPU by a CPU and for acknowledgments from a VPU to a CPU. This data record may be exchanged via a shared memory (RAM) and/or via a shared peripheral address space (IO).
  • For synchronization of the CPU and VPU, unilaterally or mutually acting interrupt methods (which are implemented, for example, by signal transfer over interrupt lines and/or interrupt inputs that are specifically dedicated and/or designed for this purpose) and/or the synchronization is accomplished by polling methods. Furthermore, interrupts may also be used for synchronization of data transfers and/or DMA transfers.
  • In an example embodiment that is particularly preferred, a VPU is started by a CPU and thereafter operates preferably independently of the application.
  • A preferred design in which the VPU provides its own mechanisms for loading and controlling configurations is particularly efficient. The generic type of these VPUs include, for example, PACT XPP and Chameleon. The circuits according to the present invention permit a method of operation in which the configurations of the VPU are loaded into a memory together with the program to be executed by the CPU. During execution of the program, the CPU may refer the VPU to the memory locations (e.g., by giving the addresses or pointers), each containing configurations to be executed. The VPU may then load the configurations independently and without further influence by the CPU. The execution by the CPU starts immediately or optionally by means of additional information (e.g., interrupt and/or start instruction).
  • In a particularly preferred expansion, the VPU may read and write data independently within a memory.
  • In a particularly preferred expansion, the VPU may also independently load new configurations out of the memory and may perform new configurations as needed without requiring any further influence by the CPU.
  • These embodiments permit extensive operation of VPUs independently of CPUs. Only a synchronization exchange between CPU and VPU, which may preferably take place bidirectionally, is provided in addition to coordinate data processing operations and/or executions of configurations.
  • It has also been recognized that methods of data processing may and/or should preferably be designed so that particularly suitable portions (VPU code) of the program to be translated are identified and extracted for the reconfigurable target architecture (VPU) to permit particularly efficient data processing. These portions are to be partitioned accordingly and the time sequence configuration of the individual partitions is to be controlled.
  • The remaining portions of the program may be translated onto a conventional processor architecture (PROCESSOR). This is preferably accomplished in such a way that these portions are output as high-level language code in a standard high-level language (e.g., ANSI C) so that an ordinary high-level language compiler (optionally pre-existing) is able to process it without difficulty.
  • It should also be pointed out that these methods may also be used for groups of a plurality of modules.
  • In particular a type of “double buffering” may be used for a particularly simple and at the same time rapid reconfiguration in which a plurality of VPUs are provided, so that a portion of the VPUs may be reconfigured at a time when another portion is computing and perhaps yet another may be inactive, for example. Data links, trigger links, status links, etc. are exchanged among a plurality of VPUs in a suitable way, and are optionally wired through addressed buses and/or multiplexers/demultiplexers according to the VPUs that are currently active and/or to be reconfigured.
  • One advantage of this method is that existing code which has been written for any processor, may continue to be used by involving a VPU, and no modifications or only comparatively minor modifications need be made. The modifications may also be performed incrementally, with more code being transferred gradually from the processor to the VPU. The project risk drops, and there is a significant increase in clarity. It should be pointed out that such a successive transfer of more and more tasks to the VPU, i.e., to the integral, multidimensional, partially reconfigurable and in particular coarse-grained field of elements, has a special meaning on its own and is regarded as being inventive per se because of its major advantages in system porting.
  • In addition, the programmer is able to work in his/her accustomed development environment and need not become adjusted to a novel and possibly foreign development environment.
  • A first aspect of the present invention may be seen in the fact that a PROCESSOR is connected to one or more VPUs so that an efficient exchange of information is possible, in particular in the form of data information and status information.
  • Importance may also be attributed to the configuration of a conventional processor and a reconfigurable processor so that exchange of data information and/or status information between same is possible during running of one or more programs and/or without having to significantly interrupt data processing on the reconfigurable processor and/or the conventional processor in particular; importance may also be attributed to the design of such a system.
  • For example, one or all of the following linking methods and/or means may be used:
    • a) shared memory,
    • b) network (e.g., bus systems such as PCI bus, serial buses such as Ethernet, for example),
    • c) connection to an internal register set or a plurality of internal register sets,
    • d) other memory media (hard drive, flash ROM, etc.).
  • In principle, the VPU and/or the CPU may also independently access the memory without the assistance of a DMA. The shared memory may also be designed as a dual port memory or a multiport memory in particular. Additional modules may be assigned to the system, and in particular reconfigurable FPGAs may be used to permit fine-grained processing of individual signals or data bits and/or to make it possible to establish flexible adaptable interfaces (e.g., various serial interfaces (V24, USB, etc.), various parallel interfaces, hard drive interfaces, Ethernet, telecommunications interfaces (a/b, TO, ISDN, DSL, etc.)).
  • The structure of a VPU is known, for example, from the patents and patent applications described above. Attempts to arrive at alternative module definitions have become known under the name Chameleon, for example. VPUs may be integrated into a system in various ways. For example, a connection to a host processor is possible. Depending on the method, the host processor may assume the configuration control (HOSTRECONF) (e.g., Chameleon) or there may be, for example, a dedicated unit (CT) for controlling the (re)configuration.
  • Accordingly, the translator according to the method described here generates the control information for the reconfiguration for a CT and/or a HOSTRECONF.
  • The translation principle may be embodied in such a way that by using a preprocessor, the portions that may be mapped efficiently and/or reasonably on the particular certain VPU(s) may be extracted from a PROGRAM via a PREPROCESSOR. These portions are transformed into a format suitable for VPUs (NML) and are then translated further into an object code.
  • The remaining code and/or the extracted code is expanded according to experience at or with respect to the location of the code portions that are missing due to the extraction, by adding an interface code which controls communication between PROCESSOR(s) and VPU(s) according to the architecture of the target system. The remaining code which has been optionally expanded may preferably be extracted. This may take place as follows, for example:
  • ...
    Code
    ...
    # START_EXTRACTION
    Code to be extracted
    # END_EXTRACTION
    ...
    Code
    ...
    “// START_EXTRACTION” denotes the start of a code to be extracted.
    “// END_EXTRACTION” denotes the end of a code to be extracted.
  • In such a case, the unit for implementation of the program in configuration codes is designed to recognize the hints and/or implementation instructions.
  • It is also possible for portions of the PROGRAM to be implemented directly in NML for extraction by calling NML routines and to jump to the NML routines using calls. This may take place as follows, for example:
  • a) NML code
    ...
    procedure EXAMPLE
    begin
    ...
    end
    ...
    b) PROGRAM code
    ...
    Code
    ...
    call EXAMPLE      // call of the NML code
    ...
    Code
    ...
  • In this case, the unit for implementation is designed to tie NML program portions, i.e., program portions for execution in and/or on a reconfigurable array, into a larger program.
  • Alternatively and/or additionally, extraction from an object-oriented class is also possible.
  • Macros suitable for a VPU are defined as a class in the class hierarchy of an object-oriented programming language. The macros may be characterized by annotation so that they are recognized as codes intended for a VPU and are processed further accordingly—even in higher hierarchies of the language.
  • Within a macro, a certain networking and/or mapping is preferably predetermined by the macro which then determines the mapping of the macro onto the VPU.
  • Instantiation and chaining of the class results in implementation of the function which includes a plurality of macros on the VPU. In other words, instantiation and chaining of macros define the mapping and interconnection of the individual operations of all macros on the VPU and/or the interconnection and/or data exchange between the VPU and CPU, if necessary.
  • The interface codes are added in instantiation. Chaining describes the detailed mapping of the class on the VPU.
  • A class may also be formed as a call of one or more NML routines, for example.
  • a) Class code
    ...
    class EXAMPLE
    begin
    ...
    end
    ...
    b) PROGRAM code
    ...
    Code
    ...
    EXAMPLE var( )       // instantiation of the class
    ...
    Code
    ...
  • Extraction by analysis is also possible. Portions within the PROGRAM which may be mapped efficiently and/or appropriately on the VPU are recognized using the analytical methods adapted to the particular VPU.
  • These portions are extracted from the PROGRAM.
  • An analytical method suitable for many VPUs, for example, is to create data flow graphs and/or control flow graphs from the PROGRAM. These graphs may then be analyzed automatically with regard to their possible partitioning and/or mapping onto the target VPU. In this case, the portions of the graphs generated and/or the corresponding PROGRAM PORTIONS, which may be partitioned and/or mapped sufficiently well, are extracted. To do so, a partitionability and/or mappability analysis may be performed, evaluating the particular property. Partitioning and extraction of the program portions on the VPU as well as the introduction of the interfaces provided are then performed according to this evaluation.
  • Reference is made here explicitly to the analytical methods described in German Patent Application DE 101 39 170.6 which may be used, for example. The aforementioned patent application is herewith incorporated to full extent for disclosure purposes.
  • One possible analytical method is also provided by recognition of certain data types.
  • Different data types are more or less suitable for processing on a VPU. For example, complex pointer arithmetics, i.e., pointer-based data addressing (pointer) is difficult to map onto a VPU, whereas arrays are very easily mappable.
  • Therefore, the particular suitable data types and at least essential portions of their data processing may be transferred largely automatically or manually to a VPU according to the present invention and extracted accordingly. The extraction is performed in response to the occurrence of certain data types and/or data operations.
  • It should be pointed out here that additional parameters assigned to the data types may provide additional information for determining the executability and/or execution performance on a VPU and therefore may also be used to a significant extent for extraction. For example, the size of the arrays to be computed plays a significant role. It is usually not worthwhile to perform computations for small arrays on a VPU because the resources needed for synchronization and data exchange between the CPU and VPU may be excessive. However, it should again be pointed out that small arrays for which computations are performed particularly frequently within a loop are nevertheless very suitable for VPUs if the loop is computed almost completely on the VPU. Large arrays, however, may usually be computed particularly efficiently on a VPU.
  • In addition, it should be pointed out that certain data types may be created by a specially adapted compiler or, optionally, by a user (e.g., by using TYPE in Pascal), these being particularly suitable for VPUs and data processing of which is then executed on a VPU.
  • For example, there may be the following data types:
  • TYPE stream1 of byte [ ];
    TYPE stream2 of byte [0..255;
  • The term “stream” defines a data stream usually of a great, possibly not previously known, and/or infinite, length. Stream1 here had a length that was not previously known. For example, an FIR filter programmed with this type of data (or, for example, an FFT or DCT) could be mapped automatically onto a VPU—and optionally rolled out. The reconfiguration is then typically and preferably performed in response to other mechanisms than the data stream, e.g., by counters, comparators, CT-controlled and/or by timeout. For example, if wave configuration or some other reconfiguration is to be triggered here, then this characterization of a data packet, in particular data bytes, prompted via conventional methods may be the last to take place to trigger the reconfiguration after and/or with the run-through of this data packet, which is characterized as the last data packet.
  • stream2 defines a data stream having the length of 256 bytes here, which may be treated like stream1, but has the property of ending after 256 bytes and thus possibly triggering a reconfiguration after the end in the sense of the patents cited above by the same applicant. In particular a wave reconfiguration, e.g., according to DE 197 04 728.9, DE 199 26 538.0, DE 102 06 857.7, DE 100 28 397.7 may be triggered with the occurrence of the last data byte and the particular PAE processing the byte may be reconfigured with the processing of this last data byte.
  • A translation of the extracted code according to NML which is suitable for the implemented VPU may preferably be performed.
  • For data flow-oriented VPUs, a data flow graph and/or a control flow graph may be created automatically, for example. The graphs are then translated into NML code.
  • Corresponding code portions such as loops may then be translated via a database (lookup) or ordinary transformations may be performed. For code portions, macros may also be provided and are then used further according to the IKR disclosed in the aforementioned patent applications.
  • Modularization according to PACT13 (PCT/DE00/01869), FIG. 28 may also be supported.
  • Optionally, the mapping and/or its preparation may already take place on the VPU, e.g., by performing the placement of the required resources and routing the connections (place and route). This may be done, for example, according to the conventional rules of placement and routing.
  • It is also possible to analyze the extracted code and/or the translated NML code for its processing efficiency by using an automatic analytical method. The analytical method is preferably selected so that the interface code and the performance influences derived from it are also included in the analysis at a suitable point. Suitable analytical methods are described, for example, in the patent applications by the present patent applicant as cited above.
  • The analysis is optionally performed via complete translation and implementation on the hardware system by executing the PROGRAM and performing measurements using suitable conventional methods.
  • It is also possible that, based on the analyses performed, various portions that have been selected for a VPU by extraction might be identified as unsuitable. Conversely, the analysis may reveal that certain portions that have been extracted for a PROCESSOR would be suitable for execution on a VPU.
  • An optional loop which leads back to the extraction portion after analysis based on suitable decision criteria to execute this loop with extraction specifications according to the analysis permits optimization of the translation results. This is thus an iteration. This procedure is preferred.
  • A loop may be introduced into the compiler run at various points.
  • The resulting NML code is to be partitioned according to the properties of the VPU used as needed, i.e., broken down into individual portions which may be mapped into the particular resources available.
  • A plurality of such mechanisms, in particular those based on graphic analysis, are known per se according to the related art. However, a preferred variant is based on analysis of the program sources and is known by the term temporal partitioning. This method is described in the aforementioned Ph.D. thesis by Cardoso, which is herewith incorporated to the full extent for disclosure purposes.
  • Partitioning methods, regardless of the type, are to be adapted according to the type of VPU used. When using VPUs which allow storage of intermediate results in registers and/or memories, the tie-in of the memories for storage of data and/or states is to be taken into account through the partitioning. The partitioning algorithms (e.g., the temporal partitioning) are to be adapted accordingly. Usually the actual partitioning and scheduling are greatly simplified and made possible in a reasonable manner for the first time through these patents.
  • Many VPUs offer the possibility of differential reconfiguration. This may be used when only relatively few changes within the configuration of PAEs are necessary in a reconfiguration. In other words, only the changes in a configuration in comparison with the present configuration are reconfigured. The partitioning in this case may be done so that the possibly differential configuration following a configuration contains only the required configuration data and does not constitute a complete configuration. It is possible to also take into account the configuration data overhead for analytical purposes in evaluating the partitioning efficiency.
  • The scheduling mechanisms for the partitioned codes may be expanded so that scheduling is controlled by acknowledgment messages of the VPU to the particular unit being reconfigured (CT and/or HOSTRECONF). In particular, the resulting possibility of a conditional execution, i.e., explicit determination of the subsequent partition by the state of the instantaneous partition, is utilized in partitioning. In other words, it is possible to optimize the partitioning so that conditional executions such as IF, CASE, etc. are taken into account.
  • If VPUs which have the ability to transmit status signals between PAEs are used, the PAEs responding to the particular states transmitted and/or cooperating in their processing, then within the partitioning and the scheduling, the additional execution may also be taken into account within the configuration of PAEs, i.e., without the necessity of complete or partial reconfiguration due to an altered conditional program run.
  • In addition, scheduling may support the possibility of preloading configurations during the run time of another configuration. A plurality of configurations may also be preloaded speculatively, i.e., without being certain that the configurations are needed at all. Through selection mechanisms, the configurations that are used may then be selected at run time (see also the example NLS in DE 100 50 442.6, EP 01 102 674.7).
  • According to an additional or alternative variant, data processing within the VPU connected to the CPU requires exactly the same number of cycles as data processing within the computation pipeline of the CPU. In the case of today's high-performance CPUs having a plurality of pipeline stages (>20) in particular, this concept may be used ideally. The special advantage is that no separate synchronization measures such as RDY/ACK are necessary and/or no adaptation of opcodes to the register control is necessary. In this method, the compiler must ensure that the VPU maintains the required number of cycles and that data processing may be balanced by the insertion of delay stages such as a fall-through FIFO, such as that described in other patent applications cited above.
  • The code that is output is usually completely processable on the particular downstream compilers, preferably without any additional measures. If necessary, compiler flags and constraints may be generated for controlling downstream compilers, in which case the user may optionally add his or her own specifications and/or may modify the specifications generated. The downstream compilers do not require any significant modifications, so that standard conventional tools may in principle be used.
  • The method proposed here is thus suitable in particular as a preprocessor and/or as a processor method, for example, upstream from compilers and development systems. However, it should be pointed out explicitly that instead of and/or together with the translator described previously, compilers according to PACT11 (DE 101 39 1706; US 2003/0056202) may also be involved in principle.
  • An FPGA may be connected to the architecture described here, in particular directly to the VPU, to permit fine-grained data processing and/or to permit a flexibly adaptable interface (e.g., various serial interfaces (V24, USB, etc.), various parallel interfaces, hard drive interfaces, Ethernet, telecommunications interfaces (a/b, TO, ISDN, DSL, etc.)) to additional modules. The FPGA may be configured from the VPU architecture, in particular by the CT and/or by the CPU. The FPGA may be operated statically, i.e., without run time reconfiguration, and/or dynamically, i.e., with run time reconfiguration.
  • Providing an interface code has already been mentioned. The interface code which is inserted into the extracted code may be predefined by various methods. The interface code is preferably stored in a database which is accessed. The unit for implementation may be designed to take into account a selection, e.g., by the programmer, in which the appropriate interface code is selected, e.g., based on instructions in the PROGRAM or by compiler flags. An interface code suitable for the implementation method of the VPU/CPU system, used in each case, may be selected.
  • The database itself may be created and maintained by various methods. A few examples will be presented here to illustrate the possibilities:
    • a) The interface code may be predefined by the supplier of the compiler for certain connection methods between the VPU and CPU(s). This may be taken into account in the organization of the database by keeping an appropriate memory device ready and available for this information.
    • b) The interface code may be written by the user himself, who determined the system structure, or it may be modified from existing (exemplary) interface code and added to the database. The database is preferably designed to be user-modifiable in this regard to allow the user to modify the database.
    • c) The interface code may be generated automatically by a development system using which the system structure of the VPU-CPU system has been planned and/or described and/or tested, for example.
  • The interface code is usually preferably designed in such a way that it conforms to the requirements of the programming language in which the extracted code was written and into which the interface code is to be inserted.
  • Debugging and Integration of the Tool Sets
  • Communication routines may be introduced into the interface codes to synchronize various development systems for the PROCESSOR and the VPU. In particular, code for the particular debugger (e.g., according to PACT11) may also be included.
  • The interface code is designed to control and/or enable data exchange between the PROCESSOR and the VPU. It is therefore a suitable and preferred interface for controlling the particular development systems and debuggers. For example, it is possible to activate a debugger for the PROCESSOR as long as the data is being processed by the processor. As soon as the data is transferred via the interface code to one or more VPUs, a debugger for the VPUs is to be activated. If the code is sent back to the PROCESSOR, the PROCESSOR debugger is again to be activated. It is therefore also possible and preferable to handle such sequences by inserting control codes for debuggers and/or development systems into the interface code.
  • Communication and control between the different development systems should therefore preferably be handled via control codes introduced into the interface codes of the PROCESSOR and/or VPU. The control codes may largely correspond to existing standards for the control of development systems.
  • Administration and communication of the development systems are preferably handled as described in the interface codes, but they may also be handled separately from them (if appropriate) according to a corresponding similar method.
  • In many programming languages, in particular in sequential languages such as C, a precise chronological order is predetermined implicitly by the language. In the case of sequential programming languages, this is accomplished by the sequence of individual instructions, for example. If required by the programming language and/or the algorithm, the time information may be mapped onto synchronization models such as RDY/ACK and/or REQ/ACK or to a time stamp method.
  • For example, a subsequent FOR loop may be run and iterated only when a variable (inputstream here) is acknowledged with a RDY in each run. If there is no RDY, the loop run is stopped until RDY is received:
  • while TRUE
      s := 0
      for i: 1 to 3
        s := s + inputstream;
  • The property of sequential languages of being controlled only by instruction processing is connected to the data flow principle of controlling processing through the data flow, i.e., the existence of data. In other words, an instruction and/or a statement (e.g., s:=s+inputstream;) is processed only when it is possible to execute the operation and the data is available.
  • It is noteworthy that this method does not usually result in any change in the syntax or semantics of a high-level language.
  • More complex functions of a high-level language such as looping are implemented by macros. The macros are predefined by the compiler and are instantiated at the translation time.
  • Macros are constructed either of simple language constructs of the high-level language or they are constructed at the assembler level. Macros may be parameterized to permit simple adaptation to the algorithm described (see also PACT11).
  • A standard processor, e.g., an RISC, CISC or DSP (CPU), is thus linked to a reconfigurable processor (VPU).
  • Two different linkage variants, but preferably variants that may also be implemented simultaneously, may be described as follows.
  • A first variant includes a direct link to the instruction set of a CPU (instruction set linkage).
  • A second variant involves linkage via tables in the main memory. Tabulation means are therefore provided in this variant.
  • Free unused instructions are usually present within an instruction set (USA) of a CPU. One or more of these free unused instructions is now used to control VPUs (VPUCODE).
  • A configuration unit (CT) of a VPU is triggered by the decoding of a VPUCODE, and executes certain sequences as a function of the VPUCODE. There is thus a responsive CT for VPU decoding.
  • A VPUCODE may, for example, trigger the loading and/or execution of configurations by the configuration unit (CT) for a VPU.
  • In an expanded embodiment, a VPUCODE may be translated to different VPU instructions via a translation table which is preferably managed by the CPU, or alternatively it may also be managed by the CPU, by a VPU, or from an external unit.
  • The configuration table may be set as a function of the CPU program or code section that has been executed.
  • After arrival of a load instruction, the VPU loads configurations out of its own memory or a memory shared with the CPU. In particular, a VPU configuration may be included in the code of the CPU program being executed at the moment.
  • After receiving an execution instruction, a VPU executes the configuration to be executed and performs the corresponding data processing. The end of data processing may be indicated to the CPU by a termination signal (TERM). Appropriate signal lines/interrupt inputs, etc. are present and/or configured accordingly.
  • Due to the occurrence of a VPUCODE, wait cycles may be executed on the CPU until the termination signal (TERM) of the termination of data processing by the CPU arrives.
  • In a preferred embodiment, processing of the next code continues. If another VPUCODE occurs, then it is possible to wait for the preceding code to be terminated or all the VPCODEs that have been started are queued in a processing pipeline or a task switch is performed, in particular as described below.
  • Termination of data processing is signaled by the arrival of the termination signal (TERM) in a status register. Termination signals arrive in the order of a possible processing pipeline.
  • Data processing on the CPU may be synchronized to the arrival of a termination signal by testing the status register.
  • In one possible embodiment, a task switch may be triggered if an application cannot be continued before the arrival of TERM, e.g., due to data dependencies.
  • It is preferable if loose links are established between processors and VPUs, in which VPUs function largely as independent coprocessors.
  • Such a linkage involves one or more shared data sources and data sinks, usually over shared bus systems and/or shared memories. Data is exchanged between a CPU and a VPU via DMAs and/or other memory access controllers. Data processing is preferably synchronized via an interrupt control or a status query mechanism (e.g., polling).
  • A tight linkage corresponds to the direct linkage of a VPU to the instruction set of a CPU, as described above.
  • In a direct arithmetic unit linkage, a high reconfiguration performance in particular is important. Therefore, wave reconfiguration is preferred. In addition, the configuration words are preferably preloaded so that when the instruction is executed, the configuration may be configured particularly rapidly (via wave reconfiguration, in the optimum case within one cycle). It would also be possible to provide a plurality of arrays, identical arrays in particular, instead of a partial array configuration in the case of high-performance applications, but also in the case of primarily low-performance applications in particular, and to reconfigure at least one of these for a new task, in particular in advance, and then to change easily and completely to another array as needed instead of a reconfiguration or partial reconfiguration of an integral multidimensional coarse-grained field which is partially reconfigurable in run time. Signals may be sent to the subarrays, e.g., via MUX/DEMUX stages, in particular I/O signals, data signals, status signals, and/or trigger signals.
  • For wave reconfiguration, the configurations that are presumably to be executed will preferably be recognized in advance by the compiler at compilation time and preloaded accordingly at run time.
  • At the time of instruction execution, the corresponding configuration is optionally selected and executed individually for each PAE and/or for a PAE subset. Such methods are also described in the publications identified above.
  • A preferred implementation may provide for different data transfers between a CPU and a VPU. Three particularly preferred methods that may be used individually or in combination are described below.
  • In the case of register linkage, the VPU may take data from a CPU register, process it and write it back to a CPU register.
  • Synchronization mechanisms are preferably used between the CPU and the VPU.
  • For example, the VPU may receive a RDY signal due to the data being written to the CPU register by the CPU and then the VPU may process the data thus written. Readout of data from a CPU register by the CPU may result in an ACK signal, which thus signals to the VPU data acceptance by the CPU. Use of the conventional RDY/ACK protocol in a different manifestation is advantageous in the present case precisely with coarse-grained cells of reconfigurable units.
  • CPUs do not typically make similar mechanisms available.
  • Two possible implementations are described in greater detail.
  • One approach that is easily implemented is to perform the data synchronization via a status register. For example, the VPU may indicate to the status register the successful readout of data from a register and the associated ACK signal and/or input of data into a register and the associated RDY signal. The CPU first tests the status register and performs wait loops or task switching, for example, until the RDY or ACK is received, depending on the operation. The CPU will then continue to perform the particular register data transfer.
  • In an expanded embodiment, the instruction set of the CPU is expanded by adding load/store instructions with an integrated status query (load_rdy, store_ack). For example, a new data word is written into a CPU register only when the register has first been read out by the VPU and an ACK signal has been received. Accordingly, load_rdy reads data out of a CPU register only when the VPU has previously entered new data and generated a RDY signal.
  • Data belonging to a configuration to be executed may be written to the CPU registers and/or may be read out of the registers successively more or less by block moves as in the related art. Block move instructions that are implemented if necessary may preferably be expanded by the integrated RDY/ACK status query described here.
  • A plurality of modifications and different embodiments of this basic method are possible.
  • The wave reconfiguration mentioned above allows starting of a new VPU instruction and the corresponding configuration as soon as the operand of the previous VPU instruction has been accepted from the CPU registers. The operands for the new instruction may be written directly into the CPU register after the instruction start.
  • According to the wave reconfiguration method, the VPU is reconfigured successively for the new VPU instruction on completion of data processing of the previous VPU instruction, and the new operands are processed.
  • In addition, data may be exchanged between a VPU and a CPU through suitable bus accesses to shared resources.
  • If there is to be an exchange of data that has been processed by the CPU just prior to the exchange and therefore is presumably still in the cache of the CPU which is preferably to be provided or if the data is processed by the CPU immediately next and therefore is logically placed in the cache of the CPU, this data is preferably read by the VPU out of the cache of the CPU or it is written to the cache of the CPU. This may be determined largely in advance at the compilation time through suitable analyses of the application by the compiler and the binary code may be generated accordingly.
  • If there is to be an exchange of data that is presumably not in the cache of the CPU and/or is presumably not needed subsequently in the cache of the CPU, it is preferably read directly by the VPU from the external bus and the data source connected to it (e.g., memory, peripheral) and/or written to the external bus and the data sink associated with it (e.g., memory, peripheral). This may be ascertained by the compiler largely in advance at compilation time of the application through suitable analyses, and the binary code may be generated accordingly.
  • In a transfer over the bus bypassing the cache, a protocol between the cache and the bus is preferably implemented, ensuring correct contents of the cache. For example, the conventional MESI protocol may be used for this purpose.
  • The methods described here need not at first have any particular mechanism for operating system support. It is preferable to ensure that an operating system to be executed behaves according to the status of a VPU to be supported, which is possible and to which end in particular schedulers may be provided.
  • In the case of a tight arithmetic unit linkage, the status register of the CPU into which the linked VPU enters its data processing status (termination signal) is preferably queried. If further data processing is to be transmitted to the VPU and the VPU has not yet terminated the previous data processing, the system will wait and/or a task switch will preferably be performed.
  • For coprocessor coupling, mechanisms controlled via the operating system, in particular the scheduler, are preferably used.
  • A simple scheduler may either allow the current task to continue running on the CPU after transfer of a function to a VPU, if it is able to run independently and simultaneously with data processing on a VPU. If or as soon as the task must wait for termination of data processing on the VPU, the task scheduler switches to another task.
  • Each task newly activated will check (if it uses the VPU) before use on whether the VPU is available for data processing and/or whether it is still processing data at the present time. Either it must then wait for termination of data processing or preferably the task is switched.
  • A simple and nevertheless efficient method may be created by so-called descriptor tables which may be implemented as follows, for example.
  • Each task generates one or more tables (VPUCALL) having a suitable fixed data format in the memory area assigned to it for callup of the VPU. This table contains all the control information for a VPU such as the program/configuration to be executed and/or the pointer to the memory location(s) or data sources of the input data and/or the memory location(s) or data sinks of the result data and/or additional execution parameters, e.g., data array variables.
  • The memory area of the operating system contains a table or an interlinked list (LINKLIST) which points to all the VPUCALL tables in the order of their creation.
  • Data processing on the VPU then takes place in such a way that a task creates a VPUCALL and calls up the VPU via the operating system. The operating system creates an entry in the LINKLIST. The VPU processes the LINKLIST and executes the particular VPU call referenced. The termination of the particular data processing is indicated by a corresponding entry in the LINKLIST and/or VPUCALL table.
  • The VPU thus works largely independently of the CPU. The operating system and/or the particular task must only monitor the tables (LINKLIST and/or VPUCALL).
  • These two methods are particularly efficient in performance if the VPU used has an architecture which allows reconfiguration that is and/or may be superimposed on data processing.
  • It is thus possible to start a new data processing and possibly a reconfiguration associated with it, immediately after reading the last operands out of the data sources. In other words, it is no longer the termination of data processing, but instead reading the last operands is necessary for synchronization. This greatly increases the performance in data processing.
  • The possible use of an operating system has an additional influence on the handling of states.
  • Operating systems use task schedulers, for example, for managing multiple tasks to permit multitasking.
  • Task schedulers interrupt tasks at a certain point in time, start other tasks and, after the latter have been processed, resume processing of the interrupted task. Locally relevant states may remain unsaved if it is ensured that a configuration (which corresponds to processing of a task) will be terminated only after complete processing—i.e., when all data and states to be processed within this configuration cycle have been saved.
  • However, if the task scheduler interrupts configurations before they have been completely processed, local states and/or data must be stored. In addition, this is advantageous when the processing time of a configuration cannot be predicted. In conjunction with the known holding problem and the risk that a configuration will not be terminated at all (e.g., due to an error), this also seems appropriate to prevent a deadlock of the entire system.
  • In other words, taking into account task switching, relevant states may also be regarded as states which are necessary for task switching and correct restart of data processing.
  • Thus, in task switching the memory for results and, if necessary, also the memory for the operands must be saved and restored again at a later point in time, i.e., on returning to this task. This may be performed by a method comparable to the conventional PUSH/POP instructions and methods. In addition, the state of data processing, i.e., the pointer to the last operand processed completely, must be saved. Reference should be made here in particular to PACT18.
  • Depending on the optimization of task switching, there are two options, for example:
  • a) The interrupted configuration is reconfigured and only the operands are loaded. Data processing begins anew as if the processing of the configuration had not even been started. In other words, all data computations are executed from the beginning, and if necessary, computations are even performed in advance. This option is simple but not very efficient.
    b) The interrupted configuration is reconfigured, the operands and results that have already been calculated being loaded into the particular memory. Data processing is continued with the operands that have not been completely computed. This method is much more efficient, but it presupposes that additional states which occur during processing of the configuration may become relevant, if necessary; for example, at least one pointer to the last operand completely computed must be saved, so that it is possible to begin again with their successors after reconfiguration.
  • A particularly preferred variant for managing relevant data is made available through the context switching described below. In task switching and/or in executing and switching configurations (see, for example, patent application PACT15 (PCT/EP02/02398), which is herewith fully included for disclosure purposes) it may be necessary to save data or states, which are not typically saved together with the working data in the memories for a following configuration because they merely mark an end value, for example.
  • Context switching according to the present invention is implemented by removing a first configuration while the data to be saved remains in the corresponding memories (REGs) (memories, registers, counters, etc.).
  • A second configuration is loaded, connecting the REG in a suitable manner and in a defined order to one or more global memories.
  • The configuration may use address generators, for example, to access the global memory (memories). The configuration may use address generators, for example, to access REGs designed as memories. According to the configured connection between the REGs, the contents of the REGs are written into the global memory in a defined order, with the particular addresses being specified by address generators. The address generator generates the addresses for the global memory (memories) so that the memory areas containing data (PUSH AREA) of the first configuration that has been removed may be assigned unambiguously.
  • In other words, different address spaces are preferably provided for different configurations. This configuration corresponds to a PUSH of conventional processors.
  • Other configurations then use the resources.
  • The first configuration should be restarted. Before that, a third configuration interconnecting the REGs of the first configuration in a defined order is started.
  • The configuration may use address generators, for example, to access the global memory (memories).
  • The configuration may use address generators, for example, to access REGs configured as memories.
  • An address generator generates addresses so that correct access to the PUSH AREA assigned to the first configuration is achieved. The generated addresses and the configured order of the REGs are such that the data of the REGs is output from the memories and into the REGs in the original order. The configuration corresponds to that of a POP of conventional processors.
  • The first configuration is restarted.
  • In summary, a context switch is performed so that by loading particular configurations which operate like PUSH/POP of conventional processor architectures, the data to be saved is exchanged with a global memory.
  • The function is to be illustrated in an example. A function adds up two rows of numbers, where the length of the rows is not known at translation time, but instead is known only at run time.
  • proc example
      while i<length do
        x[i] = a[i] + b[i]
  • This function is now interrupted during execution, e.g., by a task switch, or because the memory provided for x is full. At this point in time, a, b and x are in memories according to the present invention; i and optionally length must be saved, however.
  • To do so, the configuration “example” is terminated, with the register content being saved and a configuration push being started, reading i and length out of the registers and writing them into a memory.
  • proc push
      mem[<push_adr_example>] = i
      push_adr_example++
      mem{<push_adr_example>] = length
  • According to this embodiment, push is terminated and the register content may be deleted.
  • Other configurations are executed. After a period of time, the example configuration is restarted.
  • Before that, a configuration pop is started, and it reads the register contents out of the memory again.
  • proc pop
      i = mem[<push_adr_example>]
      push_adr_example++
      length = mem[<push_adr_example>]
  • After execution, pop is terminated and the register contents remain unchanged. The configuration “example” is restarted.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows an example of a possible system structure.
  • FIG. 2 shows an example compilation sequence.
  • FIG. 3 shows the structure of an example VPU.
  • FIG. 4 shows an example CPU.
  • FIG. 5 shows an example abstract system definition.
  • FIG. 6 shows an example interface.
  • FIG. 7 shows data transfers between VPU and CPU.
  • FIG. 8 shows a memory area of the operating system.
  • DETAILED DESCRIPTION
  • FIG. 1 illustrates an example of, in accordance with the present invention, an example method and shows a possible system structure, a PROCESSOR (0101) being connected to a VPU (0103) via a suitable interface (0102) for data exchange and status exchange.
  • A PROGRAM code (0110) is broken down (e.g., by a preprocessor for a compiler) into a portion (0111) suitable for the PROCESSOR and a VPU-suitable portion (0112), for example, according to the extraction methods described here.
  • Portion 0111 is translated by a standard compiler (0113) corresponding to the PROGRAM code, the additional code from a database (0114) for description and management of the interface (0102) between the PROCESSOR and a VPU being previously inserted. Sequential code executable on 0101 is generated (0116) and the corresponding programming (0117) of the interface (0102) is generated if necessary. The standard compiler may be of a type that is available as a conventional commercially available tool or as a portion of a development environment that is commercially available. The preprocessor and/or possibly the VPU compiler and/or possibly the debugger and additional tools may be integrated into an existing commercially available development environment, for example.
  • Portion 0112 is translated by a VPU compiler (0115), additional code for description and management of the interface (0102) being inserted from a database (0114). Configurations executable on 0103 are generated (0118) and, if necessary, the corresponding programming (0119) of the interface (0102) is also generated. It should be pointed out explicitly that in principle, compilers as described in DE 101 39 170.6 may also be used for 0115.
  • FIG. 2 shows a basic compilation sequence as an example. In the extraction unit (0202), a PROGRAM (0201) is broken down into VPU code (0203) and PROCESSOR code (0204) according to different methods. Different methods may be used in any combination for extraction, e.g., instructions in the original PROGRAM (0205) and/or subprogram calls (0206) and/or analytical methods (0207) and/or utilization of object-oriented class libraries (0206 a). The code extracted is translated, if necessary, and checked for its suitability for the particular target system (0208), if necessary. Feedback (0209) to the extraction is possible to obtain improvements due to modified allocation of the codes to a PROCESSOR or a VPU and/or a plurality of same.
  • Thereafter (0211) VPU code 0203 is expanded (0212) using the interface code from a database (0210) and/or (0204) is expanded using the interface code from 0210 to 0213.
  • The resulting code is analyzed for its performance (0214) and, if necessary, feedback (0215) to the extraction is possible to obtain improvements due to modified allocation of the codes to the PROCESSOR or a VPU.
  • The resulting VPU code (0216) is forwarded for further translation to a downstream compiler suitable for the VPU. For further translation, the resulting PROCESSOR code (0217) is processed further in any downstream compiler suitable for the PROCESSOR.
  • It should be pointed out that individual steps may be omitted, depending on the method. Generally, however, at least largely complete code, which is directly translatable without significant intervention by the programmer, or at least without any significant intervention, is output to the particular downstream compiler systems.
  • It is thus proposed that a preprocessor means be provided with a code input for supplying code to be compiled, with code analyzing means, in particular code structure and/or data format and/or data stream recognition and/or evaluation units, and with a segmenting evaluation unit for evaluating a code segmentation performed in response to signals from the code analyzing unit and, if necessary, with an iteration means for repeating a code segmentation until stable and/or sufficiently acceptable values are achieved, and with at least two partial code outputs, a first partial code output outputting partial code for at least one conventional processor, and at least one additional partial code output outputting code intended for processing by means of reconfigurable logic units, in particular multidimensional units having cell structures, in particular register means which process coarse-grained data and/or logic cells (PAEs) having arithmetic units and the like plus allocated register units, if necessary, and/or a fine-grained control means and/or monitoring means, such as state machines, RDY/ACK trigger lines and communication lines, etc. Both partial code outputs may be located at one physical output as serial multiplex outputs.
  • The database for the interface codes (0210) is constructed independently of and prior to the compiler run. For example, the following sources for the database are possible: predefined by the supplier (0220), programmed by the user (0221) or generated automatically by a development system (0222).
  • FIG. 3 shows the structure of a particularly preferred VPU. Preferably hierarchical configuration managers (CTs) (0301) control and manage a system of reconfigurable elements (PACs) (0302). The CTs are assigned a local memory for the configurations (0303). The memory also has an interface (0304) to a global memory which makes the configuration data available. The configuration runs in a controllable manner via an interface (0305). An interface of the reconfigurable elements (0302) to sequence control and event management (0306) is present, as is an interface to the data exchange (0307). An interface of the reconfigurable elements (0302) for sequence control and event management (0306) is present as is an interface for data exchange (0307).
  • FIG. 4 shows details of an exemplary CPU system, e.g., a DSP of the C6000 type (0401) by Texas Instruments. This shows the program memory (0402), data memory (0403), any peripheral device (0404) and EMIF (0405). A VPU is integrated (0408) as a coprocessor via a memory bus (0406) and a peripheral bus (0407). A DMA controller (EDMA) (0409) may perform any DMA transfers, e.g., between the memory (0403) and the VPU (0408) or the memory (0403) and the peripheral device (0404).
  • FIG. 5 shows a more abstract system definition. A CPU (0501) is assigned a memory (0502) to which it has reading access and/or writing access. A VPU (0503) is connected to the memory. The VPU is subdivided into a CT portion (0509) and the reconfigurable elements for data processing (0510).
  • To increase the memory accesses, the memory may have a plurality of independent access buses (multiport). In a particularly preferred embodiment, the memory is segmented into a plurality of independent segments (memory banks), each bank being independently accessible. All the segments are preferably located within a uniform address space. One segment is preferably available mainly for the CPU (0504) and another segment is mainly available for data processing by the VPU (0505) while yet another segment is mainly available for the configuration data of the VPU (0506).
  • Typically and preferably, a fully configured VPU will have its own address generators and/or DMAs to perform data transfers. Alternatively and/or additionally, it is possible for a DMA (0507) to be provided within the system (FIG. 5) for data transfers with the VPU.
  • The system includes IO (0508) which may be accessible by the CPU and VPU.
  • The CPU and VPU may each have dedicated memory areas and IO areas to which the other has no access.
  • A data record (0511) which may be in the memory area and/or in the IO area and/or partially in one of the two is used for communication between the CPU and the VPU, e.g., for exchanging basic parameters and control information. The data record may contain the following information, for example:
      • 1. Basic address(es) of the CT memory area in 0506 for localizing the configurations.
      • 2. Basic address(es) of data transfers with 0505.
      • 3. IO address(es) of data transfers with 0508.
      • 4. Synchronization information, e.g., resetting, stopping, starting the VPU.
      • 5. Status information on the VPU, e.g., errors or states of data processing.
  • The CPU and the VPU are synchronized by data polling and/or preferably by interrupt control (0512).
  • FIG. 6 shows one possible embodiment of the interface structure of a VPU for tying into a system similar to that shown in FIG. 5. To do so, a memory/DMA interface and/or an IO interface is assigned (0601) to the VPU for data transfer; another system interface (0602) is responsible for sequence control such as managing interrupts, starting and stopping the processing, exchange of error states, etc.
  • The memory/DMA interface and/or IO interface is connected to a memory bus and/or an IO bus.
  • The system interface is preferably connected to an IO bus, but alternatively or additionally, it may also be connected to a memory according to 0511.
  • The interfaces (0601, 0402) may be designed for adaptation of different working frequencies of the CPU and/or the VPU and/or the system; for example, the system and/or the CPU may currently operate at 500 MHz and the VPU at 200 MHz.
  • The interfaces may perform a translation of the bus protocols, e.g., the VPU-internal protocol may be converted to an external AMBA bus protocol. They thus trigger bus protocol translation means and/or are designed for bus protocol translation, in particular bus protocol translation between an internal VPU protocol and a known bus protocol. It is also possible to provide for conversion directly to CPU-internal bus protocols.
  • The memory/DMA interface and/or the IO interface supports memory access by the CT to an external memory, which is preferably performed directly (memory mapped). The data transfer of the CT(s) and/or PAC(s) may be buffered, e.g., via FIFO stages. External memories may be addressed directly; in addition, DMA-internal and/or external DMA transfers are also performed.
  • Data processing, e.g., the initialization, i.e., the start of configurations, is controlled via the system interface. In addition, status and/or error states are exchanged. Interrupts for the control and synchronization between the CTs and a CPU may be supported.
  • The system interface is capable of converting VPU-internal protocols so that they are converted to external (standard) protocols (e.g., AMBA).
  • A preferred method of code generation for the system described here is described herein. This method describes a compiler which breaks down program code into code for a CPU and code for a VPU. The breakdown is performed by different methods on different processors. In a particularly preferred embodiment, the particular codes broken down are expanded by adding the interface routines for communication between CPU and VPU. The expansion may be performed automatically by the compiler.
  • The following tables show examples of communication between a CPU and a VPU. The columns are assigned to the particular active function units: CPU, system DMA and DMA interface (EDMA) and/or memory interface (memory I/F), system interface (system I/F, 0602), CTs and the PAC. The individual cycles are entered into the cells in the order of their execution. K1 references a configuration 1 that is to be executed.
  • The first table shows as an example a sequence when using the system DMA (EDMA) for data transfer:
  • CPU EDMA System I/F CTs PAC
    Initiate
    K1
    Load
    K1
    Start Configure
    K1 K1
    Initiate Start Wait for
    loading of K1 data
    data by EDMA
    Initiate Data transfer Data
    reading of read data processing
    data by EDMA
    Data transfer Signal the end
    write data of the operation
  • It should be pointed out that synchronization between the EDMA and the VPU is performed automatically via interface 0401, i.e., DMA transfers take place only when the VPU is ready.
  • A second table shows a preferred optimized sequence as an example. The VPU itself has direct access to the configuration memory (0306). In addition, data transfers are executed by
  • DMA circuit within the VPU, which may be fixedly implemented, for example, and/or formed by the configuration of configurable parts of the PAC.
  • CPU EDMA System I/F CTs PAC
    Initiate
    K1
    Start Read the Configure
    K1 configuration K1
    Data transfer Start Read data
    read data K1
    Data
    processing
    Data transfer Signal the end Write data
    write data of the operation
  • The complexity for the CPU is minimal.
  • In summary, the present invention relates to methods that permit translation of a traditional high-level language such as Pascal, C, C++, Java, etc., onto a reconfigurable architecture. This method is designed so that only those portions of the program that are to be translated and are suitable for the reconfigurable target architecture are extracted. The remaining portions of the program are translated onto a conventional processor architecture.
  • For reasons of simplicity, FIG. 7 shows only the relevant components (in particular the CPU), although a significant number of other components and networks would typically be present.
  • A preferred implementation such as that in FIG. 7 may provide different data transfers between a CPU (0701) and a VPU (0702). The configurations to be executed on the VPU are selected by the instruction decoder (0705) of the CPU, which recognizes certain instructions intended for the VPU and triggers the CT (0706), so that it loads the corresponding configurations out of a memory (0707) assigned to the CT—which may be shared with the CPU in particular or may be the same as the working memory of the CPU—into the array of PAEs (PA, 0108).
  • CPU registers (0703) are provided to obtain data in a register connection, to process the data and to write it back to a CPU register. A status register (0704) is provided for data synchronization. In addition, a cache is also provided, so that when data that has just been processed by the CPU is to be exchanged, it is still presumably in the cache (0709) of the CPU and/or will be processed immediately thereafter by the CPU.
  • The external bus is labeled as (0710) and through it, data is read out of a data source (e.g., memory, peripheral device) connected to it, for example, and/or is written to the external bus and the data sink connected to it (e.g., memory, peripheral device). This bus may in particular be the same as the external bus of the CPU (0712 & dashed line).
  • A protocol (0711) between cache and bus is implemented, ensuring the correct contents of the cache. An FPGA (0713) may be connected to the VPU to permit fine-grained data processing and/or to permit a flexible adaptable interface (0714) (e.g., various serial interfaces (V24, USB, etc.), various parallel interfaces, hard drive interfaces, Ethernet, telecommunications interfaces (a/b, TO, ISDN, DSL, etc.)) to additional modules and/or the external bus system (0712).
  • According to FIG. 8, the memory area of the operating system contains a table or an interlinked list (LINKLIST, 0801) which points to all VPUCALL tables (0802) in the order in which they are created.

Claims (12)

  1. 1. A method for translating a program for a system including at least one first processor and a reconfigurable unit, the method comprising:
    determining from the program, code portions of the program suitable for the reconfigurable unit; and
    at least one of extracting and separating, remaining code of the program for processing by the first processor.
  2. 2. The method as recited in claim 1, further comprising:
    appending interface code to the code portions extracted for the first processor to permit communication between the first processor and the reconfigurable unit according to the system.
  3. 3. The method as recited in claim 1, further comprising:
    appending interface to the code portions extracted for the reconfigurable unit so that communication is enabled between the first processor and the reconfigurable unit according to the system.
  4. 4. The method as recited in claim 1, wherein the determining step includes determining the code portions based on automated analyses.
  5. 5. The method as recited in claim 1, wherein the program includes instructions defining the code portions to be extracted, and wherein the method further comprises automatically analyzing the instructions.
  6. 6. The method as recited in claim 1, wherein the code portions to be extracted are determined based on calls of subprograms.
  7. 7. The method as recited in claim 1, further comprising:
    providing an interface code which provides at least one of memory linkage, register linkage, and linkage via a network.
  8. 8. The method as recited in claim 1, further comprising:
    analyzing at least one of the extracted code portions and results achievable with a given extraction; and
    restarting an extraction with new improved parameters based on the analysis.
  9. 9. The method as recited in claim 1, further comprising:
    appending control code to the extracted code for at least one of management, control, and communication of the development system.
  10. 10. The method as recited in claim 1, wherein the first processor has a conventional processor architecture, the architecture including at least one of a von-Neumann architecture, Harvard architecture, controller, CISC processor, RISC processor, VLIW processor, or DSP processor.
  11. 11. The method as recited in claim 1, wherein the remaining code is extracted so that it is translatable via any ordinary unmodified compiler that is suitable for the first processor.
  12. 12. A device for data processing, comprising:
    at least one conventional processor;
    at least one reconfigurable unit; and
    an arrangement configured to exchange data and status information between a conventional processor and a reconfigurable unit, the arrangement being configured so that the data and status information exchange is possible therebetween at least one of: i) during processing of one or more programs, ii) without having to interrupt data processing on the reconfigurable processor, and iii) without having to interrupt data processing on the conventional processor.
US12640201 2000-10-09 2009-12-17 Method for processing data Abandoned US20100095094A1 (en)

Priority Applications (64)

Application Number Priority Date Filing Date Title
DE2001129237 DE10129237A1 (en) 2000-10-09 2001-06-20 Integrated cell matrix circuit has at least 2 different types of cells with interconnection terminals positioned to allow mixing of different cell types within matrix circuit
EP01115021.6 2001-06-20
EP01115021 2001-06-20
DE10129237.6 2001-06-20
DE10135211 2001-07-24
DE10135211.5 2001-07-24
DE10135210.7 2001-07-24
DE10135210 2001-07-24
DE10139170 2001-08-16
DE10139170.6 2001-08-16
DE10142231.8 2001-08-29
DE10142231 2001-08-29
DE10142904.5 2001-09-03
DE10142903.7 2001-09-03
DE10142894 2001-09-03
DE10142894.4 2001-09-03
DE10142903 2001-09-03
DE10142904 2001-09-03
DE10144732.9 2001-09-11
DE10144733 2001-09-11
DE10144733.7 2001-09-11
DE10144732 2001-09-11
DE10145795.2 2001-09-17
DE10145795 2001-09-17
DE10145792 2001-09-17
DE10145792.8 2001-09-17
DE10146132.1 2001-09-19
DE10146132 2001-09-19
DE10154260 2001-11-05
DE10154259 2001-11-05
DE10154259.3 2001-11-05
DE10154260.7 2001-11-05
EP01129923.7 2001-12-14
EP01129923 2001-12-14
EP02001331.4 2002-01-18
EP02001331 2002-01-18
DE10202044 2002-01-19
DE10202044.2 2002-01-19
DE10202175.9 2002-01-20
DE10202175 2002-01-20
DE10206653 2002-02-15
DE10206653.1 2002-02-15
DE10206856 2002-02-18
DE10206857 2002-02-18
DE10206857.7 2002-02-18
DE10206856.9 2002-02-18
DE10207225.6 2002-02-21
DE10207226 2002-02-21
DE10207225 2002-02-21
DE10207224 2002-02-21
DE10207224.8 2002-02-21
DE10207226.4 2002-02-21
DE10208434.3 2002-02-27
DE10208434 2002-02-27
DE10208435.1 2002-02-27
DE10208435 2002-02-27
DE10212621.6 2002-03-21
DE10212622.4 2002-03-21
DE10212621 2002-03-21
DE2002112622 DE10212622A1 (en) 2002-03-21 2002-03-21 Computer program translation method allows classic language to be converted for system with re-configurable architecture
EP02009868.7 2002-05-02
EP02009868 2002-05-02
US10480003 US7657877B2 (en) 2001-06-20 2002-06-20 Method for processing data
US12640201 US20100095094A1 (en) 2001-06-20 2009-12-17 Method for processing data

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12640201 US20100095094A1 (en) 2001-06-20 2009-12-17 Method for processing data
US14223793 US10031733B2 (en) 2001-06-20 2014-03-24 Method for processing data

Related Parent Applications (3)

Application Number Title Priority Date Filing Date
US10480003 Continuation 2002-06-20
PCT/EP2002/006865 Continuation WO2002103532A3 (en) 2000-10-09 2002-06-20 Data processing method
US10480003 Continuation US7657877B2 (en) 2000-10-09 2002-06-20 Method for processing data

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US14223793 Continuation US10031733B2 (en) 2000-10-09 2014-03-24 Method for processing data

Publications (1)

Publication Number Publication Date
US20100095094A1 true true US20100095094A1 (en) 2010-04-15

Family

ID=42676650

Family Applications (2)

Application Number Title Priority Date Filing Date
US10480003 Active 2025-04-05 US7657877B2 (en) 2000-10-09 2002-06-20 Method for processing data
US12640201 Abandoned US20100095094A1 (en) 2000-10-09 2009-12-17 Method for processing data

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US10480003 Active 2025-04-05 US7657877B2 (en) 2000-10-09 2002-06-20 Method for processing data

Country Status (4)

Country Link
US (2) US7657877B2 (en)
EP (2) EP1402382B1 (en)
JP (1) JP2004533691A (en)
WO (1) WO2002103532A3 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140237603A1 (en) * 2013-02-20 2014-08-21 International Business Machines Corporation Rule matching in the presence of languages with no types or as an adjunct to current analyses for security vulnerability analysis

Families Citing this family (62)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19654595A1 (en) * 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- and memory bus system for DFPs and modules having a two- or multidimensional programmable cell structures
EP1329816B1 (en) * 1996-12-27 2011-06-22 Richter, Thomas Method for automatic dynamic unloading of data flow processors (dfp) as well as modules with bidimensional or multidimensional programmable cell structures (fpgas, dpgas or the like)
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
DE19861088A1 (en) * 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Repairing integrated circuits by replacing subassemblies with substitutes
CN100355105C (en) * 1999-04-05 2007-12-12 出光兴产株式会社 Organic electroluminescence device and its manufacturing method
CN1378665A (en) * 1999-06-10 2002-11-06 Pact信息技术有限公司 Programming concept
DE50115584D1 (en) * 2000-06-13 2010-09-16 Krass Maren Pipeline ct protocols and communication
US9037807B2 (en) * 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US8686475B2 (en) * 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US7444531B2 (en) * 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US20090210653A1 (en) * 2001-03-05 2009-08-20 Pact Xpp Technologies Ag Method and device for treating and processing data
US7844796B2 (en) * 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US8686549B2 (en) * 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
US7434191B2 (en) * 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US20110161977A1 (en) * 2002-03-21 2011-06-30 Martin Vorbach Method and device for data processing
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
WO2004021176A3 (en) * 2002-08-07 2005-02-03 Pact Xpp Technologies Ag Method and device for processing data
US7266725B2 (en) * 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
EP1483682A2 (en) 2002-01-19 2004-12-08 PACT XPP Technologies AG Reconfigurable processor
EP2043000B1 (en) 2002-02-18 2011-12-21 Richter, Thomas Bus systems and reconfiguration method
US7657861B2 (en) * 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
WO2004038599A1 (en) 2002-09-06 2004-05-06 Pact Xpp Technologies Ag Reconfigurable sequencer structure
JP2006524850A (en) * 2003-04-04 2006-11-02 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフトPACT XPP Technologies AG Data processing method and data processing apparatus
US20070186076A1 (en) * 2003-06-18 2007-08-09 Jones Anthony M Data pipeline transport system
KR20060063800A (en) * 2003-06-18 2006-06-12 앰브릭, 인크. Integrated circuit development system
EP1676208A2 (en) * 2003-08-28 2006-07-05 PACT XPP Technologies AG Data processing device and method
US7620162B2 (en) 2004-08-27 2009-11-17 At&T Intellectual Property I.L.P. Methods, systems and computer program products for monitoring service usage
EP1849095B1 (en) * 2005-02-07 2013-01-02 Richter, Thomas Low latency massive parallel data processing device
US7805708B2 (en) * 2005-05-13 2010-09-28 Texas Instruments Incorporated Automatic tool to eliminate conflict cache misses
WO2007028226A1 (en) * 2005-09-09 2007-03-15 Ibm Canada Limited - Ibm Canada Limitee Method and system for state machine translation
US20080216064A1 (en) * 2005-09-29 2008-09-04 William Braswell Method, Architecture and Software of Meta-Operating System, Operating Systems and Applications For Parallel Computing Platforms
US7711990B1 (en) * 2005-12-13 2010-05-04 Nvidia Corporation Apparatus and method for debugging a graphics processing unit in response to a debug instruction
US7600155B1 (en) * 2005-12-13 2009-10-06 Nvidia Corporation Apparatus and method for monitoring and debugging a graphics processing unit
US8212824B1 (en) 2005-12-19 2012-07-03 Nvidia Corporation Apparatus and method for serial save and restore of graphics processing unit state information
US8250503B2 (en) * 2006-01-18 2012-08-21 Martin Vorbach Hardware definition method including determining whether to implement a function as hardware or software
US9013494B2 (en) 2006-12-07 2015-04-21 Sony Computer Entertainment Inc. Heads-up-display software development tool
US7950003B1 (en) * 2006-12-07 2011-05-24 Sony Computer Entertainment Inc. Heads-up-display software development tool for analyzing and optimizing computer software
US8341612B2 (en) * 2007-05-16 2012-12-25 International Business Machines Corporation Method and apparatus for run-time statistics dependent program execution using source-coding
US7739440B2 (en) * 2007-08-16 2010-06-15 Texas Instruments Incorporated ATA HDD interface for personal media player with increased data transfer throughput
US9015399B2 (en) 2007-08-20 2015-04-21 Convey Computer Multiple data channel memory module architecture
US8156307B2 (en) * 2007-08-20 2012-04-10 Convey Computer Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set
US8561037B2 (en) 2007-08-29 2013-10-15 Convey Computer Compiler for generating an executable comprising instructions for a plurality of different instruction sets
US8122229B2 (en) * 2007-09-12 2012-02-21 Convey Computer Dispatch mechanism for dispatching instructions from a host processor to a co-processor
WO2009062496A1 (en) * 2007-11-17 2009-05-22 Pact Xpp Technologies Ag Reconfigurable floating-point and bit level data processing unit
DE112008003670A5 (en) * 2007-11-28 2010-10-28 Pact Xpp Technologies Ag About Computer
US8402438B1 (en) 2007-12-03 2013-03-19 Cadence Design Systems, Inc. Method and system for generating verification information and tests for software
EP2235627A1 (en) * 2007-12-07 2010-10-06 Krass, Maren Using function calls as compiler directives
US8434076B2 (en) * 2007-12-12 2013-04-30 Oracle International Corporation Efficient compilation and execution of imperative-query languages
US8156474B2 (en) * 2007-12-28 2012-04-10 Cadence Design Systems, Inc. Automation of software verification
US9710384B2 (en) * 2008-01-04 2017-07-18 Micron Technology, Inc. Microprocessor architecture having alternative memory access paths
US8095735B2 (en) * 2008-08-05 2012-01-10 Convey Computer Memory interleave for heterogeneous computing
US8504344B2 (en) * 2008-09-30 2013-08-06 Cadence Design Systems, Inc. Interface between a verification environment and a hardware acceleration engine
US20100115233A1 (en) * 2008-10-31 2010-05-06 Convey Computer Dynamically-selectable vector register partitioning
US8205066B2 (en) * 2008-10-31 2012-06-19 Convey Computer Dynamically configured coprocessor for different extended instruction set personality specific to application program with shared memory storing instructions invisibly dispatched from host processor
US8463820B2 (en) * 2009-05-26 2013-06-11 Intel Corporation System and method for memory bandwidth friendly sorting on multi-core architectures
GB0909192D0 (en) * 2009-05-29 2009-07-15 Vestas Wind Sys As Wind turbine rotor blade having segmented tip
US9086973B2 (en) 2009-06-09 2015-07-21 Hyperion Core, Inc. System and method for a cache in a multi-core processor
US8423745B1 (en) 2009-11-16 2013-04-16 Convey Computer Systems and methods for mapping a neighborhood of data to general registers of a processing element
US8701099B2 (en) * 2010-11-02 2014-04-15 International Business Machines Corporation Accelerating generic loop iterators using speculative execution
JP2016178229A (en) 2015-03-20 2016-10-06 株式会社東芝 Reconfigurable circuit

Citations (203)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6173434B2 (en) *
US10450A (en) * 1854-01-24 Thomas peossbr
US566597A (en) * 1896-08-25 James a
US3564506A (en) * 1968-01-17 1971-02-16 Ibm Instruction retry byte counter
US3681578A (en) * 1969-11-21 1972-08-01 Marconi Co Ltd Fault location and reconfiguration in redundant data processors
US3753008A (en) * 1970-06-20 1973-08-14 Honeywell Inf Systems Memory pre-driver circuit
US3754211A (en) * 1971-12-30 1973-08-21 Ibm Fast error recovery communication controller
US4498172A (en) * 1982-07-26 1985-02-05 General Electric Company System for polynomial division self-testing of digital networks
US4498134A (en) * 1982-01-26 1985-02-05 Hughes Aircraft Company Segregator functional plane for use in a modular array processor
US4566102A (en) * 1983-04-18 1986-01-21 International Business Machines Corporation Parallel-shift error reconfiguration
US4571736A (en) * 1983-10-31 1986-02-18 University Of Southwestern Louisiana Digital communication system employing differential coding and sample robbing
US4646300A (en) * 1983-11-14 1987-02-24 Tandem Computers Incorporated Communications method
US4686386A (en) * 1984-03-21 1987-08-11 Oki Electric Industry Co., Ltd. Power-down circuits for dynamic MOS integrated circuits
US4720778A (en) * 1985-01-31 1988-01-19 Hewlett Packard Company Software debugging analyzer
US4720780A (en) * 1985-09-17 1988-01-19 The Johns Hopkins University Memory-linked wavefront array processor
US4761755A (en) * 1984-07-11 1988-08-02 Prime Computer, Inc. Data processing system and method having an improved arithmetic unit
US4860201A (en) * 1986-09-02 1989-08-22 The Trustees Of Columbia University In The City Of New York Binary tree parallel processor
US4870302A (en) * 1984-03-12 1989-09-26 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US4891810A (en) * 1986-10-31 1990-01-02 Thomson-Csf Reconfigurable computing device
US4901268A (en) * 1988-08-19 1990-02-13 General Electric Company Multiple function data processor
US4959781A (en) * 1988-05-16 1990-09-25 Stardent Computer, Inc. System for assigning interrupts to least busy processor that already loaded same class of interrupt routines
US4992933A (en) * 1986-10-27 1991-02-12 International Business Machines Corporation SIMD array processor with global instruction control and reprogrammable instruction decoders
US5041924A (en) * 1988-11-30 1991-08-20 Quantum Corporation Removable and transportable hard disk subsystem
US5043978A (en) * 1988-09-22 1991-08-27 Siemens Aktiengesellschaft Circuit arrangement for telecommunications exchanges
US5081375A (en) * 1989-01-19 1992-01-14 National Semiconductor Corp. Method for operating a multiple page programmable logic device
US5142469A (en) * 1990-03-29 1992-08-25 Ge Fanuc Automation North America, Inc. Method for converting a programmable logic controller hardware configuration and corresponding control program for use on a first programmable logic controller to use on a second programmable logic controller
US5233539A (en) * 1989-08-15 1993-08-03 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure, input/output structure and configurable logic block
US5237686A (en) * 1989-05-10 1993-08-17 Mitsubishi Denki Kabushiki Kaisha Multiprocessor type time varying image encoding system and image processor with memory bus control table for arbitration priority
USRE34363E (en) * 1984-03-12 1993-08-31 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US5276836A (en) * 1991-01-10 1994-01-04 Hitachi, Ltd. Data processing device with common memory connecting mechanism
US5287472A (en) * 1989-05-02 1994-02-15 Tandem Computers Incorporated Memory system using linear array wafer scale integration architecture
US5287511A (en) * 1988-07-11 1994-02-15 Star Semiconductor Corporation Architectures and methods for dividing processing tasks into tasks for a programmable real time signal processor and tasks for a decision making microprocessor interfacing therewith
US5287532A (en) * 1989-11-14 1994-02-15 Amt (Holdings) Limited Processor elements having multi-byte structure shift register for shifting data either byte wise or bit wise with single-bit output formed at bit positions thereof spaced by one byte
US5336950A (en) * 1991-08-29 1994-08-09 National Semiconductor Corporation Configuration features in a configurable logic array
US5339840A (en) * 1993-04-26 1994-08-23 Sunbelt Precision Products Inc. Adjustable comb
US5343406A (en) * 1989-07-28 1994-08-30 Xilinx, Inc. Distributed memory architecture for a configurable logic array and method for using distributed memory
US5379444A (en) * 1989-07-28 1995-01-03 Hughes Aircraft Company Array of one-bit processors each having only one bit of memory
US5386518A (en) * 1993-02-12 1995-01-31 Hughes Aircraft Company Reconfigurable computer interface and method
US5386154A (en) * 1992-07-23 1995-01-31 Xilinx, Inc. Compact logic cell for field programmable gate array chip
US5392437A (en) * 1992-11-06 1995-02-21 Intel Corporation Method and apparatus for independently stopping and restarting functional units
US5440538A (en) * 1993-09-23 1995-08-08 Massachusetts Institute Of Technology Communication system with redundant links and data bit time multiplexing
US5440245A (en) * 1990-05-11 1995-08-08 Actel Corporation Logic module with configurable combinational and sequential blocks
US5442790A (en) * 1991-05-24 1995-08-15 The Trustees Of Princeton University Optimizing compiler for computers
US5444394A (en) * 1993-07-08 1995-08-22 Altera Corporation PLD with selective inputs from local and global conductors
US5483620A (en) * 1990-05-22 1996-01-09 International Business Machines Corp. Learning machine synapse processor system apparatus
US5485104A (en) * 1985-03-29 1996-01-16 Advanced Micro Devices, Inc. Logic allocator for a programmable logic device
US5485103A (en) * 1991-09-03 1996-01-16 Altera Corporation Programmable logic array with local and global conductors
US5489857A (en) * 1992-08-03 1996-02-06 Advanced Micro Devices, Inc. Flexible synchronous/asynchronous cell structure for a high density programmable logic device
US5491353A (en) * 1989-03-17 1996-02-13 Xilinx, Inc. Configurable cellular array
US5493663A (en) * 1992-04-22 1996-02-20 International Business Machines Corporation Method and apparatus for predetermining pages for swapping from physical memory in accordance with the number of accesses
US5493239A (en) * 1995-01-31 1996-02-20 Motorola, Inc. Circuit and method of configuring a field programmable gate array
US5544336A (en) * 1991-03-19 1996-08-06 Fujitsu Limited Parallel data processing system which efficiently performs matrix and neurocomputer operations, in a negligible data transmission time
US5548773A (en) * 1993-03-30 1996-08-20 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Digital parallel processor array for optimum path planning
US5550782A (en) * 1991-09-03 1996-08-27 Altera Corporation Programmable logic array integrated circuits
US5596742A (en) * 1993-04-02 1997-01-21 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
US5600845A (en) * 1994-07-27 1997-02-04 Metalithic Systems Incorporated Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5600265A (en) * 1986-09-19 1997-02-04 Actel Corporation Programmable interconnect architecture
US5602999A (en) * 1970-12-28 1997-02-11 Hyatt; Gilbert P. Memory system having a plurality of memories, a plurality of detector circuits, and a delay circuit
US5603005A (en) * 1994-12-27 1997-02-11 Unisys Corporation Cache coherency scheme for XBAR storage structure with delayed invalidates until associated write request is executed
US5606698A (en) * 1993-04-26 1997-02-25 Cadence Design Systems, Inc. Method for deriving optimal code schedule sequences from synchronous dataflow graphs
US5649179A (en) * 1995-05-19 1997-07-15 Motorola, Inc. Dynamic instruction allocation for a SIMD processor
US5649176A (en) * 1995-08-10 1997-07-15 Virtual Machine Works, Inc. Transition analysis and circuit resynthesis method and device for digital circuit modeling
US5652529A (en) * 1995-06-02 1997-07-29 International Business Machines Corporation Programmable array clock/reset resource
US5652894A (en) * 1995-09-29 1997-07-29 Intel Corporation Method and apparatus for providing power saving modes to a pipelined processor
US5655069A (en) * 1994-07-29 1997-08-05 Fujitsu Limited Apparatus having a plurality of programmable logic processing units for self-repair
US5655124A (en) * 1992-03-31 1997-08-05 Seiko Epson Corporation Selective power-down for high performance CPU/system
US5656545A (en) * 1996-02-26 1997-08-12 Taiwan Semiconductor Manufacturing Company, Ltd Elimination of tungsten dimple for stacked contact or via application
US5657330A (en) * 1994-11-15 1997-08-12 Mitsubishi Denki Kabushiki Kaisha Single-chip microprocessor with built-in self-testing function
US5656950A (en) * 1995-10-26 1997-08-12 Xilinx, Inc. Interconnect lines including tri-directional buffer circuits
US5659797A (en) * 1991-06-24 1997-08-19 U.S. Philips Corporation Sparc RISC based computer system including a single chip processor with memory management and DMA units coupled to a DRAM interface
US5659785A (en) * 1995-02-10 1997-08-19 International Business Machines Corporation Array processor communication architecture with broadcast processor instructions
US5705938A (en) * 1995-05-02 1998-01-06 Xilinx, Inc. Programmable switch for FPGA input/output signals
US5706482A (en) * 1995-05-31 1998-01-06 Nec Corporation Memory access controller
US5713037A (en) * 1990-11-13 1998-01-27 International Business Machines Corporation Slide bus communication functions for SIMD/MIMD array processor
US5717943A (en) * 1990-11-13 1998-02-10 International Business Machines Corporation Advanced parallel array processor (APAP)
US5717890A (en) * 1991-04-30 1998-02-10 Kabushiki Kaisha Toshiba Method for processing data by utilizing hierarchical cache memories and processing system with the hierarchiacal cache memories
US5778439A (en) * 1995-08-18 1998-07-07 Xilinx, Inc. Programmable logic device with hierarchical confiquration and state storage
US5778237A (en) * 1995-01-10 1998-07-07 Hitachi, Ltd. Data processor and single-chip microcomputer with changing clock frequency and operating voltage
US5781756A (en) * 1994-04-01 1998-07-14 Xilinx, Inc. Programmable logic device with partially configurable memory cells and a method for configuration
US5784630A (en) * 1990-09-07 1998-07-21 Hitachi, Ltd. Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory
US5784636A (en) * 1996-05-28 1998-07-21 National Semiconductor Corporation Reconfigurable computer architecture for use in signal processing applications
US5784313A (en) * 1995-08-18 1998-07-21 Xilinx, Inc. Programmable logic device including configuration data or user data memory slices
US5794059A (en) * 1990-11-13 1998-08-11 International Business Machines Corporation N-dimensional modified hypercube
US5794062A (en) * 1995-04-17 1998-08-11 Ricoh Company Ltd. System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
US5844422A (en) * 1996-11-13 1998-12-01 Xilinx, Inc. State saving and restoration in reprogrammable FPGAs
US5857109A (en) * 1992-11-05 1999-01-05 Giga Operations Corporation Programmable logic device for real time video processing
US5857097A (en) * 1997-03-10 1999-01-05 Digital Equipment Corporation Method for identifying reasons for dynamic stall cycles during the execution of a program
US5859544A (en) * 1996-09-05 1999-01-12 Altera Corporation Dynamic configurable elements for programmable logic devices
US5860119A (en) * 1996-11-25 1999-01-12 Vlsi Technology, Inc. Data-packet fifo buffer system with end-of-packet flags
US5862403A (en) * 1995-02-17 1999-01-19 Kabushiki Kaisha Toshiba Continuous data server apparatus and data transfer scheme enabling multiple simultaneous data accesses
US5867723A (en) * 1992-08-05 1999-02-02 Sarnoff Corporation Advanced massively parallel computer with a secondary storage device coupled through a secondary storage interface
US5867691A (en) * 1992-03-13 1999-02-02 Kabushiki Kaisha Toshiba Synchronizing system between function blocks arranged in hierarchical structures and large scale integrated circuit using the same
US5870620A (en) * 1995-06-01 1999-02-09 Sharp Kabushiki Kaisha Data driven type information processor with reduced instruction execution requirements
US5924119A (en) * 1990-11-30 1999-07-13 Xerox Corporation Consistent packet switched memory bus for shared memory multiprocessors
US5926638A (en) * 1996-01-17 1999-07-20 Nec Corporation Program debugging system for debugging a program having graphical user interface
US5933023A (en) * 1996-09-03 1999-08-03 Xilinx, Inc. FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines
US5933642A (en) * 1995-04-17 1999-08-03 Ricoh Corporation Compiling system and method for reconfigurable computing
US5936424A (en) * 1996-02-02 1999-08-10 Xilinx, Inc. High speed bus with tree structure for selecting bus driver
US5943242A (en) * 1995-11-17 1999-08-24 Pact Gmbh Dynamically reconfigurable data processing system
US5966534A (en) * 1997-06-27 1999-10-12 Cooke; Laurence H. Method for compiling high level programming languages into an integrated processor with reconfigurable logic
US5978583A (en) * 1995-08-07 1999-11-02 International Business Machines Corp. Method for resource control in parallel environments using program organization and run-time support
US6011407A (en) * 1997-06-13 2000-01-04 Xilinx, Inc. Field programmable gate array with dedicated computer bus interface and method for configuring both
US6014509A (en) * 1996-05-20 2000-01-11 Atmel Corporation Field programmable gate array having access to orthogonal and diagonal adjacent neighboring cells
US6021490A (en) * 1996-12-20 2000-02-01 Pact Gmbh Run-time reconfiguration method for programmable units
US6020758A (en) * 1996-03-11 2000-02-01 Altera Corporation Partially reconfigurable programmable logic device
US6020760A (en) * 1997-07-16 2000-02-01 Altera Corporation I/O buffer circuit with pin multiplexing
US6023742A (en) * 1996-07-18 2000-02-08 University Of Washington Reconfigurable computing architecture for providing pipelined data paths
US6023564A (en) * 1996-07-19 2000-02-08 Xilinx, Inc. Data processing system using a flash reconfigurable logic device as a dynamic execution unit for a sequence of instructions
US6026478A (en) * 1997-08-01 2000-02-15 Micron Technology, Inc. Split embedded DRAM processor
US6026481A (en) * 1995-04-28 2000-02-15 Xilinx, Inc. Microprocessor with distributed registers accessible by programmable logic device
US6075935A (en) * 1997-12-01 2000-06-13 Improv Systems, Inc. Method of generating application specific integrated circuits using a programmable hardware architecture
US6077315A (en) * 1995-04-17 2000-06-20 Ricoh Company Ltd. Compiling system and method for partially reconfigurable computing
US6084429A (en) * 1998-04-24 2000-07-04 Xilinx, Inc. PLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arrays
US6085317A (en) * 1997-08-15 2000-07-04 Altera Corporation Reconfigurable computer architecture using programmable logic devices
US6086628A (en) * 1998-02-17 2000-07-11 Lucent Technologies Inc. Power-related hardware-software co-synthesis of heterogeneous distributed embedded systems
US6088795A (en) * 1996-12-27 2000-07-11 Pact Gmbh Process for automatic dynamic reloading of data flow processors (DFPs) and units with two or three-dimensional programmable cell architectures (FPGAs, DPGAs and the like)
US6092174A (en) * 1998-06-01 2000-07-18 Context, Inc. Dynamically reconfigurable distributed integrated circuit processor and method
US6096091A (en) * 1998-02-24 2000-08-01 Advanced Micro Devices, Inc. Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip
US6105106A (en) * 1997-12-31 2000-08-15 Micron Technology, Inc. Computer system, memory device and shift register including a balanced switching circuit with series connected transfer gates which are selectively clocked for fast switching times
US6108760A (en) * 1997-10-31 2000-08-22 Silicon Spice Method and apparatus for position independent reconfiguration in a network of multiple context processing elements
USRE36839E (en) * 1995-02-14 2000-08-29 Philips Semiconductor, Inc. Method and apparatus for reducing power consumption in digital electronic circuits
US6170051B1 (en) * 1997-08-01 2001-01-02 Micron Technology, Inc. Apparatus and method for program level parallelism in a VLIW processor
US6173434B1 (en) * 1996-04-22 2001-01-09 Brigham Young University Dynamically-configurable digital processor using method for relocating logic array modules
US6173419B1 (en) * 1998-05-14 2001-01-09 Advanced Technology Materials, Inc. Field programmable gate array (FPGA) emulator for debugging software
US6172520B1 (en) * 1997-12-30 2001-01-09 Xilinx, Inc. FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA
US6175247B1 (en) * 1998-04-14 2001-01-16 Lockheed Martin Corporation Context switchable field programmable gate array with public-private addressable sharing of intermediate data
US6178494B1 (en) * 1996-09-23 2001-01-23 Virtual Computer Corporation Modular, hybrid processor and method for producing a modular, hybrid processor
US6185256B1 (en) * 1997-11-19 2001-02-06 Fujitsu Limited Signal transmission system using PRD method, receiver circuit for use in the signal transmission system, and semiconductor memory device to which the signal transmission system is applied
US6185731B1 (en) * 1995-04-14 2001-02-06 Mitsubishi Electric Semiconductor Software Co., Ltd. Real time debugger for a microcomputer
US6188650B1 (en) * 1997-10-21 2001-02-13 Sony Corporation Recording and reproducing system having resume function
US6188240B1 (en) * 1998-06-04 2001-02-13 Nec Corporation Programmable function block
US6191614B1 (en) * 1999-04-05 2001-02-20 Xilinx, Inc. FPGA configuration circuit including bus-based CRC register
US6219833B1 (en) * 1997-12-17 2001-04-17 Hewlett-Packard Company Method of using primary and secondary processors
US6256724B1 (en) * 1998-02-04 2001-07-03 Texas Instruments Incorporated Digital signal processor with efficiently connectable hardware co-processor
US6260114B1 (en) * 1997-12-30 2001-07-10 Mcmz Technology Innovations, Llc Computer cache memory windowing
US6260179B1 (en) * 1997-10-23 2001-07-10 Fujitsu Limited Cell arrangement evaluating method, storage medium storing cell arrangement evaluating program, cell arranging apparatus and method, and storage medium storing cell arranging program
US6262908B1 (en) * 1997-01-29 2001-07-17 Elixent Limited Field programmable processor devices
US6266760B1 (en) * 1996-04-11 2001-07-24 Massachusetts Institute Of Technology Intermediate-grain reconfigurable processing device
US20010010074A1 (en) * 2000-01-20 2001-07-26 Fuji Xerox Co., Ltd. Data processing method by programmable logic device, programmable logic device, information processing system and method of reconfiguring circuit in programmable logic
US6279077B1 (en) * 1996-03-22 2001-08-21 Texas Instruments Incorporated Bus interface buffer control in a microprocessor
US6282701B1 (en) * 1997-07-31 2001-08-28 Mutek Solutions, Ltd. System and method for monitoring and analyzing the execution of computer programs
US6282627B1 (en) * 1998-06-29 2001-08-28 Chameleon Systems, Inc. Integrated processor and programmable data path chip for reconfigurable computing
US20010018733A1 (en) * 2000-02-25 2001-08-30 Taro Fujii Array-type processor
US6338106B1 (en) * 1996-12-20 2002-01-08 Pact Gmbh I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
US20020004916A1 (en) * 2000-05-12 2002-01-10 Marchand Patrick R. Methods and apparatus for power control in a scalable array of processor elements
US6339424B1 (en) * 1997-11-18 2002-01-15 Fuji Xerox Co., Ltd Drawing processor
US6341318B1 (en) * 1999-08-10 2002-01-22 Chameleon Systems, Inc. DMA data streaming
US20020013861A1 (en) * 1999-12-28 2002-01-31 Intel Corporation Method and apparatus for low overhead multithreaded communication in a parallel processing environment
US6347346B1 (en) * 1999-06-30 2002-02-12 Chameleon Systems, Inc. Local memory unit system with global access for use on reconfigurable chips
US6349346B1 (en) * 1999-09-23 2002-02-19 Chameleon Systems, Inc. Control fabric unit including associated configuration memory and PSOP state machine adapted to provide configuration address to reconfigurable functional unit
US6421809B1 (en) * 1998-07-24 2002-07-16 Interuniversitaire Micro-Elektronica Centrum (Imec Vzw) Method for determining a storage bandwidth optimized memory organization of an essentially digital device
US6421817B1 (en) * 1997-05-29 2002-07-16 Xilinx, Inc. System and method of computation in a programmable logic device using virtual instructions
US6421808B1 (en) * 1998-04-24 2002-07-16 Cadance Design Systems, Inc. Hardware design language for the design of integrated circuits
US6425054B1 (en) * 1996-08-19 2002-07-23 Samsung Electronics Co., Ltd. Multiprocessor operation in a multimedia signal processor
US6425068B1 (en) * 1996-12-09 2002-07-23 Pact Gmbh Unit for processing numeric and logic operations for use in central processing units (cpus), multiprocessor systems, data-flow processors (dsps), systolic processors and field programmable gate arrays (epgas)
US20020099759A1 (en) * 2001-01-24 2002-07-25 Gootherts Paul David Load balancer with starvation avoidance
US6427156B1 (en) * 1997-01-21 2002-07-30 Xilinx, Inc. Configurable logic block with AND gate for efficient multiplication in FPGAS
US6426649B1 (en) * 2000-12-29 2002-07-30 Quicklogic Corporation Architecture for field programmable gate array
US20020103839A1 (en) * 2001-01-19 2002-08-01 Kunihiko Ozawa Reconfigurable arithmetic device and arithmetic system including that arithmetic device and address generation device and interleave device applicable to arithmetic system
US6430309B1 (en) * 1995-09-15 2002-08-06 Monogen, Inc. Specimen preview and inspection system
US6434695B1 (en) * 1998-12-23 2002-08-13 Apple Computer, Inc. Computer operating system using compressed ROM image in RAM
US6434699B1 (en) * 1998-02-27 2002-08-13 Mosaid Technologies Inc. Encryption processor with shared memory interconnect
US6434642B1 (en) * 1999-10-07 2002-08-13 Xilinx, Inc. FIFO memory system and method with improved determination of full and empty conditions and amount of data stored
US6437441B1 (en) * 1997-07-10 2002-08-20 Kawasaki Microelectronics, Inc. Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure
US6438747B1 (en) * 1999-08-20 2002-08-20 Hewlett-Packard Company Programmatic iteration scheduling for parallel processors
US6438737B1 (en) * 2000-02-15 2002-08-20 Intel Corporation Reconfigurable logic for a computer
US6496971B1 (en) * 2000-02-07 2002-12-17 Xilinx, Inc. Supporting multiple FPGA configuration modes using dedicated on-chip processor
US20030001615A1 (en) * 2001-06-29 2003-01-02 Semiconductor Technology Academic Research Center Programmable logic circuit device having look up table enabling to reduce implementation area
US6504398B1 (en) * 1999-05-25 2003-01-07 Actel Corporation Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure
US6507947B1 (en) * 1999-08-20 2003-01-14 Hewlett-Packard Company Programmatic synthesis of processor element arrays
US6507898B1 (en) * 1997-04-30 2003-01-14 Canon Kabushiki Kaisha Reconfigurable data cache controller
US6519674B1 (en) * 2000-02-18 2003-02-11 Chameleon Systems, Inc. Configuration bits layout
US6518787B1 (en) * 2000-09-21 2003-02-11 Triscend Corporation Input/output architecture for efficient configuration of programmable input/output cells
US6523107B1 (en) * 1997-12-17 2003-02-18 Elixent Limited Method and apparatus for providing instruction streams to a processing device
US6525678B1 (en) * 2000-10-06 2003-02-25 Altera Corporation Configuring a programmable logic device
US6526520B1 (en) * 1997-02-08 2003-02-25 Pact Gmbh Method of self-synchronization of configurable elements of a programmable unit
US6539438B1 (en) * 1999-01-15 2003-03-25 Quickflex Inc. Reconfigurable computing system and method and apparatus employing same
US6587939B1 (en) * 1999-01-13 2003-07-01 Kabushiki Kaisha Toshiba Information processing apparatus provided with an optimized executable instruction extracting unit for extending compressed instructions
US20030123579A1 (en) * 2001-11-16 2003-07-03 Saeid Safavi Viterbi convolutional coding method and apparatus
US20030135686A1 (en) * 1997-02-11 2003-07-17 Martin Vorbach Internal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity
US20030154349A1 (en) * 2002-01-24 2003-08-14 Berg Stefan G. Program-directed cache prefetching for media processors
US6681388B1 (en) * 1998-10-02 2004-01-20 Real World Computing Partnership Method and compiler for rearranging array data into sub-arrays of consecutively-addressed elements for distribution processing
US20040015899A1 (en) * 2000-10-06 2004-01-22 Frank May Method for processing data
US6687788B2 (en) * 1998-02-25 2004-02-03 Pact Xpp Technologies Ag Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.)
US20040025005A1 (en) * 2000-06-13 2004-02-05 Martin Vorbach Pipeline configuration unit protocols and communication
US6694434B1 (en) * 1998-12-23 2004-02-17 Entrust Technologies Limited Method and apparatus for controlling program execution and program distribution
US6697979B1 (en) * 1997-12-22 2004-02-24 Pact Xpp Technologies Ag Method of repairing integrated circuits
US6757892B1 (en) * 1999-06-24 2004-06-29 Sarnoff Corporation Method for determining an optimal partitioning of data among several memories
US6782445B1 (en) * 1999-06-15 2004-08-24 Hewlett-Packard Development Company, L.P. Memory and instructions in computer architecture containing processor and coprocessor
US6785826B1 (en) * 1996-07-17 2004-08-31 International Business Machines Corporation Self power audit and control circuitry for microprocessor functional units
US6847370B2 (en) * 2001-02-20 2005-01-25 3D Labs, Inc., Ltd. Planar byte memory organization with linear access
US6871341B1 (en) * 2000-03-24 2005-03-22 Intel Corporation Adaptive scheduling of function cells in dynamic reconfigurable logic
US6928523B2 (en) * 2000-07-25 2005-08-09 Renesas Technology Corp. Synchronous signal producing circuit for controlling a data ready signal indicative of end of access to a shared memory and thereby controlling synchronization between processor and coprocessor
US7000161B1 (en) * 2001-10-15 2006-02-14 Altera Corporation Reconfigurable programmable logic system with configuration recovery mode
US20060036988A1 (en) * 2001-06-12 2006-02-16 Altera Corporation Methods and apparatus for implementing parameterizable processors and peripherals
US7007096B1 (en) * 1999-05-12 2006-02-28 Microsoft Corporation Efficient splitting and mixing of streaming-data frames for processing through multiple processing modules
US7164422B1 (en) * 2000-07-28 2007-01-16 Ab Initio Software Corporation Parameterized graphs with conditional components
US7249351B1 (en) * 2000-08-30 2007-07-24 Broadcom Corporation System and method for preparing software for execution in a dynamically configurable hardware environment
US7254649B2 (en) * 2000-01-28 2007-08-07 Infineon Technologies Ag Wireless spread spectrum communication platform using dynamically reconfigurable logic
US7266725B2 (en) * 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
US20090193384A1 (en) * 2008-01-25 2009-07-30 Mihai Sima Shift-enabled reconfigurable device
US7759968B1 (en) * 2006-09-27 2010-07-20 Xilinx, Inc. Method of and system for verifying configuration data
US7873811B1 (en) * 2003-03-10 2011-01-18 The United States Of America As Represented By The United States Department Of Energy Polymorphous computing fabric

Family Cites Families (303)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2067477A (en) * 1931-03-20 1937-01-12 Allis Chalmers Mfg Co Gearing
GB971191A (en) * 1962-05-28 1964-09-30 Wolf Electric Tools Ltd Improvements relating to electrically driven equipment
DE2057312A1 (en) 1970-11-21 1972-05-25 Bhs Bayerische Berg Planetary gear with load pressure compensation
US3855577A (en) 1973-06-11 1974-12-17 Texas Instruments Inc Power saving circuit for calculator system
US4233667A (en) 1978-10-23 1980-11-11 International Business Machines Corporation Demand powered programmable logic array
US4442508A (en) 1981-08-05 1984-04-10 General Instrument Corporation Storage cells for use in two conductor data column storage logic arrays
US4590583A (en) 1982-07-16 1986-05-20 At&T Bell Laboratories Coin telephone measurement circuitry
US4667190A (en) 1982-07-30 1987-05-19 Honeywell Inc. Two axis fast access memory
JPH0222423B2 (en) 1982-08-25 1990-05-18 Nippon Electric Co
US4663706A (en) 1982-10-28 1987-05-05 Tandem Computers Incorporated Multiprocessor multisystem communications network
US4739474A (en) 1983-03-10 1988-04-19 Martin Marietta Corporation Geometric-arithmetic parallel processor
US5123109A (en) 1983-05-31 1992-06-16 Thinking Machines Corporation Parallel processor including a processor array with plural data transfer arrangements including (1) a global router and (2) a proximate-neighbor transfer system
US4682284A (en) 1984-12-06 1987-07-21 American Telephone & Telegraph Co., At&T Bell Lab. Queue administration method and apparatus
EP0190813B1 (en) 1985-01-29 1991-09-18 Secretary of State for Defence in Her Britannic Majesty's Gov. of the United Kingdom of Great Britain and Northern Ireland Processing cell for fault tolerant arrays
US5023775A (en) 1985-02-14 1991-06-11 Intel Corporation Software programmable logic array utilizing "and" and "or" gates
US5247689A (en) 1985-02-25 1993-09-21 Ewert Alfred P Parallel digital processor including lateral transfer buses with interrupt switches to form bus interconnection segments
US4706216A (en) 1985-02-27 1987-11-10 Xilinx, Inc. Configurable logic element
US5015884A (en) 1985-03-29 1991-05-14 Advanced Micro Devices, Inc. Multiple array high performance programmable logic device family
US4972314A (en) 1985-05-20 1990-11-20 Hughes Aircraft Company Data flow signal processor method and apparatus
US4967340A (en) 1985-06-12 1990-10-30 E-Systems, Inc. Adaptive processing system having an array of individually configurable processing components
GB8517376D0 (en) 1985-07-09 1985-08-14 Jesshope C R Processor array
DE3687400T2 (en) 1985-11-04 1993-07-15 Ibm nachrichtenuebertragungsnetzwerke digital and construction of uebertragungswegen in these networks.
US4852048A (en) 1985-12-12 1989-07-25 Itt Corporation Single instruction multiple data (SIMD) cellular array processing apparatus employing a common bus where a first number of bits manifest a first bus portion and a second number of bits manifest a second bus portion
US5021947A (en) 1986-03-31 1991-06-04 Hughes Aircraft Company Data-flow multiprocessor architecture with three dimensional multistage interconnection network for efficient signal and data processing
US4882687A (en) 1986-03-31 1989-11-21 Schlumberger Technology Corporation Pixel processor
US5034914A (en) 1986-05-15 1991-07-23 Aquidneck Systems International, Inc. Optical disk data storage method and apparatus with buffered interface
GB8612396D0 (en) 1986-05-21 1986-06-25 Hewlett Packard Ltd Chain-configured interface bus system
US4910665A (en) * 1986-09-02 1990-03-20 General Electric Company Distributed processing system including reconfigurable elements
US4884231A (en) 1986-09-26 1989-11-28 Performance Semiconductor Corporation Microprocessor system with extended arithmetic logic unit
US4918440A (en) 1986-11-07 1990-04-17 Furtek Frederick C Programmable logic cell and array
US4811214A (en) * 1986-11-14 1989-03-07 Princeton University Multinode reconfigurable pipeline computer
US5226122A (en) 1987-08-21 1993-07-06 Compaq Computer Corp. Programmable logic system for filtering commands to a microprocessor
CA1299757C (en) 1987-08-28 1992-04-28 Brent Cameron Beardsley Device initiated partial system quiescing
US5115510A (en) 1987-10-20 1992-05-19 Sharp Kabushiki Kaisha Multistage data flow processor with instruction packet, fetch, storage transmission and address generation controlled by destination information
US4918690A (en) 1987-11-10 1990-04-17 Echelon Systems Corp. Network and intelligent cell for providing sensing, bidirectional communications and control
US5113498A (en) 1987-11-10 1992-05-12 Echelon Corporation Input/output section for an intelligent cell which provides sensing, bidirectional communications and control
USRE34444E (en) 1988-01-13 1993-11-16 Xilinx, Inc. Programmable logic device
US5303172A (en) 1988-02-16 1994-04-12 Array Microsystems Pipelined combination and vector signal processor
JPH06101043B2 (en) 1988-06-30 1994-12-12 三菱電機株式会社 Micro computer
US5010401A (en) 1988-08-11 1991-04-23 Mitsubishi Denki Kabushiki Kaisha Picture coding and decoding apparatus using vector quantization
US5204935A (en) 1988-08-19 1993-04-20 Fuji Xerox Co., Ltd. Programmable fuzzy logic circuits
US5353432A (en) 1988-09-09 1994-10-04 Compaq Computer Corporation Interactive method for configuration of computer system and circuit boards with user specification of system resources and computer resolution of resource conflicts
DE68926783D1 (en) 1988-10-07 1996-08-08 Martin Marietta Corp Parallel data processor
US5014193A (en) 1988-10-14 1991-05-07 Compaq Computer Corporation Dynamically configurable portable computer system
US5136717A (en) 1988-11-23 1992-08-04 Flavors Technology Inc. Realtime systolic, multiple-instruction, single-data parallel computer system
US5109503A (en) 1989-05-22 1992-04-28 Ge Fanuc Automation North America, Inc. Apparatus with reconfigurable counter includes memory for storing plurality of counter configuration files which respectively define plurality of predetermined counters
JP2584673B2 (en) 1989-06-09 1997-02-26 株式会社日立製作所 Logic tester having a test data changing circuit
US5212652A (en) 1989-08-15 1993-05-18 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure
US5128559A (en) 1989-09-29 1992-07-07 Sgs-Thomson Microelectronics, Inc. Logic block for programmable logic devices
JP2968289B2 (en) 1989-11-08 1999-10-25 株式会社リコー Central processing unit
GB8925721D0 (en) 1989-11-14 1990-01-04 Amt Holdings Processor array system
US5522083A (en) 1989-11-17 1996-05-28 Texas Instruments Incorporated Reconfigurable multi-processor operating in SIMD mode with one processor fetching instructions for use by remaining processors
DE58908974D1 (en) 1989-11-21 1995-03-16 Itt Ind Gmbh Deutsche Data-controlled array processor.
US5099447A (en) * 1990-01-22 1992-03-24 Alliant Computer Systems Corporation Blocked matrix multiplication for computers with hierarchical memory
US5125801A (en) 1990-02-02 1992-06-30 Isco, Inc. Pumping system
EP0463721A3 (en) 1990-04-30 1993-06-16 Gennum Corporation Digital signal processing device
US5193202A (en) * 1990-05-29 1993-03-09 Wavetracer, Inc. Processor array with relocated operand physical address generator capable of data transfer to distant physical processor for each virtual processor while simulating dimensionally larger array processor
US5111079A (en) 1990-06-29 1992-05-05 Sgs-Thomson Microelectronics, Inc. Power reduction circuit for programmable logic device
DE69107460D1 (en) 1990-08-02 1995-03-23 Carlstedt Elektronik Ab Associative memory.
US5274593A (en) 1990-09-28 1993-12-28 Intergraph Corporation High speed redundant rows and columns for semiconductor memories
US5076482A (en) 1990-10-05 1991-12-31 The Fletcher Terry Company Pneumatic point driver
US5144166A (en) 1990-11-02 1992-09-01 Concurrent Logic, Inc. Programmable logic cell and array
DE69131272T2 (en) 1990-11-13 1999-12-09 Ibm Parallel associative processor system
US5625836A (en) 1990-11-13 1997-04-29 International Business Machines Corporation SIMD/MIMD processing memory element (PME)
US5734921A (en) * 1990-11-13 1998-03-31 International Business Machines Corporation Advanced parallel array processor computer package
US5588152A (en) 1990-11-13 1996-12-24 International Business Machines Corporation Advanced parallel processor including advanced support hardware
US5765011A (en) 1990-11-13 1998-06-09 International Business Machines Corporation Parallel processing system having a synchronous SIMD processing with processing elements emulating SIMD operation using individual instruction streams
US5301284A (en) 1991-01-16 1994-04-05 Walker-Estes Corporation Mixed-resolution, N-dimensional object space method and apparatus
US5301344A (en) 1991-01-29 1994-04-05 Analogic Corporation Multibus sequential processor to perform in parallel a plurality of reconfigurable logic operations on a plurality of data sets
US5212716A (en) 1991-02-05 1993-05-18 International Business Machines Corporation Data edge phase sorting circuits
US5218302A (en) 1991-02-06 1993-06-08 Sun Electric Corporation Interface for coupling an analyzer to a distributorless ignition system
JPH07168610A (en) 1991-02-22 1995-07-04 Siemens Ag Memory programmable controller and operation method therefor
JPH04293151A (en) 1991-03-20 1992-10-16 Fujitsu Ltd Parallel data processing system
US5617547A (en) 1991-03-29 1997-04-01 International Business Machines Corporation Switch network extension of bus architecture
WO1992018935A1 (en) 1991-04-09 1992-10-29 Fujitsu Limited Data processor and data processing method
US5551033A (en) 1991-05-17 1996-08-27 Zenith Data Systems Corporation Apparatus for maintaining one interrupt mask register in conformity with another in a manner invisible to an executing program
JP3259969B2 (en) 1991-07-09 2002-02-25 株式会社東芝 Cache memory controller
US5347639A (en) 1991-07-15 1994-09-13 International Business Machines Corporation Self-parallelizing computer system and method
US5581731A (en) 1991-08-30 1996-12-03 King; Edward C. Method and apparatus for managing video data for faster access by selectively caching video data
FR2681791B1 (en) * 1991-09-27 1994-05-06 Salomon Sa Device vibration damping golf club.
CA2073516A1 (en) 1991-11-27 1993-05-28 Peter Michael Kogge Dynamic multi-mode parallel processor array architecture computer system
WO1993011503A1 (en) 1991-12-06 1993-06-10 Norman Richard S Massively-parallel direct output processor array
US5208491A (en) 1992-01-07 1993-05-04 Washington Research Foundation Field programmable gate array
FR2686175B1 (en) 1992-01-14 1996-12-20 Andre Thepaut multiprocessor data processing system.
US5412795A (en) 1992-02-25 1995-05-02 Micral, Inc. State machine having a variable timing mechanism for varying the duration of logical output states of the state machine based on variation in the clock frequency
US5611049A (en) * 1992-06-03 1997-03-11 Pitts; William M. System for accessing distributed data cache channel at each network node to pass requests and data
WO1993024895A3 (en) 1992-06-04 1994-02-17 Xilinx Inc Timing driven method for laying out a user's circuit onto a programmable integrated circuit device
DE4221278C2 (en) 1992-06-29 1996-02-29 Martin Vorbach Busgekoppeltes multicomputer system
US5475803A (en) 1992-07-10 1995-12-12 Lsi Logic Corporation Method for 2-D affine transformation of images
JP3032382B2 (en) 1992-07-13 2000-04-17 シャープ株式会社 Sampling frequency converting apparatus of the digital signal
US5590348A (en) 1992-07-28 1996-12-31 International Business Machines Corporation Status predictor for combined shifter-rotate/merge unit
US5802290A (en) 1992-07-29 1998-09-01 Virtual Computer Corporation Computer network of distributed virtual computers which are EAC reconfigurable in response to instruction to be executed
DE69332901T2 (en) 1992-09-03 2004-01-29 Sony Corp Data recording apparatus and method
US5425036A (en) 1992-09-18 1995-06-13 Quickturn Design Systems, Inc. Method and apparatus for debugging reconfigurable emulation systems
JPH06180653A (en) 1992-10-02 1994-06-28 Hudson Soft Co Ltd Interruption processing method and device therefor
GB9223226D0 (en) 1992-11-05 1992-12-16 Algotronix Ltd Improved configurable cellular array (cal ii)
US5497498A (en) * 1992-11-05 1996-03-05 Giga Operations Corporation Video processing module using a second programmable logic device which reconfigures a first programmable logic device for data transformation
US5361373A (en) 1992-12-11 1994-11-01 Gilson Kent L Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5311079A (en) 1992-12-17 1994-05-10 Ditlow Gary S Low power, high performance PLA
US5428526A (en) 1993-02-03 1995-06-27 Flood; Mark A. Programmable controller with time periodic communication
GB9303084D0 (en) 1993-02-16 1993-03-31 Inmos Ltd Programmable logic circuit
JPH06276086A (en) 1993-03-18 1994-09-30 Fuji Xerox Co Ltd Field programmable gate array
US5761484A (en) 1994-04-01 1998-06-02 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
US5418953A (en) 1993-04-12 1995-05-23 Loral/Rohm Mil-Spec Corp. Method for automated deployment of a software program onto a multi-processor architecture
US5473266A (en) 1993-04-19 1995-12-05 Altera Corporation Programmable logic device having fast programmable logic array blocks and a central global interconnect array
DE4416881C2 (en) 1993-05-13 1998-03-19 Pact Inf Tech Gmbh A method of operating a data processing device
US5349193A (en) 1993-05-20 1994-09-20 Princeton Gamma Tech, Inc. Highly sensitive nuclear spectrometer apparatus and method
EP0628917B1 (en) 1993-06-11 2000-05-03 Elsag Spa Multiprocessor system
JPH0736858A (en) 1993-07-21 1995-02-07 Hitachi Ltd Signal processor
US5457644A (en) 1993-08-20 1995-10-10 Actel Corporation Field programmable digital signal processing array integrated circuit
GB2282244B (en) 1993-09-23 1998-01-14 Advanced Risc Mach Ltd Integrated circuit
US6219688B1 (en) 1993-11-30 2001-04-17 Texas Instruments Incorporated Method, apparatus and system for sum of plural absolute differences
US5455525A (en) 1993-12-06 1995-10-03 Intelligent Logic Systems, Inc. Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array
US5535406A (en) 1993-12-29 1996-07-09 Kolchinsky; Alexander Virtual processor module including a reconfigurable programmable matrix
US5680583A (en) 1994-02-16 1997-10-21 Arkos Design, Inc. Method and apparatus for a trace buffer in an emulation system
CN1104683C (en) 1994-03-22 2003-04-02 海珀奇普公司 Efficient direct cell replacement fault tolerant structure support completely integrated system with means of direct communication with system operator
US5561738A (en) 1994-03-25 1996-10-01 Motorola, Inc. Data processor for executing a fuzzy logic operation and method therefor
US5430687A (en) 1994-04-01 1995-07-04 Xilinx, Inc. Programmable logic device including a parallel input device for loading memory cells
US5896551A (en) * 1994-04-15 1999-04-20 Micron Technology, Inc. Initializing and reprogramming circuitry for state independent memory array burst operations control
US5426378A (en) 1994-04-20 1995-06-20 Xilinx, Inc. Programmable logic device which stores more than one configuration and means for switching configurations
JP2671804B2 (en) 1994-05-27 1997-11-05 日本電気株式会社 Hierarchical resource management method
US5532693A (en) 1994-06-13 1996-07-02 Advanced Hardware Architectures Adaptive data compression system with systolic string matching logic
EP0690378A1 (en) 1994-06-30 1996-01-03 Tandem Computers Incorporated Tool and method for diagnosing and correcting errors in a computer programm
JP3308770B2 (en) 1994-07-22 2002-07-29 三菱電機株式会社 The calculation method in an information processing apparatus and an information processing apparatus
US5574930A (en) 1994-08-12 1996-11-12 University Of Hawaii Computer system and method using functional memory
US5513366A (en) 1994-09-28 1996-04-30 International Business Machines Corporation Method and system for dynamically reconfiguring a register file in a vector processor
EP0707269A1 (en) 1994-10-11 1996-04-17 International Business Machines Corporation Cache coherence network for a multiprocessor data processing system
US5530946A (en) 1994-10-28 1996-06-25 Dell Usa, L.P. Processor failure detection and recovery circuit in a dual processor computer system and method of operation thereof
US5815726A (en) 1994-11-04 1998-09-29 Altera Corporation Coarse-grained look-up table architecture
EP0721157A1 (en) 1994-12-12 1996-07-10 Advanced Micro Devices Inc. Microprocessor with selectable clock frequency
US5537580A (en) 1994-12-21 1996-07-16 Vlsi Technology, Inc. Integrated circuit fabrication using state machine extraction from behavioral hardware description language
US5532957A (en) 1995-01-31 1996-07-02 Texas Instruments Incorporated Field reconfigurable logic/memory array
US5742180A (en) 1995-02-10 1998-04-21 Massachusetts Institute Of Technology Dynamically programmable gate array with multiple contexts
US6052773A (en) 1995-02-10 2000-04-18 Massachusetts Institute Of Technology DPGA-coupled microprocessors
US5537057A (en) 1995-02-14 1996-07-16 Altera Corporation Programmable logic array device with grouped logic regions and three types of conductors
US5892961A (en) 1995-02-17 1999-04-06 Xilinx, Inc. Field programmable gate array having programming instructions in the configuration bitstream
US5675743A (en) 1995-02-22 1997-10-07 Callisto Media Systems Inc. Multi-media server
US5757207A (en) 1995-03-22 1998-05-26 Altera Corporation Programmable logic array integrated circuit incorporating a first-in first-out memory
US5570040A (en) 1995-03-22 1996-10-29 Altera Corporation Programmable logic array integrated circuit incorporating a first-in first-out memory
US5748979A (en) 1995-04-05 1998-05-05 Xilinx Inc Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page table
US5752035A (en) * 1995-04-05 1998-05-12 Xilinx, Inc. Method for compiling and executing programs for reprogrammable instruction set accelerator
US5541530A (en) 1995-05-17 1996-07-30 Altera Corporation Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks
US5821774A (en) 1995-05-26 1998-10-13 Xilinx, Inc. Structure and method for arithmetic function implementation in an EPLD having high speed product term allocation structure
US5671432A (en) 1995-06-02 1997-09-23 International Business Machines Corporation Programmable array I/O-routing resource
US5646544A (en) 1995-06-05 1997-07-08 International Business Machines Corporation System and method for dynamically reconfiguring a programmable gate array
US5815715A (en) 1995-06-05 1998-09-29 Motorola, Inc. Method for designing a product having hardware and software components and product therefor
US5889982A (en) * 1995-07-01 1999-03-30 Intel Corporation Method and apparatus for generating event handler vectors based on both operating mode and event type
US5559450A (en) 1995-07-27 1996-09-24 Lucent Technologies Inc. Field programmable gate array with multi-port RAM
US5996083A (en) 1995-08-11 1999-11-30 Hewlett-Packard Company Microprocessor having software controllable power consumption
GB9516877D0 (en) 1995-08-17 1995-10-18 Austin Kenneth Re-configurable application specific device
US5583450A (en) 1995-08-18 1996-12-10 Xilinx, Inc. Sequencer for a time multiplexed programmable logic device
US5646545A (en) 1995-08-18 1997-07-08 Xilinx, Inc. Time multiplexed programmable logic device
US5737565A (en) 1995-08-24 1998-04-07 International Business Machines Corporation System and method for diallocating stream from a stream buffer
US5737516A (en) 1995-08-30 1998-04-07 Motorola, Inc. Data processing system for performing a debug function and method therefor
US5745734A (en) 1995-09-29 1998-04-28 International Business Machines Corporation Method and system for programming a gate array using a compressed configuration bit stream
US5754827A (en) 1995-10-13 1998-05-19 Mentor Graphics Corporation Method and apparatus for performing fully visible tracing of an emulation
US5633830A (en) 1995-11-08 1997-05-27 Altera Corporation Random access memory block circuitry for programmable logic array integrated circuit devices
US5732209A (en) * 1995-11-29 1998-03-24 Exponential Technology, Inc. Self-testing multi-processor die with internal compare points
US5773994A (en) 1995-12-15 1998-06-30 Cypress Semiconductor Corp. Method and apparatus for implementing an internal tri-state bus within a programmable logic circuit
JPH09231788A (en) 1995-12-19 1997-09-05 Fujitsu Ltd Shift register and programmable logic circuit and programmable logic circuit system
JP3247043B2 (en) 1996-01-12 2002-01-15 株式会社日立製作所 The information processing system and logic lsi performing fault detection in internal signal
US5760602A (en) 1996-01-17 1998-06-02 Hewlett-Packard Company Time multiplexing a plurality of configuration settings of a programmable switch element in a FPGA
US5854918A (en) 1996-01-24 1998-12-29 Ricoh Company Ltd. Apparatus and method for self-timed algorithmic execution
US5754459A (en) 1996-02-08 1998-05-19 Xilinx, Inc. Multiplier circuit design for a programmable logic device
KR0165515B1 (en) * 1996-02-17 1999-01-15 김광호 Fifo method and apparatus of graphic data
GB9604496D0 (en) 1996-03-01 1996-05-01 Xilinx Inc Embedded memory for field programmable gate array
US5841973A (en) 1996-03-13 1998-11-24 Cray Research, Inc. Messaging in distributed memory multiprocessing system having shell circuitry for atomic control of message storage queue's tail pointer structure in local memory
US6311265B1 (en) 1996-03-25 2001-10-30 Torrent Systems, Inc. Apparatuses and methods for programming parallel computers
US5960200A (en) 1996-05-03 1999-09-28 I-Cube System to transition an enterprise to a distributed infrastructure
EP0978051A1 (en) * 1996-06-21 2000-02-09 Mirage Technologies, Inc. Dynamically reconfigurable hardware system for real-time control of processes
US5892370A (en) 1996-06-21 1999-04-06 Quicklogic Corporation Clock network for field programmable gate array
US5838165A (en) 1996-08-21 1998-11-17 Chatter; Mukesh High performance self modifying on-the-fly alterable logic FPGA, architecture and method
US5828858A (en) 1996-09-16 1998-10-27 Virginia Tech Intellectual Properties, Inc. Worm-hole run-time reconfigurable processor field programmable gate array (FPGA)
US5694602A (en) 1996-10-01 1997-12-02 The United States Of America As Represented By The Secretary Of The Air Force Weighted system and method for spatial allocation of a parallel load
US6004477A (en) 1996-10-14 1999-12-21 Mitsubishi Gas Chemical Company, Inc. Oxygen absorption composition
US5901279A (en) 1996-10-18 1999-05-04 Hughes Electronics Corporation Connection of spares between multiple programmable devices
US6247147B1 (en) 1997-10-27 2001-06-12 Altera Corporation Enhanced embedded logic analyzer
US5892962A (en) 1996-11-12 1999-04-06 Lucent Technologies Inc. FPGA-based processor
US6005410A (en) 1996-12-05 1999-12-21 International Business Machines Corporation Interconnect structure between heterogeneous core regions in a programmable array
DE19654595A1 (en) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- and memory bus system for DFPs and modules having a two- or multidimensional programmable cell structures
EP0858168A1 (en) 1997-01-29 1998-08-12 Hewlett-Packard Company Field programmable processor array
DE19704044A1 (en) * 1997-02-04 1998-08-13 Pact Inf Tech Gmbh Address generation with systems having programmable modules
US5865239A (en) * 1997-02-05 1999-02-02 Micropump, Inc. Method for making herringbone gears
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US6150837A (en) 1997-02-28 2000-11-21 Actel Corporation Enhanced field programmable gate array
US5927423A (en) 1997-03-05 1999-07-27 Massachusetts Institute Of Technology Reconfigurable footprint mechanism for omnidirectional vehicles
US5884075A (en) * 1997-03-10 1999-03-16 Compaq Computer Corporation Conflict resolution using self-contained virtual devices
US6125408A (en) 1997-03-10 2000-09-26 Compaq Computer Corporation Resource type prioritization in generating a device configuration
US6389379B1 (en) 1997-05-02 2002-05-14 Axis Systems, Inc. Converification system and method
US6321366B1 (en) 1997-05-02 2001-11-20 Axis Systems, Inc. Timing-insensitive glitch-free logic system and method
US6035371A (en) * 1997-05-28 2000-03-07 3Com Corporation Method and apparatus for addressing a static random access memory device based on signals for addressing a dynamic memory access device
US6047115A (en) 1997-05-29 2000-04-04 Xilinx, Inc. Method for configuring FPGA memory planes for virtual hardware computation
US5946712A (en) 1997-06-04 1999-08-31 Oak Technology, Inc. Apparatus and method for reading data from synchronous memory
US6240502B1 (en) 1997-06-25 2001-05-29 Sun Microsystems, Inc. Apparatus for dynamically reconfiguring a processor
US5970254A (en) 1997-06-27 1999-10-19 Cooke; Laurence H. Integrated processor and programmable data path chip for reconfigurable computing
US6038656A (en) * 1997-09-12 2000-03-14 California Institute Of Technology Pipelined completion for asynchronous communication
US7152027B2 (en) 1998-02-17 2006-12-19 National Instruments Corporation Reconfigurable test system
JP3612186B2 (en) 1997-09-19 2005-01-19 株式会社ルネサステクノロジ Data processing equipment
US6539415B1 (en) 1997-09-24 2003-03-25 Sony Corporation Method and apparatus for the allocation of audio/video tasks in a network system
US5966143A (en) 1997-10-14 1999-10-12 Motorola, Inc. Data allocation into multiple memories for concurrent access
US6076157A (en) 1997-10-23 2000-06-13 International Business Machines Corporation Method and apparatus to force a thread switch in a multithreaded processor
US6122719A (en) 1997-10-31 2000-09-19 Silicon Spice Method and apparatus for retiming in a network of multiple context processing elements
US5915123A (en) 1997-10-31 1999-06-22 Silicon Spice Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements
US6127908A (en) 1997-11-17 2000-10-03 Massachusetts Institute Of Technology Microelectro-mechanical system actuator device and reconfigurable circuits utilizing same
US6212650B1 (en) 1997-11-24 2001-04-03 Xilinx, Inc. Interactive dubug tool for programmable circuits
US6091263A (en) 1997-12-12 2000-07-18 Xilinx, Inc. Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM
DE69827589D1 (en) * 1997-12-17 2004-12-23 Elixent Ltd establish configurable processing arrangement and method for use of this arrangement to a central processing unit
DE69834942D1 (en) 1997-12-17 2006-07-27 Elixent Ltd Multiplier in field programmable arrays
US6049222A (en) 1997-12-30 2000-04-11 Xilinx, Inc Configuring an FPGA using embedded memory
US6301706B1 (en) 1997-12-31 2001-10-09 Elbrus International Limited Compiler method and apparatus for elimination of redundant speculative computations from innermost loops
US6216223B1 (en) 1998-01-12 2001-04-10 Billions Of Operations Per Second, Inc. Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor
US6034538A (en) * 1998-01-21 2000-03-07 Lucent Technologies Inc. Virtual logic system for reconfigurable hardware
WO1999038071A1 (en) 1998-01-26 1999-07-29 Chameleon Systems, Inc. Reconfigurable logic for table lookup
US6230307B1 (en) 1998-01-26 2001-05-08 Xilinx, Inc. System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects
US6198304B1 (en) * 1998-02-23 2001-03-06 Xilinx, Inc. Programmable logic device
US6154049A (en) 1998-03-27 2000-11-28 Xilinx, Inc. Multiplier fabric for use in field programmable gate arrays
US6374286B1 (en) 1998-04-06 2002-04-16 Rockwell Collins, Inc. Real time processor capable of concurrently running multiple independent JAVA machines
US5999990A (en) 1998-05-18 1999-12-07 Motorola, Inc. Communicator having reconfigurable resources
US6202182B1 (en) 1998-06-30 2001-03-13 Lucent Technologies Inc. Method and apparatus for testing field programmable gate arrays
DE69803373T2 (en) 1998-07-06 2002-08-14 Hewlett Packard Co Wiring of cells in logical fields
DE19835189C2 (en) 1998-08-04 2001-02-08 Unicor Rohrsysteme Gmbh An apparatus for continuously producing seamless plastic pipes
US6137307A (en) 1998-08-04 2000-10-24 Xilinx, Inc. Structure and method for loading wide frames of data from a narrow input bus
US6205458B1 (en) 1998-09-21 2001-03-20 Rn2R, L.L.C. Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith
US6215326B1 (en) 1998-11-18 2001-04-10 Altera Corporation Programmable logic device architecture with super-regions having logic regions and a memory region
DE69910826T2 (en) 1998-11-20 2004-06-17 Altera Corp., San Jose Computer system having a reconfigurable programmable logic device
US6977649B1 (en) 1998-11-23 2005-12-20 3Dlabs, Inc. Ltd 3D graphics rendering with selective read suspend
US6044030A (en) * 1998-12-21 2000-03-28 Philips Electronics North America Corporation FIFO unit with single pointer
US6757847B1 (en) 1998-12-29 2004-06-29 International Business Machines Corporation Synchronization for system analysis
US6490695B1 (en) 1999-01-22 2002-12-03 Sun Microsystems, Inc. Platform independent memory image analysis architecture for debugging a computer program
EP1073951A1 (en) 1999-02-15 2001-02-07 Philips Electronics N.V. Data processor with a configurable functional unit and method using such a data processor
US6243808B1 (en) 1999-03-08 2001-06-05 Chameleon Systems, Inc. Digital data bit order conversion using universal switch matrix comprising rows of bit swapping selector groups
US6286134B1 (en) 1999-04-23 2001-09-04 Sun Microsystems, Inc. Instruction selection in a multi-platform environment
US6381624B1 (en) 1999-04-29 2002-04-30 Hewlett-Packard Company Faster multiply/accumulator
US6298472B1 (en) 1999-05-07 2001-10-02 Chameleon Systems, Inc. Behavioral silicon construct architecture and mapping
US6748440B1 (en) 1999-05-12 2004-06-08 Microsoft Corporation Flow of streaming data through multiple processing modules
DE19926538A1 (en) 1999-06-10 2000-12-14 Pact Inf Tech Gmbh Hardware with decoupled configuration register partitions data flow or control flow graphs into time-separated sub-graphs and forms and implements them sequentially on a component
CN1378665A (en) * 1999-06-10 2002-11-06 Pact信息技术有限公司 Programming concept
JP3420121B2 (en) 1999-06-30 2003-06-23 Necエレクトロニクス株式会社 Nonvolatile semiconductor memory device
GB2352548B (en) 1999-07-26 2001-06-06 Sun Microsystems Inc Method and apparatus for executing standard functions in a computer system
US6370596B1 (en) 1999-08-03 2002-04-09 Chameleon Systems, Inc. Logic flag registers for monitoring processing system events
US6204687B1 (en) * 1999-08-13 2001-03-20 Xilinx, Inc. Method and structure for configuring FPGAS
US6779016B1 (en) 1999-08-23 2004-08-17 Terraspring, Inc. Extensible computing system
US6311200B1 (en) 1999-09-23 2001-10-30 Chameleon Systems, Inc. Reconfigurable program sum of products generator
US6288566B1 (en) 1999-09-23 2001-09-11 Chameleon Systems, Inc. Configuration state memory for functional blocks on a reconfigurable chip
US6631487B1 (en) 1999-09-27 2003-10-07 Lattice Semiconductor Corp. On-line testing of field programmable gate array resources
DE19946752A1 (en) 1999-09-29 2001-04-12 Infineon Technologies Ag Reconfigurable gate array
US6665758B1 (en) 1999-10-04 2003-12-16 Ncr Corporation Software sanity monitor
US6633181B1 (en) 1999-12-30 2003-10-14 Stretch, Inc. Multi-scale programmable array
EP1630685B1 (en) 2000-01-07 2008-04-09 Nippon Telegraph and Telephone Corporation Function reconfigurable semiconductor device and integrated circuit configuring the semiconductor device
US6487709B1 (en) 2000-02-09 2002-11-26 Xilinx, Inc. Run-time routing for programmable logic devices
WO2001063434A1 (en) 2000-02-24 2001-08-30 Bops, Incorporated Methods and apparatus for dual-use coprocessing/debug interface
US6539477B1 (en) 2000-03-03 2003-03-25 Chameleon Systems, Inc. System and method for control synthesis using a reachable states look-up table
KR100841411B1 (en) 2000-03-14 2008-06-25 소니 가부시끼 가이샤 Transmission apparatus, reception apparatus, transmission method, reception method and recording medium
US6657457B1 (en) 2000-03-15 2003-12-02 Intel Corporation Data transfer on reconfigurable chip
US6362650B1 (en) * 2000-05-18 2002-03-26 Xilinx, Inc. Method and apparatus for incorporating a multiplier into an FPGA
US6373779B1 (en) 2000-05-19 2002-04-16 Xilinx, Inc. Block RAM having multiple configurable write modes for use in a field programmable gate array
US7340596B1 (en) 2000-06-12 2008-03-04 Altera Corporation Embedded processor with watchdog timer for programmable logic
DE10028397A1 (en) 2000-06-13 2001-12-20 Pact Inf Tech Gmbh Registration method in operating a reconfigurable unit, involves evaluating acknowledgement signals of configurable cells with time offset to configuration
US6285624B1 (en) 2000-07-08 2001-09-04 Han-Ping Chen Multilevel memory access method
DE10036627A1 (en) 2000-07-24 2002-02-14 Pact Inf Tech Gmbh Integrated cell matrix circuit has at least 2 different types of cells with interconnection terminals positioned to allow mixing of different cell types within matrix circuit
US6538468B1 (en) 2000-07-31 2003-03-25 Cypress Semiconductor Corporation Method and apparatus for multiple boot-up functionalities for a programmable logic device (PLD)
US6542844B1 (en) 2000-08-02 2003-04-01 International Business Machines Corporation Method and apparatus for tracing hardware states using dynamically reconfigurable test circuits
US6754805B1 (en) 2000-08-07 2004-06-22 Transwitch Corporation Method and apparatus for configurable multi-cell digital signal processing employing global parallel configuration
EP1356400A2 (en) 2000-08-07 2003-10-29 Altera Corporation Inter-device communication interface
US6829697B1 (en) 2000-09-06 2004-12-07 International Business Machines Corporation Multiple logical interfaces to a shared coprocessor resource
US7346644B1 (en) 2000-09-18 2008-03-18 Altera Corporation Devices and methods with programmable logic and digital signal processing regions
US6538470B1 (en) 2000-09-18 2003-03-25 Altera Corporation Devices and methods with programmable logic and digital signal processing regions
DE10129237A1 (en) 2000-10-09 2002-04-18 Pact Inf Tech Gmbh Integrated cell matrix circuit has at least 2 different types of cells with interconnection terminals positioned to allow mixing of different cell types within matrix circuit
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US20020045952A1 (en) 2000-10-12 2002-04-18 Blemel Kenneth G. High performance hybrid micro-computer
US6398383B1 (en) 2000-10-30 2002-06-04 Yu-Hwei Huang Flashlight carriable on one's person
JP3636986B2 (en) 2000-12-06 2005-04-06 松下電器産業株式会社 The semiconductor integrated circuit
GB2370380B (en) 2000-12-19 2003-12-31 Picochip Designs Ltd Processor architecture
EP1346280A1 (en) 2000-12-20 2003-09-24 Philips Electronics N.V. Data processing device with a configurable functional unit
US6483343B1 (en) 2000-12-29 2002-11-19 Quicklogic Corporation Configurable computational unit embedded in a programmable device
US6392912B1 (en) 2001-01-10 2002-05-21 Chameleon Systems, Inc. Loading data plane on reconfigurable chip
US6836839B2 (en) 2001-03-22 2004-12-28 Quicksilver Technology, Inc. Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements
US20020143505A1 (en) 2001-04-02 2002-10-03 Doron Drusinsky Implementing a finite state machine using concurrent finite state machines with delayed communications and no shared control signals
US6792588B2 (en) 2001-04-02 2004-09-14 Intel Corporation Faster scalable floorplan which enables easier data control flow
US20030086300A1 (en) 2001-04-06 2003-05-08 Gareth Noyes FPGA coprocessing system
US6999984B2 (en) 2001-05-02 2006-02-14 Intel Corporation Modification to reconfigurable functional unit in a reconfigurable chip to perform linear feedback shift register function
US7210129B2 (en) 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
US6868476B2 (en) 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
US6874108B1 (en) 2001-08-27 2005-03-29 Agere Systems Inc. Fault tolerant operation of reconfigurable devices utilizing an adjustable system clock
US7216204B2 (en) 2001-08-27 2007-05-08 Intel Corporation Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
US20030056091A1 (en) 2001-09-14 2003-03-20 Greenberg Craig B. Method of scheduling in a reconfigurable hardware architecture with multiple hardware configurations
US20030055861A1 (en) 2001-09-18 2003-03-20 Lai Gary N. Multipler unit in reconfigurable chip
US20030052711A1 (en) * 2001-09-19 2003-03-20 Taylor Bradley L. Despreader/correlator unit for use in reconfigurable chip
US6854073B2 (en) 2001-09-25 2005-02-08 International Business Machines Corporation Debugger program time monitor
US6798239B2 (en) 2001-09-28 2004-09-28 Xilinx, Inc. Programmable gate array having interconnecting logic to support embedded fixed logic circuitry
US6886092B1 (en) 2001-11-19 2005-04-26 Xilinx, Inc. Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion
US6476634B1 (en) 2002-02-01 2002-11-05 Xilinx, Inc. ALU implementation in single PLD logic cell
DE20221985U1 (en) 2002-02-01 2010-03-04 Tridonicatco Gmbh & Co. Kg Electronic ballast for gas discharge lamp
US6961924B2 (en) 2002-05-21 2005-11-01 International Business Machines Corporation Displaying variable usage while debugging
US6803787B1 (en) 2002-09-25 2004-10-12 Lattice Semiconductor Corp. State machine in a programmable logic device
US7383421B2 (en) 2002-12-05 2008-06-03 Brightscale, Inc. Cellular engine for a data processing system
US7567997B2 (en) 2003-12-29 2009-07-28 Xilinx, Inc. Applications of cascading DSP slices
US7472155B2 (en) 2003-12-29 2008-12-30 Xilinx, Inc. Programmable logic device with cascading DSP slices
US8495122B2 (en) 2003-12-29 2013-07-23 Xilinx, Inc. Programmable device with dynamic DSP architecture
US7870182B2 (en) 2003-12-29 2011-01-11 Xilinx Inc. Digital signal processing circuit having an adder circuit with carry-outs
US7840627B2 (en) 2003-12-29 2010-11-23 Xilinx, Inc. Digital signal processing circuit having input register blocks
US7038952B1 (en) 2004-05-04 2006-05-02 Xilinx, Inc. Block RAM with embedded FIFO buffer
US7971051B2 (en) 2007-09-27 2011-06-28 Fujitsu Limited FPGA configuration protection and control using hardware watchdog timer

Patent Citations (212)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6173434B2 (en) *
US10450A (en) * 1854-01-24 Thomas peossbr
US566597A (en) * 1896-08-25 James a
US3564506A (en) * 1968-01-17 1971-02-16 Ibm Instruction retry byte counter
US3681578A (en) * 1969-11-21 1972-08-01 Marconi Co Ltd Fault location and reconfiguration in redundant data processors
US3753008A (en) * 1970-06-20 1973-08-14 Honeywell Inf Systems Memory pre-driver circuit
US5602999A (en) * 1970-12-28 1997-02-11 Hyatt; Gilbert P. Memory system having a plurality of memories, a plurality of detector circuits, and a delay circuit
US3754211A (en) * 1971-12-30 1973-08-21 Ibm Fast error recovery communication controller
US4498134A (en) * 1982-01-26 1985-02-05 Hughes Aircraft Company Segregator functional plane for use in a modular array processor
US4498172A (en) * 1982-07-26 1985-02-05 General Electric Company System for polynomial division self-testing of digital networks
US4566102A (en) * 1983-04-18 1986-01-21 International Business Machines Corporation Parallel-shift error reconfiguration
US4571736A (en) * 1983-10-31 1986-02-18 University Of Southwestern Louisiana Digital communication system employing differential coding and sample robbing
US4646300A (en) * 1983-11-14 1987-02-24 Tandem Computers Incorporated Communications method
US4870302A (en) * 1984-03-12 1989-09-26 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
USRE34363E (en) * 1984-03-12 1993-08-31 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US4686386A (en) * 1984-03-21 1987-08-11 Oki Electric Industry Co., Ltd. Power-down circuits for dynamic MOS integrated circuits
US4761755A (en) * 1984-07-11 1988-08-02 Prime Computer, Inc. Data processing system and method having an improved arithmetic unit
US4720778A (en) * 1985-01-31 1988-01-19 Hewlett Packard Company Software debugging analyzer
US5485104A (en) * 1985-03-29 1996-01-16 Advanced Micro Devices, Inc. Logic allocator for a programmable logic device
US4720780A (en) * 1985-09-17 1988-01-19 The Johns Hopkins University Memory-linked wavefront array processor
US4860201A (en) * 1986-09-02 1989-08-22 The Trustees Of Columbia University In The City Of New York Binary tree parallel processor
US5600265A (en) * 1986-09-19 1997-02-04 Actel Corporation Programmable interconnect architecture
US4992933A (en) * 1986-10-27 1991-02-12 International Business Machines Corporation SIMD array processor with global instruction control and reprogrammable instruction decoders
US4891810A (en) * 1986-10-31 1990-01-02 Thomson-Csf Reconfigurable computing device
US4959781A (en) * 1988-05-16 1990-09-25 Stardent Computer, Inc. System for assigning interrupts to least busy processor that already loaded same class of interrupt routines
US5287511A (en) * 1988-07-11 1994-02-15 Star Semiconductor Corporation Architectures and methods for dividing processing tasks into tasks for a programmable real time signal processor and tasks for a decision making microprocessor interfacing therewith
US4901268A (en) * 1988-08-19 1990-02-13 General Electric Company Multiple function data processor
US5043978A (en) * 1988-09-22 1991-08-27 Siemens Aktiengesellschaft Circuit arrangement for telecommunications exchanges
US5041924A (en) * 1988-11-30 1991-08-20 Quantum Corporation Removable and transportable hard disk subsystem
US5081375A (en) * 1989-01-19 1992-01-14 National Semiconductor Corp. Method for operating a multiple page programmable logic device
US5491353A (en) * 1989-03-17 1996-02-13 Xilinx, Inc. Configurable cellular array
US5287472A (en) * 1989-05-02 1994-02-15 Tandem Computers Incorporated Memory system using linear array wafer scale integration architecture
US5237686A (en) * 1989-05-10 1993-08-17 Mitsubishi Denki Kabushiki Kaisha Multiprocessor type time varying image encoding system and image processor with memory bus control table for arbitration priority
US5379444A (en) * 1989-07-28 1995-01-03 Hughes Aircraft Company Array of one-bit processors each having only one bit of memory
US5343406A (en) * 1989-07-28 1994-08-30 Xilinx, Inc. Distributed memory architecture for a configurable logic array and method for using distributed memory
US5233539A (en) * 1989-08-15 1993-08-03 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure, input/output structure and configurable logic block
US5287532A (en) * 1989-11-14 1994-02-15 Amt (Holdings) Limited Processor elements having multi-byte structure shift register for shifting data either byte wise or bit wise with single-bit output formed at bit positions thereof spaced by one byte
US5142469A (en) * 1990-03-29 1992-08-25 Ge Fanuc Automation North America, Inc. Method for converting a programmable logic controller hardware configuration and corresponding control program for use on a first programmable logic controller to use on a second programmable logic controller
US5440245A (en) * 1990-05-11 1995-08-08 Actel Corporation Logic module with configurable combinational and sequential blocks
US5483620A (en) * 1990-05-22 1996-01-09 International Business Machines Corp. Learning machine synapse processor system apparatus
US5784630A (en) * 1990-09-07 1998-07-21 Hitachi, Ltd. Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory
US5717943A (en) * 1990-11-13 1998-02-10 International Business Machines Corporation Advanced parallel array processor (APAP)
US5794059A (en) * 1990-11-13 1998-08-11 International Business Machines Corporation N-dimensional modified hypercube
US5713037A (en) * 1990-11-13 1998-01-27 International Business Machines Corporation Slide bus communication functions for SIMD/MIMD array processor
US5924119A (en) * 1990-11-30 1999-07-13 Xerox Corporation Consistent packet switched memory bus for shared memory multiprocessors
US5276836A (en) * 1991-01-10 1994-01-04 Hitachi, Ltd. Data processing device with common memory connecting mechanism
US5544336A (en) * 1991-03-19 1996-08-06 Fujitsu Limited Parallel data processing system which efficiently performs matrix and neurocomputer operations, in a negligible data transmission time
US5717890A (en) * 1991-04-30 1998-02-10 Kabushiki Kaisha Toshiba Method for processing data by utilizing hierarchical cache memories and processing system with the hierarchiacal cache memories
US5442790A (en) * 1991-05-24 1995-08-15 The Trustees Of Princeton University Optimizing compiler for computers
US5659797A (en) * 1991-06-24 1997-08-19 U.S. Philips Corporation Sparc RISC based computer system including a single chip processor with memory management and DMA units coupled to a DRAM interface
US5336950A (en) * 1991-08-29 1994-08-09 National Semiconductor Corporation Configuration features in a configurable logic array
US5550782A (en) * 1991-09-03 1996-08-27 Altera Corporation Programmable logic array integrated circuits
US5485103A (en) * 1991-09-03 1996-01-16 Altera Corporation Programmable logic array with local and global conductors
US5867691A (en) * 1992-03-13 1999-02-02 Kabushiki Kaisha Toshiba Synchronizing system between function blocks arranged in hierarchical structures and large scale integrated circuit using the same
US5655124A (en) * 1992-03-31 1997-08-05 Seiko Epson Corporation Selective power-down for high performance CPU/system
US5493663A (en) * 1992-04-22 1996-02-20 International Business Machines Corporation Method and apparatus for predetermining pages for swapping from physical memory in accordance with the number of accesses
US5386154A (en) * 1992-07-23 1995-01-31 Xilinx, Inc. Compact logic cell for field programmable gate array chip
US5489857A (en) * 1992-08-03 1996-02-06 Advanced Micro Devices, Inc. Flexible synchronous/asynchronous cell structure for a high density programmable logic device
US5867723A (en) * 1992-08-05 1999-02-02 Sarnoff Corporation Advanced massively parallel computer with a secondary storage device coupled through a secondary storage interface
US5857109A (en) * 1992-11-05 1999-01-05 Giga Operations Corporation Programmable logic device for real time video processing
US5392437A (en) * 1992-11-06 1995-02-21 Intel Corporation Method and apparatus for independently stopping and restarting functional units
US5386518A (en) * 1993-02-12 1995-01-31 Hughes Aircraft Company Reconfigurable computer interface and method
US5548773A (en) * 1993-03-30 1996-08-20 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Digital parallel processor array for optimum path planning
US5596742A (en) * 1993-04-02 1997-01-21 Massachusetts Institute Of Technology Virtual interconnections for reconfigurable logic systems
US5339840A (en) * 1993-04-26 1994-08-23 Sunbelt Precision Products Inc. Adjustable comb
US5606698A (en) * 1993-04-26 1997-02-25 Cadence Design Systems, Inc. Method for deriving optimal code schedule sequences from synchronous dataflow graphs
US5444394A (en) * 1993-07-08 1995-08-22 Altera Corporation PLD with selective inputs from local and global conductors
US5440538A (en) * 1993-09-23 1995-08-08 Massachusetts Institute Of Technology Communication system with redundant links and data bit time multiplexing
US5781756A (en) * 1994-04-01 1998-07-14 Xilinx, Inc. Programmable logic device with partially configurable memory cells and a method for configuration
US5600845A (en) * 1994-07-27 1997-02-04 Metalithic Systems Incorporated Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5655069A (en) * 1994-07-29 1997-08-05 Fujitsu Limited Apparatus having a plurality of programmable logic processing units for self-repair
US5657330A (en) * 1994-11-15 1997-08-12 Mitsubishi Denki Kabushiki Kaisha Single-chip microprocessor with built-in self-testing function
US5603005A (en) * 1994-12-27 1997-02-11 Unisys Corporation Cache coherency scheme for XBAR storage structure with delayed invalidates until associated write request is executed
US5778237A (en) * 1995-01-10 1998-07-07 Hitachi, Ltd. Data processor and single-chip microcomputer with changing clock frequency and operating voltage
US5493239A (en) * 1995-01-31 1996-02-20 Motorola, Inc. Circuit and method of configuring a field programmable gate array
US5659785A (en) * 1995-02-10 1997-08-19 International Business Machines Corporation Array processor communication architecture with broadcast processor instructions
USRE36839E (en) * 1995-02-14 2000-08-29 Philips Semiconductor, Inc. Method and apparatus for reducing power consumption in digital electronic circuits
US5862403A (en) * 1995-02-17 1999-01-19 Kabushiki Kaisha Toshiba Continuous data server apparatus and data transfer scheme enabling multiple simultaneous data accesses
US6185731B1 (en) * 1995-04-14 2001-02-06 Mitsubishi Electric Semiconductor Software Co., Ltd. Real time debugger for a microcomputer
US5933642A (en) * 1995-04-17 1999-08-03 Ricoh Corporation Compiling system and method for reconfigurable computing
US6077315A (en) * 1995-04-17 2000-06-20 Ricoh Company Ltd. Compiling system and method for partially reconfigurable computing
US5794062A (en) * 1995-04-17 1998-08-11 Ricoh Company Ltd. System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
US6026481A (en) * 1995-04-28 2000-02-15 Xilinx, Inc. Microprocessor with distributed registers accessible by programmable logic device
US5705938A (en) * 1995-05-02 1998-01-06 Xilinx, Inc. Programmable switch for FPGA input/output signals
US5649179A (en) * 1995-05-19 1997-07-15 Motorola, Inc. Dynamic instruction allocation for a SIMD processor
US5706482A (en) * 1995-05-31 1998-01-06 Nec Corporation Memory access controller
US5870620A (en) * 1995-06-01 1999-02-09 Sharp Kabushiki Kaisha Data driven type information processor with reduced instruction execution requirements
US5652529A (en) * 1995-06-02 1997-07-29 International Business Machines Corporation Programmable array clock/reset resource
US6321373B1 (en) * 1995-08-07 2001-11-20 International Business Machines Corporation Method for resource control in parallel environments using program organization and run-time support
US5978583A (en) * 1995-08-07 1999-11-02 International Business Machines Corp. Method for resource control in parallel environments using program organization and run-time support
US5649176A (en) * 1995-08-10 1997-07-15 Virtual Machine Works, Inc. Transition analysis and circuit resynthesis method and device for digital circuit modeling
US5784313A (en) * 1995-08-18 1998-07-21 Xilinx, Inc. Programmable logic device including configuration data or user data memory slices
US6263430B1 (en) * 1995-08-18 2001-07-17 Xilinx, Inc. Method of time multiplexing a programmable logic device
US5778439A (en) * 1995-08-18 1998-07-07 Xilinx, Inc. Programmable logic device with hierarchical confiquration and state storage
US6430309B1 (en) * 1995-09-15 2002-08-06 Monogen, Inc. Specimen preview and inspection system
US5652894A (en) * 1995-09-29 1997-07-29 Intel Corporation Method and apparatus for providing power saving modes to a pipelined processor
US5656950A (en) * 1995-10-26 1997-08-12 Xilinx, Inc. Interconnect lines including tri-directional buffer circuits
US5943242A (en) * 1995-11-17 1999-08-24 Pact Gmbh Dynamically reconfigurable data processing system
US6859869B1 (en) * 1995-11-17 2005-02-22 Pact Xpp Technologies Ag Data processing system
US5926638A (en) * 1996-01-17 1999-07-20 Nec Corporation Program debugging system for debugging a program having graphical user interface
US5936424A (en) * 1996-02-02 1999-08-10 Xilinx, Inc. High speed bus with tree structure for selecting bus driver
US5656545A (en) * 1996-02-26 1997-08-12 Taiwan Semiconductor Manufacturing Company, Ltd Elimination of tungsten dimple for stacked contact or via application
US6020758A (en) * 1996-03-11 2000-02-01 Altera Corporation Partially reconfigurable programmable logic device
US6279077B1 (en) * 1996-03-22 2001-08-21 Texas Instruments Incorporated Bus interface buffer control in a microprocessor
US6266760B1 (en) * 1996-04-11 2001-07-24 Massachusetts Institute Of Technology Intermediate-grain reconfigurable processing device
US6173434B1 (en) * 1996-04-22 2001-01-09 Brigham Young University Dynamically-configurable digital processor using method for relocating logic array modules
US6014509A (en) * 1996-05-20 2000-01-11 Atmel Corporation Field programmable gate array having access to orthogonal and diagonal adjacent neighboring cells
US5784636A (en) * 1996-05-28 1998-07-21 National Semiconductor Corporation Reconfigurable computer architecture for use in signal processing applications
US6785826B1 (en) * 1996-07-17 2004-08-31 International Business Machines Corporation Self power audit and control circuitry for microprocessor functional units
US6023742A (en) * 1996-07-18 2000-02-08 University Of Washington Reconfigurable computing architecture for providing pipelined data paths
US6105105A (en) * 1996-07-19 2000-08-15 Xilinx, Inc. Data processing system using configuration select logic, an instruction store, and sequencing logic during instruction execution
US6023564A (en) * 1996-07-19 2000-02-08 Xilinx, Inc. Data processing system using a flash reconfigurable logic device as a dynamic execution unit for a sequence of instructions
US6425054B1 (en) * 1996-08-19 2002-07-23 Samsung Electronics Co., Ltd. Multiprocessor operation in a multimedia signal processor
US5933023A (en) * 1996-09-03 1999-08-03 Xilinx, Inc. FPGA architecture having RAM blocks with programmable word length and width and dedicated address and data lines
US5859544A (en) * 1996-09-05 1999-01-12 Altera Corporation Dynamic configurable elements for programmable logic devices
US6178494B1 (en) * 1996-09-23 2001-01-23 Virtual Computer Corporation Modular, hybrid processor and method for producing a modular, hybrid processor
US5844422A (en) * 1996-11-13 1998-12-01 Xilinx, Inc. State saving and restoration in reprogrammable FPGAs
US5860119A (en) * 1996-11-25 1999-01-12 Vlsi Technology, Inc. Data-packet fifo buffer system with end-of-packet flags
US20040168099A1 (en) * 1996-12-09 2004-08-26 Martin Vorbach Unit for processing numeric and logic operations for use in central processing units (CPUs), multiprocessor systems
US6425068B1 (en) * 1996-12-09 2002-07-23 Pact Gmbh Unit for processing numeric and logic operations for use in central processing units (cpus), multiprocessor systems, data-flow processors (dsps), systolic processors and field programmable gate arrays (epgas)
US6513077B2 (en) * 1996-12-20 2003-01-28 Pact Gmbh I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures
US6021490A (en) * 1996-12-20 2000-02-01 Pact Gmbh Run-time reconfiguration method for programmable units
US6338106B1 (en) * 1996-12-20 2002-01-08 Pact Gmbh I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
US6088795A (en) * 1996-12-27 2000-07-11 Pact Gmbh Process for automatic dynamic reloading of data flow processors (DFPs) and units with two or three-dimensional programmable cell architectures (FPGAs, DPGAs and the like)
US6427156B1 (en) * 1997-01-21 2002-07-30 Xilinx, Inc. Configurable logic block with AND gate for efficient multiplication in FPGAS
US6262908B1 (en) * 1997-01-29 2001-07-17 Elixent Limited Field programmable processor devices
US6526520B1 (en) * 1997-02-08 2003-02-25 Pact Gmbh Method of self-synchronization of configurable elements of a programmable unit
US20030135686A1 (en) * 1997-02-11 2003-07-17 Martin Vorbach Internal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity
US5857097A (en) * 1997-03-10 1999-01-05 Digital Equipment Corporation Method for identifying reasons for dynamic stall cycles during the execution of a program
US6507898B1 (en) * 1997-04-30 2003-01-14 Canon Kabushiki Kaisha Reconfigurable data cache controller
US6421817B1 (en) * 1997-05-29 2002-07-16 Xilinx, Inc. System and method of computation in a programmable logic device using virtual instructions
US6011407A (en) * 1997-06-13 2000-01-04 Xilinx, Inc. Field programmable gate array with dedicated computer bus interface and method for configuring both
US5966534A (en) * 1997-06-27 1999-10-12 Cooke; Laurence H. Method for compiling high level programming languages into an integrated processor with reconfigurable logic
US20030014743A1 (en) * 1997-06-27 2003-01-16 Cooke Laurence H. Method for compiling high level programming languages
US6708325B2 (en) * 1997-06-27 2004-03-16 Intel Corporation Method for compiling high level programming languages into embedded microprocessor with multiple reconfigurable logic
US6437441B1 (en) * 1997-07-10 2002-08-20 Kawasaki Microelectronics, Inc. Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure
US6020760A (en) * 1997-07-16 2000-02-01 Altera Corporation I/O buffer circuit with pin multiplexing
US6282701B1 (en) * 1997-07-31 2001-08-28 Mutek Solutions, Ltd. System and method for monitoring and analyzing the execution of computer programs
US6170051B1 (en) * 1997-08-01 2001-01-02 Micron Technology, Inc. Apparatus and method for program level parallelism in a VLIW processor
US6026478A (en) * 1997-08-01 2000-02-15 Micron Technology, Inc. Split embedded DRAM processor
US6085317A (en) * 1997-08-15 2000-07-04 Altera Corporation Reconfigurable computer architecture using programmable logic devices
US6188650B1 (en) * 1997-10-21 2001-02-13 Sony Corporation Recording and reproducing system having resume function
US6260179B1 (en) * 1997-10-23 2001-07-10 Fujitsu Limited Cell arrangement evaluating method, storage medium storing cell arrangement evaluating program, cell arranging apparatus and method, and storage medium storing cell arranging program
US6108760A (en) * 1997-10-31 2000-08-22 Silicon Spice Method and apparatus for position independent reconfiguration in a network of multiple context processing elements
US6339424B1 (en) * 1997-11-18 2002-01-15 Fuji Xerox Co., Ltd Drawing processor
US6185256B1 (en) * 1997-11-19 2001-02-06 Fujitsu Limited Signal transmission system using PRD method, receiver circuit for use in the signal transmission system, and semiconductor memory device to which the signal transmission system is applied
US6075935A (en) * 1997-12-01 2000-06-13 Improv Systems, Inc. Method of generating application specific integrated circuits using a programmable hardware architecture
US6219833B1 (en) * 1997-12-17 2001-04-17 Hewlett-Packard Company Method of using primary and secondary processors
US6523107B1 (en) * 1997-12-17 2003-02-18 Elixent Limited Method and apparatus for providing instruction streams to a processing device
US6697979B1 (en) * 1997-12-22 2004-02-24 Pact Xpp Technologies Ag Method of repairing integrated circuits
US6260114B1 (en) * 1997-12-30 2001-07-10 Mcmz Technology Innovations, Llc Computer cache memory windowing
US6172520B1 (en) * 1997-12-30 2001-01-09 Xilinx, Inc. FPGA system with user-programmable configuration ports and method for reconfiguring the FPGA
US6516382B2 (en) * 1997-12-31 2003-02-04 Micron Technology, Inc. Memory device balanced switching circuit and method of controlling an array of transfer gates for fast switching times
US6105106A (en) * 1997-12-31 2000-08-15 Micron Technology, Inc. Computer system, memory device and shift register including a balanced switching circuit with series connected transfer gates which are selectively clocked for fast switching times
US6256724B1 (en) * 1998-02-04 2001-07-03 Texas Instruments Incorporated Digital signal processor with efficiently connectable hardware co-processor
US6086628A (en) * 1998-02-17 2000-07-11 Lucent Technologies Inc. Power-related hardware-software co-synthesis of heterogeneous distributed embedded systems
US6096091A (en) * 1998-02-24 2000-08-01 Advanced Micro Devices, Inc. Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip
US6687788B2 (en) * 1998-02-25 2004-02-03 Pact Xpp Technologies Ag Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.)
US6434699B1 (en) * 1998-02-27 2002-08-13 Mosaid Technologies Inc. Encryption processor with shared memory interconnect
US6175247B1 (en) * 1998-04-14 2001-01-16 Lockheed Martin Corporation Context switchable field programmable gate array with public-private addressable sharing of intermediate data
US6421808B1 (en) * 1998-04-24 2002-07-16 Cadance Design Systems, Inc. Hardware design language for the design of integrated circuits
US6084429A (en) * 1998-04-24 2000-07-04 Xilinx, Inc. PLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arrays
US6173419B1 (en) * 1998-05-14 2001-01-09 Advanced Technology Materials, Inc. Field programmable gate array (FPGA) emulator for debugging software
US6092174A (en) * 1998-06-01 2000-07-18 Context, Inc. Dynamically reconfigurable distributed integrated circuit processor and method
US6188240B1 (en) * 1998-06-04 2001-02-13 Nec Corporation Programmable function block
US6282627B1 (en) * 1998-06-29 2001-08-28 Chameleon Systems, Inc. Integrated processor and programmable data path chip for reconfigurable computing
US6421809B1 (en) * 1998-07-24 2002-07-16 Interuniversitaire Micro-Elektronica Centrum (Imec Vzw) Method for determining a storage bandwidth optimized memory organization of an essentially digital device
US6681388B1 (en) * 1998-10-02 2004-01-20 Real World Computing Partnership Method and compiler for rearranging array data into sub-arrays of consecutively-addressed elements for distribution processing
US6694434B1 (en) * 1998-12-23 2004-02-17 Entrust Technologies Limited Method and apparatus for controlling program execution and program distribution
US6434695B1 (en) * 1998-12-23 2002-08-13 Apple Computer, Inc. Computer operating system using compressed ROM image in RAM
US6587939B1 (en) * 1999-01-13 2003-07-01 Kabushiki Kaisha Toshiba Information processing apparatus provided with an optimized executable instruction extracting unit for extending compressed instructions
US6539438B1 (en) * 1999-01-15 2003-03-25 Quickflex Inc. Reconfigurable computing system and method and apparatus employing same
US6191614B1 (en) * 1999-04-05 2001-02-20 Xilinx, Inc. FPGA configuration circuit including bus-based CRC register
US7007096B1 (en) * 1999-05-12 2006-02-28 Microsoft Corporation Efficient splitting and mixing of streaming-data frames for processing through multiple processing modules
US6504398B1 (en) * 1999-05-25 2003-01-07 Actel Corporation Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure
US6782445B1 (en) * 1999-06-15 2004-08-24 Hewlett-Packard Development Company, L.P. Memory and instructions in computer architecture containing processor and coprocessor
US6757892B1 (en) * 1999-06-24 2004-06-29 Sarnoff Corporation Method for determining an optimal partitioning of data among several memories
US6347346B1 (en) * 1999-06-30 2002-02-12 Chameleon Systems, Inc. Local memory unit system with global access for use on reconfigurable chips
US6341318B1 (en) * 1999-08-10 2002-01-22 Chameleon Systems, Inc. DMA data streaming
US6438747B1 (en) * 1999-08-20 2002-08-20 Hewlett-Packard Company Programmatic iteration scheduling for parallel processors
US6507947B1 (en) * 1999-08-20 2003-01-14 Hewlett-Packard Company Programmatic synthesis of processor element arrays
US6349346B1 (en) * 1999-09-23 2002-02-19 Chameleon Systems, Inc. Control fabric unit including associated configuration memory and PSOP state machine adapted to provide configuration address to reconfigurable functional unit
US6434642B1 (en) * 1999-10-07 2002-08-13 Xilinx, Inc. FIFO memory system and method with improved determination of full and empty conditions and amount of data stored
US20020013861A1 (en) * 1999-12-28 2002-01-31 Intel Corporation Method and apparatus for low overhead multithreaded communication in a parallel processing environment
US20010010074A1 (en) * 2000-01-20 2001-07-26 Fuji Xerox Co., Ltd. Data processing method by programmable logic device, programmable logic device, information processing system and method of reconfiguring circuit in programmable logic
US7254649B2 (en) * 2000-01-28 2007-08-07 Infineon Technologies Ag Wireless spread spectrum communication platform using dynamically reconfigurable logic
US6496971B1 (en) * 2000-02-07 2002-12-17 Xilinx, Inc. Supporting multiple FPGA configuration modes using dedicated on-chip processor
US6438737B1 (en) * 2000-02-15 2002-08-20 Intel Corporation Reconfigurable logic for a computer
US6519674B1 (en) * 2000-02-18 2003-02-11 Chameleon Systems, Inc. Configuration bits layout
US20010018733A1 (en) * 2000-02-25 2001-08-30 Taro Fujii Array-type processor
US6871341B1 (en) * 2000-03-24 2005-03-22 Intel Corporation Adaptive scheduling of function cells in dynamic reconfigurable logic
US20020004916A1 (en) * 2000-05-12 2002-01-10 Marchand Patrick R. Methods and apparatus for power control in a scalable array of processor elements
US20040025005A1 (en) * 2000-06-13 2004-02-05 Martin Vorbach Pipeline configuration unit protocols and communication
US6928523B2 (en) * 2000-07-25 2005-08-09 Renesas Technology Corp. Synchronous signal producing circuit for controlling a data ready signal indicative of end of access to a shared memory and thereby controlling synchronization between processor and coprocessor
US7164422B1 (en) * 2000-07-28 2007-01-16 Ab Initio Software Corporation Parameterized graphs with conditional components
US7249351B1 (en) * 2000-08-30 2007-07-24 Broadcom Corporation System and method for preparing software for execution in a dynamically configurable hardware environment
US6518787B1 (en) * 2000-09-21 2003-02-11 Triscend Corporation Input/output architecture for efficient configuration of programmable input/output cells
US20040015899A1 (en) * 2000-10-06 2004-01-22 Frank May Method for processing data
US6525678B1 (en) * 2000-10-06 2003-02-25 Altera Corporation Configuring a programmable logic device
US6426649B1 (en) * 2000-12-29 2002-07-30 Quicklogic Corporation Architecture for field programmable gate array
US20020103839A1 (en) * 2001-01-19 2002-08-01 Kunihiko Ozawa Reconfigurable arithmetic device and arithmetic system including that arithmetic device and address generation device and interleave device applicable to arithmetic system
US20020099759A1 (en) * 2001-01-24 2002-07-25 Gootherts Paul David Load balancer with starvation avoidance
US6847370B2 (en) * 2001-02-20 2005-01-25 3D Labs, Inc., Ltd. Planar byte memory organization with linear access
US20060036988A1 (en) * 2001-06-12 2006-02-16 Altera Corporation Methods and apparatus for implementing parameterizable processors and peripherals
US20030001615A1 (en) * 2001-06-29 2003-01-02 Semiconductor Technology Academic Research Center Programmable logic circuit device having look up table enabling to reduce implementation area
US7266725B2 (en) * 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
US7000161B1 (en) * 2001-10-15 2006-02-14 Altera Corporation Reconfigurable programmable logic system with configuration recovery mode
US20030123579A1 (en) * 2001-11-16 2003-07-03 Saeid Safavi Viterbi convolutional coding method and apparatus
US20030154349A1 (en) * 2002-01-24 2003-08-14 Berg Stefan G. Program-directed cache prefetching for media processors
US7873811B1 (en) * 2003-03-10 2011-01-18 The United States Of America As Represented By The United States Department Of Energy Polymorphous computing fabric
US7759968B1 (en) * 2006-09-27 2010-07-20 Xilinx, Inc. Method of and system for verifying configuration data
US20090193384A1 (en) * 2008-01-25 2009-07-30 Mihai Sima Shift-enabled reconfigurable device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140237603A1 (en) * 2013-02-20 2014-08-21 International Business Machines Corporation Rule matching in the presence of languages with no types or as an adjunct to current analyses for security vulnerability analysis
US9384354B2 (en) * 2013-02-20 2016-07-05 International Business Machines Corporation Rule matching in the presence of languages with no types or as an adjunct to current analyses for security vulnerability analysis

Also Published As

Publication number Publication date Type
EP1402382A2 (en) 2004-03-31 application
US7657877B2 (en) 2010-02-02 grant
WO2002103532A3 (en) 2003-12-11 application
EP2224330B1 (en) 2012-05-09 grant
WO2002103532A2 (en) 2002-12-27 application
EP2224330A1 (en) 2010-09-01 application
US20040243984A1 (en) 2004-12-02 application
JP2004533691A (en) 2004-11-04 application
EP1402382B1 (en) 2010-08-18 grant

Similar Documents

Publication Publication Date Title
So et al. A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH
Dally et al. The message-driven processor: A multicomputer processing node with efficient mechanisms
US5724590A (en) Technique for executing translated software
Gupta et al. Program implementation schemes for hardware-software systems
US6148381A (en) Single-port trace buffer architecture with overflow reduction
Waingold et al. Baring it all to software: The raw machine
Schmit et al. Pipeline reconfigurable fpgas
US6571381B1 (en) Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
Baumgarte et al. PACT XPP—A self-reconfigurable data processing architecture
US6826674B1 (en) Program product and data processor
US5933642A (en) Compiling system and method for reconfigurable computing
US7734895B1 (en) Configuring sets of processor cores for processing instructions
US20040083462A1 (en) Method and apparatus for creating and executing integrated executables in a heterogeneous architecture
US20060015701A1 (en) Arithmetic node including general digital signal processing functions for an adaptive computing machine
US7003660B2 (en) Pipeline configuration unit protocols and communication
US6088795A (en) Process for automatic dynamic reloading of data flow processors (DFPs) and units with two or three-dimensional programmable cell architectures (FPGAs, DPGAs and the like)
US5339429A (en) Parallel processing system and compiling method used therefor
US20010021959A1 (en) Static cache
US20040154002A1 (en) System &amp; method of linking separately compiled simulations
US7249351B1 (en) System and method for preparing software for execution in a dynamically configurable hardware environment
Caspi et al. A streaming multi-threaded model
US20040107331A1 (en) Meta-address architecture for parallel, dynamically reconfigurable computing
US20030014736A1 (en) Debugger breakpoint management in a multicore DSP device having shared program memory
EP0372835A2 (en) Translation technique
US20010025363A1 (en) Designer configurable multi-processor system

Legal Events

Date Code Title Description
AS Assignment

Owner name: PACT XPP TECHNOLOGIES AG, GERMANY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:RICHTER, THOMAS;KRASS, MAREN;REEL/FRAME:032225/0089

Effective date: 20140117