US20100060348A9 - Bandwidth-adjustable filter - Google Patents
Bandwidth-adjustable filter Download PDFInfo
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- US20100060348A9 US20100060348A9 US11/381,548 US38154806A US2010060348A9 US 20100060348 A9 US20100060348 A9 US 20100060348A9 US 38154806 A US38154806 A US 38154806A US 2010060348 A9 US2010060348 A9 US 2010060348A9
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- resistor
- coupled
- filtering device
- ladder circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
- H03K5/082—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold
- H03K5/086—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold generated by feedback
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/04—Frequency selective two-port networks
- H03H11/12—Frequency selective two-port networks using amplifiers with feedback
- H03H11/126—Frequency selective two-port networks using amplifiers with feedback using a single operational amplifier
- H03H11/1286—Sallen-Key biquad
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/04—Frequency selective two-port networks
- H03H11/12—Frequency selective two-port networks using amplifiers with feedback
- H03H11/1291—Current or voltage controlled filters
Definitions
- the invention relates in general to a filter, and more particularly to a bandwidth-adjustable filter.
- in-phase signals I-channel
- quadrature-phase signals Q-channel
- these two kinds of signals cannot match in phase.
- the signals in the I-channel and in the Q-channel have a phase difference not equal to 90 degrees, the signal constellation is distorted and the bit error rate is thus increased. Therefore, in order to maintain system stability, it is very important that the filter has accurate 3dB bandwidth.
- FIG. 1 a schematic diagram of a filter disposed in a wireless communication system is shown.
- the 3 dB frequency ⁇ 0 can reach the expected value.
- a capacitive array method is used to achieve the modulation of 3 dB frequency by adjusting the valid capacitance C.
- the conventional modulation mechanism has a minimum adjustable scale only about 2 ⁇ 3%, which cannot meet the requirement of high accuracy for the wireless communication system.
- the adjustable bandwidth of the filter can have a higher resolution.
- the invention achieves the above-identified object by providing a filter including an operational amplifier, a first resistor device and a first capacitor.
- the operational amplifier has a first input terminal, a second input terminal and an output terminal.
- the first resistor device is coupled to the first input terminal of the operational amplifier.
- the first capacitor is coupled to the first resistor device and the output terminal of the operational amplifier.
- the first resistor device has an equivalent resistance and includes a resistor ladder circuit, and the equivalent resistance corresponds to the resistor ladder circuit.
- the bandwidth of the filtering device corresponds to the equivalent resistance of the first resistor device and capacitance of the first capacitor.
- the resistor ladder circuit of the filtering device includes first switches and second switches for changing the resistance of the resistor ladder circuit so as to adjust the bandwidth of the filtering device.
- FIG. 1 (Prior Art) is a schematic diagram of a filter disposed in a wireless communication system
- FIG. 2 is a circuit diagram of a bandwidth-adjustable filter according to a preferred embodiment of the invention.
- FIG. 3 is a circuit diagram of a resistor ladder circuit according to a preferred embodiment of the invention.
- FIG. 4 is a diagram of a resistor ladder circuit configured with switches.
- FIG. 5 is a circuit diagram of a bandwidth adjustable filter according to another preferred embodiment of the invention.
- the filter 200 includes an operational amplifier 210 .
- the operational amplifier 210 has a negative input terminal and a positive input terminal coupled to the ground.
- the operational amplifier 210 is a single-input-terminal amplifier preferably.
- the filter 200 further includes a first adjustable resistor R 1 ′, a first capacitor C 1 , a second capacitor C 2 , a second resistor R 2 and a third resistor R 3 .
- the adjustable resistor R 1 ′ has a first terminal defined as a node N 1 and a second terminal defined as a node N 2 .
- the first terminal of the first adjustable resistor R 1 ′ is coupled to the negative input terminal of the operational amplifier 210 .
- the first capacitor C 1 has a first terminal coupled to the node N 1 and a second terminal coupled to the output terminal of the operational amplifier 210 .
- the second capacitor C 2 has a first terminal grounded and a second terminal coupled to the node N 2 .
- the second resistor R 2 is coupled to the node N 2
- the third resistor R 3 is coupled between the node N 2 and the output terminal of the operational amplifier 210 , wherein the output terminal is for outputting an output voltage V 0 .
- the 3 dB frequency ⁇ 0 of the filter 200 can be effectively controlled by adjusting the first adjustable resistor R 1 ′.
- a resistor ladder circuit R LADDER1 is used to finely adjust the value of the first adjustable resistor R 1 ′ so as to achieve the purpose of controlling the 3dB frequency ⁇ 0 accurately.
- the first adjustable resistor R 1 ′ includes the resistor ladder circuit R LADDER1 coupled in parallel to a first resistor R 1 .
- the resistor ladder circuit R LADDER1 has one terminal coupled to the node N 2 and the other terminal coupled to the node N 1 .
- the resistor ladder circuit R LADDER1 is an R-2R resistor ladder circuit (R ⁇ 2R) 1
- the R ⁇ 2R resistor ladder circuit (R ⁇ 2R) includes a plurality of second resistors 2R′, first resistors R′ and third resistors Rt.
- the resistance of the second resistor 2R′ is preferably twice of the resistance of the first resistor R′.
- the second resistors are denoted sequentially by the second resistor 2R′(1) ⁇ 2R′(P), wherein P is a positive integer.
- Each of the second resistors 2R′ has a first terminal a 1 grounded.
- the second terminals a 2 of the second resistor 2R′(1) and the first resistor R′(1) are coupled to the node N 2 .
- the first resistors are denoted sequentially by R′(1) ⁇ R′(P ⁇ 1).
- Each of the first resistor R′ is coupled between the second terminals a 2 of the two corresponding adjacent second resistors 2R′.
- the third resistor Rt has a first terminal coupled to the second terminal a 2 of the second resistor 2R′(P) and a second terminal coupled to the node N 1 .
- the third resistor Rt and the second resistor 2R′ have substantially the same resistance preferably.
- the second resistors 2R′(1) ⁇ 2R′(P) are arranged respectively in correspondence to the first resistors R′(1) ⁇ R′(P ⁇ 1) and the third resistor Rt.
- Each of the second resistors 2R′combined with the corresponding first resistor R′ is called a resistor pair.
- the second resistor 2R′(i) and the first resistor R′(i) form a resistor pair, wherein 0 ⁇ i ⁇ P, and the second resistor 2R′(P) and the third resistor Rt form a resistor pair.
- the equivalent resistance of the R ⁇ 2R resistor ladder circuit is 2 P ⁇ R′.
- the equivalent resistance of the first adjustable resistor R 1 ′ can be obtained by the following formulation.
- the equivalent resistance of the first adjustable resistor R 1 ′ can be adjusted by increasing or decreasing the number of resistor pairs, i.e. the P value.
- FIG. 4 shows a resistor ladder circuit (R LADDER1 ) configured with switches.
- the resistor ladder circuit (R LADDER1 ) is an R ⁇ 2R resistor ladder circuit (R ⁇ 2R) 1
- the R ⁇ 2R resistor ladder circuit (R ⁇ 2R) 1 includes a plurality of first switches, which are sequentially denoted by SW 1 (1) ⁇ SW 1 (P), and a plurality of second switches, which are sequentially denoted by SW 2 (1) ⁇ SW 2 (P).
- the switch SW 1 (1), . . . , or SW 1 (P) is coupled between the corresponding second resistor 2R′ and a ground voltage.
- the switches SW 2 (1 ) ⁇ SW 2 (P) are coupled in parallel to the corresponding first resistors R′.
- the first switches and the second switches are complementary. That is, taking R′(1) and 2R′(1) as an example, when the first switch SW 1 (1) is closed such that a current flows by the resistor 2R′(1), the corresponding second switch SW 2 (2) is open.
- the bit resolution of the R ⁇ 2R resistor ladder circuit (R ⁇ 2R) 1 can be adjusted through the first switches SW 1 and the second switches SW 2 .
- each of the first switches SW 1 and the second switches SW 2 receives a control signal outputted by a control logic circuit (not shown in the figure).
- the control logic circuit generates the required control signal in a calibration mode, and outputs the control signal in a normal mode.
- the two stages of amplifiers can be selected to have the same R and C values (referring to Eq. 4) such that the 3 dB bandwidth of the two stages of amplifiers is maintained the same.
- the capacitors C of the two stages of amplifiers cannot match.
- the resistor ladder circuit can be disposed in the second stage of amplifier and the 3 dB bandwidth ⁇ 0 in the first-stage and the second-stage amplifiers can be adjusted to be nearly equal by changing the resistance of the resistor ladder circuit.
- FIG. 5 a circuit diagram of a bandwidth adjustable filter according to another preferred embodiment of the invention is shown.
- the filter in this embodiment is applied to a differential signal system.
- the operational amplifier 210 is a differential amplifier 510 .
- the control logic circuit obtains the difference of the 3 dB bandwidth ( ⁇ 0 ) of signals transmitted at I/Q (in-phase/quadrature-phase) channels of the filtering device 500 .
- the control logic circuit In a normal mode, the control logic circuit outputs the control signal to control the resistor ladder circuit R LADDER1 , or R LADDER2 , or both at the same time such that the I-channel and Q-channel signals of the filtering device 500 have substantially the same 3 dB bandwidth ( ⁇ 0 ). In this way, the minimum scale of bandwidth modulation in the filtering device of the invention is smaller than that of the prior-art filter.
- a low-pass filter structure is taken as an example for illustrating the operation of the operational amplifier.
- the operational amplifier can also be disposed in inverting/non-inverting configuration through a high-pass filter or a band-pass filter structure.
- the filter can improve the modulation resolution of the 3 dB bandwidth by changing the equivalent resistance of the resistor ladder circuit, all these decorations are not apart from the scope of the invention.
Abstract
Description
- This application claims the benefit of Taiwan application Serial No. 94114457, filed May 4, 2005, and U.S. application Ser. No. 11/148,132, filed Jun. 9, 2005, the subject matter of which is incorporated herein by reference.
- 1. Field of the Invention
- The invention relates in general to a filter, and more particularly to a bandwidth-adjustable filter.
- 2. Description of the Related Art
- In wireless communication systems, according to a common modulation mechanism, when in-phase signals (I-channel) and quadrature-phase signals (Q-channel) have different 3 dB bandwidth (ω0) in the filter, these two kinds of signals cannot match in phase. When the signals in the I-channel and in the Q-channel have a phase difference not equal to 90 degrees, the signal constellation is distorted and the bit error rate is thus increased. Therefore, in order to maintain system stability, it is very important that the filter has accurate 3dB bandwidth.
- Referring to
FIG. 1 , a schematic diagram of a filter disposed in a wireless communication system is shown. Thefilter 100 has a closed-loop gain H0 equal to −R3/R2, and has a 3 dB frequency ω0 represented by - When the gain H0 is −1, Eq.1 can be represented by
wherein R1=mR, R2=R, C1=C, C2=nC. - As shown in Eq. 2, by selecting suitable values R and C, the 3 dB frequency ω0 can reach the expected value. In the modulation mechanism of
FIG. 1 , a capacitive array method is used to achieve the modulation of 3 dB frequency by adjusting the valid capacitance C. However, the conventional modulation mechanism has a minimum adjustable scale only about 2˜3%, which cannot meet the requirement of high accuracy for the wireless communication system. - It is therefore an object of the invention to provide a filter. The adjustable bandwidth of the filter can have a higher resolution.
- The invention achieves the above-identified object by providing a filter including an operational amplifier, a first resistor device and a first capacitor. The operational amplifier has a first input terminal, a second input terminal and an output terminal. The first resistor device is coupled to the first input terminal of the operational amplifier. The first capacitor is coupled to the first resistor device and the output terminal of the operational amplifier. The first resistor device has an equivalent resistance and includes a resistor ladder circuit, and the equivalent resistance corresponds to the resistor ladder circuit. The bandwidth of the filtering device corresponds to the equivalent resistance of the first resistor device and capacitance of the first capacitor.
- Preferably, the resistor ladder circuit of the filtering device includes first switches and second switches for changing the resistance of the resistor ladder circuit so as to adjust the bandwidth of the filtering device.
- Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.
-
FIG. 1 (Prior Art) is a schematic diagram of a filter disposed in a wireless communication system -
FIG. 2 is a circuit diagram of a bandwidth-adjustable filter according to a preferred embodiment of the invention. -
FIG. 3 is a circuit diagram of a resistor ladder circuit according to a preferred embodiment of the invention. -
FIG. 4 is a diagram of a resistor ladder circuit configured with switches. -
FIG. 5 is a circuit diagram of a bandwidth adjustable filter according to another preferred embodiment of the invention. - Referring to
FIG. 2 , a circuit diagram of a bandwidth-adjustable filter according to a preferred embodiment of the invention is shown. Thefilter 200 includes anoperational amplifier 210. Theoperational amplifier 210 has a negative input terminal and a positive input terminal coupled to the ground. Theoperational amplifier 210 is a single-input-terminal amplifier preferably. Thefilter 200 further includes a first adjustable resistor R1′, a first capacitor C1, a second capacitor C2, a second resistor R2 and a third resistor R3. The adjustable resistor R1′ has a first terminal defined as a node N1 and a second terminal defined as a node N2. The first terminal of the first adjustable resistor R1′ is coupled to the negative input terminal of theoperational amplifier 210. The first capacitor C1 has a first terminal coupled to the node N1 and a second terminal coupled to the output terminal of theoperational amplifier 210. The second capacitor C2 has a first terminal grounded and a second terminal coupled to the node N2. The second resistor R2 is coupled to the node N2, and the third resistor R3 is coupled between the node N2 and the output terminal of theoperational amplifier 210, wherein the output terminal is for outputting an output voltage V0. - As shown in Eq. 2, the 3 dB frequency ω0 of the
filter 200 inFIG. 2 can be represented by
wherein R1′=m′×R, R2=R, C1=C, C2=n×C. - From Eq. 3, it can be known that the 3 dB frequency ω0 of the
filter 200 can be effectively controlled by adjusting the first adjustable resistor R1′. In the embodiment, a resistor ladder circuit RLADDER1 is used to finely adjust the value of the first adjustable resistor R1′ so as to achieve the purpose of controlling the 3dB frequency ω0 accurately. In the embodiment, the first adjustable resistor R1′ includes the resistor ladder circuit RLADDER1 coupled in parallel to a first resistor R1. The resistor ladder circuit RLADDER1 has one terminal coupled to the node N2 and the other terminal coupled to the node N1. - Referring to
FIG. 3 , a circuit diagram of a resistor ladder circuit RLADDER1 according to a preferred embodiment of the invention is shown. In the embodiment, the resistor ladder circuit RLADDER1 is an R-2R resistor ladder circuit (R−2R)1, and the R−2R resistor ladder circuit (R−2R), includes a plurality ofsecond resistors 2R′, first resistors R′ and third resistors Rt. The resistance of thesecond resistor 2R′ is preferably twice of the resistance of the first resistor R′. The second resistors are denoted sequentially by thesecond resistor 2R′(1)˜2R′(P), wherein P is a positive integer. Each of thesecond resistors 2R′ has a first terminal a1 grounded. The second terminals a2 of thesecond resistor 2R′(1) and the first resistor R′(1) are coupled to the node N2. The first resistors are denoted sequentially by R′(1)˜R′(P−1). Each of the first resistor R′ is coupled between the second terminals a2 of the two corresponding adjacentsecond resistors 2R′. The third resistor Rt has a first terminal coupled to the second terminal a2 of thesecond resistor 2R′(P) and a second terminal coupled to the node N1. The third resistor Rt and thesecond resistor 2R′ have substantially the same resistance preferably. - The
second resistors 2R′(1)˜2R′(P) are arranged respectively in correspondence to the first resistors R′(1)˜R′(P−1) and the third resistor Rt. Each of thesecond resistors 2R′combined with the corresponding first resistor R′ is called a resistor pair. For example, thesecond resistor 2R′(i) and the first resistor R′(i) form a resistor pair, wherein 0<i<P, and thesecond resistor 2R′(P) and the third resistor Rt form a resistor pair. The equivalent resistance of the R−2R resistor ladder circuit is 2P×R′. - If the first resistor R1 of the first adjustable resistor R1′ is m×R, and the equivalent resistance of the R−2R resistor ladder circuit is 2P×R, the equivalent resistance of the first adjustable resistor R1′ can be obtained by the following formulation.
- Therefore, the equivalent resistance of the first adjustable resistor R1′ can be adjusted by increasing or decreasing the number of resistor pairs, i.e. the P value.
- Another method for adjusting the resistance of the resistor ladder circuit is referred to
FIG. 4 , which shows a resistor ladder circuit (RLADDER1) configured with switches. In the embodiment, the resistor ladder circuit (RLADDER1) is an R−2R resistor ladder circuit (R−2R)1, the R−2R resistor ladder circuit (R−2R)1 includes a plurality of first switches, which are sequentially denoted by SW1(1)˜SW1(P), and a plurality of second switches, which are sequentially denoted by SW2(1)˜SW2(P). The switch SW1(1), . . . , or SW1(P) is coupled between the correspondingsecond resistor 2R′ and a ground voltage. The switches SW2(1 )˜SW2(P) are coupled in parallel to the corresponding first resistors R′. - In practical operation, the first switches and the second switches are complementary. That is, taking R′(1) and 2R′(1) as an example, when the first switch SW1(1) is closed such that a current flows by the
resistor 2R′(1), the corresponding second switch SW2(2) is open. In other words, when the first switch SW1(1) is open, the corresponding first resistor R′(1) is open relative to the ground voltage, and when the second switch SW2(1) is closed, the corresponding first resistor R′(1) is short-cut. Therefore, the bit resolution of the R−2R resistor ladder circuit (R−2R)1 can be adjusted through the first switches SW1 and the second switches SW2. The effect that P is equal to K can be achieved by turning on K first switches and turning off the corresponding K second switches. Accordingly, P=6 when all the first SW1 are turned on and the second switches are turned off in the R−2R resistor ladder circuit, and P=4 when two of the first switches SW1 are turned off and the two corresponding second switches are closed. - The larger the P value is, the more accurately the 3 dB bandwidth of the filter can be adjusted. In a practical experiment, the 7 stage (p=7) R−2R resistor ladder circuit can have 0.88% resolution, that is, a 0.88% fine-tuning scale. Therefore, the method of the invention can be applied to an I/Q signal application having low error tolerance. Each of the first switches SW1 and the second switches SW2 receives a control signal outputted by a control logic circuit (not shown in the figure). In one embodiment, the control logic circuit generates the required control signal in a calibration mode, and outputs the control signal in a normal mode.
- Besides, when the filter has two stages of amplifiers, the two stages of amplifiers can be selected to have the same R and C values (referring to Eq. 4) such that the 3 dB bandwidth of the two stages of amplifiers is maintained the same. However, when there exists uncontrollable deviation in manufacturing process, the capacitors C of the two stages of amplifiers cannot match. Under this situation, the resistor ladder circuit can be disposed in the second stage of amplifier and the 3 dB bandwidth ω0 in the first-stage and the second-stage amplifiers can be adjusted to be nearly equal by changing the resistance of the resistor ladder circuit.
- Referring to
FIG. 5 , a circuit diagram of a bandwidth adjustable filter according to another preferred embodiment of the invention is shown. The filter in this embodiment is applied to a differential signal system. Theoperational amplifier 210 is adifferential amplifier 510. In a calibration mode, the control logic circuit (not shown in the figure) obtains the difference of the 3 dB bandwidth (ω0) of signals transmitted at I/Q (in-phase/quadrature-phase) channels of thefiltering device 500. In a normal mode, the control logic circuit outputs the control signal to control the resistor ladder circuit RLADDER1, or RLADDER2, or both at the same time such that the I-channel and Q-channel signals of thefiltering device 500 have substantially the same 3 dB bandwidth (ω0). In this way, the minimum scale of bandwidth modulation in the filtering device of the invention is smaller than that of the prior-art filter. - According to the above-mentioned embodiments of the invention, a low-pass filter structure is taken as an example for illustrating the operation of the operational amplifier. However, the operational amplifier can also be disposed in inverting/non-inverting configuration through a high-pass filter or a band-pass filter structure. As long as the filter can improve the modulation resolution of the 3 dB bandwidth by changing the equivalent resistance of the resistor ladder circuit, all these decorations are not apart from the scope of the invention.
- While the invention has been described by way of example and in terms of two preferred embodiments, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
Claims (17)
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US11/381,548 US7737772B2 (en) | 2003-12-31 | 2006-05-04 | Bandwidth-adjustable filter |
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US10/748,667 US7138869B2 (en) | 2003-01-10 | 2003-12-31 | Amplifier circuit |
TW093117032 | 2004-06-14 | ||
TW93117032A TWI241765B (en) | 2004-06-14 | 2004-06-14 | Variable gain amplifying circuit |
TW93117032A | 2004-06-14 | ||
TW094114457A TWI257202B (en) | 2005-05-04 | 2005-05-04 | Filter of tunable bandwidth |
TW94114457 | 2005-05-04 | ||
TW94114457A | 2005-05-04 | ||
US11/148,132 US7102441B2 (en) | 2003-12-31 | 2005-06-08 | Variable gain amplifying circuit |
US11/381,548 US7737772B2 (en) | 2003-12-31 | 2006-05-04 | Bandwidth-adjustable filter |
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US11/148,132 Continuation-In-Part US7102441B2 (en) | 2003-12-31 | 2005-06-08 | Variable gain amplifying circuit |
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US20100060348A9 true US20100060348A9 (en) | 2010-03-11 |
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US7876148B2 (en) * | 2007-12-28 | 2011-01-25 | Hynix Semiconductor Inc. | Low pass filter and lock detector circuit |
Also Published As
Publication number | Publication date |
---|---|
TW200640128A (en) | 2006-11-16 |
US7737772B2 (en) | 2010-06-15 |
TWI257202B (en) | 2006-06-21 |
US20060250181A1 (en) | 2006-11-09 |
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