US20100060348A9 - Bandwidth-adjustable filter - Google Patents

Bandwidth-adjustable filter Download PDF

Info

Publication number
US20100060348A9
US20100060348A9 US11/381,548 US38154806A US2010060348A9 US 20100060348 A9 US20100060348 A9 US 20100060348A9 US 38154806 A US38154806 A US 38154806A US 2010060348 A9 US2010060348 A9 US 2010060348A9
Authority
US
United States
Prior art keywords
resistor
coupled
filtering device
ladder circuit
resistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US11/381,548
Other versions
US7737772B2 (en
US20060250181A1 (en
Inventor
Chao-Cheng Lee
Ying-Yao Lin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Realtek Semiconductor Corp
Original Assignee
Realtek Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/748,667 external-priority patent/US7138869B2/en
Priority claimed from TW93117032A external-priority patent/TWI241765B/en
Priority claimed from US11/148,132 external-priority patent/US7102441B2/en
Application filed by Realtek Semiconductor Corp filed Critical Realtek Semiconductor Corp
Priority to US11/381,548 priority Critical patent/US7737772B2/en
Assigned to REALTEK SEMICONDUCTOR CORP. reassignment REALTEK SEMICONDUCTOR CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LEE, CHAO-CHENG, LIN, YING-YAO
Publication of US20060250181A1 publication Critical patent/US20060250181A1/en
Publication of US20100060348A9 publication Critical patent/US20100060348A9/en
Application granted granted Critical
Publication of US7737772B2 publication Critical patent/US7737772B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01Shaping pulses
    • H03K5/08Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
    • H03K5/082Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold
    • H03K5/086Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold generated by feedback
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00Networks using active elements
    • H03H11/02Multiple-port networks
    • H03H11/04Frequency selective two-port networks
    • H03H11/12Frequency selective two-port networks using amplifiers with feedback
    • H03H11/126Frequency selective two-port networks using amplifiers with feedback using a single operational amplifier
    • H03H11/1286Sallen-Key biquad
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00Networks using active elements
    • H03H11/02Multiple-port networks
    • H03H11/04Frequency selective two-port networks
    • H03H11/12Frequency selective two-port networks using amplifiers with feedback
    • H03H11/1291Current or voltage controlled filters

Definitions

  • the invention relates in general to a filter, and more particularly to a bandwidth-adjustable filter.
  • in-phase signals I-channel
  • quadrature-phase signals Q-channel
  • these two kinds of signals cannot match in phase.
  • the signals in the I-channel and in the Q-channel have a phase difference not equal to 90 degrees, the signal constellation is distorted and the bit error rate is thus increased. Therefore, in order to maintain system stability, it is very important that the filter has accurate 3dB bandwidth.
  • FIG. 1 a schematic diagram of a filter disposed in a wireless communication system is shown.
  • the 3 dB frequency ⁇ 0 can reach the expected value.
  • a capacitive array method is used to achieve the modulation of 3 dB frequency by adjusting the valid capacitance C.
  • the conventional modulation mechanism has a minimum adjustable scale only about 2 ⁇ 3%, which cannot meet the requirement of high accuracy for the wireless communication system.
  • the adjustable bandwidth of the filter can have a higher resolution.
  • the invention achieves the above-identified object by providing a filter including an operational amplifier, a first resistor device and a first capacitor.
  • the operational amplifier has a first input terminal, a second input terminal and an output terminal.
  • the first resistor device is coupled to the first input terminal of the operational amplifier.
  • the first capacitor is coupled to the first resistor device and the output terminal of the operational amplifier.
  • the first resistor device has an equivalent resistance and includes a resistor ladder circuit, and the equivalent resistance corresponds to the resistor ladder circuit.
  • the bandwidth of the filtering device corresponds to the equivalent resistance of the first resistor device and capacitance of the first capacitor.
  • the resistor ladder circuit of the filtering device includes first switches and second switches for changing the resistance of the resistor ladder circuit so as to adjust the bandwidth of the filtering device.
  • FIG. 1 (Prior Art) is a schematic diagram of a filter disposed in a wireless communication system
  • FIG. 2 is a circuit diagram of a bandwidth-adjustable filter according to a preferred embodiment of the invention.
  • FIG. 3 is a circuit diagram of a resistor ladder circuit according to a preferred embodiment of the invention.
  • FIG. 4 is a diagram of a resistor ladder circuit configured with switches.
  • FIG. 5 is a circuit diagram of a bandwidth adjustable filter according to another preferred embodiment of the invention.
  • the filter 200 includes an operational amplifier 210 .
  • the operational amplifier 210 has a negative input terminal and a positive input terminal coupled to the ground.
  • the operational amplifier 210 is a single-input-terminal amplifier preferably.
  • the filter 200 further includes a first adjustable resistor R 1 ′, a first capacitor C 1 , a second capacitor C 2 , a second resistor R 2 and a third resistor R 3 .
  • the adjustable resistor R 1 ′ has a first terminal defined as a node N 1 and a second terminal defined as a node N 2 .
  • the first terminal of the first adjustable resistor R 1 ′ is coupled to the negative input terminal of the operational amplifier 210 .
  • the first capacitor C 1 has a first terminal coupled to the node N 1 and a second terminal coupled to the output terminal of the operational amplifier 210 .
  • the second capacitor C 2 has a first terminal grounded and a second terminal coupled to the node N 2 .
  • the second resistor R 2 is coupled to the node N 2
  • the third resistor R 3 is coupled between the node N 2 and the output terminal of the operational amplifier 210 , wherein the output terminal is for outputting an output voltage V 0 .
  • the 3 dB frequency ⁇ 0 of the filter 200 can be effectively controlled by adjusting the first adjustable resistor R 1 ′.
  • a resistor ladder circuit R LADDER1 is used to finely adjust the value of the first adjustable resistor R 1 ′ so as to achieve the purpose of controlling the 3dB frequency ⁇ 0 accurately.
  • the first adjustable resistor R 1 ′ includes the resistor ladder circuit R LADDER1 coupled in parallel to a first resistor R 1 .
  • the resistor ladder circuit R LADDER1 has one terminal coupled to the node N 2 and the other terminal coupled to the node N 1 .
  • the resistor ladder circuit R LADDER1 is an R-2R resistor ladder circuit (R ⁇ 2R) 1
  • the R ⁇ 2R resistor ladder circuit (R ⁇ 2R) includes a plurality of second resistors 2R′, first resistors R′ and third resistors Rt.
  • the resistance of the second resistor 2R′ is preferably twice of the resistance of the first resistor R′.
  • the second resistors are denoted sequentially by the second resistor 2R′(1) ⁇ 2R′(P), wherein P is a positive integer.
  • Each of the second resistors 2R′ has a first terminal a 1 grounded.
  • the second terminals a 2 of the second resistor 2R′(1) and the first resistor R′(1) are coupled to the node N 2 .
  • the first resistors are denoted sequentially by R′(1) ⁇ R′(P ⁇ 1).
  • Each of the first resistor R′ is coupled between the second terminals a 2 of the two corresponding adjacent second resistors 2R′.
  • the third resistor Rt has a first terminal coupled to the second terminal a 2 of the second resistor 2R′(P) and a second terminal coupled to the node N 1 .
  • the third resistor Rt and the second resistor 2R′ have substantially the same resistance preferably.
  • the second resistors 2R′(1) ⁇ 2R′(P) are arranged respectively in correspondence to the first resistors R′(1) ⁇ R′(P ⁇ 1) and the third resistor Rt.
  • Each of the second resistors 2R′combined with the corresponding first resistor R′ is called a resistor pair.
  • the second resistor 2R′(i) and the first resistor R′(i) form a resistor pair, wherein 0 ⁇ i ⁇ P, and the second resistor 2R′(P) and the third resistor Rt form a resistor pair.
  • the equivalent resistance of the R ⁇ 2R resistor ladder circuit is 2 P ⁇ R′.
  • the equivalent resistance of the first adjustable resistor R 1 ′ can be obtained by the following formulation.
  • the equivalent resistance of the first adjustable resistor R 1 ′ can be adjusted by increasing or decreasing the number of resistor pairs, i.e. the P value.
  • FIG. 4 shows a resistor ladder circuit (R LADDER1 ) configured with switches.
  • the resistor ladder circuit (R LADDER1 ) is an R ⁇ 2R resistor ladder circuit (R ⁇ 2R) 1
  • the R ⁇ 2R resistor ladder circuit (R ⁇ 2R) 1 includes a plurality of first switches, which are sequentially denoted by SW 1 (1) ⁇ SW 1 (P), and a plurality of second switches, which are sequentially denoted by SW 2 (1) ⁇ SW 2 (P).
  • the switch SW 1 (1), . . . , or SW 1 (P) is coupled between the corresponding second resistor 2R′ and a ground voltage.
  • the switches SW 2 (1 ) ⁇ SW 2 (P) are coupled in parallel to the corresponding first resistors R′.
  • the first switches and the second switches are complementary. That is, taking R′(1) and 2R′(1) as an example, when the first switch SW 1 (1) is closed such that a current flows by the resistor 2R′(1), the corresponding second switch SW 2 (2) is open.
  • the bit resolution of the R ⁇ 2R resistor ladder circuit (R ⁇ 2R) 1 can be adjusted through the first switches SW 1 and the second switches SW 2 .
  • each of the first switches SW 1 and the second switches SW 2 receives a control signal outputted by a control logic circuit (not shown in the figure).
  • the control logic circuit generates the required control signal in a calibration mode, and outputs the control signal in a normal mode.
  • the two stages of amplifiers can be selected to have the same R and C values (referring to Eq. 4) such that the 3 dB bandwidth of the two stages of amplifiers is maintained the same.
  • the capacitors C of the two stages of amplifiers cannot match.
  • the resistor ladder circuit can be disposed in the second stage of amplifier and the 3 dB bandwidth ⁇ 0 in the first-stage and the second-stage amplifiers can be adjusted to be nearly equal by changing the resistance of the resistor ladder circuit.
  • FIG. 5 a circuit diagram of a bandwidth adjustable filter according to another preferred embodiment of the invention is shown.
  • the filter in this embodiment is applied to a differential signal system.
  • the operational amplifier 210 is a differential amplifier 510 .
  • the control logic circuit obtains the difference of the 3 dB bandwidth ( ⁇ 0 ) of signals transmitted at I/Q (in-phase/quadrature-phase) channels of the filtering device 500 .
  • the control logic circuit In a normal mode, the control logic circuit outputs the control signal to control the resistor ladder circuit R LADDER1 , or R LADDER2 , or both at the same time such that the I-channel and Q-channel signals of the filtering device 500 have substantially the same 3 dB bandwidth ( ⁇ 0 ). In this way, the minimum scale of bandwidth modulation in the filtering device of the invention is smaller than that of the prior-art filter.
  • a low-pass filter structure is taken as an example for illustrating the operation of the operational amplifier.
  • the operational amplifier can also be disposed in inverting/non-inverting configuration through a high-pass filter or a band-pass filter structure.
  • the filter can improve the modulation resolution of the 3 dB bandwidth by changing the equivalent resistance of the resistor ladder circuit, all these decorations are not apart from the scope of the invention.

Abstract

A bandwidth-adjustable filter includes an operational amplifier, a first resistor, a first capacitor and a first resistor ladder circuit. The operational amplifier has a negative input terminal and a positive input terminal The first resistor is coupled to one of the input terminals of the operational amplifier. The first capacitor is coupled to the first resistor. The first resistor ladder circuit is coupled in parallel to the first resistor for changing the resistance of the first resistor so as to adjust the bandwidth of the filter.

Description

  • This application claims the benefit of Taiwan application Serial No. 94114457, filed May 4, 2005, and U.S. application Ser. No. 11/148,132, filed Jun. 9, 2005, the subject matter of which is incorporated herein by reference.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The invention relates in general to a filter, and more particularly to a bandwidth-adjustable filter.
  • 2. Description of the Related Art
  • In wireless communication systems, according to a common modulation mechanism, when in-phase signals (I-channel) and quadrature-phase signals (Q-channel) have different 3 dB bandwidth (ω0) in the filter, these two kinds of signals cannot match in phase. When the signals in the I-channel and in the Q-channel have a phase difference not equal to 90 degrees, the signal constellation is distorted and the bit error rate is thus increased. Therefore, in order to maintain system stability, it is very important that the filter has accurate 3dB bandwidth.
  • Referring to FIG. 1, a schematic diagram of a filter disposed in a wireless communication system is shown. The filter 100 has a closed-loop gain H0 equal to −R3/R2, and has a 3 dB frequency ω0 represented by ω 0 = 1 R 1 × R 3 × C 2 × C 1 Eq . 1
  • When the gain H0 is −1, Eq.1 can be represented by ω 0 = 1 m × n × R × C Eq . 2
    wherein R1=mR, R2=R, C1=C, C2=nC.
  • As shown in Eq. 2, by selecting suitable values R and C, the 3 dB frequency ω0 can reach the expected value. In the modulation mechanism of FIG. 1, a capacitive array method is used to achieve the modulation of 3 dB frequency by adjusting the valid capacitance C. However, the conventional modulation mechanism has a minimum adjustable scale only about 2˜3%, which cannot meet the requirement of high accuracy for the wireless communication system.
  • SUMMARY OF THE INVENTION
  • It is therefore an object of the invention to provide a filter. The adjustable bandwidth of the filter can have a higher resolution.
  • The invention achieves the above-identified object by providing a filter including an operational amplifier, a first resistor device and a first capacitor. The operational amplifier has a first input terminal, a second input terminal and an output terminal. The first resistor device is coupled to the first input terminal of the operational amplifier. The first capacitor is coupled to the first resistor device and the output terminal of the operational amplifier. The first resistor device has an equivalent resistance and includes a resistor ladder circuit, and the equivalent resistance corresponds to the resistor ladder circuit. The bandwidth of the filtering device corresponds to the equivalent resistance of the first resistor device and capacitance of the first capacitor.
  • Preferably, the resistor ladder circuit of the filtering device includes first switches and second switches for changing the resistance of the resistor ladder circuit so as to adjust the bandwidth of the filtering device.
  • Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 (Prior Art) is a schematic diagram of a filter disposed in a wireless communication system
  • FIG. 2 is a circuit diagram of a bandwidth-adjustable filter according to a preferred embodiment of the invention.
  • FIG. 3 is a circuit diagram of a resistor ladder circuit according to a preferred embodiment of the invention.
  • FIG. 4 is a diagram of a resistor ladder circuit configured with switches.
  • FIG. 5 is a circuit diagram of a bandwidth adjustable filter according to another preferred embodiment of the invention.
  • DETAILED DESCRIPTION OF THE INVENTION
  • Referring to FIG. 2, a circuit diagram of a bandwidth-adjustable filter according to a preferred embodiment of the invention is shown. The filter 200 includes an operational amplifier 210. The operational amplifier 210 has a negative input terminal and a positive input terminal coupled to the ground. The operational amplifier 210 is a single-input-terminal amplifier preferably. The filter 200 further includes a first adjustable resistor R1′, a first capacitor C1, a second capacitor C2, a second resistor R2 and a third resistor R3. The adjustable resistor R1′ has a first terminal defined as a node N1 and a second terminal defined as a node N2. The first terminal of the first adjustable resistor R1′ is coupled to the negative input terminal of the operational amplifier 210. The first capacitor C1 has a first terminal coupled to the node N1 and a second terminal coupled to the output terminal of the operational amplifier 210. The second capacitor C2 has a first terminal grounded and a second terminal coupled to the node N2. The second resistor R2 is coupled to the node N2, and the third resistor R3 is coupled between the node N2 and the output terminal of the operational amplifier 210, wherein the output terminal is for outputting an output voltage V0.
  • As shown in Eq. 2, the 3 dB frequency ω0 of the filter 200 in FIG. 2 can be represented by ω 0 = 1 m × n × R × C Eq . 3
    wherein R1′=m′×R, R2=R, C1=C, C2=n×C.
  • From Eq. 3, it can be known that the 3 dB frequency ω0 of the filter 200 can be effectively controlled by adjusting the first adjustable resistor R1′. In the embodiment, a resistor ladder circuit RLADDER1 is used to finely adjust the value of the first adjustable resistor R1′ so as to achieve the purpose of controlling the 3dB frequency ω0 accurately. In the embodiment, the first adjustable resistor R1′ includes the resistor ladder circuit RLADDER1 coupled in parallel to a first resistor R1. The resistor ladder circuit RLADDER1 has one terminal coupled to the node N2 and the other terminal coupled to the node N1.
  • Referring to FIG. 3, a circuit diagram of a resistor ladder circuit RLADDER1 according to a preferred embodiment of the invention is shown. In the embodiment, the resistor ladder circuit RLADDER1 is an R-2R resistor ladder circuit (R−2R)1, and the R−2R resistor ladder circuit (R−2R), includes a plurality of second resistors 2R′, first resistors R′ and third resistors Rt. The resistance of the second resistor 2R′ is preferably twice of the resistance of the first resistor R′. The second resistors are denoted sequentially by the second resistor 2R′(1)˜2R′(P), wherein P is a positive integer. Each of the second resistors 2R′ has a first terminal a1 grounded. The second terminals a2 of the second resistor 2R′(1) and the first resistor R′(1) are coupled to the node N2. The first resistors are denoted sequentially by R′(1)˜R′(P−1). Each of the first resistor R′ is coupled between the second terminals a2 of the two corresponding adjacent second resistors 2R′. The third resistor Rt has a first terminal coupled to the second terminal a2 of the second resistor 2R′(P) and a second terminal coupled to the node N1. The third resistor Rt and the second resistor 2R′ have substantially the same resistance preferably.
  • The second resistors 2R′(1)˜2R′(P) are arranged respectively in correspondence to the first resistors R′(1)˜R′(P−1) and the third resistor Rt. Each of the second resistors 2R′combined with the corresponding first resistor R′ is called a resistor pair. For example, the second resistor 2R′(i) and the first resistor R′(i) form a resistor pair, wherein 0<i<P, and the second resistor 2R′(P) and the third resistor Rt form a resistor pair. The equivalent resistance of the R−2R resistor ladder circuit is 2P×R′.
  • If the first resistor R1 of the first adjustable resistor R1′ is m×R, and the equivalent resistance of the R−2R resistor ladder circuit is 2P×R, the equivalent resistance of the first adjustable resistor R1′ can be obtained by the following formulation. R 1 = m × R = m × R // 2 P × R = ( m - m 2 2 p + m ) × R , and m = ( m - m 2 2 p + m )
  • Therefore, the equivalent resistance of the first adjustable resistor R1′ can be adjusted by increasing or decreasing the number of resistor pairs, i.e. the P value.
  • Another method for adjusting the resistance of the resistor ladder circuit is referred to FIG. 4, which shows a resistor ladder circuit (RLADDER1) configured with switches. In the embodiment, the resistor ladder circuit (RLADDER1) is an R−2R resistor ladder circuit (R−2R)1, the R−2R resistor ladder circuit (R−2R)1 includes a plurality of first switches, which are sequentially denoted by SW1(1)˜SW1(P), and a plurality of second switches, which are sequentially denoted by SW2(1)˜SW2(P). The switch SW1(1), . . . , or SW1(P) is coupled between the corresponding second resistor 2R′ and a ground voltage. The switches SW2(1 )˜SW2(P) are coupled in parallel to the corresponding first resistors R′.
  • In practical operation, the first switches and the second switches are complementary. That is, taking R′(1) and 2R′(1) as an example, when the first switch SW1(1) is closed such that a current flows by the resistor 2R′(1), the corresponding second switch SW2(2) is open. In other words, when the first switch SW1(1) is open, the corresponding first resistor R′(1) is open relative to the ground voltage, and when the second switch SW2(1) is closed, the corresponding first resistor R′(1) is short-cut. Therefore, the bit resolution of the R−2R resistor ladder circuit (R−2R)1 can be adjusted through the first switches SW1 and the second switches SW2. The effect that P is equal to K can be achieved by turning on K first switches and turning off the corresponding K second switches. Accordingly, P=6 when all the first SW1 are turned on and the second switches are turned off in the R−2R resistor ladder circuit, and P=4 when two of the first switches SW1 are turned off and the two corresponding second switches are closed.
  • The larger the P value is, the more accurately the 3 dB bandwidth of the filter can be adjusted. In a practical experiment, the 7 stage (p=7) R−2R resistor ladder circuit can have 0.88% resolution, that is, a 0.88% fine-tuning scale. Therefore, the method of the invention can be applied to an I/Q signal application having low error tolerance. Each of the first switches SW1 and the second switches SW2 receives a control signal outputted by a control logic circuit (not shown in the figure). In one embodiment, the control logic circuit generates the required control signal in a calibration mode, and outputs the control signal in a normal mode.
  • Besides, when the filter has two stages of amplifiers, the two stages of amplifiers can be selected to have the same R and C values (referring to Eq. 4) such that the 3 dB bandwidth of the two stages of amplifiers is maintained the same. However, when there exists uncontrollable deviation in manufacturing process, the capacitors C of the two stages of amplifiers cannot match. Under this situation, the resistor ladder circuit can be disposed in the second stage of amplifier and the 3 dB bandwidth ω0 in the first-stage and the second-stage amplifiers can be adjusted to be nearly equal by changing the resistance of the resistor ladder circuit.
  • Referring to FIG. 5, a circuit diagram of a bandwidth adjustable filter according to another preferred embodiment of the invention is shown. The filter in this embodiment is applied to a differential signal system. The operational amplifier 210 is a differential amplifier 510. In a calibration mode, the control logic circuit (not shown in the figure) obtains the difference of the 3 dB bandwidth (ω0) of signals transmitted at I/Q (in-phase/quadrature-phase) channels of the filtering device 500. In a normal mode, the control logic circuit outputs the control signal to control the resistor ladder circuit RLADDER1, or RLADDER2, or both at the same time such that the I-channel and Q-channel signals of the filtering device 500 have substantially the same 3 dB bandwidth (ω0). In this way, the minimum scale of bandwidth modulation in the filtering device of the invention is smaller than that of the prior-art filter.
  • According to the above-mentioned embodiments of the invention, a low-pass filter structure is taken as an example for illustrating the operation of the operational amplifier. However, the operational amplifier can also be disposed in inverting/non-inverting configuration through a high-pass filter or a band-pass filter structure. As long as the filter can improve the modulation resolution of the 3 dB bandwidth by changing the equivalent resistance of the resistor ladder circuit, all these decorations are not apart from the scope of the invention.
  • While the invention has been described by way of example and in terms of two preferred embodiments, it is to be understood that the invention is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.

Claims (17)

1. A filtering device, comprising:
an operational amplifier, having a first input, a second input and an output;
a first resistor device, coupled to the first input of the operational amplifier; and
a first capacitor, coupled to the first resistor device and the output of the operational amplifier;
wherein the first resistor device has an equivalent resistance and includes a resistor ladder circuit, and the equivalent resistance corresponds to the resistor ladder circuit;
wherein the bandwidth of the filtering device corresponds to the equivalent resistance of the first resistor device and capacitance of the first capacitor.
2. The filtering device according to claim 1, wherein the bandwidth of the filtering device can be adjusted by changing a stage number of the resistor ladder circuit.
3. The filtering device according to claim 2, wherein the resistor ladder circuit is an R−2R resistor ladder circuit.
4. The filtering device according to claim 2, further comprising:
a second capacitor, having one terminal grounded and the other terminal coupled to the first resistor device;
a second resistor device, coupled to the first resistor device and the second capacitor; and
a third resistor device, having one terminal coupled to the first resistor device and the second capacitor, and the other terminal coupled to the output of the operational amplifier.
5. The filtering device according to claim 1, wherein the resistor ladder circuit comprises:
a plurality of second resistors, each of the second resistors having a first terminal grounded;
a plurality of first resistors, coupled to second terminals of the second resistors; and
a third resistor, coupled in series to the last one of the first resistors.
6. The filtering device according to claim 5, wherein the resistance of the first resistor is substantially twice of the resistance of the second resistor.
7. The filtering device according to claim 5, wherein the resistor ladder circuit further comprises:
a plurality of first switches, coupled between the second resistors and a ground; and
a plurality of second switches, respectively coupled in parallel to the first resistors;
wherein the first switches and the second switches are complementary.
8. The filtering device according to claim 7, wherein the bandwidth of the filtering device is adjusted by controlling the first switches and the second switches.
9. The filtering device according to claim 1, wherein the bandwidth modulation of the filtering device has a minimum scale smaller than 3%.
10. A filtering device, comprising:
a differential amplifier, having a first input, a second input, a first output and a second output;
a first resistor device, coupled to the first input of the differential amplifier;
a first resistor device, coupled to the second input of the differential amplifier;
a first capacitor, coupled to the first resistor device;
a second capacitor, coupled to the second resistor device; and
wherein the first resistor device has an equivalent resistance and includes a first resistor ladder circuit, and the equivalent resistance corresponds to the first resistor ladder circuit;
wherein by adjusting the first resistor ladder circuit, the multiplication of the equivalent resistance of the first resistor device and the capacitance of the first capacitor is substantially the same as the multiplication of the resistance of the second resistor device and the capacitance of the second capacitor.
11. The filtering device according to claim 10, wherein the bandwidth of the filtering device is adjusted by changing a stage number of the first resistor ladder circuit.
12. The filtering device according to claim 11, wherein the first resistor ladder circuit is an R−2R resistor ladder circuit.
13. The filtering device according to claim 11, wherein the first resistor ladder circuit comprises:
a plurality of second resistors, each of the second resistors having a first terminal grounded;
a plurality of first resistors, respectively coupled to second terminals of the second resistors; and
a third resistor, coupled in series to the last one of the first resistors.
14. The filtering device according to claim 13, wherein the first resistor ladder circuit further comprise:
a plurality of first switches, coupled between the second resistors and a ground; and
a plurality of second switches, coupled in parallel to the first resistors;
wherein the first switches and the second switches are complementary.
15. The filtering device according to claim 14, wherein the bandwidth of the filtering device is adjusted by controlling the first switches and the second switches.
16. The filtering device according to claim 10, wherein the bandwidth modulation of the filtering device has a minimum scale smaller than 3%.
17. The filtering device according to claim 10, wherein the second resistor device includes a second resistor ladder circuit.
US11/381,548 2003-12-31 2006-05-04 Bandwidth-adjustable filter Expired - Lifetime US7737772B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/381,548 US7737772B2 (en) 2003-12-31 2006-05-04 Bandwidth-adjustable filter

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US10/748,667 US7138869B2 (en) 2003-01-10 2003-12-31 Amplifier circuit
TW093117032 2004-06-14
TW93117032A TWI241765B (en) 2004-06-14 2004-06-14 Variable gain amplifying circuit
TW93117032A 2004-06-14
TW094114457A TWI257202B (en) 2005-05-04 2005-05-04 Filter of tunable bandwidth
TW94114457 2005-05-04
TW94114457A 2005-05-04
US11/148,132 US7102441B2 (en) 2003-12-31 2005-06-08 Variable gain amplifying circuit
US11/381,548 US7737772B2 (en) 2003-12-31 2006-05-04 Bandwidth-adjustable filter

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US11/148,132 Continuation-In-Part US7102441B2 (en) 2003-12-31 2005-06-08 Variable gain amplifying circuit

Publications (3)

Publication Number Publication Date
US20060250181A1 US20060250181A1 (en) 2006-11-09
US20100060348A9 true US20100060348A9 (en) 2010-03-11
US7737772B2 US7737772B2 (en) 2010-06-15

Family

ID=37393500

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/381,548 Expired - Lifetime US7737772B2 (en) 2003-12-31 2006-05-04 Bandwidth-adjustable filter

Country Status (2)

Country Link
US (1) US7737772B2 (en)
TW (1) TWI257202B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090168944A1 (en) * 2007-12-28 2009-07-02 Hynix Semiconductor, Inc. Low pass filter and lock detector circuit

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7812746B2 (en) 2005-12-14 2010-10-12 Broadcom Corporation Variable gain and multiplexing in a digital calibration for an analog-to-digital converter
US7466249B2 (en) * 2005-12-14 2008-12-16 Broadcom Corporation System and method for common mode calibration in an analog to digital converter
US7843368B2 (en) * 2005-12-14 2010-11-30 Broadcom Corporation Programmable settling for high speed analog to digital converter
US7456764B2 (en) * 2005-12-14 2008-11-25 Broadcom Corporation Analog to digital converter with dynamic power configuration
US8378731B1 (en) * 2010-06-14 2013-02-19 Marvell International Ltd. Asymmetric correction circuit with negative resistance
US10263581B2 (en) * 2016-09-30 2019-04-16 Analog Devices, Inc. Amplifier calibration
US10340891B1 (en) * 2017-12-19 2019-07-02 Quantenna Communications, Inc. Differential elliptic filter with a single op-amp
CN110380692B (en) * 2019-06-28 2020-11-24 上海类比半导体技术有限公司 Trimming circuit of differential amplifier
RU2718212C1 (en) * 2019-11-21 2020-03-31 федеральное государственное бюджетное образовательное учреждение высшего образования "Донской государственный технический университет" (ДГТУ) Universal programmable arc-filter

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US552598A (en) * 1896-01-07 tucker
US560492A (en) * 1896-05-19 Valve for pneumatic tires
US591738A (en) * 1897-10-12 cheney
US670368A (en) * 1901-01-02 1901-03-19 William Lumsdon Byers Pivoted anchor.
US673116A (en) * 1900-09-06 1901-04-30 Talbot C Dexter Means for protecting printing-presses.
US5455582A (en) * 1992-12-17 1995-10-03 Ulsi Technology, Inc. Digital to analog converter employing R-2R ladders with substituted shunt arms
US6127893A (en) * 1998-09-18 2000-10-03 Tripath Technology, Inc. Method and apparatus for controlling an audio signal level
US6344780B1 (en) * 1998-09-18 2002-02-05 Kabushiki Kaisha Toshiba Impedance adjusting circuit
US6545534B1 (en) * 2001-02-13 2003-04-08 Analog Devices, Inc. Low voltage variable gain amplifier with constant input impedance and adjustable one-pole filtering characteristic
US6693491B1 (en) * 2000-04-17 2004-02-17 Tripath Technology, Inc. Method and apparatus for controlling an audio signal level
US20040232981A1 (en) * 2003-01-10 2004-11-25 Chao-Cheng Lee Amplifier circuit
US20050008107A1 (en) * 2003-07-10 2005-01-13 Brown James E. C. Receiver for correcting frequency dependent I/Q phase error
US7057451B2 (en) * 2004-04-30 2006-06-06 Industrial Technology Research Institute Programmable/tunable active RC filter
US7239196B2 (en) * 2004-04-05 2007-07-03 Sony Corporation Filter circuit

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3735393A (en) 1971-11-22 1973-05-22 Bell Telephone Labor Inc Self companding pulse code modulation systems
US3863200A (en) 1973-01-15 1975-01-28 Amoco Prod Co Built-in seismometer amplifier
US3863201A (en) 1973-05-29 1975-01-28 Amoco Prod Co Seismometer arrays using operational amplifiers
US4037170A (en) 1976-04-05 1977-07-19 Stromberg-Carlson Corporation Difference amplifier having extended common mode range
US4484295A (en) 1981-05-26 1984-11-20 General Electric Company Control circuit and method for varying the output of a waveform generator to gradually or rapidly vary a control signal from an initial value to a desired value
US5525985A (en) 1990-12-28 1996-06-11 Eaton Corporation Sure chip
JP3002555B2 (en) 1991-03-18 2000-01-24 三菱電機株式会社 Signal processing device
US5231627A (en) 1991-09-10 1993-07-27 National Film Board Of Canada Apparatus for reading optically encoded soundtracks
JPH06303060A (en) 1993-04-15 1994-10-28 Mitsubishi Electric Corp Gain control amplifier circuit
GB9326464D0 (en) 1993-12-24 1994-02-23 Philips Electronics Uk Ltd Receiver having an adjustable bandwidth filter
FR2719105B1 (en) 1994-04-21 1996-05-31 Yto Quick coupler for pressure pipe with controlled uncoupling.
US5917387A (en) 1996-09-27 1999-06-29 Lucent Technologies Inc. Filter having tunable center frequency and/or tunable bandwidth
US5999052A (en) 1998-04-28 1999-12-07 Lucent Technologies Inc. High speed, fine-resolution gain programmable amplifier
JPH11340760A (en) 1998-05-28 1999-12-10 Fuji Film Microdevices Co Ltd Variable gain amplifier circuit
US6731160B1 (en) 1999-11-11 2004-05-04 Broadcom Corporation Adjustable bandwidth high pass filter for large input signal, low supply voltage applications
US6703682B2 (en) 1999-12-22 2004-03-09 Texas Advanced Optoelectronic Solutions, Inc. High sheet MOS resistor method and apparatus
US7102441B2 (en) 2003-12-31 2006-09-05 Realtek Semiconductor Corp. Variable gain amplifying circuit

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US552598A (en) * 1896-01-07 tucker
US560492A (en) * 1896-05-19 Valve for pneumatic tires
US591738A (en) * 1897-10-12 cheney
US673116A (en) * 1900-09-06 1901-04-30 Talbot C Dexter Means for protecting printing-presses.
US670368A (en) * 1901-01-02 1901-03-19 William Lumsdon Byers Pivoted anchor.
US5455582A (en) * 1992-12-17 1995-10-03 Ulsi Technology, Inc. Digital to analog converter employing R-2R ladders with substituted shunt arms
US6127893A (en) * 1998-09-18 2000-10-03 Tripath Technology, Inc. Method and apparatus for controlling an audio signal level
US6344780B1 (en) * 1998-09-18 2002-02-05 Kabushiki Kaisha Toshiba Impedance adjusting circuit
US6693491B1 (en) * 2000-04-17 2004-02-17 Tripath Technology, Inc. Method and apparatus for controlling an audio signal level
US6545534B1 (en) * 2001-02-13 2003-04-08 Analog Devices, Inc. Low voltage variable gain amplifier with constant input impedance and adjustable one-pole filtering characteristic
US20040232981A1 (en) * 2003-01-10 2004-11-25 Chao-Cheng Lee Amplifier circuit
US7138869B2 (en) * 2003-01-10 2006-11-21 Realtek Semiconductors Corp. Amplifier circuit
US20050008107A1 (en) * 2003-07-10 2005-01-13 Brown James E. C. Receiver for correcting frequency dependent I/Q phase error
US7239196B2 (en) * 2004-04-05 2007-07-03 Sony Corporation Filter circuit
US7057451B2 (en) * 2004-04-30 2006-06-06 Industrial Technology Research Institute Programmable/tunable active RC filter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090168944A1 (en) * 2007-12-28 2009-07-02 Hynix Semiconductor, Inc. Low pass filter and lock detector circuit
US7876148B2 (en) * 2007-12-28 2011-01-25 Hynix Semiconductor Inc. Low pass filter and lock detector circuit

Also Published As

Publication number Publication date
TW200640128A (en) 2006-11-16
US7737772B2 (en) 2010-06-15
TWI257202B (en) 2006-06-21
US20060250181A1 (en) 2006-11-09

Similar Documents

Publication Publication Date Title
US7737772B2 (en) Bandwidth-adjustable filter
US7102441B2 (en) Variable gain amplifying circuit
US7239196B2 (en) Filter circuit
EP0362935B1 (en) Drain-biassed transresistance device
CN102217192B (en) Variable gain amplifier
US7639076B2 (en) Gain controlled amplifier and cascoded gain controlled amplifier based on the same
JPS60500395A (en) Tunable active filter
JPH11261764A (en) Variable gain amplifier
US6737919B2 (en) Method and apparatus for calibrating a Gm cell utilizing a replica Gm cell
CN112332803A (en) Active low-pass filter bandwidth calibration circuit
US20110012689A1 (en) Impedance Adjustment Circuit for Adjusting Terminal Resistance and Related Method
JPH07240662A (en) Multiplication device of capacitance by variable coefficientfor the purpose of adjustment of particularly cut-off frequency of filter and filter therewith
US20090108927A1 (en) Filter adjusting circuit
US6831506B1 (en) Reconfigurable filter architecture
US6791415B2 (en) Integrated circuit arrangement with a transconductance amplifier
US6452444B1 (en) Method and apparatus for background calibration of active RC filters
US20030044027A1 (en) Volume circuit using resistive ladder circuits
US6963238B2 (en) Level shift circuit
US6854076B2 (en) Method and apparatus for calibration of an electronic device
JP2000013168A (en) Ninety-degree phase shift circuit
EP0816857B1 (en) Differential attenuator common mode rejection correction circuit
US6812780B2 (en) Filter circuit and detection circuit having filter circuit
US6906584B1 (en) Switchable gain amplifier having a high-pass filter pole
CN109905089B (en) High-speed composite loop controller and control method thereof
US6642779B2 (en) Trimming impedance between two nodes connected to a non-fixed voltage level

Legal Events

Date Code Title Description
AS Assignment

Owner name: REALTEK SEMICONDUCTOR CORP.,TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, CHAO-CHENG;LIN, YING-YAO;REEL/FRAME:017943/0153

Effective date: 20060505

Owner name: REALTEK SEMICONDUCTOR CORP., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, CHAO-CHENG;LIN, YING-YAO;REEL/FRAME:017943/0153

Effective date: 20060505

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552)

Year of fee payment: 8

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12