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Wear leveling in flash storage devices

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US20090327804A1
US20090327804A1 US12464856 US46485609A US2009327804A1 US 20090327804 A1 US20090327804 A1 US 20090327804A1 US 12464856 US12464856 US 12464856 US 46485609 A US46485609 A US 46485609A US 2009327804 A1 US2009327804 A1 US 2009327804A1
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data
block
flash
storage
segment
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US12464856
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Mark Moshayedi
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HGST Technologies Santa Ana Inc
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HGST Technologies Santa Ana Inc
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from or digital output to record carriers, e.g. RAID, emulated record carriers, networked record carriers
    • G06F3/0601Dedicated interfaces to storage systems
    • G06F3/0602Dedicated interfaces to storage systems specifically adapted to achieve a particular effect
    • G06F3/061Improving I/O performance
    • G06F3/0613Improving I/O performance in relation to throughput
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14Error detection or correction of the data by redundancy in operation
    • G06F11/1402Saving, restoring, recovering or retrying
    • G06F11/1415Saving, restoring, recovering or retrying at system level
    • G06F11/1441Resetting or repowering
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from or digital output to record carriers, e.g. RAID, emulated record carriers, networked record carriers
    • G06F3/0601Dedicated interfaces to storage systems
    • G06F3/0628Dedicated interfaces to storage systems making use of a particular technique
    • G06F3/0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659Command handling arrangements, e.g. command buffers, queues, command scheduling
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from or digital output to record carriers, e.g. RAID, emulated record carriers, networked record carriers
    • G06F3/0601Dedicated interfaces to storage systems
    • G06F3/0668Dedicated interfaces to storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0683Plurality of storage devices
    • G06F3/0688Non-volatile semiconductor memory arrays

Abstract

A method of wear leveling in a flash storage device comprising a plurality of data blocks is provided. The method comprises the steps of detecting a data error in a read of dynamic data from a first data segment of a first data block of the plurality of data blocks, correcting the data error, and moving the dynamic data from the first data segment to a second data segment in a second one of the plurality of data blocks.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • [0001]
    The present application claims the benefit of priority under 35 U.S.C. §119 from U.S. Provisional Patent Application Ser. No. 61/075,709, entitled “SOLID STATE DEVICE,” filed on Jun. 25, 2008, the disclosure of which is hereby incorporated by reference in its entirety for all purposes.
  • FIELD OF THE INVENTION
  • [0002]
    The present invention relates to flash storage devices and, in particular, relates to improved wear leveling in flash storage devices.
  • BACKGROUND OF THE INVENTION
  • [0003]
    Flash memory is an improved form of Electrically-Erasable Programmable Read-Only Memory (EEPROM). Traditional EEPROM devices are only capable of erasing or writing one memory location at a time. In contrast, flash memory allows multiple memory locations to be erased or written in one programming operation. Flash memory can thus operate at higher effective speeds than traditional EEPROM.
  • [0004]
    Flash memory enjoys a number of advantages over other storage devices. It generally offers faster read access times and better shock resistance than a hard disk drive (HDD). Unlike dynamic random access memory (DRAM), flash memory is non-volatile, meaning that data stored in a flash storage device is not lost when power to the device is removed. For this reason, a flash memory device is frequently referred to as a flash storage device, to differentiate it from volatile forms of memory. These advantages, and others, may explain the increasing popularity of flash memory for storage applications in devices such as memory cards, USB flash drives, mobile phones, digital cameras, mass storage devices, MP3 players and the like.
  • [0005]
    Due to flash memory's unique structure, however, each region of memory can only be rewritten a certain number of times before it can no longer reliably hold data. Accordingly, if some regions of memory are written to and rewritten more frequently than others, the lifetime of a flash storage device may be unacceptably shortened by the early failure of those regions of the memory.
  • SUMMARY OF THE INVENTION
  • [0006]
    Various aspects of the subject disclosure solve the foregoing problem by providing improved wear leveling for flash storage devices. The wear leveling improves the lifespan of flash storage devices and improves the reliability of data access therefrom.
  • [0007]
    According to one aspect of the subject disclosure, a method of wear leveling in a flash storage device comprising a plurality of data blocks is provided. The method comprises the steps of detecting a data error in a read of dynamic data from a first data segment of a first data block of the plurality of data blocks, correcting the data error, and moving the dynamic data from the first data segment to a second data segment in a second one of the plurality of data blocks.
  • [0008]
    According to another aspect of the subject disclosure, a flash storage device comprises a plurality of data blocks and a controller. The controller is configured to detect a data error in a read of dynamic data from a first data segment of a first data block of the plurality of data blocks, to correct the data error, and to move the dynamic data from the first data segment to a second data segment in a second one of the plurality of data blocks.
  • [0009]
    According to yet another aspect of the subject disclosure, a machine readable medium carries one or more sequences of instructions for wear leveling in a flash storage device having a plurality of data blocks. Execution of the one or more sequences of instructions by one or more processors causes the one or more processors to perform the steps of detecting a data error in a read of dynamic data from a first data segment of a first data block of the plurality of data blocks, correcting the data error, and moving the dynamic data from the first data segment to a second data segment in a second one of the plurality of data blocks.
  • [0010]
    It is to be understood that both the foregoing summary of the invention and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0011]
    The accompanying drawings, which are included to provide further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:
  • [0012]
    FIG. 1 illustrates a flash storage device in accordance with one aspect of the subject disclosure;
  • [0013]
    FIG. 2 illustrates a flash storage device in accordance with one aspect of the subject disclosure;
  • [0014]
    FIGS. 3 a and 3 b illustrate a data structure of a flash storage device in accordance with one aspect of the subject disclosure;
  • [0015]
    FIGS. 4 a and 4 b illustrate a data structure of a flash storage device in accordance with one aspect of the subject disclosure;
  • [0016]
    FIG. 5 is a flow chart illustrating a method of wear leveling in a flash storage device comprising a plurality of data blocks in accordance with one aspect of the subject disclosure; and
  • [0017]
    FIG. 6 is a block diagram that illustrates processor 101 in greater detail, in accordance with one aspect of the subject disclosure
  • DETAILED DESCRIPTION OF THE INVENTION
  • [0018]
    In the following detailed description, numerous specific details are set forth to provide a full understanding of the present invention. It will be apparent, however, to one ordinarily skilled in the art that the present invention may be practiced without some of these specific details. In other instances, well-known structures and techniques have not been shown in detail to avoid unnecessarily obscuring the present invention.
  • [0019]
    Referring to FIG. 1, a block diagram of a flash storage device according to one aspect of the subject disclosure is depicted. Flash storage device 100 includes a controller 101 and a number of data blocks 110 1, 110 2, 110 3, 110 4 . . . 110 n. While the term “data block” is used throughout the description, it will be understood by those of skill in the art that the term data block is frequently used interchangeably with the term “memory block” in the art. Each data block has a plurality of data segments for storing data. In the present exemplary flash storage device, each data block is illustrated as including 16 data segments. The scope of the present invention, however, is not limited to such an arrangement. Rather, as will be apparent to one of skill in the art, a data block may be configured with more or less than 16 data segments as desired to provide various levels of storage space. For example, in accordance with one aspect of the subject disclosure, a data block may include 32 data segments of 4 kilobytes (kB) each to provide 128 kB of data storage. While data blocks are usually configured with 2n data segments (e.g., 16, 32, 64, 128, 256, etc.), the scope of the invention is not so limited. Similarly, while each data block 110 1-110 n is illustrated as including the same number of data segments, the scope of the invention is not so limited, as a flash storage device may comprise a number of data blocks with differing capacities and/or numbers of data segments. In accordance with one aspect of the subject disclosure, a data block may span over more than one flash memory chip in a storage array of multiple chips. In accordance with another aspect, a data block is stored on a single flash memory chip in a storage array of multiple flash memory chips.
  • [0020]
    Three types of data segments are illustrated with different graphical conventions in FIG. 1. In particular, empty data segments, such as data segment 121, are indicated by a white field surrounded with a black line, data segments containing dynamic data (e.g., data which is frequently updated or rewritten), such as data segment 122, are indicated by a shaded field surrounded by a black line, and data segments containing static data (e.g., data which is infrequently updated or rewritten), such as data segment 123, are indicated by a field with diagonal hatches surrounded by black lines. In addition, a data segment containing data which has become corrupted or is otherwise erroneous, such as data segment 124, is indicated by intersecting diagonal black lines. A data segment may contain erroneous data as a result of the degradation of a data block that has been written to/rewritten so many times that the hardware thereof has become unreliable. Other manners in which the data of a data segment may be corrupted or otherwise rendered erroneous will be readily apparent to those of skill in the art, and are omitted herefrom for brevity's sake.
  • [0021]
    Flash storage device 100 further includes a data structure for storing information associated with each data block 110 1-110 n. According to one exemplary aspect of the subject disclosure, the data structure may store information about the number of data errors that have occurred in read operations corresponding to each of the data blocks. For example, the data structure may store information indicating that data block 110 1 has experienced three read errors, that data block 110 2 has experienced one read error, that data block 110 3 has experienced two read errors, etc. This information may allow controller 101 to select a data block from which to move dynamic data in favor of static data, as described in greater detail below.
  • [0022]
    According to one exemplary aspect of the subject disclosure, the data structure may include information about the number of data read errors that have occurred in each data block since flash storage device 100 was last powered on. In accordance with an alternative aspect, the data structure may include information about the total number of data read errors that have occurred in each data block since some time prior to the last time flash storage device 100 was powered on (e.g., since flash storage device 100 was initialized, formatted, manufactured, first powered on, etc.). In accordance with still another aspect of the subject disclosure, the data structure may include information about the number of data read errors that have occurred in each data block both since flash storage device 100 was last powered on and since a time previous to the last time flash storage device 100 was powered on (e.g., since flash storage device 100 was initialized, formatted, manufactured, first powered on, etc.).
  • [0023]
    Information regarding the number of data read errors associated with a given data block may be used to determine whether the data stored therein is dynamic or static. For example, if the number of read errors of a certain data block, such as data block 110 2, is below a predetermined threshold (e.g., 2), then controller 101 may be configured to determine that the data segments therein contain “static” data. If the number of read errors of a certain data block, such as data block 110 3, meets or exceeds a predetermined threshold (e.g., 2), then controller 101 may be configured to determine that the data segments therein contain “dynamic” data. In this way, data which is subject to more frequent write or rewrite operations (e.g., operations which may reduce the reliability of the associated data segments and/or data blocks) is determined to be dynamic data, and can be relocated to data blocks with less wear (e.g., as determined by the number of data read errors associated therewith).
  • [0024]
    While in the foregoing description, a data block has been described as being determined to contain static or dynamic data based upon a predetermined threshold of two data read errors, the scope of the present invention is not limited to such an arrangement. Rather, as will be apparent to those of skill in the art, any threshold value greater than 0 may be used to determine whether a data block contains static or dynamic data. Moreover, the predetermined threshold may be subject to change as necessary to characterize at least some of the data in flash storage device 100 as static, as is described in greater detail below. Accordingly, the terms “dynamic” and “static” are used herein to describe the relative frequency with which data is updated among data blocks in a flash storage device, and do not imply a rigid or unchanging definition. Moreover, data which is at one time determined to be static may later be determined to be dynamic, and vice versa, as is set forth in greater detail below.
  • [0025]
    While FIG. 1 graphically illustrates the three data read errors that have occurred in data block 110 1 as occurring in three discrete data segments, it will be readily understood that a data block may experience multiple data read errors arising from multiple reads of data from a single data segment. As can be seen with reference to FIGS. 3 a and 3 b below, the information concerning the number of data read errors associated with a given data block need not include information regarding which particular data segments from which the data read errors have arisen. Accordingly, the graphical convention of FIGS. 1 and 2 is merely intended to provide a simple illustration of data blocks with multiple data read errors, and not to specify that particular data segments are associated with information regarding a number of data read errors occurring therein. According to another exemplary aspect of the subject disclosure, however, the data structures may contain information associating particular data segments with a status indicator which indicates a number of data read errors associated therewith.
  • [0026]
    According to one aspect of the subject disclosure, upon a read of dynamic data segment 124, controller 101 may detect an error in the read data (e.g., using an error checking algorithm or the like). Upon detecting the error, controller 101 may be configured to correct the data error in data segment 124 (e.g., by utilizing an error correction code, parity information, or the like). After correcting the data error, controller 101 may be configured to move the data from data segment 124 (or the entire data block 110 1) to one or more data segments of an available data block, such as data block 110 4. Controller 101 may be further configured to move data (e.g., from a single data segment, or from multiple data segments) which has been determined to be static data from one or more data segments of another data block, such as data block 110 2, to one or more data segments of data block 110 1. In accordance with one aspect of the subject disclosure, controller 101 is configured to move data by first copying the data from the data segment(s) of one data block to the data segment(s) of another data block, and then deleting the first data block.
  • [0027]
    The foregoing operation may be more easily understood with reference to FIG. 2, which illustrates flash storage device 100 after the foregoing operations have been completed, in accordance with one aspect of the subject disclosure. As can be seen with reference to FIG. 2, the dynamic data previously located in the data segments of data block 110 1 have been moved to data segments of data block 110 4, while the static data previously located in the data segments of data block 110 2 have been moved to data segments of data block 110 1. For the sake of clarity, the crossed diagonal lines used to indicate the data read errors experienced by data blocks 110 1 and 110 2 have been omitted from FIG. 2.
  • [0028]
    According to various aspects of the subject disclosure, data in a data block may be determined to be “static” data in any one of a number of ways. As indicated above, if the data block in question is associated in a data structure with a number of data read errors which is below a predetermined threshold, the data in the data block may be determined to be static. Alternatively, a data block may be determined to contain static data based upon the time at which the data block in question was last written to (which information may be stored in a data structure of flash storage device 100). For example, if the data block in question has not been written to for a predetermined period of time (e.g., whether one hour, one day, etc.), the data therein may be determined by controller 101 to be static. Similarly, if the data block in question has not been written to since flash storage device 100 was last powered on, the data in the data block may be determined to be static. According to another aspect of the subject disclosure, information about the time of the most recent data write operation in a block of data may “follow” that data if it is moved to a different data block, such that data in a data block may be determined to be dynamic based upon the time of a last write operation even after that data is moved from a different data block that has experienced a number of read errors above the threshold for dynamic data. In this regard, controller 101 may consider both the number of data read errors associated with a data block as well as the time of a last data write operation thereto in determining whether or not a data block contains static or dynamic data.
  • [0029]
    In this regard, flash storage device 100 may include a data structure which stores information about a time at which each of the data blocks 110 1-110 n was last written to, in accordance with one aspect of the subject disclosure. The information about a time at which each of the data blocks was last written to may be as simple as a status indicator which indicates whether an associated data block has been written to since flash storage device 100 was last powered on, according to one exemplary aspect. For example, the data structure may store information indicating that data block 110 1 has been written to since the last time flash storage device 100 was powered on, that data block 110 4 has not been written to since flash storage device 100 was last powered on, etc. According to another exemplary aspect of the subject disclosure, the status indicator may indicate a time of the last write operation in an associated data block (e.g., with reference to a clock signal).
  • [0030]
    According to one aspect of the subject disclosure, if controller 101 is configured to consider a number of data read errors associated with a data block in determining whether or not that data block contains static data, it may be necessary to revise the threshold number of data errors in making such a determination. For example, if a flash storage device has been in operation for a significant length of time, the foregoing wear-leveling technique may result in every data block in the flash storage device having experienced some number of data read errors. Accordingly, if every data block is determined to have experienced a number of data read errors in excess of the threshold value controller 101 uses to determine whether or not data is static, controller 101 may be configured to revise the threshold value upwards, until at least one data block has a number of data read errors below the revised threshold value.
  • [0031]
    After moving data from one data block to another, controller 101 may be configured to update an address mapping associated with each data block to properly identify the new location of the moved data, according to one aspect of the subject disclosure. For example, controller 101 may maintain a list of logical addresses (by which a host device identifies data to flash storage device 100) corresponding to the physical address (e.g., of a data block and/or data segment) in which data is stored in flash storage device 100. Upon moving data from one data block to another, as described above with reference to FIGS. 1 and 2, controller 101 may be configured to update the physical addresses of the relocated data to ensure that the logical address properly identifies the location thereof.
  • [0032]
    Controller 101 may be further configured to modify the data structures containing information associated with the data blocks affected by the foregoing operations. This may be more easily understood with reference to FIGS. 3 a and 3 b, which illustrate a data structure of flash storage device 100 in accordance with one aspect of the subject disclosure.
  • [0033]
    As can be seen with reference to FIG. 3 a, prior to the foregoing operations, data structure 300 includes a linked list 300 a that associates each data block with a number of data read errors experienced thereby (e.g., in the present exemplary embodiment, since the last time flash storage device 100 was powered on). In this regard, data block 110 1 has experienced three read errors, data block 110 2 has experienced one read error, data block 110 3 has experienced two read errors, data block 110 4 has experienced no read errors, and data block 110 n has experienced no read errors. After the foregoing operations (described with reference to FIGS. 1 and 2) are complete, controller 101 may be configured to update data structure 300 such that updated linked list 300 b shown in FIG. 3 b reflects the updated values for the number of data read errors experienced by each data block. In this regard, as can be seen with reference to FIG. 3 b, the number of data read errors associated with data block 110 1 has been changed to 0. Moreover, the data that had previously been categorized as dynamic when it was located in data block 110 1 (having a number of read errors exceeding the threshold) is categorized as static after being moved to data block 110 4 (as can be seen with reference to FIG. 3 b, which indicates that a number of read errors associated with the data now located in data block 110 4 is 0).
  • [0034]
    Turning to FIGS. 4 a and 4 b, a similar updating of the data structure which contains information regarding the last time a data block has been written to (or, more specifically, whether a data block has been written to since flash storage device 100 was last powered on) is illustrated in accordance with one aspect of the subject disclosure. Prior to the foregoing operations, data structure 400 includes a linked list 400 a that indicates whether or not each data block 110 1-110 n, has been written to since flash storage device 100 was last powered on. As can be seen with reference to FIG. 4 a, data blocks 110 1, 110 2 and 110 3 are each associated with a 1 (by which convention controller 101 indicates that these data blocks have been written to since the last time flash storage device 100 was powered on), and data blocks 110 4 and 110 n, are each associated with a 0 (by which convention controller 101 indicates that these data blocks have not been written to since the last time flash storage device 100 was powered on). After the foregoing wear-leveling operations (described with reference to FIGS. 1 and 2) are complete, controller 101 may be configured to update data structure 400 such that updated linked list 400 b shown in FIG. 4 b reflects that data block 110 4 has been written to since the last time flash storage device 100 was powered on (i.e., by changing the associated 0 to 1).
  • [0035]
    The foregoing exemplary data structures may be provided on a flash storage device in any one of a number of manners. For example, in accordance with one exemplary aspect of the subject disclosure, the data structure may be provided in a random access memory (RAM) or dynamic random access memory (DRAM) module of flash storage device 100. According to one aspect, controller 101 may include DRAM or RAM modules, as illustrated in greater detail below with respect to FIG. 6. Alternatively, the data structure may be provided in one of the plurality of data blocks of flash storage device. Where the data structure is stored may depend upon a power state of the flash storage device. When in an unpowered condition, the data structure may be copied from a volatile storage medium (e.g., DRAM) to a non-volatile storage medium (e.g., a data block) to prevent the information in the data structure from being lost when the reserve power of flash storage device 100 (e.g., provided by capacitors, super-capacitors, batteries, etc.) is exhausted.
  • [0036]
    While in the foregoing exemplary embodiments, the data structures have been illustrated as including a single linked list, the scope of the present invention is not so limited. Rather, as will be apparent to those of skill in the art, information regarding the number of data read errors corresponding to each data block of a flash storage device and information regarding the last time a data write operation took place in a data block of a flash storage device may be provided in any one of a number of ways. For example, rather than a single linked list, a data structure may comprise multiple linked lists, whereby data blocks with similar numbers of data read errors may be included on a single list (e.g., one list indicating data blocks with between 0 and 7 data read errors, another list indicating data blocks with between 8 and 15 data read errors, etc.). In such an embodiment, controller 101 may provide a “rough” sorting feature by organizing data blocks into “bins” of similarly situated data blocks. This allows controller 101 to simply select one data block from the unordered list representing data blocks with fewer read errors (e.g., data blocks with between 0 and 7 read errors) to designate as “static” data blocks. Controller 101 may update the unordered lists when an operation changes the number of data read errors detected in a given data block, moving the data block to the appropriate list that reflects the updated number of data read errors.
  • [0037]
    While in the foregoing exemplary embodiments, the data structures have been described as including one or more linked lists for keeping track of the number of data read errors in each data block of a flash storage device and the time of a last data write operation in each data block of a flash storage device, the scope of the present invention is not limited to such an arrangement. Rather, as will be apparent to those of skill in the art, any one of a number of different data structures may be employed to maintain this information, including, for example, tables, pointers, and the like.
  • [0038]
    While in the foregoing exemplary embodiments, data moving operations have been described with reference to block-level copying, the scope of the present invention is not limited to this particular arrangement. Rather, according to one aspect of the subject disclosure, only valid data segments are copied from one data block to another before the first data block is erased. Moreover, the valid data segments copied from the first data block to the destination data block may be combined with valid data segments from other data blocks, so that the destination data block is provided with enough valid data segments to fully populate the destination data block with valid data. The valid data segments may be copied from other data blocks that have been identified as containing dynamic or static data (e.g., as a result of a read error count of a time of last write operation), as appropriate, or may be copied from other data blocks based upon any one of a number of other selection criteria (e.g., data blocks containing the number of data segments necessary to fully populate the destination data block). After such an operation, the other data blocks may be erased and labeled as “free” blocks for future use, although the read error count associated with these data blocks may or may not be changed.
  • [0039]
    While in the foregoing exemplary embodiments, data moving operations have been described as triggered by a determination that these data blocks contain dynamic or static data, the scope of the present invention is not limited to this particular arrangement. Rather, as will be readily apparent to those of skill in the art, data moving operations may be triggered by any one of a number of other determinations. For example, in accordance with one aspect of the subject disclosure, data moving operations may be triggered by a background operation that combines the valid data segments of various blocks into one data block.
  • [0040]
    FIG. 5 is a flow chart illustrating a method of wear leveling in a flash storage device having a plurality of data blocks, in accordance with one aspect of the subject disclosure. The method begins with step 501, in which a data error is detected in a read of dynamic data from a first data segment of a first data block. In step 502, the data error is corrected (e.g., using an error correction code, parity bits, or the like). In step 503, the dynamic data is moved to a second data segment of a second one of the plurality of data blocks. In step 504, a third data block is selected based on an associated status indicator (e.g., identifying a number of data read errors associated with the third data block, or identifying a time at which the third data block was last written to), and in step 505, static data is moved from a third data segment of the third data block to an available data segment of the first data block.
  • [0041]
    FIG. 6 is a block diagram that illustrates controller 101 in greater detail, in accordance with one aspect of the subject disclosure. Controller 101 includes a bus 602 or other communication mechanism for communicating information, and a processor 604 coupled with bus 602 for processing information. Controller 101 also includes a machine-readable media 606 for storing a data structure, such as a random access memory (“RAM”) or other dynamic storage device, coupled to bus 602 for storing information and instructions to be executed by processor 604. Media 606 may also be used for storing temporary variables or other intermediate information during execution of instructions by processor 604. Media 606 may also comprise non-volatile storage media, such as flash memory, a magnetic disk or an optical disk, coupled to bus 602 for storing information and instructions. Controller 101 may be coupled via I/O module 608 to data blocks 110 1-110 n, and to an external system with which flash storage device 100 communicates.
  • [0042]
    According to one aspect of the present invention, wear leveling in a flash storage device is performed by controller 101 in response to processor 604 executing one or more sequences of one or more instructions contained in media 606. Such instructions may be read into media 606 from another machine-readable medium, such as through I/O module 608. Execution of the sequences of instructions contained in media 606 causes processor 604 to perform the process steps described herein. One or more processors in a multi-processing arrangement may also be employed to execute the sequences of instructions contained in media 606. In alternative embodiments, hard-wired circuitry may be used in place of or in combination with software instructions to implement various embodiments of the present invention. Thus, embodiments of the present invention are not limited to any specific combination of hardware circuitry and software.
  • [0043]
    The term “machine-readable medium” as used herein refers to any medium that participates in providing instructions to processor 604 for execution. Such a medium may take many forms, including, but not limited to, non-volatile media, volatile media, and transmission media. Non-volatile media include, for example, optical or magnetic disks. Volatile media include dynamic memory, such as memory 606. Transmission media include coaxial cables, copper wire, and fiber optics, including the wires that comprise bus 602. Transmission media can also take the form of acoustic or light waves, such as those generated during radio frequency and infrared data communications. Common forms of machine-readable media include, for example, floppy disk, a flexible disk, hard disk, magnetic tape, any other magnetic medium, a CD-ROM, DVD, any other optical medium, punch cards, paper tape, any other physical medium with patterns of holes, a RAM, a PROM, an EPROM, a FLASH EPROM, any other memory chip or cartridge, a carrier wave, or any other medium from which a computer can read.
  • [0044]
    The description of the invention is provided to enable any person skilled in the art to practice the various embodiments described herein. While the present invention has been particularly described with reference to the various figures and embodiments, it should be understood that these are for illustration purposes only and should not be taken as limiting the scope of the invention.
  • [0045]
    There may be many other ways to implement the invention. Various functions and elements described herein may be partitioned differently from those shown without departing from the spirit and scope of the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and generic principles defined herein may be applied to other embodiments. Thus, many changes and modifications may be made to the invention, by one having ordinary skill in the art, without departing from the spirit and scope of the invention.
  • [0046]
    A reference to an element in the singular is not intended to mean “one and only one” unless specifically stated, but rather “one or more.” The term “some” refers to one or more. Underlined and/or italicized headings and subheadings are used for convenience only, do not limit the invention, and are not referred to in connection with the interpretation of the description of the invention. All structural and functional equivalents to the elements of the various embodiments of the invention described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and intended to be encompassed by the invention. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the above description.

Claims (37)

1. A method of wear leveling in a flash storage device comprising a plurality of data blocks, the method comprising the steps of:
detecting a data error in a read of dynamic data from a first data segment of a first data block of the plurality of data blocks;
correcting the data error; and
moving the dynamic data from the first data segment to a second data segment in a second one of the plurality of data blocks.
2. The method according to claim 1, wherein the available data segment of the first data block is the first data segment.
3. The method according to claim 1, wherein the step of correcting the data error is performed using an error correction code.
4. The method according to claim 1, wherein the step of moving the dynamic data from the first data segment to the second data segment in the second one of the plurality of data blocks comprises:
writing the dynamic data to the second data segment, and
erasing the first data block.
5. The method according to claim 1, further comprising the step of:
moving static data from a third data segment of a third data block to an available data segment of the first data block.
6. The method according to claim 5, wherein the step of moving the static data from the third data segment to the available data segment of the first data block comprises:
writing the static data to the available data segment of the first data block, and
erasing the third data block.
7. The method according to claim 5, wherein the step of moving the static data to the available data segment of the first data block comprises:
changing an address mapping associated with the static data from the third data segment to the available data segment of the first data block.
8. The method according to claim 1, wherein the step of moving the dynamic data to the second data segment comprises:
changing an address mapping associated with the dynamic data from the first data segment to the second data segment.
9. The method according to claim 1, wherein each data block of the plurality of data blocks is associated with a first status indicator that indicates a number of data errors that have occurred in reads of data segments of the associated data block.
10. The method according to claim 9, wherein the first status indicator indicates the number of data errors that have occurred in reads of data segments of the associated data block since the flash storage device was last powered on.
11. The method according to claim 9, further comprising adjusting the first status indicator associated with the first data block to indicate that the number of data errors that have occurred in reads of data segments of the first data block is 0.
12. The method according to claim 9, wherein the first data segment is determined to comprise dynamic data based upon the first status indicator associated with the first data block exceeding a predetermined threshold.
13. The method according to claim 9, further comprising:
selecting a third data block based on the associated first status indicator indicating that a number of data errors that have occurred in reads of data segments of the third data block does not exceed a predetermined threshold; and
moving static data from a third data segment of the third data block to an available data segment of the first data block.
14. The method according to claim 13, wherein if the first status indicator for each of the plurality of data blocks exceeds the predetermined threshold, the predetermined threshold is modified such that the first status indicator of at least one of the plurality of data blocks does not exceed the predetermined threshold.
15. The method according to claim 1, wherein each data block of the plurality of data blocks is associated with a second status indicator that indicates a time of the last data write operation to a data segment of the associated data block.
16. The method according to claim 15, further comprising selecting a third data block based on the associated second status indicator indicating that the time of the last data write operation to a data segment of the third data block was prior to a predetermined time; and
moving static data from a third data segment of the third data block to an available data segment of the first data block.
17. The method according to claim 15, wherein the second status indicator indicates whether data has been written to a data segment of the associated data block since the flash storage device was last powered on.
18. The method according to claim 17, further comprising selecting a third data block based on the associated second status indicator indicating that no data has been written to a data segment of the third data block since the flash storage device was last powered on; and
moving static data from a third data segment of a third data block to an available data segment of the first data block.
19. A flash storage device comprising:
a plurality of data blocks; and
a controller configured to:
detect a data error in a read of dynamic data from a first data segment of a first data block of the plurality of data blocks,
correct the data error, and
move the dynamic data from the first data segment to a second data segment in a second one of the plurality of data blocks.
20. The flash storage device according to claim 19, wherein the available data segment of the first data block is the first data segment.
21. The flash storage device according to claim 19, wherein the controller is configured to correct the data error with an error correction code.
22. The flash storage device according to claim 19, wherein the controller is configured to move the dynamic data from the first data segment to the second data segment in the second one of the plurality of data blocks by:
writing the dynamic data to the second data segment, and
erasing the first data block
23. The flash storage device according to claim 19, wherein the controller is further configured to:
move static data from a third data segment of a third data block to an available data segment of the first data block.
24. The flash storage device according to claim 23, wherein the controller is configured to move the static data from the third data segment to the first data block by:
writing the static data to the available data segment of the first data block, and
erasing the third data block.
25. The flash storage device according to claim 23, wherein the controller is further configured to change an address mapping associated with the static data from the third data segment to the first data segment.
26. The flash storage device according to claim 19, wherein the controller is further configured to change an address mapping associated with the dynamic data from the first data segment to the second data segment.
27. The flash storage device according to claim 19, wherein each data block of the plurality of data blocks is associated with a first status indicator that indicates a number of data errors that have occurred in reads of data segments of the associated data block.
28. The flash storage device according to claim 27, wherein the first status indicator indicates the number of data errors that have occurred in reads of data segments of the associated data block since the flash storage device was last powered on.
29. The flash storage device according to claim 27, wherein the controller is further configured to adjust the first status indicator associated with the first data block.
30. The flash storage device according to claim 27, wherein the first data segment is determined to comprise dynamic data based upon the first status indicator associated with the first data block exceeding a predetermined threshold.
31. The flash storage device according to claim 27, wherein the controller is configured to:
select a third data block based on the associated first status indicator indicating that a number of data errors that have occurred in reads of data segments the second data block does not exceed a predetermined threshold; and
move static data from a third data segment of the third data block to an available data segment of the first data block.
32. The flash storage device according to claim 31, wherein if the first status indicator for each of the plurality of data blocks exceeds the predetermined threshold, the controller is configured to modify the predetermined threshold such that the first status indicator of at least one of the plurality of data blocks does not exceed the predetermined threshold.
33. The flash storage device according to claim 19, wherein each data block of the plurality of data blocks is associated with a second status indicator that indicates a time of the last data write operation to a data segment of the associated data block.
34. The flash storage device according to claim 33, wherein the controller is configured to:
select a third data block based on the associated second status indicator indicating that the time of the last data write operation of the second data block was prior to a predetermined time; and
move static data from a third data segment of the third data block to an available data segment of the first data block.
35. The flash storage device according to claim 33, wherein the second status indicator indicates whether data has been written to a data segment of the associated data block since the flash storage device was last powered on.
36. The flash storage device according to claim 33, wherein the controller is configured to:
select a third data block based on the associated second status indicator indicating that no data has been written to a data segment of the third data block since the flash storage device was last powered on; and
move static data from a third data segment of the third data block to an available data segment of the first data block.
37. A machine readable medium carrying one or more sequences of instructions for wear leveling in a flash storage device having a plurality of data blocks, wherein execution of the one or more sequences of instructions by one or more processors causes the one or more processors to perform the steps of:
detecting a data error in a read of dynamic data from a first data segment of a first data block of the plurality of data blocks;
correcting the data error; and
moving the dynamic data from the first data segment to a second data segment in a second one of the plurality of data blocks.
US12464856 2008-06-25 2009-05-12 Wear leveling in flash storage devices Abandoned US20090327804A1 (en)

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US12343378 Active 2031-03-24 US8843691B2 (en) 2008-06-25 2008-12-23 Prioritized erasure of data blocks in a flash storage device
US12464856 Abandoned US20090327804A1 (en) 2008-06-25 2009-05-12 Wear leveling in flash storage devices
US12492107 Active 2031-07-07 US8347138B2 (en) 2008-06-25 2009-06-25 Redundant data distribution in a flash storage device
US12492103 Active 2032-03-16 US8572308B2 (en) 2008-06-25 2009-06-25 Supporting variable sector sizes in flash storage devices
US12492113 Active 2030-09-13 US8825941B2 (en) 2008-06-25 2009-06-25 SLC-MLC combination flash storage device
US12492112 Active 2030-08-02 US8762622B2 (en) 2008-06-25 2009-06-25 Enhanced MLC solid state device
US12492110 Abandoned US20120239853A1 (en) 2008-06-25 2009-06-25 Solid state device with allocated flash cache
US12492104 Active 2030-06-04 US9311006B2 (en) 2008-06-25 2009-06-25 Table journaling in flash storage devices
US12492109 Active 2030-06-15 US9043531B2 (en) 2008-06-25 2009-06-25 High speed input/output performance in solid state devices
US14720697 Active US9411522B2 (en) 2008-06-25 2015-05-22 High speed input/output performance in solid state devices

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US12492113 Active 2030-09-13 US8825941B2 (en) 2008-06-25 2009-06-25 SLC-MLC combination flash storage device
US12492112 Active 2030-08-02 US8762622B2 (en) 2008-06-25 2009-06-25 Enhanced MLC solid state device
US12492110 Abandoned US20120239853A1 (en) 2008-06-25 2009-06-25 Solid state device with allocated flash cache
US12492104 Active 2030-06-04 US9311006B2 (en) 2008-06-25 2009-06-25 Table journaling in flash storage devices
US12492109 Active 2030-06-15 US9043531B2 (en) 2008-06-25 2009-06-25 High speed input/output performance in solid state devices
US14720697 Active US9411522B2 (en) 2008-06-25 2015-05-22 High speed input/output performance in solid state devices

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Cited By (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090034994A1 (en) * 2007-07-31 2009-02-05 Canon Kabushiki Kaisha Image forming apparatus and control method thereof
US8285927B2 (en) 2006-12-06 2012-10-09 Fusion-Io, Inc. Apparatus, system, and method for solid-state storage as cache for high-capacity, non-volatile storage
CN103092770A (en) * 2013-01-18 2013-05-08 山东华芯半导体有限公司 Method for reducing random access memory (RAM) expense in abrasion balanced processing
US8443134B2 (en) 2006-12-06 2013-05-14 Fusion-Io, Inc. Apparatus, system, and method for graceful cache device degradation
US8489817B2 (en) 2007-12-06 2013-07-16 Fusion-Io, Inc. Apparatus, system, and method for caching data
US8489804B1 (en) * 2009-09-14 2013-07-16 Marvell International Ltd. System for using dynamic random access memory to reduce the effect of write amplification in flash memory
US8578127B2 (en) 2009-09-09 2013-11-05 Fusion-Io, Inc. Apparatus, system, and method for allocating storage
US8612804B1 (en) 2010-09-30 2013-12-17 Western Digital Technologies, Inc. System and method for improving wear-leveling performance in solid-state memory
US8706968B2 (en) 2007-12-06 2014-04-22 Fusion-Io, Inc. Apparatus, system, and method for redundant write caching
US8719501B2 (en) 2009-09-08 2014-05-06 Fusion-Io Apparatus, system, and method for caching data on a solid-state storage device
US8782344B2 (en) 2012-01-12 2014-07-15 Fusion-Io, Inc. Systems and methods for managing cache admission
US8825937B2 (en) 2011-02-25 2014-09-02 Fusion-Io, Inc. Writing cached data forward on read
US8874823B2 (en) 2011-02-15 2014-10-28 Intellectual Property Holdings 2 Llc Systems and methods for managing data input/output operations
US8898373B1 (en) 2011-06-29 2014-11-25 Western Digital Technologies, Inc. System and method for improving wear-leveling performance in solid-state memory
US8966191B2 (en) 2011-03-18 2015-02-24 Fusion-Io, Inc. Logical interface for contextual storage
US8966184B2 (en) 2011-01-31 2015-02-24 Intelligent Intellectual Property Holdings 2, LLC. Apparatus, system, and method for managing eviction of data
US9003104B2 (en) 2011-02-15 2015-04-07 Intelligent Intellectual Property Holdings 2 Llc Systems and methods for a file-level cache
US9058123B2 (en) 2012-08-31 2015-06-16 Intelligent Intellectual Property Holdings 2 Llc Systems, methods, and interfaces for adaptive persistence
US9104599B2 (en) 2007-12-06 2015-08-11 Intelligent Intellectual Property Holdings 2 Llc Apparatus, system, and method for destaging cached data
US9116812B2 (en) 2012-01-27 2015-08-25 Intelligent Intellectual Property Holdings 2 Llc Systems and methods for a de-duplication cache
US9122579B2 (en) 2010-01-06 2015-09-01 Intelligent Intellectual Property Holdings 2 Llc Apparatus, system, and method for a storage layer
US9201677B2 (en) 2011-05-23 2015-12-01 Intelligent Intellectual Property Holdings 2 Llc Managing data input/output operations
US9251086B2 (en) 2012-01-24 2016-02-02 SanDisk Technologies, Inc. Apparatus, system, and method for managing a cache
US9251052B2 (en) 2012-01-12 2016-02-02 Intelligent Intellectual Property Holdings 2 Llc Systems and methods for profiling a non-volatile cache having a logical-to-physical translation layer
US9274937B2 (en) 2011-12-22 2016-03-01 Longitude Enterprise Flash S.A.R.L. Systems, methods, and interfaces for vector input/output operations
US9519540B2 (en) 2007-12-06 2016-12-13 Sandisk Technologies Llc Apparatus, system, and method for destaging cached data
US9563555B2 (en) 2011-03-18 2017-02-07 Sandisk Technologies Llc Systems and methods for storage allocation
US9600184B2 (en) 2007-12-06 2017-03-21 Sandisk Technologies Llc Apparatus, system, and method for coordinating storage requests in a multi-processor/multi-thread environment
US9612966B2 (en) 2012-07-03 2017-04-04 Sandisk Technologies Llc Systems, methods and apparatus for a virtual machine cache
US9767032B2 (en) 2012-01-12 2017-09-19 Sandisk Technologies Llc Systems and methods for cache endurance
US9842053B2 (en) 2013-03-15 2017-12-12 Sandisk Technologies Llc Systems and methods for persistent cache logging
US9842128B2 (en) 2013-08-01 2017-12-12 Sandisk Technologies Llc Systems and methods for atomic storage operations

Families Citing this family (206)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7852654B2 (en) * 2006-12-28 2010-12-14 Hynix Semiconductor Inc. Semiconductor memory device, and multi-chip package and method of operating the same
US7975105B1 (en) * 2007-12-03 2011-07-05 Yingju Sun Solid state storage devices with changeable capacity
CN101632068B (en) * 2007-12-28 2015-01-14 株式会社东芝 Semiconductor storage device
US8843691B2 (en) 2008-06-25 2014-09-23 Stec, Inc. Prioritized erasure of data blocks in a flash storage device
JP5192352B2 (en) * 2008-10-30 2013-05-08 株式会社日立製作所 Storage apparatus and a data storage area management method
US20100115153A1 (en) * 2008-11-05 2010-05-06 Industrial Technology Research Institute Adaptive multi-channel controller and method for storage device
US8239613B2 (en) * 2008-12-30 2012-08-07 Intel Corporation Hybrid memory device
US8225067B2 (en) * 2009-02-10 2012-07-17 Phison Electronics Corp. Multilevel cell NAND flash memory storage system, and controller and access method thereof
KR20100097456A (en) * 2009-02-26 2010-09-03 삼성전자주식회사 Memory system and address allocating method of flash translation layer thereof
US8261158B2 (en) * 2009-03-13 2012-09-04 Fusion-Io, Inc. Apparatus, system, and method for using multi-level cell solid-state storage as single level cell solid-state storage
US9245653B2 (en) 2010-03-15 2016-01-26 Intelligent Intellectual Property Holdings 2 Llc Reduced level cell mode for non-volatile memory
US8854882B2 (en) 2010-01-27 2014-10-07 Intelligent Intellectual Property Holdings 2 Llc Configuring storage cells
US8266503B2 (en) 2009-03-13 2012-09-11 Fusion-Io Apparatus, system, and method for using multi-level cell storage in a single-level cell mode
US8661184B2 (en) 2010-01-27 2014-02-25 Fusion-Io, Inc. Managing non-volatile media
KR101581679B1 (en) * 2009-03-18 2015-12-31 삼성전자주식회사 A buffer memory management method of a storage device and a storage device,
US8195891B2 (en) * 2009-03-30 2012-06-05 Intel Corporation Techniques to perform power fail-safe caching without atomic metadata
US8171219B2 (en) * 2009-03-31 2012-05-01 Intel Corporation Method and system to perform caching based on file-level heuristics
US8341501B2 (en) * 2009-04-30 2012-12-25 International Business Machines Corporation Adaptive endurance coding of non-volatile memories
US20100318746A1 (en) * 2009-06-12 2010-12-16 Seakr Engineering, Incorporated Memory change track logging
US20100332726A1 (en) * 2009-06-26 2010-12-30 Solid State System Co., Ltd. Structure and method for managing writing operation on mlc flash memory
US20100332922A1 (en) * 2009-06-30 2010-12-30 Mediatek Inc. Method for managing device and solid state disk drive utilizing the same
US8510497B2 (en) * 2009-07-29 2013-08-13 Stec, Inc. Flash storage device with flexible data format
US8930622B2 (en) 2009-08-11 2015-01-06 International Business Machines Corporation Multi-level data protection for flash memory system
US7941696B2 (en) * 2009-08-11 2011-05-10 Texas Memory Systems, Inc. Flash-based memory system with static or variable length page stripes including data protection information and auxiliary protection stripes
US8176284B2 (en) * 2009-08-11 2012-05-08 Texas Memory Systems, Inc. FLASH-based memory system with variable length page stripes including data protection information
US8189379B2 (en) 2009-08-12 2012-05-29 Texas Memory Systems, Inc. Reduction of read disturb errors in NAND FLASH memory
US7818525B1 (en) 2009-08-12 2010-10-19 Texas Memory Systems, Inc. Efficient reduction of read disturb errors in NAND FLASH memory
JP5002629B2 (en) * 2009-08-28 2012-08-15 株式会社東芝 Memory system
US8990476B2 (en) 2009-10-01 2015-03-24 Micron Technology, Inc. Power interrupt management
US8214700B2 (en) 2009-10-28 2012-07-03 Sandisk Technologies Inc. Non-volatile memory and method with post-write read and adaptive re-write to manage errors
US8423866B2 (en) * 2009-10-28 2013-04-16 SanDisk Technologies, Inc. Non-volatile memory and method with post-write read and adaptive re-write to manage errors
US8634240B2 (en) * 2009-10-28 2014-01-21 SanDisk Technologies, Inc. Non-volatile memory and method with accelerated post-write read to manage errors
US8560770B2 (en) * 2009-11-13 2013-10-15 Seagate Technology Llc Non-volatile write cache for a data storage system
US8176235B2 (en) * 2009-12-04 2012-05-08 International Business Machines Corporation Non-volatile memories with enhanced write performance and endurance
GB2488457B (en) * 2009-12-17 2018-01-03 Ibm Data management in solid state storage devices
US8473808B2 (en) * 2010-01-26 2013-06-25 Qimonda Ag Semiconductor memory having non-standard form factor
US8725931B1 (en) 2010-03-26 2014-05-13 Western Digital Technologies, Inc. System and method for managing the execution of memory commands in a solid-state memory
US8713066B1 (en) * 2010-03-29 2014-04-29 Western Digital Technologies, Inc. Managing wear leveling and garbage collection operations in a solid-state memory using linked lists
JP2011209973A (en) * 2010-03-30 2011-10-20 Hitachi Ltd Disk array configuration program, computer and computer system
US8751740B1 (en) * 2010-03-31 2014-06-10 Emc Corporation Systems, methods, and computer readable media for performance optimization of storage allocation to virtual logical units
US8621141B2 (en) * 2010-04-01 2013-12-31 Intel Corporations Method and system for wear leveling in a solid state drive
US9311105B2 (en) * 2010-04-21 2016-04-12 Hewlett-Packard Development Company, L.P. Communicating operating system booting information
US8782327B1 (en) 2010-05-11 2014-07-15 Western Digital Technologies, Inc. System and method for managing execution of internal commands and host commands in a solid-state memory
US9026716B2 (en) * 2010-05-12 2015-05-05 Western Digital Technologies, Inc. System and method for managing garbage collection in solid-state memory
US8959300B2 (en) * 2010-05-18 2015-02-17 International Business Machines Corporation Cascade ordering
US8886870B2 (en) * 2010-05-25 2014-11-11 Marvell World Trade Ltd. Memory access table saving and restoring system and methods
US8966176B2 (en) 2010-05-27 2015-02-24 Sandisk Il Ltd. Memory management storage to a host device
US9043533B1 (en) * 2010-06-29 2015-05-26 Emc Corporation Sizing volatile memory cache based on flash-based cache usage
US8656256B2 (en) * 2010-07-07 2014-02-18 Stec, Inc. Apparatus and method for multi-mode operation of a flash memory device
WO2012020544A1 (en) * 2010-08-11 2012-02-16 日本電気株式会社 Data processing system, data processing method, and program
US8417878B2 (en) 2010-09-20 2013-04-09 Seagate Technology Llc Selection of units for garbage collection in flash memory
US9164886B1 (en) 2010-09-21 2015-10-20 Western Digital Technologies, Inc. System and method for multistage processing in a memory storage subsystem
US9021192B1 (en) 2010-09-21 2015-04-28 Western Digital Technologies, Inc. System and method for enhancing processing of memory access requests
WO2012039983A1 (en) 2010-09-24 2012-03-29 Rambus Inc. Memory device with ecc history table
US8949507B2 (en) * 2010-09-27 2015-02-03 Silicon Motion Inc. Method for performing block management, and associated memory device and controller thereof
US8856425B2 (en) * 2010-09-27 2014-10-07 Silicon Motion Inc. Method for performing meta block management, and associated memory device and controller thereof
US9110850B2 (en) * 2010-10-12 2015-08-18 Eci Telecom Ltd. Method for accelerating start up of a computerized system
US8769374B2 (en) 2010-10-13 2014-07-01 International Business Machines Corporation Multi-write endurance and error control coding of non-volatile memories
US20120124275A1 (en) * 2010-11-15 2012-05-17 Kabushiki Kaisha Toshiba Memory system and data storage method
US8949502B2 (en) * 2010-11-18 2015-02-03 Nimble Storage, Inc. PCIe NVRAM card based on NVDIMM
US8089807B1 (en) 2010-11-22 2012-01-03 Ge Aviation Systems, Llc Method and system for data storage
CN102479156B (en) * 2010-11-22 2015-03-11 慧荣科技股份有限公司 Method for carrying out block management and memory device and controller thereof
US8495338B2 (en) 2010-12-03 2013-07-23 Micron Technology, Inc. Transaction log recovery
US9465544B2 (en) * 2010-12-03 2016-10-11 Samsung Electronics Co., Ltd. Method of processing data and system using the same
US9268646B1 (en) * 2010-12-21 2016-02-23 Western Digital Technologies, Inc. System and method for optimized management of operation data in a solid-state memory
US8909851B2 (en) 2011-02-08 2014-12-09 SMART Storage Systems, Inc. Storage control system with change logging mechanism and method of operation thereof
KR101800444B1 (en) * 2011-03-28 2017-12-20 삼성전자주식회사 Control method of nonvolatile memory and memory system including the same
US9361044B2 (en) 2011-03-28 2016-06-07 Western Digital Technologies, Inc. Power-safe data management system
US8935466B2 (en) 2011-03-28 2015-01-13 SMART Storage Systems, Inc. Data storage system with non-volatile memory and method of operation thereof
KR101810932B1 (en) * 2011-04-27 2017-12-20 시게이트 테크놀로지 엘엘씨 Method for managing address mapping information, accessing method of disk drive, method for managing address mapping information via network, and storage device, computer system and storage medium applying the same
US8886911B2 (en) 2011-05-31 2014-11-11 Micron Technology, Inc. Dynamic memory cache size adjustment in a memory device
US8792273B2 (en) 2011-06-13 2014-07-29 SMART Storage Systems, Inc. Data storage system with power cycle management and method of operation thereof
US9003101B1 (en) 2011-06-29 2015-04-07 Western Digital Technologies, Inc. Prioritized access for media with heterogeneous access rates
US9158670B1 (en) * 2011-06-30 2015-10-13 Western Digital Technologies, Inc. System and method for dynamically adjusting garbage collection policies in solid-state memory
US20130007373A1 (en) * 2011-06-30 2013-01-03 Advanced Micro Devices, Inc. Region based cache replacement policy utilizing usage information
US9032269B2 (en) 2011-07-22 2015-05-12 Sandisk Technologies Inc. Systems and methods of storing data
US8726104B2 (en) 2011-07-28 2014-05-13 Sandisk Technologies Inc. Non-volatile memory and method with accelerated post-write read using combined verification of multiple pages
KR20130019567A (en) 2011-08-17 2013-02-27 삼성전자주식회사 Memory system including migration manager
US9098399B2 (en) 2011-08-31 2015-08-04 SMART Storage Systems, Inc. Electronic system with storage management mechanism and method of operation thereof
US9021231B2 (en) 2011-09-02 2015-04-28 SMART Storage Systems, Inc. Storage control system with write amplification control mechanism and method of operation thereof
US9021319B2 (en) 2011-09-02 2015-04-28 SMART Storage Systems, Inc. Non-volatile memory management system with load leveling and method of operation thereof
US9063844B2 (en) 2011-09-02 2015-06-23 SMART Storage Systems, Inc. Non-volatile memory management system with time measure mechanism and method of operation thereof
CN102279808A (en) * 2011-09-06 2011-12-14 晨星半导体股份有限公司 An embedded device management method and an image memory apparatus
US20130067182A1 (en) * 2011-09-09 2013-03-14 Onzo Limited Data processing method and system
US9298603B2 (en) * 2011-09-09 2016-03-29 OCZ Storage Solutions Inc. NAND flash-based storage device and methods of using
US9367453B1 (en) * 2011-09-30 2016-06-14 Emc Corporation System and method for migrating cache data
US8635407B2 (en) * 2011-09-30 2014-01-21 International Business Machines Corporation Direct memory address for solid-state drives
US9367452B1 (en) * 2011-09-30 2016-06-14 Emc Corporation System and method for apportioning storage
US20130086300A1 (en) * 2011-10-04 2013-04-04 Lsi Corporation Storage caching acceleration through usage of r5 protected fast tier
US8539007B2 (en) 2011-10-17 2013-09-17 International Business Machines Corporation Efficient garbage collection in a compressed journal file
US8949553B2 (en) 2011-10-28 2015-02-03 Dell Products L.P. System and method for retention of historical data in storage resources
US8977803B2 (en) * 2011-11-21 2015-03-10 Western Digital Technologies, Inc. Disk drive data caching using a multi-tiered memory
US9240240B2 (en) * 2011-11-29 2016-01-19 Micron Technology, Inc. Apparatus having indications of memory cell density and methods of their determination and use
KR20130063191A (en) 2011-12-06 2013-06-14 삼성전자주식회사 Memory systems and block copy methods thereof
US9176862B2 (en) 2011-12-29 2015-11-03 Sandisk Technologies Inc. SLC-MLC wear balancing
US20130185503A1 (en) * 2012-01-12 2013-07-18 Vigneshwara Bhatta Method for metadata persistence
US8898423B1 (en) * 2012-01-31 2014-11-25 Western Digital Technologies, Inc. High performance caching architecture for data storage systems
US9223686B1 (en) * 2012-02-01 2015-12-29 Amazon Technologies, Inc. Cache memory data storage control system and method
US9239781B2 (en) 2012-02-07 2016-01-19 SMART Storage Systems, Inc. Storage control system with erase block mechanism and method of operation thereof
KR20130096489A (en) 2012-02-22 2013-08-30 삼성전자주식회사 Memory system and program method thereof
JP5659178B2 (en) * 2012-03-16 2015-01-28 株式会社東芝 Nonvolatile memory device and a control method of a nonvolatile memory
US9298252B2 (en) 2012-04-17 2016-03-29 SMART Storage Systems, Inc. Storage control system with power down mechanism and method of operation thereof
US8990477B2 (en) * 2012-04-19 2015-03-24 Sandisk Technologies Inc. System and method for limiting fragmentation
US8868824B2 (en) 2012-04-19 2014-10-21 Microsoft Corporation Solid-state drive management and control
US9003224B2 (en) 2012-04-25 2015-04-07 Western Digital Technologies, Inc. Managing unreliable memory in data storage systems
US9116792B2 (en) * 2012-05-18 2015-08-25 Silicon Motion, Inc. Data storage device and method for flash block management
US20130311700A1 (en) * 2012-05-20 2013-11-21 Chung-Jwu Chen Extending Lifetime For Non-volatile Memory Apparatus
US9021337B1 (en) 2012-05-22 2015-04-28 Pmc-Sierra, Inc. Systems and methods for adaptively selecting among different error correction coding schemes in a flash drive
US8996957B1 (en) 2012-05-22 2015-03-31 Pmc-Sierra, Inc. Systems and methods for initializing regions of a flash drive having diverse error correction coding (ECC) schemes
US9021336B1 (en) 2012-05-22 2015-04-28 Pmc-Sierra, Inc. Systems and methods for redundantly storing error correction codes in a flash drive with secondary parity information spread out across each page of a group of pages
US8788910B1 (en) 2012-05-22 2014-07-22 Pmc-Sierra, Inc. Systems and methods for low latency, high reliability error correction in a flash drive
US9021333B1 (en) 2012-05-22 2015-04-28 Pmc-Sierra, Inc. Systems and methods for recovering data from failed portions of a flash drive
US9176812B1 (en) * 2012-05-22 2015-11-03 Pmc-Sierra, Inc. Systems and methods for storing data in page stripes of a flash drive
US9183085B1 (en) 2012-05-22 2015-11-10 Pmc-Sierra, Inc. Systems and methods for adaptively selecting from among a plurality of error correction coding schemes in a flash drive for robustness and low latency
US8793556B1 (en) 2012-05-22 2014-07-29 Pmc-Sierra, Inc. Systems and methods for reclaiming flash blocks of a flash drive
US9047214B1 (en) 2012-05-22 2015-06-02 Pmc-Sierra, Inc. System and method for tolerating a failed page in a flash device
US8972824B1 (en) 2012-05-22 2015-03-03 Pmc-Sierra, Inc. Systems and methods for transparently varying error correction code strength in a flash drive
CN103455428B (en) * 2012-05-31 2016-10-05 慧荣科技股份有限公司 A data storage device and method of operating a flash memory
US9195598B2 (en) 2012-06-08 2015-11-24 International Business Machines Corporation Synchronous and asynchronous discard scans based on the type of cache memory
US9336150B2 (en) 2012-06-08 2016-05-10 International Business Machines Corporation Performing asynchronous discard scans with staging and destaging operations
US8949689B2 (en) 2012-06-11 2015-02-03 SMART Storage Systems, Inc. Storage control system with data management mechanism and method of operation thereof
US8954653B1 (en) 2012-06-26 2015-02-10 Western Digital Technologies, Inc. Mechanisms for efficient management of system data in data storage systems
US9141530B2 (en) * 2012-06-26 2015-09-22 Phison Electronics Corp. Data writing method, memory controller and memory storage device
KR20140006234A (en) * 2012-06-29 2014-01-16 에스케이하이닉스 주식회사 Data storage device and operating method thereof
US8566671B1 (en) 2012-06-29 2013-10-22 Sandisk Technologies Inc. Configurable accelerated post-write read to manage errors
US8751730B2 (en) * 2012-07-27 2014-06-10 Winbond Electronics Corp. Serial interface flash memory apparatus and writing method for status register thereof
US9208099B2 (en) 2012-08-08 2015-12-08 International Business Machines Corporation Adjustment of the number of task control blocks allocated for discard scans
US8880786B2 (en) * 2012-09-28 2014-11-04 Apple Inc. Flash translation layer (FTL) database journaling schemes
KR20140044640A (en) 2012-10-05 2014-04-15 삼성전자주식회사 Memory system and read reclaim method thereof
US9507523B1 (en) 2012-10-12 2016-11-29 Western Digital Technologies, Inc. Methods, devices and systems for variable size logical page management in a solid state drive
US9489296B1 (en) * 2012-10-17 2016-11-08 Western Digital Technologies, Inc. Methods, devices and systems for hardware-based garbage collection in solid state drives
US20140136575A1 (en) * 2012-11-10 2014-05-15 Yuanyuan Zhao Log-structured garbage collection
US9671962B2 (en) 2012-11-30 2017-06-06 Sandisk Technologies Llc Storage control system with data management mechanism of parity and method of operation thereof
CN103034603B (en) * 2012-12-07 2014-06-18 天津瑞发科半导体技术有限公司 Multi-channel flash memory card control device and control method thereof
US20150143021A1 (en) * 2012-12-26 2015-05-21 Unisys Corporation Equalizing wear on storage devices through file system controls
JP2016506585A (en) * 2013-01-08 2016-03-03 ヴァイオリン メモリー インコーポレイテッド Method and system for data storage
US9123445B2 (en) 2013-01-22 2015-09-01 SMART Storage Systems, Inc. Storage control system with data management mechanism and method of operation thereof
US9176892B2 (en) * 2013-01-22 2015-11-03 International Business Machines Corporation Performing staging or destaging based on the number of waiting discard scans
US20140223072A1 (en) * 2013-02-07 2014-08-07 Lsi Corporation Tiered Caching Using Single Level Cell and Multi-Level Cell Flash Technology
US9214965B2 (en) 2013-02-20 2015-12-15 Sandisk Enterprise Ip Llc Method and system for improving data integrity in non-volatile storage
US9329928B2 (en) 2013-02-20 2016-05-03 Sandisk Enterprise IP LLC. Bandwidth optimization in a non-volatile memory system
US9183137B2 (en) 2013-02-27 2015-11-10 SMART Storage Systems, Inc. Storage control system with data management mechanism and method of operation thereof
US20140250277A1 (en) * 2013-03-04 2014-09-04 Kabushiki Kaisha Toshiba Memory system
US9470720B2 (en) 2013-03-08 2016-10-18 Sandisk Technologies Llc Test system with localized heating and method of manufacture thereof
US9208018B1 (en) 2013-03-15 2015-12-08 Pmc-Sierra, Inc. Systems and methods for reclaiming memory for solid-state memory
US9081701B1 (en) 2013-03-15 2015-07-14 Pmc-Sierra, Inc. Systems and methods for decoding data for solid-state memory
US9009565B1 (en) 2013-03-15 2015-04-14 Pmc-Sierra, Inc. Systems and methods for mapping for solid-state memory
US9053012B1 (en) 2013-03-15 2015-06-09 Pmc-Sierra, Inc. Systems and methods for storing data for solid-state memory
US9026867B1 (en) 2013-03-15 2015-05-05 Pmc-Sierra, Inc. Systems and methods for adapting to changing characteristics of multi-level cells in solid-state memory
US9043780B2 (en) 2013-03-27 2015-05-26 SMART Storage Systems, Inc. Electronic system with system modification control mechanism and method of operation thereof
US9170941B2 (en) 2013-04-05 2015-10-27 Sandisk Enterprises IP LLC Data hardening in a storage system
US9543025B2 (en) 2013-04-11 2017-01-10 Sandisk Technologies Llc Storage control system with power-off time estimation mechanism and method of operation thereof
US9830257B1 (en) * 2013-06-12 2017-11-28 Western Digital Technologies, Inc. Fast saving of data during power interruption in data storage systems
US9313874B2 (en) 2013-06-19 2016-04-12 SMART Storage Systems, Inc. Electronic system with heat extraction and method of manufacture thereof
US9367353B1 (en) 2013-06-25 2016-06-14 Sandisk Technologies Inc. Storage control system with power throttling mechanism and method of operation thereof
US9244519B1 (en) 2013-06-25 2016-01-26 Smart Storage Systems. Inc. Storage system with data transfer rate adjustment for power throttling
CN104298605A (en) * 2013-07-17 2015-01-21 光宝科技股份有限公司 Method of grouping blocks used for garbage collection action in solid state drive
CN104298465B (en) * 2013-07-17 2017-06-20 光宝电子(广州)有限公司 Solid state storage device block grouping method
US9146850B2 (en) 2013-08-01 2015-09-29 SMART Storage Systems, Inc. Data storage system with dynamic read threshold mechanism and method of operation thereof
US9274865B2 (en) 2013-08-01 2016-03-01 HGST Netherlands B.V. Implementing enhanced buffer management for data storage devices
US9361222B2 (en) 2013-08-07 2016-06-07 SMART Storage Systems, Inc. Electronic system with storage drive life estimation mechanism and method of operation thereof
US9431113B2 (en) 2013-08-07 2016-08-30 Sandisk Technologies Llc Data storage system with dynamic erase block grouping mechanism and method of operation thereof
US9448946B2 (en) 2013-08-07 2016-09-20 Sandisk Technologies Llc Data storage system with stale data mechanism and method of operation thereof
KR20150020384A (en) * 2013-08-13 2015-02-26 에스케이하이닉스 주식회사 Data storage device and operating method thereof
KR20150020385A (en) * 2013-08-13 2015-02-26 에스케이하이닉스 주식회사 Data storage device, operating method thereof and data processing system including the same
JP5768100B2 (en) * 2013-09-10 2015-08-26 株式会社東芝 Memory device, a server device, and a memory control method
US20150089162A1 (en) * 2013-09-26 2015-03-26 Bushra Ahsan Distributed memory operations
US9152555B2 (en) 2013-11-15 2015-10-06 Sandisk Enterprise IP LLC. Data management with modular erase in a data storage system
US9463737B2 (en) 2013-11-21 2016-10-11 Ford Global Technologies, Llc Illuminated seatbelt assembly
US9213601B2 (en) 2013-12-03 2015-12-15 Sandisk Technologies Inc. Adaptive data re-compaction after post-write read verification operations
US9645894B2 (en) 2013-12-26 2017-05-09 Silicon Motion, Inc. Data storage device and flash memory control method
US9274891B2 (en) 2013-12-31 2016-03-01 Phison Electronics Corp. Decoding method, memory storage device, and memory controlling circuit unit
WO2015109128A1 (en) * 2014-01-16 2015-07-23 Pure Storage, Inc. Data replacement based on data properties and data retention in a tiered storage device system
US8874835B1 (en) 2014-01-16 2014-10-28 Pure Storage, Inc. Data placement based on data properties in a tiered storage device system
US9354955B1 (en) 2014-03-19 2016-05-31 Western Digital Technologies, Inc. Partial garbage collection for fast error handling and optimized garbage collection for the invisible band
US20150278088A1 (en) * 2014-03-27 2015-10-01 Canon Kabushiki Kaisha Memory control apparatus, information processing apparatus and control method thereof, and storage medium
US9529670B2 (en) * 2014-05-16 2016-12-27 International Business Machines Corporation Storage element polymorphism to reduce performance degradation during error recovery
US20150370700A1 (en) * 2014-06-23 2015-12-24 Google Inc. Managing storage devices
JP2016028319A (en) * 2014-07-08 2016-02-25 富士通株式会社 Access control program, access control device, and access control method
US9766972B2 (en) 2014-08-07 2017-09-19 Pure Storage, Inc. Masking defective bits in a storage array
US9558069B2 (en) 2014-08-07 2017-01-31 Pure Storage, Inc. Failure mapping in a storage array
KR20160024530A (en) * 2014-08-26 2016-03-07 에스케이하이닉스 주식회사 Semiconductor device and operating method thereof
US20160062832A1 (en) * 2014-09-02 2016-03-03 Netapp. Inc. Wide spreading data storage architecture
US9823969B2 (en) 2014-09-02 2017-11-21 Netapp, Inc. Hierarchical wide spreading of distributed storage
US9767104B2 (en) 2014-09-02 2017-09-19 Netapp, Inc. File system for efficient object fragment access
US9632702B2 (en) 2014-10-15 2017-04-25 International Business Machines Corporation Efficient initialization of a thinly provisioned storage array
JP6193834B2 (en) * 2014-10-29 2017-09-06 ファナック株式会社 Data storage system
US20160225461A1 (en) * 2015-01-30 2016-08-04 Sandisk Technologies Inc. Memory System and Method for Reducing Read Disturb Errors
JP2016178575A (en) * 2015-03-23 2016-10-06 富士通株式会社 Portable equipment and information processing device
US9431061B1 (en) 2015-04-24 2016-08-30 Netapp, Inc. Data write deferral during hostile events
US9817715B2 (en) 2015-04-24 2017-11-14 Netapp, Inc. Resiliency fragment tiering
US9697134B2 (en) 2015-06-10 2017-07-04 Micron Technology, Inc. Memory having a static cache and a dynamic cache
CN104991738A (en) * 2015-06-19 2015-10-21 华中科技大学 Solid state disk and read and write operation method thereof
KR20160150478A (en) * 2015-06-22 2016-12-30 삼성전자주식회사 Data storage device and data processing system having the same
US9792068B2 (en) * 2015-09-10 2017-10-17 Toshiba Memory Corporation Memory system and method of controlling nonvolatile memory
US20170075812A1 (en) * 2015-09-16 2017-03-16 Intel Corporation Technologies for managing a dynamic read cache of a solid state drive
US9830108B2 (en) 2015-10-12 2017-11-28 Sandisk Technologies Llc Write redirect
US9778855B2 (en) 2015-10-30 2017-10-03 Sandisk Technologies Llc System and method for precision interleaving of data writes in a non-volatile memory
US20170123726A1 (en) * 2015-10-30 2017-05-04 Sandisk Technologies Inc. System and method for rescheduling host and maintenance operations in a non-volatile memory
US9530491B1 (en) * 2015-11-16 2016-12-27 Sandisk Technologies Llc System and method for direct write to MLC memory
US20170177258A1 (en) * 2015-12-18 2017-06-22 Pmc Sierra Us, Inc. Method of configuring memory cells in a solid state drive and controller therefor
US20170255564A1 (en) * 2016-03-04 2017-09-07 Kabushiki Kaisha Toshiba Memory system
US20170269844A1 (en) 2016-03-21 2017-09-21 Apple Inc. Managing backup of logical-to-physical translation information to control boot-time and write amplification
US9792995B1 (en) 2016-04-26 2017-10-17 Sandisk Technologies Llc Independent multi-plane read and low latency hybrid read
US9672905B1 (en) 2016-07-22 2017-06-06 Pure Storage, Inc. Optimize data protection layouts based on distributed flash wear leveling
US9747158B1 (en) 2017-01-13 2017-08-29 Pure Storage, Inc. Intelligent refresh of 3D NAND

Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5956473A (en) * 1996-11-25 1999-09-21 Macronix International Co., Ltd. Method and system for managing a flash memory mass storage system
US6732221B2 (en) * 2001-06-01 2004-05-04 M-Systems Flash Disk Pioneers Ltd Wear leveling of static areas in flash memory
US6895464B2 (en) * 2002-06-03 2005-05-17 Honeywell International Inc. Flash memory management system and method utilizing multiple block list windows
US7173852B2 (en) * 2003-10-03 2007-02-06 Sandisk Corporation Corrected data storage and handling methods
US7188210B2 (en) * 1993-10-01 2007-03-06 Fujitsu Limited Method of writing, erasing, and controlling memory for memory device
US20070260811A1 (en) * 2006-05-08 2007-11-08 Merry David E Jr Systems and methods for measuring the useful life of solid-state storage devices
US20080052599A1 (en) * 2006-08-09 2008-02-28 Microsoft Corporation Dynamic electronic correction code feedback to extend memory device lifetime
US20080098192A1 (en) * 2006-10-19 2008-04-24 Samsung Electronics Co., Ltd. Methods of reusing log blocks in non-volatile memories and related non-volatile memory devices
US20080147998A1 (en) * 2006-12-18 2008-06-19 Samsung Electronics Co., Ltd. Method and apparatus for detecting static data area, wear-leveling, and merging data units in nonvolatile data storage device
US20080162796A1 (en) * 2006-12-28 2008-07-03 Genesys Logic, Inc. Method for performing static wear leveling on flash memory
US20090077429A1 (en) * 2007-09-13 2009-03-19 Samsung Electronics Co., Ltd. Memory system and wear-leveling method thereof
US20090157950A1 (en) * 2007-12-14 2009-06-18 Robert David Selinger NAND flash module replacement for DRAM module
US20090172250A1 (en) * 2007-12-28 2009-07-02 Spansion Llc Relocating data in a memory device
US7743203B2 (en) * 2007-05-11 2010-06-22 Spansion Llc Managing flash memory based upon usage history
US7945759B2 (en) * 2003-12-30 2011-05-17 Sandisk Corporation Non-volatile memory and method with phased program failure handling
US8266481B2 (en) * 2009-07-29 2012-09-11 Stec, Inc. System and method of wear-leveling in flash storage
US8453021B2 (en) * 2009-07-29 2013-05-28 Stec, Inc. Wear leveling in solid-state device

Family Cites Families (104)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2251324B (en) * 1990-12-31 1995-05-10 Intel Corp File structure for a non-volatile semiconductor memory
US5822781A (en) * 1992-10-30 1998-10-13 Intel Corporation Sector-based storage device emulator having variable-sized sector
US5341339A (en) * 1992-10-30 1994-08-23 Intel Corporation Method for wear leveling in a flash EEPROM memory
US5603001A (en) * 1994-05-09 1997-02-11 Kabushiki Kaisha Toshiba Semiconductor disk system having a plurality of flash memories
JPH08137634A (en) * 1994-11-09 1996-05-31 Mitsubishi Electric Corp Flash disk card
DE19540915A1 (en) * 1994-11-10 1996-05-15 Raymond Engineering Redundant array of solid state memory devices
US5671388A (en) * 1995-05-03 1997-09-23 Intel Corporation Method and apparatus for performing write operations in multi-level cell storage device
US6728851B1 (en) * 1995-07-31 2004-04-27 Lexar Media, Inc. Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
US5845313A (en) * 1995-07-31 1998-12-01 Lexar Direct logical block addressing flash memory mass storage architecture
US5812335A (en) * 1995-09-01 1998-09-22 Adaptec, Inc. Programmable data transfer without sector pulses in a headerless disk drive architecture
JP4079506B2 (en) * 1997-08-08 2008-04-23 株式会社東芝 Control method for a nonvolatile semiconductor memory system
US5881253A (en) * 1996-12-31 1999-03-09 Compaq Computer Corporation Computer system using posted memory write buffers in a bridge to implement system management mode
US5835741A (en) * 1996-12-31 1998-11-10 Compaq Computer Corporation Bus-to-bus bridge in computer system, with fast burst memory range
US5870567A (en) * 1996-12-31 1999-02-09 Compaq Computer Corporation Delayed transaction protocol for computer system bus
US5930167A (en) * 1997-07-30 1999-07-27 Sandisk Corporation Multi-state non-volatile flash memory capable of being its own two state write cache
US6041430A (en) * 1997-11-03 2000-03-21 Sun Microsystems, Inc. Error detection and correction code for data and check code fields
US6567889B1 (en) * 1997-12-19 2003-05-20 Lsi Logic Corporation Apparatus and method to provide virtual solid state disk in cache memory in a storage controller
US6408357B1 (en) * 1999-01-15 2002-06-18 Western Digital Technologies, Inc. Disk drive having a cache portion for storing write data segments of a predetermined length
US6449625B1 (en) * 1999-04-20 2002-09-10 Lucent Technologies Inc. Use of a two-way stack approach to optimize flash memory management for embedded database systems
US8037234B2 (en) 2003-12-02 2011-10-11 Super Talent Electronics, Inc. Command queuing smart storage transfer manager for striping data to raw-NAND flash modules
US8112574B2 (en) * 2004-02-26 2012-02-07 Super Talent Electronics, Inc. Swappable sets of partial-mapping tables in a flash-memory system with a command queue for combining flash writes
US8078794B2 (en) * 2000-01-06 2011-12-13 Super Talent Electronics, Inc. Hybrid SSD using a combination of SLC and MLC flash memory arrays
US7827348B2 (en) * 2000-01-06 2010-11-02 Super Talent Electronics, Inc. High performance flash memory devices (FMD)
US20080071973A1 (en) 2000-01-06 2008-03-20 Chow David Q Electronic data flash card with various flash memory cells
US6426893B1 (en) * 2000-02-17 2002-07-30 Sandisk Corporation Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
US6799268B1 (en) * 2000-06-30 2004-09-28 Intel Corporation Branch ordering buffer
US6684289B1 (en) * 2000-11-22 2004-01-27 Sandisk Corporation Techniques for operating non-volatile memory systems with data sectors having different sizes than the sizes of the pages and/or blocks of the memory
GB0028516D0 (en) * 2000-11-23 2001-01-10 Ibm Data logging method ,apparatus,system and computer program
KR100389867B1 (en) * 2001-06-04 2003-07-04 삼성전자주식회사 Flash memory management method
US6456528B1 (en) * 2001-09-17 2002-09-24 Sandisk Corporation Selective operation of a multi-state non-volatile memory system in a binary mode
GB0123415D0 (en) 2001-09-28 2001-11-21 Memquest Ltd Method of writing data to non-volatile memory
US6711663B2 (en) * 2001-11-15 2004-03-23 Key Technology Corporation Algorithm of flash memory capable of quickly building table and preventing improper operation and control system thereof
JP2003233993A (en) 2002-02-08 2003-08-22 Matsushita Electric Ind Co Ltd Method for rewriting nonvolatile memory device
US7533214B2 (en) * 2002-02-27 2009-05-12 Microsoft Corporation Open architecture flash driver
US6938140B2 (en) * 2002-08-29 2005-08-30 Micron Technology, Inc. System and method for linear object reallocation in place
US6676022B1 (en) * 2002-10-04 2004-01-13 Mobile-Mind, Inc. Smart card system with command queuing
US6973531B1 (en) * 2002-10-28 2005-12-06 Sandisk Corporation Tracking the most frequently erased blocks in non-volatile memory systems
KR101122511B1 (en) * 2002-10-28 2012-03-15 쌘디스크 코포레이션 Automated wear leveling in non-volatile storage systems
US6831865B2 (en) * 2002-10-28 2004-12-14 Sandisk Corporation Maintaining erase counts in non-volatile storage systems
US7003620B2 (en) * 2002-11-26 2006-02-21 M-Systems Flash Disk Pioneers Ltd. Appliance, including a flash memory, that is robust under power failure
US20050015557A1 (en) * 2002-12-27 2005-01-20 Chih-Hung Wang Nonvolatile memory unit with specific cache
US8041878B2 (en) * 2003-03-19 2011-10-18 Samsung Electronics Co., Ltd. Flash file system
JP2005108304A (en) * 2003-09-29 2005-04-21 Toshiba Corp Semiconductor memory and its control method
US7127549B2 (en) * 2004-02-04 2006-10-24 Sandisk Corporation Disk acceleration using first and second storage devices
KR100706242B1 (en) * 2005-02-07 2007-04-11 삼성전자주식회사 Memory system and run level address mapping table forming method thereof
US7275140B2 (en) * 2005-05-12 2007-09-25 Sandisk Il Ltd. Flash memory management method that is resistant to data corruption by power loss
US7779218B2 (en) * 2005-07-22 2010-08-17 Hewlett-Packard Development Company, L.P. Data synchronization management
KR100732628B1 (en) * 2005-07-28 2007-06-27 삼성전자주식회사 Flash memory device capable of multi-bit data and single-bit data
US7409489B2 (en) 2005-08-03 2008-08-05 Sandisk Corporation Scheduling of reclaim operations in non-volatile memory
US7571275B2 (en) 2005-08-31 2009-08-04 Hamilton Sundstrand Corporation Flash real-time operating system for small embedded applications
US7752382B2 (en) * 2005-09-09 2010-07-06 Sandisk Il Ltd Flash memory storage system and method
US20070165457A1 (en) * 2005-09-30 2007-07-19 Jin-Ki Kim Nonvolatile memory system
US20070083697A1 (en) * 2005-10-07 2007-04-12 Microsoft Corporation Flash memory management
US7263015B2 (en) * 2005-11-07 2007-08-28 Arm Limited Address decoding
US7366013B2 (en) * 2005-12-09 2008-04-29 Micron Technology, Inc. Single level cell programming in a multiple level cell non-volatile memory device
US20070156998A1 (en) * 2005-12-21 2007-07-05 Gorobets Sergey A Methods for memory allocation in non-volatile memories with a directly mapped file storage system
US7793068B2 (en) * 2005-12-21 2010-09-07 Sandisk Corporation Dual mode access for non-volatile storage devices
US7930468B2 (en) * 2006-05-23 2011-04-19 Dataram, Inc. System for reading and writing on flash memory device having plural microprocessors
US7882320B2 (en) * 2006-05-23 2011-02-01 Dataram, Inc. Multi-processor flash memory storage device and management system
US7424587B2 (en) * 2006-05-23 2008-09-09 Dataram, Inc. Methods for managing data writes and reads to a hybrid solid-state disk drive
US7464240B2 (en) * 2006-05-23 2008-12-09 Data Ram, Inc. Hybrid solid state disk drive with controller
US7461229B2 (en) * 2006-05-23 2008-12-02 Dataram, Inc. Software program for managing and protecting data written to a hybrid solid-state disk drive
JP4818812B2 (en) * 2006-05-31 2011-11-16 株式会社日立製作所 Flash memory storage system
US20070294467A1 (en) * 2006-06-20 2007-12-20 Kwok-Yan Leung Multi-Channel Flash Memory Data Access Method
JP4842719B2 (en) * 2006-06-28 2011-12-21 株式会社日立製作所 Storage system and method of data protection
US8234457B2 (en) * 2006-06-30 2012-07-31 Seagate Technology Llc Dynamic adaptive flushing of cached data
JP2008015769A (en) * 2006-07-05 2008-01-24 Hitachi Ltd Storage system and writing distribution method
KR20080017982A (en) * 2006-08-23 2008-02-27 삼성전자주식회사 Flash memory system and program method thereof
KR100771521B1 (en) 2006-10-30 2007-10-30 삼성전자주식회사 Flash memory device having a multi-leveled cell and programming method thereof
US7840877B2 (en) * 2006-10-31 2010-11-23 Hewlett-Packard Development Company, L.P. Mass storage system and method
KR100833188B1 (en) * 2006-11-03 2008-05-28 삼성전자주식회사 Non-volatile memory system storing data at single-level cell or multi-level cell based on the feature of data
US8296337B2 (en) * 2006-12-06 2012-10-23 Fusion-Io, Inc. Apparatus, system, and method for managing data from a requesting device with an empty data token directive
JP2008146254A (en) 2006-12-07 2008-06-26 Sony Corp Storage device, computer system and data processing method for storage device
US20080140918A1 (en) * 2006-12-11 2008-06-12 Pantas Sutardja Hybrid non-volatile solid state memory system
US7660911B2 (en) 2006-12-20 2010-02-09 Smart Modular Technologies, Inc. Block-based data striping to flash memory
US8095723B2 (en) 2007-02-16 2012-01-10 Electronics And Telecommunications Research Institute Log-based flash translation layer and operating method thereof
JP2008204041A (en) * 2007-02-19 2008-09-04 Hitachi Ltd Storage device and data arrangement control method
US20080282024A1 (en) 2007-05-09 2008-11-13 Sudeep Biswas Management of erase operations in storage devices based on flash memories
US7882301B2 (en) 2007-05-09 2011-02-01 Stmicroelectronics S.R.L. Wear leveling in storage devices based on flash memories and related circuit, system, and method
CN100458751C (en) * 2007-05-10 2009-02-04 忆正存储技术(深圳)有限公司 Paralleling flash memory controller
US9396103B2 (en) * 2007-06-08 2016-07-19 Sandisk Technologies Llc Method and system for storage address re-mapping for a memory device
KR100857761B1 (en) * 2007-06-14 2008-09-10 삼성전자주식회사 Memory system performing wear levelling and write method thereof
US7873803B2 (en) * 2007-09-25 2011-01-18 Sandisk Corporation Nonvolatile memory with self recovery
US8046526B2 (en) * 2007-09-27 2011-10-25 Phison Electronics Corp. Wear leveling method and controller using the same
US7876616B2 (en) * 2007-11-12 2011-01-25 Cadence Design Systems, Inc. System and method for wear leveling utilizing a relative wear counter
US8296498B2 (en) 2007-11-13 2012-10-23 Sandisk Technologies Inc. Method and system for virtual fast access non-volatile RAM
US8656083B2 (en) * 2007-12-21 2014-02-18 Spansion Llc Frequency distributed flash memory allocation based on free page tables
US8533384B2 (en) * 2007-12-27 2013-09-10 Sandisk Enterprise Ip Llc Flash memory controller garbage collection operations performed independently in multiple flash memory groups
US8103820B2 (en) * 2007-12-31 2012-01-24 Phison Electronics Corp. Wear leveling method and controller using the same
US7937521B2 (en) * 2008-01-29 2011-05-03 Cadence Design Systems, Inc. Read disturbance management in a non-volatile memory system
JP4675985B2 (en) * 2008-03-01 2011-04-27 株式会社東芝 Memory system
US7873619B1 (en) * 2008-03-31 2011-01-18 Emc Corporation Managing metadata
US7983051B2 (en) * 2008-04-09 2011-07-19 Apacer Technology Inc. DRAM module with solid state disk
US8131911B2 (en) 2008-04-18 2012-03-06 Phison Electronics Corp. Data writing method, and flash storage system and controller using the same
US20090271562A1 (en) * 2008-04-25 2009-10-29 Sinclair Alan W Method and system for storage address re-mapping for a multi-bank memory device
US7979626B2 (en) * 2008-05-13 2011-07-12 Microsoft Corporation Flash recovery employing transaction log
JP2010003055A (en) 2008-06-19 2010-01-07 Oki Comtec Ltd Control method of semiconductor auxiliary storage
US8843691B2 (en) * 2008-06-25 2014-09-23 Stec, Inc. Prioritized erasure of data blocks in a flash storage device
US8130554B1 (en) * 2008-09-29 2012-03-06 Emc Corporation Securely erasing flash-based memory
US8046530B2 (en) 2008-10-02 2011-10-25 Infineon Technologies Ag Process and method for erase strategy in solid state disks
US8219781B2 (en) * 2008-11-06 2012-07-10 Silicon Motion Inc. Method for managing a memory apparatus, and associated memory apparatus thereof
US8225067B2 (en) 2009-02-10 2012-07-17 Phison Electronics Corp. Multilevel cell NAND flash memory storage system, and controller and access method thereof
US7945822B1 (en) * 2009-04-27 2011-05-17 Netapp, Inc. Storing data to multi-chip low-latency random read memory device using non-aligned striping
US8688894B2 (en) * 2009-09-03 2014-04-01 Pioneer Chip Technology Ltd. Page based management of flash storage

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7188210B2 (en) * 1993-10-01 2007-03-06 Fujitsu Limited Method of writing, erasing, and controlling memory for memory device
US5956473A (en) * 1996-11-25 1999-09-21 Macronix International Co., Ltd. Method and system for managing a flash memory mass storage system
US6732221B2 (en) * 2001-06-01 2004-05-04 M-Systems Flash Disk Pioneers Ltd Wear leveling of static areas in flash memory
US6895464B2 (en) * 2002-06-03 2005-05-17 Honeywell International Inc. Flash memory management system and method utilizing multiple block list windows
US7173852B2 (en) * 2003-10-03 2007-02-06 Sandisk Corporation Corrected data storage and handling methods
US7945759B2 (en) * 2003-12-30 2011-05-17 Sandisk Corporation Non-volatile memory and method with phased program failure handling
US20070260811A1 (en) * 2006-05-08 2007-11-08 Merry David E Jr Systems and methods for measuring the useful life of solid-state storage devices
US20080052599A1 (en) * 2006-08-09 2008-02-28 Microsoft Corporation Dynamic electronic correction code feedback to extend memory device lifetime
US20080098192A1 (en) * 2006-10-19 2008-04-24 Samsung Electronics Co., Ltd. Methods of reusing log blocks in non-volatile memories and related non-volatile memory devices
US20080147998A1 (en) * 2006-12-18 2008-06-19 Samsung Electronics Co., Ltd. Method and apparatus for detecting static data area, wear-leveling, and merging data units in nonvolatile data storage device
US20080162796A1 (en) * 2006-12-28 2008-07-03 Genesys Logic, Inc. Method for performing static wear leveling on flash memory
US7743203B2 (en) * 2007-05-11 2010-06-22 Spansion Llc Managing flash memory based upon usage history
US20090077429A1 (en) * 2007-09-13 2009-03-19 Samsung Electronics Co., Ltd. Memory system and wear-leveling method thereof
US20090157950A1 (en) * 2007-12-14 2009-06-18 Robert David Selinger NAND flash module replacement for DRAM module
US20090172250A1 (en) * 2007-12-28 2009-07-02 Spansion Llc Relocating data in a memory device
US8266481B2 (en) * 2009-07-29 2012-09-11 Stec, Inc. System and method of wear-leveling in flash storage
US8453021B2 (en) * 2009-07-29 2013-05-28 Stec, Inc. Wear leveling in solid-state device

Non-Patent Citations (11)

* Cited by examiner, † Cited by third party
Title
Chang et al, "Endurance Enhancement of Flash-Memory Storage Systems: An Efficient Static Wear Leveling Design," Proceedings of the 44th Annual Design Automation Conference (DAC), June 4-8, 2007, pp. 212-217. *
Chang, "On Efficient Wear Leveling for Large-Scale Flash Memory Storage Systems," Proceedings of the 2007 ACM Symposium on Applied Computing (SAC '07), March 11-15, 2007, pp. 1126-1130. *
Cooke, "The Inconvenient Truths of NAND Flash Memory," Flash Memory Summit, Santa Clara, CA, August 2007, pp. 1-32. *
M-Systems DiskOnChip 2000 DIP, Data Sheet, Rev. 3.9, March 2006, pp. 1-27. *
Shmidt, "TrueFFS Wear-Leveling Mechanism," Technical Note (TN-DOC-017), Rev. 1.1, May 20, 2002, pp. 1-4. *
SiliconSystems article, "Increasing Flash SSD Reliability," retrieved from http://www.storagesearch.com/siliconsys-art1.html 04/18/2012, originally published April 2005, pp. 1-5. *
SiliconSystems White Paper, "Preventing Storage System Wear-Out, SiliconDrive Endurance," document SSWP00-Endurance-R, copyright 2006, pp. I, II and 1-10. *
STEC, Inc. Press Release, "STEC Unveils MACH8 Solid State Drive Product Family ...," August 7, 2007, pp. 1-2. *
STEC, Inc. White Paper, "How Flash Management Increases The Life Expectancy And Reliability Of Flash Media," WP-070615-B, dated August 2007, pp. 1-9. *
STEC, Inc. White Paper, "Solving The Complexity of Designing With NAND Flash," WP-061112, January 12, 2007, pp. 1-8. *
STEC, Inc., SSD Endurance White Paper, The Ins-and-Outs of SSD Endurance, STEC WP-070928, "The Appropriate Method for Determining Solid State Drive Endurance," publication date unknown, pp. 1-12. *

Cited By (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9734086B2 (en) 2006-12-06 2017-08-15 Sandisk Technologies Llc Apparatus, system, and method for a device shared between multiple independent hosts
US8756375B2 (en) 2006-12-06 2014-06-17 Fusion-Io, Inc. Non-volatile cache
US9454492B2 (en) 2006-12-06 2016-09-27 Longitude Enterprise Flash S.A.R.L. Systems and methods for storage parallelism
US8285927B2 (en) 2006-12-06 2012-10-09 Fusion-Io, Inc. Apparatus, system, and method for solid-state storage as cache for high-capacity, non-volatile storage
US9824027B2 (en) 2006-12-06 2017-11-21 Sandisk Technologies Llc Apparatus, system, and method for a storage area network
US8443134B2 (en) 2006-12-06 2013-05-14 Fusion-Io, Inc. Apparatus, system, and method for graceful cache device degradation
US9575902B2 (en) 2006-12-06 2017-02-21 Longitude Enterprise Flash S.A.R.L. Apparatus, system, and method for managing commands of solid-state storage using bank interleave
US8762658B2 (en) 2006-12-06 2014-06-24 Fusion-Io, Inc. Systems and methods for persistent deallocation
US8135291B2 (en) * 2007-07-31 2012-03-13 Canon Kabushiki Kaisha Consumable part for an image forming apparatus and a control method thereof
US20090034994A1 (en) * 2007-07-31 2009-02-05 Canon Kabushiki Kaisha Image forming apparatus and control method thereof
US20120141156A1 (en) * 2007-07-31 2012-06-07 Canon Kabushiki Kaisha Image forming apparatus and control method thereof
US8718495B2 (en) * 2007-07-31 2014-05-06 Canon Kabushiki Kaisha Image forming apparatus for controlling interval between accesses to memory in detachable unit
US9600184B2 (en) 2007-12-06 2017-03-21 Sandisk Technologies Llc Apparatus, system, and method for coordinating storage requests in a multi-processor/multi-thread environment
US8706968B2 (en) 2007-12-06 2014-04-22 Fusion-Io, Inc. Apparatus, system, and method for redundant write caching
US9519540B2 (en) 2007-12-06 2016-12-13 Sandisk Technologies Llc Apparatus, system, and method for destaging cached data
US8489817B2 (en) 2007-12-06 2013-07-16 Fusion-Io, Inc. Apparatus, system, and method for caching data
US9104599B2 (en) 2007-12-06 2015-08-11 Intelligent Intellectual Property Holdings 2 Llc Apparatus, system, and method for destaging cached data
US8719501B2 (en) 2009-09-08 2014-05-06 Fusion-Io Apparatus, system, and method for caching data on a solid-state storage device
US8578127B2 (en) 2009-09-09 2013-11-05 Fusion-Io, Inc. Apparatus, system, and method for allocating storage
US8489804B1 (en) * 2009-09-14 2013-07-16 Marvell International Ltd. System for using dynamic random access memory to reduce the effect of write amplification in flash memory
US8892816B1 (en) * 2009-09-14 2014-11-18 Marvell International Ltd. System and method for writing data to a memory
US8667217B1 (en) * 2009-09-14 2014-03-04 Marvell International Ltd. System for writing to memory
US9122579B2 (en) 2010-01-06 2015-09-01 Intelligent Intellectual Property Holdings 2 Llc Apparatus, system, and method for a storage layer
US8612804B1 (en) 2010-09-30 2013-12-17 Western Digital Technologies, Inc. System and method for improving wear-leveling performance in solid-state memory
US8966184B2 (en) 2011-01-31 2015-02-24 Intelligent Intellectual Property Holdings 2, LLC. Apparatus, system, and method for managing eviction of data
US9092337B2 (en) 2011-01-31 2015-07-28 Intelligent Intellectual Property Holdings 2 Llc Apparatus, system, and method for managing eviction of data
US9003104B2 (en) 2011-02-15 2015-04-07 Intelligent Intellectual Property Holdings 2 Llc Systems and methods for a file-level cache
US8874823B2 (en) 2011-02-15 2014-10-28 Intellectual Property Holdings 2 Llc Systems and methods for managing data input/output operations
US8825937B2 (en) 2011-02-25 2014-09-02 Fusion-Io, Inc. Writing cached data forward on read
US9141527B2 (en) 2011-02-25 2015-09-22 Intelligent Intellectual Property Holdings 2 Llc Managing cache pools
US9250817B2 (en) 2011-03-18 2016-02-02 SanDisk Technologies, Inc. Systems and methods for contextual storage
US8966191B2 (en) 2011-03-18 2015-02-24 Fusion-Io, Inc. Logical interface for contextual storage
US9563555B2 (en) 2011-03-18 2017-02-07 Sandisk Technologies Llc Systems and methods for storage allocation
US9201677B2 (en) 2011-05-23 2015-12-01 Intelligent Intellectual Property Holdings 2 Llc Managing data input/output operations
US8898373B1 (en) 2011-06-29 2014-11-25 Western Digital Technologies, Inc. System and method for improving wear-leveling performance in solid-state memory
US9274937B2 (en) 2011-12-22 2016-03-01 Longitude Enterprise Flash S.A.R.L. Systems, methods, and interfaces for vector input/output operations
US9767032B2 (en) 2012-01-12 2017-09-19 Sandisk Technologies Llc Systems and methods for cache endurance
US8782344B2 (en) 2012-01-12 2014-07-15 Fusion-Io, Inc. Systems and methods for managing cache admission
US9251052B2 (en) 2012-01-12 2016-02-02 Intelligent Intellectual Property Holdings 2 Llc Systems and methods for profiling a non-volatile cache having a logical-to-physical translation layer
US9251086B2 (en) 2012-01-24 2016-02-02 SanDisk Technologies, Inc. Apparatus, system, and method for managing a cache
US9116812B2 (en) 2012-01-27 2015-08-25 Intelligent Intellectual Property Holdings 2 Llc Systems and methods for a de-duplication cache
US9612966B2 (en) 2012-07-03 2017-04-04 Sandisk Technologies Llc Systems, methods and apparatus for a virtual machine cache
US9058123B2 (en) 2012-08-31 2015-06-16 Intelligent Intellectual Property Holdings 2 Llc Systems, methods, and interfaces for adaptive persistence
CN103092770A (en) * 2013-01-18 2013-05-08 山东华芯半导体有限公司 Method for reducing random access memory (RAM) expense in abrasion balanced processing
US9842053B2 (en) 2013-03-15 2017-12-12 Sandisk Technologies Llc Systems and methods for persistent cache logging
US9842128B2 (en) 2013-08-01 2017-12-12 Sandisk Technologies Llc Systems and methods for atomic storage operations

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