US20090315139A1 - Patterning method and semiconductor device - Google Patents

Patterning method and semiconductor device Download PDF

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US20090315139A1
US20090315139A1 US12/407,158 US40715809A US2009315139A1 US 20090315139 A1 US20090315139 A1 US 20090315139A1 US 40715809 A US40715809 A US 40715809A US 2009315139 A1 US2009315139 A1 US 2009315139A1
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region
type well
pattern
conduction type
semiconductor device
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Mitsuaki Igeta
Masahiro Sueda
Rikio TAKASE
Akihiro Usujima
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Fujitsu Semiconductor Ltd
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Fujitsu Semiconductor Ltd
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Assigned to FUJITSU MICROELECTRONICS LIMITED reassignment FUJITSU MICROELECTRONICS LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: IGETA, MITSUAKI, SUEDA, MASAHIRO, TAKASE, RIKIO, USUJIMA, AKIHIRO
Publication of US20090315139A1 publication Critical patent/US20090315139A1/en
Assigned to FUJITSU SEMICONDUCTOR LIMITED reassignment FUJITSU SEMICONDUCTOR LIMITED CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: FUJITSU MICROELECTRONICS LIMITED
Priority to US13/567,591 priority Critical patent/US8683406B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention

Definitions

  • the embodiments discussed herein are related to a patterning method and a semiconductor device.
  • STI shallow trench isolation
  • Japanese Laid-Open Patent Publication No. 2000-012680 discloses with p-channel metal oxide semiconductors (MOSes) which are typical semiconductor elements, for example, an n-type well region is formed in a p-type silicon (Si) substrate.
  • the n-type well region has a predetermined depth from the surface of the p-type Si substrate.
  • An active region is formed in the n-type well region. Source/drain regions, a gate oxide film, a gate electrode, and the like are formed in the active region. By doing so, a p-channel MOS is formed.
  • Japanese Laid-Open Patent Publication No. 03-030468 discloses a triple well structure in which a p-type well region of a p-type silicon substrate in which an n-channel MOS transistor is formed is surrounded by an n-type well region has recently been proposed.
  • a patterning method includes: defining, in the case of an electric current which exceeds an allowable limit flowing between first conduction type well regions arranged in a semiconductor substrate, a first pattern between the first conduction type well regions; defining a second pattern by removing, in the case of a first region in which arrangement is inhibited being in the first pattern, the first region from the first pattern; defining a third pattern by removing, in the case of a second region which exceeds a fabrication limit being in the second pattern, the second region from the second pattern; and using the third pattern as a dummy active region in a second conduction type well region arranged in the semiconductor substrate.
  • FIG. 1 is a view for describing the flow of a patterning method according to a first embodiment
  • FIGS. 2A and 2B are fragmentary views of a semiconductor device according to a first embodiment, FIG. 2A being a fragmentary plan view of the semiconductor device, FIG. 2B being a fragmentary sectional view taken along the line X-Y of FIG. 2A ;
  • FIGS. 3A and 3B are fragmentary views of another semiconductor device
  • FIG. 4 is a fragmentary view for describing the flow of automatically defining a dummy active region (part 1 );
  • FIG. 5 is a fragmentary view for describing the flow of automatically defining the dummy active region (part 2 );
  • FIG. 6 is a fragmentary view for describing the flow of automatically defining the dummy active region (part 3 );
  • FIG. 7 is a fragmentary view for describing the flow of automatically defining the dummy active region (part 4 );
  • FIG. 8 is a fragmentary view for describing the flow of automatically defining the dummy active region (part 5 );
  • FIG. 9 is a view for describing the flow of data processing by a patterning apparatus.
  • FIGS. 10A and 10B are fragmentary views of a semiconductor device according to a second embodiment, FIG. 10A being a fragmentary plan view of the semiconductor device, FIG. 10B being a fragmentary sectional view taken along the line X-Y of FIG. 10A ;
  • FIGS. 11A and 11B are fragmentary views of another semiconductor device.
  • FIG. 12 is a fragmentary view of a semiconductor device according to a third embodiment.
  • a patterning method according to a first embodiment will be described first.
  • FIG. 1 is a view for describing the flow of a patterning method according to a first embodiment.
  • a first pattern is defined first between the first conduction type well regions (step S 1 ).
  • a second pattern is defined next by removing the first region from the first pattern (step S 2 ).
  • a third pattern is defined by removing the second region from the second pattern (step S 3 ).
  • the third pattern is used as a dummy active region in a second conduction type well region arranged in the semiconductor substrate (step S 4 ).
  • a dummy active region is defined between n-type well (or p-type well) regions.
  • a p-type well (or an n-type well) region in which impurity concentration is high is formed locally between the n-type well (or p-type well) regions and a leakage current which flows between the n-type well (or p-type well) regions is controlled.
  • FIGS. 2A and 2B are fragmentary views of a semiconductor device according to a first embodiment.
  • FIG. 2A is a fragmentary plan view of the semiconductor device.
  • FIG. 2B is a fragmentary sectional view taken along the line X-Y of FIG. 2A .
  • STIs 20 are not depicted in order to clearly indicate well regions arranged in a semiconductor substrate.
  • a semiconductor device 1 depicted in FIGS. 2A and 2B has a twin well structure.
  • a p-type semiconductor substrate 10 p the main component of which is silicon or the like is used as a supporting substrate.
  • n-type well regions 11 n are arranged in the p-type semiconductor substrate 10 p and a p-type well region 11 p is arranged in the p-type semiconductor substrate 10 p other than the n-type well regions 11 n (see FIG. 2A ).
  • An STI 20 (not depicted in FIG. 2A ) is arranged between an n-type well region 11 n and the p-type well region 11 p and each of the n-type well regions 11 n and the p-type well region 11 p is defined in the p-type semiconductor substrate 10 p.
  • the main component of the STIs 20 is, for example, silicon oxide (SiO 2 ).
  • each n-type well region 11 n of the semiconductor device 1 is exposed from between STIs 20 . That is to say, an active region 11 na can be formed in the surface of each n-type well region 11 n .
  • an active region 11 na can be formed in the surface of each n-type well region 11 n .
  • an element is formed in each n-type well region 11 n.
  • a dummy active region 11 ph which is exposed from between STIs 20 is arranged between the n-type well regions 11 n.
  • the n-type well regions 11 n and the p-type well region 11 p are formed by implanting impurity ions from the surface of the p-type semiconductor substrate 10 p.
  • a p-type well region 11 pd in which impurity concentration is higher than impurity concentration in the p-type well region 11 p and in which impurities deeply diffuse is formed under the dummy active region 11 ph by a wafer process.
  • the above STIs 20 are not formed in the dummy active region 11 ph . Therefore, by performing the wafer process, p-type impurity ions (boron (B) ions, for example) are implanted under the dummy active region 11 ph therethrough. As a result, a local region (p-type well region 11 pd ) in which impurity concentration is higher than impurity concentration in the p-type well region 11 p and in which impurities deeply diffuse is formed under the dummy active region 11 ph.
  • p-type impurity ions boron (B) ions, for example
  • a potential barrier between the p-type well region 11 pd and an n-type well region 11 n becomes higher.
  • a leakage current which flows between the n-type well regions 11 n is controlled under an allowable limit.
  • FIGS. 3A and 3B fragmentary views of another semiconductor device are depicted in FIGS. 3A and 3B for comparison.
  • the numeric values below are indicated as examples and other numeric values may be used.
  • a semiconductor device 100 does not include the above dummy active region 11 ph .
  • the semiconductor device 100 having such a structure, an opening is not formed in each STI 20 . Therefore, even if a wafer process is performed, the above local region (p-type well region 11 pd ) is not formed. That is to say, only an ordinary p-type well region 11 p in which impurity concentration is lower than impurity concentration in the above p-type well region 11 pd is formed between n-type well regions 11 n.
  • a potential barrier between the p-type well region 11 p and an n-type well region 11 n is low compared with the semiconductor device 1 . That is to say, a leakage current LC may flow between the n-type well regions 11 n.
  • an electric current which exceeds the allowable limit, or a leakage current may flow if the distance between the n-type well regions 11 n is shorter than or equal to a predetermined value (1 ⁇ m, for example). For example, if the distance between the n-type well regions 11 n is 1 ⁇ m, an electric current of 1 ⁇ A or more is defined as a leakage current.
  • the shape and position of the dummy active region 11 ph are automatically defined by, for example, a patterning apparatus using a computer aided design (CAD) system.
  • CAD computer aided design
  • the distance between the n-type well regions 11 n between which a leakage current flows is set in advance (to, for example, 1 ⁇ m or less) and the distance between the n-type well regions 11 n is detected. By doing so, the dummy active region 11 ph is automatically defined.
  • the dummy active region 11 ph is automatically defined at a predetermined distance (1 ⁇ m or less, for example) from, for example, a control wiring (wiring for a gate electrode) the main component of which is polycrystalline silicon.
  • a combination of the control wiring and the p-type well region 11 pd forms an element which is not desired in the p-type semiconductor substrate 10 p.
  • the dummy active region 11 ph is automatically defined at a predetermined distance (1 ⁇ m or less, for example) from a boundary between well regions.
  • a metal layer arranged over the boundary by a wafer process short-circuits the n-type well region 11 n and the p-type well region 11 p.
  • the dummy active region 11 ph is automatically defined at a predetermined distance (1 ⁇ m or less, for example) from an active region, a wiring layer, and a parasitic element.
  • the above p-type well region 11 pd is formed near the active region, the wiring layer, or the parasitic element, then variation in capacitance between the active region, the wiring layer, or the parasitic element and the above p-type well region 11 pd which is not desired occurs. It is desirable that the dummy active region 11 ph is defined at a predetermined distance (1 ⁇ m or less, for example) from a member (high-frequency circuit section, for example) in particular which is easily influenced by capacitance.
  • the p-type well region 11 pd may have a bad influence on the characteristics of an element.
  • FIGS. 4 through 8 are fragmentary views for describing the flow of automatically defining the dummy active region. Members in FIGS. 4 through 8 that are the same as those depicted in FIG. 1 are marked with the same symbols. In the following descriptions a member described once will not be described again. The STIs 20 are not depicted in FIGS. 4 through 8 .
  • FIG. 4 A state in which a plurality of n-type well regions 11 n are arranged over a semiconductor substrate (p-type semiconductor substrate 10 p , for example) is depicted in FIG. 4 .
  • a region 11 g in which a control wiring is arranged is also depicted in FIG. 4 .
  • Such patterns are stored in a patterning apparatus as design data (original data).
  • design data original data
  • each pattern is stored in a storage section of the patterning apparatus, a management server, or a record medium as design data.
  • a data processing section of the patterning apparatus automatically selects a region between n-type well regions 11 n in which a leakage current flows easily.
  • the data processing section of the patterning apparatus determines that the distance between the n-type well regions 11 n depicted in FIG. 4 is shorter than or equal to a threshold (1 ⁇ m, for example) indicative of whether a leakage current flows, then the data processing section of the patterning apparatus automatically defines a pattern 11 pha between the n-type well regions 11 n.
  • the data processing section of the patterning apparatus makes determination on the basis of the distance between the n-type well regions 11 n .
  • a pattern may be defined between n-type well regions 11 n which differ in function or between n-type well regions 11 n which differ in electric potential.
  • the rectangular pattern 11 pha is defined over the semiconductor substrate.
  • the shape of the pattern 11 pha is not limited to this shape. As depicted in FIG. 5 , for example, if the data processing section of the patterning apparatus determines that distance d between the n-type well regions 11 n in the direction of a diagonal is shorter than or equal to a threshold (1 ⁇ m, for example) indicative of whether a leakage current flows, then the data processing section of the patterning apparatus may define a pattern 11 pha having a shape depicted in FIG. 5 over the semiconductor substrate.
  • a boundary between an n-type well region 11 n and a p-type well region 11 p is near the pattern 11 pha , then a region which extends over a certain distance (1 ⁇ m, for example, set as a threshold) from the boundary is selected and is removed from the pattern 11 pha.
  • the region 11 g in which the control wiring is arranged is near the pattern 11 pha , then a region which extends over a certain distance (greater than or equal to, for example, 1 ⁇ m which is a threshold) from the region 11 g is selected and is removed from the pattern 11 pha.
  • a pattern 11 phb (indicated by oblique dashed lines) which is different from the pattern 11 pha is defined by performing the above processes.
  • each portion (each region 11 naa ) which extends over a predetermined distance from a boundary between an n-type well region 11 n and the p-type well region 11 p is removed from the pattern 11 pha .
  • a portion which extends over a predetermined distance from the region 11 g is removed from the pattern 11 pha.
  • the process of removing a region in which arrangement is inhibited is automatically performed by the data processing section of the patterning apparatus.
  • a region which extends over a certain distance from at least one of an active region, a wiring layer, and an element arranged in the semiconductor substrate may be selected as a region in which arrangement is inhibited.
  • the region 11 PL is removed from the above pattern 11 phb.
  • the fabrication limit is set on the basis of the limit of patterning by a dry or wet wafer process, the limit of the fabrication of a mask member used in photolithography, or the like. Information regarding the fabrication limit is stored in the storage section of the patterning apparatus or the like as a database. The process of removing a region which exceeds the fabrication limit is also performed automatically by the data processing section of the patterning apparatus.
  • a region obtained by removing the region 11 PL from the above pattern 11 phb is defined as a finally shaped opening pattern, or a dummy active region 11 ph.
  • This state is depicted in FIG. 8 .
  • the shape, position, and the like of the finally defined dummy active region 11 ph are stored in the storage section of the patterning apparatus or the like as the design data.
  • the width of a margin set for the positional deviation of a mask member may be taken into consideration in shaping a pattern.
  • FIG. 9 is a view for describing the flow of data processing by the patterning apparatus.
  • Original design data is read out first from a storage section M of the patterning apparatus.
  • Such design data is stored in the storage section M in, for example, GDSII format.
  • the pattern 11 pha is defined between the n-type well regions 11 n.
  • the pattern 11 phb is defined by removing the region from the pattern 11 pha.
  • a region which exceeds the fabrication limit is in the pattern 11 phb , then a new pattern, or the dummy active region 11 ph is defined by removing the region from the pattern 11 phb.
  • the pattern 11 pha , the pattern 11 phb , and the dummy active region 11 ph are automatically defined by the data processing section of the patterning apparatus (step S 10 ).
  • the data processing section of the patterning apparatus automatically superimposes the data regarding the dummy active region 11 ph on the original design data (step S 20 ).
  • Data obtained by superimposing the data regarding the dummy active region 11 ph on the original design data is stored in the storage section M of the patterning apparatus.
  • step S 30 the data processing of superimposing the data regarding the dummy active region 11 ph on the original design data is completed.
  • a wafer process is performed on the basis of a pattern finally designed by the patterning apparatus.
  • the dummy active region 11 ph which is exposed from between STIs 20 is formed.
  • the p-type well region 11 pd is formed inevitably under the dummy active region 11 ph . Accordingly, a leakage current between n-type well regions 11 n is controlled.
  • the following method is used in the first embodiment. If an electric current which exceeds the allowable limit flows between the first conduction type well regions arranged in the semiconductor substrate, the first pattern is defined between the first conduction type well regions. If the first region in which arrangement is inhibited is in the first pattern, the second pattern is defined by removing the first region from the first pattern. If the second region which exceeds the fabrication limit is in the second pattern, the third pattern is defined by removing the second region from the second pattern. The third pattern is used as the dummy active region in the second conduction type well region arranged in the semiconductor substrate.
  • Patterning can be modified (dummy active region 11 ph can be defined) only by modifying a mask member used in a real wafer process for forming the STIs 20 .
  • the dummy active region 11 ph is formed between the n-type well regions 11 n of the semiconductor device 1 , so the area of the semiconductor device 1 does not increase.
  • FIGS. 10A and 10B are fragmentary views of a semiconductor device according to a second embodiment.
  • FIG. 10A is a fragmentary plan view of the semiconductor device.
  • FIG. 10B is a fragmentary sectional view taken along the line X-Y of FIG. 10A .
  • STIs 20 are not depicted in order to clearly indicate well regions arranged in a semiconductor substrate.
  • a semiconductor device 2 depicted in FIGS. 10A and 10B has a triple well structure.
  • a p-type semiconductor substrate 10 p is used as a supporting substrate.
  • an n-type well region 11 dn is arranged in a deep region of the p-type semiconductor substrate 10 p.
  • p-type well regions 11 p are arranged over the n-type well region 11 dn and an n-type well region 11 n is arranged in the p-type semiconductor substrate 10 p other than the p-type well regions 11 p over the n-type well region 11 dn (see FIGS. 10A and 10B ).
  • An STI 20 (not depicted in FIG. 10A ) is arranged between a p-type well region 11 p and the n-type well region 11 n and each of the p-type well regions 11 p and the n-type well region 11 n is defined in the p-type semiconductor substrate 10 p.
  • each p-type well region 11 p of the semiconductor device 2 is exposed from between STIs 20 . That is to say, an active region 11 pa can be formed in the surface of each p-type well region 11 p .
  • an active region 11 pa is formed in each p-type well region 11 p.
  • a dummy active region 11 nh which is exposed from between STIs 20 is arranged between the p-type well regions 11 p.
  • the reason for arranging the dummy active region 11 nh in such a position is the same as that described in the first embodiment. That is to say, by performing a wafer process, n-type impurity ions (phosphorus (P) ions, for example) are implanted under the dummy active region 11 nh therethrough. As a result, a local region (n-type well region 11 nd ) in which impurity concentration is higher than impurity concentration in the n-type well region 11 n and in which impurities deeply diffuse is formed under the dummy active region 11 nh.
  • n-type impurity ions phosphorus (P) ions, for example
  • a potential barrier between the n-type well region 11 nd and a p-type well region 11 p becomes higher.
  • a leakage current which flows between the p-type well regions 11 p is controlled under an allowable limit.
  • FIGS. 11A and 11B fragmentary views of another semiconductor device are depicted in FIGS. 11A and 11B for comparison.
  • a semiconductor device 200 does not include the above dummy active region 11 nh .
  • the semiconductor device 200 having such a structure an opening is not formed in each STI 20 . Therefore, even if a wafer process is performed, the above local region (n-type well region 11 nd) is not formed. That is to say, only an ordinary n-type well region 11 n in which impurity concentration is lower than impurity concentration in the above n-type well region 11 nd is formed between p-type well regions 11 p.
  • a potential barrier between the n-type well region 11 n and a p-type well region 11 p is low compared with the semiconductor device 2 . That is to say, a leakage current LC may flow between the p-type well regions 11 p.
  • the shape and position of the dummy active region 11 nh are automatically defined by the above patterning apparatus.
  • the dummy active region 11 nh is automatically defined at a predetermined distance from a control wiring (gate electrode wiring), a boundary between well regions, an active region, a wiring layer, or a parasitic element.
  • the n-type well region 11 nd may have a bad influence on the characteristics of an element.
  • FIG. 12 is a fragmentary view of a semiconductor device according to a third embodiment.
  • a semiconductor device 3 has a structure which is a modification of a triple well structure.
  • a p-type semiconductor substrate 10 p is used as a supporting substrate.
  • an n-type well region 11 dn is arranged in part of a deep region of the p-type semiconductor substrate 10 p.
  • a p-type well region 11 p 1 and an n-type well region 11 nd are arranged over the n-type well region 11 dn .
  • a p-type well region 11 p 2 is adjacent to the n-type well region 11 nd.
  • the p-type well region 11 p 1 is not touching the p-type well region 11 p 2 directly in this structure, so the p-type well regions 11 p 1 and 11 p 2 may differ in electric potential.
  • An STI 20 is arranged between the p-type well region 11 p 1 and the n-type well region 11 nd and between the p-type well region 11 p 2 and the n-type well region 11 nd and each of the n-type well region 11 nd and the p-type well regions 11 p 1 and 11 p 2 is defined in the p-type semiconductor substrate 10 p.
  • a dummy active region 11 nh may be arranged between the p-type well regions 11 p 1 and 11 p 2 .
  • the reason for arranging the dummy active region 11 nh in such a position is the same as that described in the first or second embodiment. That is to say, by performing a wafer process, n-type impurity ions are implanted under the dummy active region 11 nh therethrough. As a result, a local region (n-type well region 11 nd ) in which impurity concentration is higher than impurity concentration in an n-type well region 11 n and in which impurities deeply diffuse is formed under the dummy active region 11 nh.
  • a potential barrier between the n-type well region 11 nd and the p-type well region 11 p 1 and a potential barrier between the n-type well region 11 nd and the p-type well region 11 p 2 become higher.
  • numeric values or the materials described in the first through third embodiments are examples and other numeric values or materials may be used.

Abstract

A patterning method includes defining, in the case of an electric current which exceeds an allowable limit flowing between first conduction type well regions arranged in a semiconductor substrate, a first pattern between the first conduction type well regions; defining a second pattern by removing, in the case of a first region in which arrangement is inhibited being in the first pattern, the first region from the first pattern; defining a third pattern by removing, in the case of a second region which exceeds a fabrication limit being in the second pattern, the second region from the second pattern; and using the third pattern as a dummy active region in a second conduction type well region arranged in the semiconductor substrate.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is based upon and claims the benefits of priority of the prior Japanese Patent Application No. 2008-161538, filed on Jun. 20, 2008, the entire contents of which are incorporated herein by reference.
    • FIELD
  • The embodiments discussed herein are related to a patterning method and a semiconductor device.
    • BACKGROUND
  • In recent years semiconductor devices in which shallow trench isolation (STI) is put to practical use have been manufactured. An n-type well region is isolated from a p-type well region by the STI.
  • Japanese Laid-Open Patent Publication No. 2000-012680 discloses with p-channel metal oxide semiconductors (MOSes) which are typical semiconductor elements, for example, an n-type well region is formed in a p-type silicon (Si) substrate. The n-type well region has a predetermined depth from the surface of the p-type Si substrate. An active region is formed in the n-type well region. Source/drain regions, a gate oxide film, a gate electrode, and the like are formed in the active region. By doing so, a p-channel MOS is formed.
  • In addition, Japanese Laid-Open Patent Publication No. 03-030468 discloses a triple well structure in which a p-type well region of a p-type silicon substrate in which an n-channel MOS transistor is formed is surrounded by an n-type well region has recently been proposed.
  • However, with a recent increase in the integration level of semiconductor devices there is a tendency for a space between n-type well (or p-type well) regions to become narrower. Therefore, if n-type well (or p-type well) regions differ in electric potential, then a leakage current may flow between the n-type well (or p-type well) regions. As a result, excess electric power is consumed in a semiconductor device, power supply potential drops in the semiconductor device, or latch-up is caused by the leakage current in the semiconductor device.
    • SUMMARY
  • According to an aspect of the embodiment, a patterning method includes: defining, in the case of an electric current which exceeds an allowable limit flowing between first conduction type well regions arranged in a semiconductor substrate, a first pattern between the first conduction type well regions; defining a second pattern by removing, in the case of a first region in which arrangement is inhibited being in the first pattern, the first region from the first pattern; defining a third pattern by removing, in the case of a second region which exceeds a fabrication limit being in the second pattern, the second region from the second pattern; and using the third pattern as a dummy active region in a second conduction type well region arranged in the semiconductor substrate.
  • The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.
  • It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed.
    • BRIEF DESCRIPTION OF DRAWINGS
  • FIG. 1 is a view for describing the flow of a patterning method according to a first embodiment;
  • FIGS. 2A and 2B are fragmentary views of a semiconductor device according to a first embodiment, FIG. 2A being a fragmentary plan view of the semiconductor device, FIG. 2B being a fragmentary sectional view taken along the line X-Y of FIG. 2A;
  • FIGS. 3A and 3B are fragmentary views of another semiconductor device;
  • FIG. 4 is a fragmentary view for describing the flow of automatically defining a dummy active region (part 1);
  • FIG. 5 is a fragmentary view for describing the flow of automatically defining the dummy active region (part 2);
  • FIG. 6 is a fragmentary view for describing the flow of automatically defining the dummy active region (part 3);
  • FIG. 7 is a fragmentary view for describing the flow of automatically defining the dummy active region (part 4);
  • FIG. 8 is a fragmentary view for describing the flow of automatically defining the dummy active region (part 5);
  • FIG. 9 is a view for describing the flow of data processing by a patterning apparatus;
  • FIGS. 10A and 10B are fragmentary views of a semiconductor device according to a second embodiment, FIG. 10A being a fragmentary plan view of the semiconductor device, FIG. 10B being a fragmentary sectional view taken along the line X-Y of FIG. 10A;
  • FIGS. 11A and 11B are fragmentary views of another semiconductor device; and
  • FIG. 12 is a fragmentary view of a semiconductor device according to a third embodiment.
    •  DESCRIPTION OF EMBODIMENTS
  • A patterning method and a semiconductor device according to embodiments will now be described in detail with reference to the accompanying drawings, wherein like reference numerals refer to like elements throughout.
    • First Embodiment
  • A patterning method according to a first embodiment will be described first.
  • FIG. 1 is a view for describing the flow of a patterning method according to a first embodiment.
  • If an electric current which exceeds an allowable limit flows between first conduction type well regions arranged in a semiconductor substrate, a first pattern is defined first between the first conduction type well regions (step S1).
  • If a first region in which arrangement is inhibited is in the first pattern, a second pattern is defined next by removing the first region from the first pattern (step S2).
  • If a second region which exceeds a fabrication limit is in the second pattern, a third pattern is defined by removing the second region from the second pattern (step S3). The third pattern is used as a dummy active region in a second conduction type well region arranged in the semiconductor substrate (step S4).
  • By following the above flow, a dummy active region is defined between n-type well (or p-type well) regions. When a wafer process is performed in order to form such a pattern, a p-type well (or an n-type well) region in which impurity concentration is high is formed locally between the n-type well (or p-type well) regions and a leakage current which flows between the n-type well (or p-type well) regions is controlled.
  • The structure of a semiconductor device including the above dummy active region will now be described.
  • FIGS. 2A and 2B are fragmentary views of a semiconductor device according to a first embodiment. FIG. 2A is a fragmentary plan view of the semiconductor device. FIG. 2B is a fragmentary sectional view taken along the line X-Y of FIG. 2A. In FIG. 2A, STIs 20 are not depicted in order to clearly indicate well regions arranged in a semiconductor substrate. A semiconductor device 1 depicted in FIGS. 2A and 2B has a twin well structure.
  • With the semiconductor device 1 a p-type semiconductor substrate 10 p the main component of which is silicon or the like is used as a supporting substrate. n-type well regions 11 n are arranged in the p-type semiconductor substrate 10 p and a p-type well region 11 p is arranged in the p-type semiconductor substrate 10 p other than the n-type well regions 11 n (see FIG. 2A). An STI 20 (not depicted in FIG. 2A) is arranged between an n-type well region 11 n and the p-type well region 11 p and each of the n-type well regions 11 n and the p-type well region 11 p is defined in the p-type semiconductor substrate 10 p.
  • The main component of the STIs 20 is, for example, silicon oxide (SiO2).
  • The surface of each n-type well region 11 n of the semiconductor device 1 is exposed from between STIs 20. That is to say, an active region 11 na can be formed in the surface of each n-type well region 11 n. For example, by arranging a p-channel MOS transistor in the active region 11 na, an element is formed in each n-type well region 11 n.
  • With the semiconductor device 1 a dummy active region 11 ph which is exposed from between STIs 20 is arranged between the n-type well regions 11 n.
  • The reason for arranging the dummy active region 11 ph in such a position will now be described.
  • After the STIs 20 are formed in the p-type semiconductor substrate 10 p by a wafer process, the n-type well regions 11 n and the p-type well region 11 p are formed by implanting impurity ions from the surface of the p-type semiconductor substrate 10 p.
  • Accordingly, if the above dummy active region 11 ph is arranged in advance between the n-type well regions 11 n, then a p-type well region 11 pd in which impurity concentration is higher than impurity concentration in the p-type well region 11 p and in which impurities deeply diffuse is formed under the dummy active region 11 ph by a wafer process.
  • For example, the above STIs 20 are not formed in the dummy active region 11 ph. Therefore, by performing the wafer process, p-type impurity ions (boron (B) ions, for example) are implanted under the dummy active region 11 ph therethrough. As a result, a local region (p-type well region 11 pd) in which impurity concentration is higher than impurity concentration in the p-type well region 11 p and in which impurities deeply diffuse is formed under the dummy active region 11 ph.
  • If the p-type well region 11 pd is formed, a potential barrier between the p-type well region 11 pd and an n-type well region 11 n becomes higher. As a result, it is difficult for an electric current to flow between the p-type well region 11 pd and the n-type well region 11 n. Accordingly, even if the n-type well regions 11 n differ in electric potential, a leakage current which flows between the n-type well regions 11 n is controlled under an allowable limit.
  • In order to describe this phenomenon in further detail, fragmentary views of another semiconductor device are depicted in FIGS. 3A and 3B for comparison. The numeric values below are indicated as examples and other numeric values may be used.
  • As depicted in FIGS. 3A and 3B, a semiconductor device 100 does not include the above dummy active region 11 ph. With the semiconductor device 100 having such a structure, an opening is not formed in each STI 20. Therefore, even if a wafer process is performed, the above local region (p-type well region 11 pd) is not formed. That is to say, only an ordinary p-type well region 11 p in which impurity concentration is lower than impurity concentration in the above p-type well region 11 pd is formed between n-type well regions 11 n.
  • Therefore, a potential barrier between the p-type well region 11 p and an n-type well region 11 n is low compared with the semiconductor device 1. That is to say, a leakage current LC may flow between the n-type well regions 11 n.
  • With the semiconductor device 100 an electric current which exceeds the allowable limit, or a leakage current may flow if the distance between the n-type well regions 11 n is shorter than or equal to a predetermined value (1 μm, for example). For example, if the distance between the n-type well regions 11 n is 1 μm, an electric current of 1 μA or more is defined as a leakage current.
  • Accordingly, in order to control a leakage current which flows between the n-type well regions 11 n, it is desirable that the structure of the semiconductor device 1 depicted in FIGS. 2A and 2B is adopted.
  • With the semiconductor device 1 the dummy active region 11 ph is formed for this reason.
  • The shape and position of the dummy active region 11 ph are automatically defined by, for example, a patterning apparatus using a computer aided design (CAD) system.
  • For example, the distance between the n-type well regions 11 n between which a leakage current flows is set in advance (to, for example, 1 μm or less) and the distance between the n-type well regions 11 n is detected. By doing so, the dummy active region 11 ph is automatically defined.
  • In addition, the dummy active region 11 ph is automatically defined at a predetermined distance (1 μm or less, for example) from, for example, a control wiring (wiring for a gate electrode) the main component of which is polycrystalline silicon.
  • If the above p-type well region 11 pd is formed near the control wiring, then a combination of the control wiring and the p-type well region 11 pd forms an element which is not desired in the p-type semiconductor substrate 10 p.
  • Furthermore, the dummy active region 11 ph is automatically defined at a predetermined distance (1 μm or less, for example) from a boundary between well regions.
  • If the dummy active region 11 ph is formed across a boundary between an n-type well region 11 n and the p-type well region 11 p, then a metal layer arranged over the boundary by a wafer process short-circuits the n-type well region 11 n and the p-type well region 11 p.
  • Moreover, the dummy active region 11 ph is automatically defined at a predetermined distance (1 μm or less, for example) from an active region, a wiring layer, and a parasitic element.
  • If the above p-type well region 11 pd is formed near the active region, the wiring layer, or the parasitic element, then variation in capacitance between the active region, the wiring layer, or the parasitic element and the above p-type well region 11 pd which is not desired occurs. It is desirable that the dummy active region 11 ph is defined at a predetermined distance (1 μm or less, for example) from a member (high-frequency circuit section, for example) in particular which is easily influenced by capacitance.
  • In addition, if the p-type well region 11 pd is formed near a member other than the above members, the p-type well region 11 pd may have a bad influence on the characteristics of an element. In this case, it is desirable that the dummy active region 11 ph is defined at a predetermined distance from the member.
  • A concrete procedure for automatically defining the above dummy active region (dummy active region 11 ph) in position in the p-type semiconductor substrate 10 p will now be described.
  • FIGS. 4 through 8 are fragmentary views for describing the flow of automatically defining the dummy active region. Members in FIGS. 4 through 8 that are the same as those depicted in FIG. 1 are marked with the same symbols. In the following descriptions a member described once will not be described again. The STIs 20 are not depicted in FIGS. 4 through 8.
  • A state in which a plurality of n-type well regions 11 n are arranged over a semiconductor substrate (p-type semiconductor substrate 10 p, for example) is depicted in FIG. 4. A region 11 g in which a control wiring is arranged is also depicted in FIG. 4.
  • Such patterns are stored in a patterning apparatus as design data (original data). For example, each pattern is stored in a storage section of the patterning apparatus, a management server, or a record medium as design data.
  • A data processing section of the patterning apparatus automatically selects a region between n-type well regions 11 n in which a leakage current flows easily.
  • For example, if the data processing section of the patterning apparatus determines that the distance between the n-type well regions 11 n depicted in FIG. 4 is shorter than or equal to a threshold (1 μm, for example) indicative of whether a leakage current flows, then the data processing section of the patterning apparatus automatically defines a pattern 11 pha between the n-type well regions 11 n.
  • When the data processing section of the patterning apparatus defines the pattern 11 pha, the data processing section of the patterning apparatus makes determination on the basis of the distance between the n-type well regions 11 n. In addition, a pattern may be defined between n-type well regions 11 n which differ in function or between n-type well regions 11 n which differ in electric potential.
  • In FIG. 4 the rectangular pattern 11 pha is defined over the semiconductor substrate. However, the shape of the pattern 11 pha is not limited to this shape. As depicted in FIG. 5, for example, if the data processing section of the patterning apparatus determines that distance d between the n-type well regions 11 n in the direction of a diagonal is shorter than or equal to a threshold (1 μm, for example) indicative of whether a leakage current flows, then the data processing section of the patterning apparatus may define a pattern 11 pha having a shape depicted in FIG. 5 over the semiconductor substrate.
  • Next, a region in which arrangement is inhibited is removed from the pattern 11 pha.
  • For example, if a boundary between an n-type well region 11 n and a p-type well region 11 p is near the pattern 11 pha, then a region which extends over a certain distance (1 μm, for example, set as a threshold) from the boundary is selected and is removed from the pattern 11 pha.
  • In addition, if the region 11 g in which the control wiring is arranged is near the pattern 11 pha, then a region which extends over a certain distance (greater than or equal to, for example, 1 μm which is a threshold) from the region 11 g is selected and is removed from the pattern 11 pha.
  • As depicted in FIG. 6, a pattern 11 phb (indicated by oblique dashed lines) which is different from the pattern 11 pha is defined by performing the above processes.
  • As depicted in FIG. 6, each portion (each region 11 naa) which extends over a predetermined distance from a boundary between an n-type well region 11 n and the p-type well region 11 p is removed from the pattern 11 pha. In addition, a portion (region 11 ga) which extends over a predetermined distance from the region 11 g is removed from the pattern 11 pha.
  • The process of removing a region in which arrangement is inhibited is automatically performed by the data processing section of the patterning apparatus.
  • In addition to the above regions, a region which extends over a certain distance from at least one of an active region, a wiring layer, and an element arranged in the semiconductor substrate may be selected as a region in which arrangement is inhibited.
  • Next, a region which exceeds a fabrication limit from the viewpoint of a manufacturing process is removed further from the pattern 11 phb.
  • For example, if the pattern width of a region 11PL (indicated by oblique dashed lines) depicted in FIG. 7 exceeds the fabrication limit, then the region 11PL is removed from the above pattern 11 phb.
  • The fabrication limit is set on the basis of the limit of patterning by a dry or wet wafer process, the limit of the fabrication of a mask member used in photolithography, or the like. Information regarding the fabrication limit is stored in the storage section of the patterning apparatus or the like as a database. The process of removing a region which exceeds the fabrication limit is also performed automatically by the data processing section of the patterning apparatus.
  • A region obtained by removing the region 11PL from the above pattern 11 phb is defined as a finally shaped opening pattern, or a dummy active region 11 ph.
  • This state is depicted in FIG. 8.
  • The shape, position, and the like of the finally defined dummy active region 11 ph are stored in the storage section of the patterning apparatus or the like as the design data.
  • The width of a margin set for the positional deviation of a mask member may be taken into consideration in shaping a pattern.
  • The above procedure described from the viewpoint of the flow of data processing by the patterning apparatus is depicted in FIG. 9.
  • FIG. 9 is a view for describing the flow of data processing by the patterning apparatus.
  • Original design data is read out first from a storage section M of the patterning apparatus.
  • Such design data is stored in the storage section M in, for example, GDSII format.
  • Next, if a portion where a leakage current flows is detected between n-type well regions 11 n read out, then the pattern 11 pha is defined between the n-type well regions 11 n.
  • Next, if a region in which arrangement is inhibited is in the pattern 11 pha, then the pattern 11 phb is defined by removing the region from the pattern 11 pha.
  • Next, if a region which exceeds the fabrication limit is in the pattern 11 phb, then a new pattern, or the dummy active region 11 ph is defined by removing the region from the pattern 11 phb.
  • The pattern 11 pha, the pattern 11 phb, and the dummy active region 11 ph are automatically defined by the data processing section of the patterning apparatus (step S10).
  • Data (shape, position, and the like) regarding the dummy active region 11 ph is stored in the storage section M of the patterning apparatus.
  • Next, the data processing section of the patterning apparatus automatically superimposes the data regarding the dummy active region 11 ph on the original design data (step S20).
  • Data obtained by superimposing the data regarding the dummy active region 11 ph on the original design data is stored in the storage section M of the patterning apparatus.
  • By doing so, the data processing of superimposing the data regarding the dummy active region 11 ph on the original design data is completed (step S30).
  • A wafer process is performed on the basis of a pattern finally designed by the patterning apparatus. As a result, the dummy active region 11 ph which is exposed from between STIs 20 is formed. In addition, the p-type well region 11 pd is formed inevitably under the dummy active region 11 ph. Accordingly, a leakage current between n-type well regions 11 n is controlled.
  • As has been described, the following method is used in the first embodiment. If an electric current which exceeds the allowable limit flows between the first conduction type well regions arranged in the semiconductor substrate, the first pattern is defined between the first conduction type well regions. If the first region in which arrangement is inhibited is in the first pattern, the second pattern is defined by removing the first region from the first pattern. If the second region which exceeds the fabrication limit is in the second pattern, the third pattern is defined by removing the second region from the second pattern. The third pattern is used as the dummy active region in the second conduction type well region arranged in the semiconductor substrate.
  • With the semiconductor device 1 fabricated by this method, a leakage current between the n-type well regions 11 n is controlled. As a result, excess electric power is not consumed in the semiconductor device 1 and power supply potential applied to the semiconductor device 1 does not drop. In addition, latch-up caused by a leakage current does not occur in the semiconductor device 1.
  • Patterning can be modified (dummy active region 11 ph can be defined) only by modifying a mask member used in a real wafer process for forming the STIs 20.
  • Therefore, there is no need to change process conditions under which the semiconductor device 1 is fabricated or to add fabrication steps. The dummy active region 11 ph is easily formed in the semiconductor substrate. The costs of fabrication steps do not rise.
  • Furthermore, the dummy active region 11 ph is formed between the n-type well regions 11 n of the semiconductor device 1, so the area of the semiconductor device 1 does not increase.
    • Second Embodiment
  • FIGS. 10A and 10B are fragmentary views of a semiconductor device according to a second embodiment. FIG. 10A is a fragmentary plan view of the semiconductor device. FIG. 10B is a fragmentary sectional view taken along the line X-Y of FIG. 10A. In FIG. 10A, STIs 20 are not depicted in order to clearly indicate well regions arranged in a semiconductor substrate. A semiconductor device 2 depicted in FIGS. 10A and 10B has a triple well structure.
  • With the semiconductor device 2 a p-type semiconductor substrate 10 p, for example, is used as a supporting substrate. In addition, an n-type well region 11 dn is arranged in a deep region of the p-type semiconductor substrate 10 p.
  • Furthermore, p-type well regions 11 p are arranged over the n-type well region 11 dn and an n-type well region 11 n is arranged in the p-type semiconductor substrate 10 p other than the p-type well regions 11 p over the n-type well region 11 dn (see FIGS. 10A and 10B). An STI 20 (not depicted in FIG. 10A) is arranged between a p-type well region 11 p and the n-type well region 11 n and each of the p-type well regions 11 p and the n-type well region 11 n is defined in the p-type semiconductor substrate 10 p.
  • The surface of each p-type well region 11 p of the semiconductor device 2 is exposed from between STIs 20. That is to say, an active region 11 pa can be formed in the surface of each p-type well region 11 p. For example, by arranging an n-channel MOS transistor in the active region 11 pa, an element is formed in each p-type well region 11 p.
  • With the semiconductor device 2 a dummy active region 11 nh which is exposed from between STIs 20 is arranged between the p-type well regions 11 p.
  • The reason for arranging the dummy active region 11 nh in such a position is the same as that described in the first embodiment. That is to say, by performing a wafer process, n-type impurity ions (phosphorus (P) ions, for example) are implanted under the dummy active region 11 nh therethrough. As a result, a local region (n-type well region 11 nd) in which impurity concentration is higher than impurity concentration in the n-type well region 11 n and in which impurities deeply diffuse is formed under the dummy active region 11 nh.
  • If the n-type well region 11 nd is formed, a potential barrier between the n-type well region 11 nd and a p-type well region 11 p becomes higher. As a result, it is difficult for an electric current to flow between the n-type well region 11 nd and the p-type well region 11 p. Accordingly, even if the p-type well regions 11 p differ in electric potential, a leakage current which flows between the p-type well regions 11 p is controlled under an allowable limit.
  • In order to describe this phenomenon in further detail, fragmentary views of another semiconductor device are depicted in FIGS. 11A and 11B for comparison.
  • As depicted in FIGS. 11A and 11B, a semiconductor device 200 does not include the above dummy active region 11 nh. With the semiconductor device 200 having such a structure, an opening is not formed in each STI 20. Therefore, even if a wafer process is performed, the above local region (n-type well region 11nd) is not formed. That is to say, only an ordinary n-type well region 11 n in which impurity concentration is lower than impurity concentration in the above n-type well region 11 nd is formed between p-type well regions 11 p.
  • Therefore, a potential barrier between the n-type well region 11 n and a p-type well region 11 p is low compared with the semiconductor device 2. That is to say, a leakage current LC may flow between the p-type well regions 11 p.
  • As described in the first embodiment, the shape and position of the dummy active region 11 nh are automatically defined by the above patterning apparatus.
  • Furthermore, as described in the first embodiment, the dummy active region 11 nh is automatically defined at a predetermined distance from a control wiring (gate electrode wiring), a boundary between well regions, an active region, a wiring layer, or a parasitic element.
  • In addition, if the n-type well region 11 nd is formed near a member other than the above members, the n-type well region 11 nd may have a bad influence on the characteristics of an element. In this case, it is desirable that the dummy active region 11 nh is defined at a predetermined distance from the member.
  • The same effects that are obtained by the semiconductor device 1 according to the first embodiment can be achieved by the semiconductor device 2 according to the second embodiment.
    • Third Embodiment
  • FIG. 12 is a fragmentary view of a semiconductor device according to a third embodiment.
  • A semiconductor device 3 has a structure which is a modification of a triple well structure.
  • With the semiconductor device 3 a p-type semiconductor substrate 10 p, for example, is used as a supporting substrate. In addition, an n-type well region 11 dn is arranged in part of a deep region of the p-type semiconductor substrate 10 p.
  • Furthermore, a p-type well region 11 p 1 and an n-type well region 11 nd are arranged over the n-type well region 11 dn. A p-type well region 11 p 2 is adjacent to the n-type well region 11nd. The p-type well region 11 p 1 is not touching the p-type well region 11 p 2 directly in this structure, so the p-type well regions 11 p 1 and 11 p 2 may differ in electric potential.
  • An STI 20 is arranged between the p-type well region 11 p 1 and the n-type well region 11 nd and between the p-type well region 11 p 2 and the n-type well region 11 nd and each of the n-type well region 11 nd and the p-type well regions 11 p 1 and 11 p 2 is defined in the p-type semiconductor substrate 10 p.
  • With the semiconductor device 3 having the above triple well structure, a dummy active region 11 nh may be arranged between the p-type well regions 11 p 1 and 11 p 2.
  • The reason for arranging the dummy active region 11 nh in such a position is the same as that described in the first or second embodiment. That is to say, by performing a wafer process, n-type impurity ions are implanted under the dummy active region 11 nh therethrough. As a result, a local region (n-type well region 11 nd) in which impurity concentration is higher than impurity concentration in an n-type well region 11 n and in which impurities deeply diffuse is formed under the dummy active region 11 nh.
  • If the n-type well region 11 nd is formed, a potential barrier between the n-type well region 11 nd and the p-type well region 11 p 1 and a potential barrier between the n-type well region 11 nd and the p-type well region 11 p 2 become higher. As a result, it is difficult for an electric current to flow between the n-type well region 11 nd and the p-type well region 11 p 1 or between the n-type well region 11 nd and the p-type well region 11 p 2. Accordingly, even if the p-type well regions 11 p 1 and 11 p 2 differ in electric potential, a leakage current which flows between the p-type well regions 11 p 1 and 11 p 2 is controlled under an allowable limit.
  • The same effects that are obtained by the semiconductor device 1 according to the first embodiment can be achieved by the semiconductor device 3 according to the third embodiment.
  • The numeric values or the materials described in the first through third embodiments are examples and other numeric values or materials may be used.
  • By adopting the above methods, a leakage current between n-type well regions or between p-type well regions is controlled.
  • All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present inventions have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.

Claims (9)

1. A patterning method comprising:
defining, in a case of an electric current which exceeds an allowable limit flowing between first conduction type well regions arranged in a semiconductor substrate, a first pattern between the first conduction type well regions;
defining a second pattern by removing, in a case of a first region in which arrangement is inhibited being in the first pattern, the first region from the first pattern;
defining a third pattern by removing, in a case of a second region which exceeds a fabrication limit being in the second pattern, the second region from the second pattern; and
using the third pattern as a dummy active region in a second conduction type well region arranged in the semiconductor substrate.
2. The patterning method according to claim 1, wherein a region which extends over a certain distance from a wiring for a control electrode arranged over the semiconductor substrate is selected as the first region.
3. The patterning method according to claim 1, wherein a region which extends over a certain distance from a boundary between each first conduction type well region and the second conduction type well region arranged in the semiconductor substrate is selected as the first region.
4. The patterning method according to claim 1, wherein a region which extends over a certain distance from at least one of an active region, a wiring layer, and an element arranged in the semiconductor substrate is selected as the first region.
5. The patterning method according to claim 1, wherein a region which does not exceed a limit of patterning by a dry or wet wafer process is selected as the second region.
6. The patterning method according to claim 1, wherein a region which does not exceed a limit of fabrication of a mask member used for patterning is selected as the second region.
7. A semiconductor device wherein:
in a case of an electric current which exceeds an allowable limit flowing between first conduction type well regions arranged in a semiconductor substrate, a first pattern is defined between the first conduction type well regions;
a second pattern is defined by removing, in the case of a first region in which arrangement is inhibited being in the first pattern, the first region from the first pattern; and
a third pattern defined by removing, in the case of a second region which exceeds a fabrication limit being in the second pattern, the second region from the second pattern is arranged as a dummy active region in a second conduction type well region arranged in the semiconductor substrate.
8. The semiconductor device according to claim 7, wherein the first conduction type well regions and the second conduction type well region make up a twin well structure.
9. The semiconductor device according to claim 7, wherein the first conduction type well regions, the second conduction type well region, and another first or second conduction type well region make up a triple well structure.
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