US20090302322A1 - Method of Forming a Thin Film Transistor - Google Patents

Method of Forming a Thin Film Transistor Download PDF

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US20090302322A1
US20090302322A1 US12/492,991 US49299109A US2009302322A1 US 20090302322 A1 US20090302322 A1 US 20090302322A1 US 49299109 A US49299109 A US 49299109A US 2009302322 A1 US2009302322 A1 US 2009302322A1
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layer
fluorine
thin film
polycrystalline material
grain boundaries
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US12/492,991
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Gurtej S. Sandhu
Shubneesh Batra
Pierre C. Fazan
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Micron Technology Inc
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Micron Technology Inc
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Priority to US08/594,127 priority Critical patent/US5665611A/en
Priority to US08/872,789 priority patent/US6001675A/en
Priority to US09/457,206 priority patent/US6238957B1/en
Priority to US09/837,645 priority patent/US6344376B2/en
Priority to US09/902,277 priority patent/US6890842B2/en
Priority to US11/021,651 priority patent/US7385222B2/en
Priority to US12/135,761 priority patent/US7566907B2/en
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to US12/492,991 priority patent/US20090302322A1/en
Publication of US20090302322A1 publication Critical patent/US20090302322A1/en
Application status is Abandoned legal-status Critical

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    • HELECTRICITY
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
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    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
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    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • H01L29/66757Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • H01L29/66765Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
    • H01L29/7866Non-monocrystalline silicon transistors
    • H01L29/78672Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/127Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement

Abstract

A method of forming a thin film transistor relative to a substrate includes, a) providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries; b) providing a fluorine containing layer adjacent the polycrystalline thin film layer; c) annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and d) providing a transistor gate operatively adjacent the thin film transistor layer. The thin film transistor can be fabricated to be bottom gated or top gated. A buffering layer can be provided intermediate the thin film transistor layer and the fluorine containing layer, with the buffering layer being transmissive of fluorine from the fluorine containing layer during the annealing. Preferably, the annealing temperature is both sufficiently high to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries, but sufficiently low to prevent chemical reaction of the fluorine containing layer with the polycrystalline thin film layer.

Description

    RELATED PATENT DATA
  • This patent resulted from a divisional application of U.S. patent application Ser. No. 12/135,761, filed Jun. 9, 2008, which resulted from a continuation of U.S. patent application Ser. No. 11/021,651, filed Dec. 22, 2004, now U.S. Pat. No. 7,385,222, issued on Jun. 10, 2008, which is a continuation application of U.S. patent application Ser. No. 09/902,277, filed Jul. 9, 2001, now U.S. Pat. No. 6,890,842 B2, issued on May 10, 2005, which is a divisional application of U.S. patent application Ser. No. 09/837,645, filed Apr. 17, 2001, now U.S. Pat. No. 6,344,376, issued on Feb. 5, 2002, which is a continuation of U.S. patent application Ser. No. 09/457,206, filed Dec. 7, 1999, now U.S. Pat. No. 6,238,957, issued on May 29, 2001, which is a continuation of U.S. patent application Ser. No. 08/872,789, filed Jun. 10, 1997, now U.S. Pat. No. 6,001,675, issued on Dec. 14, 1999, which is a continuation of U.S. patent application Ser. No. 08/594,127, filed Jan. 31, 1996, now U.S. Pat. No. 5,665,611, issued on Sep. 9, 1997.
  • TECHNICAL FIELD
  • This invention relates to thin film transistors and to methods of forming thin film transistors.
  • BACKGROUND OF THE INVENTION
  • As circuit density continues to increase, there is a corresponding drive to produce smaller and smaller field effect transistors. Field effect transistors have typically been formed by providing active areas within a bulk substrate material or within a complementary conductivity type well formed within a bulk substrate. Although the field effect transistor feature size is reducing with advances in process technology, even greater packing density can be achieved by forming transistors in thin films deposited over insulating layers, such as oxide. These transistors are commonly referred to as “thin film transistors” (TFTs).
  • With TFTs, a thin film of semiconductive material is first provided. A central channel region of the thin film is masked, while opposing adjacent source/drain regions are doped with an appropriate p or n type conductivity enhancing impurity. A gate insulator and gate are provided either above or below the thin film channel region, thus providing a field effect transistor having an active channel region formed entirely within a thin film as opposed to a bulk substrate.
  • The invention grew out of needs associated with TFTs and their usage in high-density static random access memories (SRAMs) and flat panel displays. A static memory cell is characterized by operation in one of two mutually exclusive and cell-maintaining operating states. Each operating state defines one of the two possible binary bit values, 0 or 1. A static memory cell typically has an output which reflects the operating state of the memory cell. Such an output produces a “high” voltage to indicate a “set” operating state. The memory cell output produces a “low” voltage to indicate a “reset” memory cell operating state. A low or reset output voltage usually represents a binary value of 0, and a high or set output voltage represents a binary value of 1.
  • A static memory cell is said to be bi-stable because it has two stable or self-maintaining operating states, corresponding to two different output voltages. Without external stimuli, a static memory cell will operate continuously in a single one of its two operating states. It has internal feedback to maintain a stable output voltage, corresponding to operating states of the memory cell, as long as the memory cell receives power.
  • The operation of the static memory cell is in contrast to other types of memory cells, such as dynamic cells, which do not have stable operating states. A dynamic memory cell can be programmed to store a voltage which represents one of two binary values, but requires periodic reprogramming or “refreshing” to maintain this voltage for more than very short time periods. A dynamic memory cell has no feedback to maintain a stable output voltage. Without refreshing, the output of a dynamic memory cell will drift towards intermediate or indeterminate voltages, effectively resulting in loss of data.
  • Dynamic memory cells are used in spite of this limitation because of the significantly greater packaging densities which can be attained. For instance, a dynamic memory cell can be fabricated with a single MOSFET transistor, rather than the six transistors typically required in a static memory cell. SRAM cell density can be maximized with three-dimensional integration. For example, load transistors of the SRAM cell constitute TFTs which are folded over the bulk transistors. Because of the significantly different architectural arrangements and functional requirements of static and dynamic memory cells and circuits, static memory design has developed along a different path than has the design of dynamic memories.
  • Ongoing efforts in SRAM circuitry have brought about the development of TFTs in an attempt to minimize space and for other advantageous reasons associated with TFTs. While the invention grew out of needs associated with TFTs of SRAM circuitry, the artisan will appreciate applicability of the invention to other types of circuitry. By way of example only, such include TFT-based liquid crystal or other active matrix displays, where a TFT can be used as a pass transistor in a pixel element and also in the driver circuitry.
  • One common material utilized as the thin source, channel and drain film in a TFT is polysilicon. Such is comprised of multiple forms of individual single crystal silicon grains. The locations where two individual crystalline grains abut one another is commonly referred to as a grain boundary. Grain boundaries are inherent in polycrystalline materials, such as polysilicon, as it is the boundaries which define the breaks between individual crystal grains. The crystalline structure breaks down at the grain boundaries, giving rise to a high concentration of broken or “dangling” Si bonds. These dangling bonds “trap” carriers and give rise to potential barriers at the grain boundaries. These potential barriers impede the flow of carriers in polysilicon, thus reducing conductivity compared to bulk silicon.
  • The grain boundary potential barrier height is proportional to the square of the dangling bond density, or “trap density”. The smaller the grain size, the higher the trap density and thus the lower the conductance. In a TFT, the grain boundary potential barrier height in the channel is controlled by the gate voltage, and hence the conductivity is a function of the gate voltage. The TFTs, however, have a lower drive compared to bulk transistors because of lower mobility in the channel and higher threshold voltage to the larger trap concentration.
  • The grain boundary trap concentration also affects the leakage current of OFF-current in TFTs. In polysilicon or other polycrystalline TFTs, the presence of grain boundary traps at the drain end can dramatically increase the leakage current in the presence of a “gate-to-drain” electric field. The increase in leakage results from either “thermionic field emission” and/or “Poole-Frenkel” emission through the grain boundary traps. Accordingly, the greater the number of grain boundaries (i.e., the smaller the grain size), the greater the current leakage through the material. Greater current leakage means that more power is required to replace the leaking current to maintain an SRAM cell transistor in its desired powered-on state. Such leakage is particularly adverse in laptop computers, where desired power consumption when a cell's state is not being changed would be desired to be very low to extend battery life.
  • High density SRAMs (16 Mb or higher) typically require TFTs with low OFF currents (<50 fA) and high ON current (>5 nA) in order to obtain acceptable low standby leakage and high memory cell stability. Current state-of-the-art TFTs provide low standby current at the expense of ON current, or at the expense of additional process complexity. One present way of minimizing this current leakage at the cost of increased process complexity is by providing a “lightly doped offset” (LDO) region within the thin film. A lightly doped offset region is an elongated region within the thin film which is positioned effectively between the channel region and the drain region which is not under “direct” control of the gate fields, but rather is affected by the gate's “fringing fields”. Such a region provides a buffer zone for the electric field between the channel and drain which minimizes leakage therebetween.
  • One prior art manner of contending with problems associated with grains boundaries is to “passivate” such boundaries after their formation. One technique involves exposing the thin film polycrystalline layer to atomic or plasma hydrogen, with the intent being to tie-up the dangling Si bonds at the boundaries with hydrogen. An alternate technique is to implant fluorine into the thin film polycrystalline layer in an effort to produce silicon-fluorine bonds at the boundary interfaces. A silicon-fluorine bond is much more desirable than a silicon hydrogen bond due to increased high temperature stability. However, the existing ion implantation techniques of providing fluorine into a polycrystalline thin film is not without drawbacks. For example, the implantation undesirably damages the thin film layer and typically creates more dangling bonds inherent from the implantation process. Further, a large percentage of the fluorine does not reach the grain boundaries, even upon diffusion, and is therefore ineffective for the purpose of passivation, as ion implantation distributes the fluorine uniformly throughout the grains and grain boundaries.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
  • FIG. 1 is a diagrammatic sectional view of a wafer fragment at one processing step in accordance with the invention.
  • FIG. 2 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 1.
  • FIG. 3 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 2.
  • FIG. 4 is a view of the FIG. 1 wafer at a processing step subsequent to that shown by FIG. 3.
  • FIG. 5 is a diagrammatic sectional view of another wafer fragment at one processing step in accordance with the invention.
  • FIG. 6 is a diagrammatic sectional view of still another wafer fragment at one processing step in accordance with the invention.
  • FIG. 7 is a view of the FIG. 6 wafer at a processing step subsequent to that shown by FIG. 6.
  • FIG. 8 is a diagrammatic sectional view of still a further wafer fragment at one processing step in accordance with the invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).
  • In accordance with one aspect of the invention, a method of forming a thin film transistor relative to a substrate comprises the following steps:
  • providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries;
  • providing a fluorine containing layer adjacent the polycrystalline thin film layer;
  • annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries; and
  • providing a transistor gate operatively adjacent the thin film transistor layer.
  • In accordance with another aspect of the invention, a method of forming a thin film transistor relative to a substrate comprises the following steps:
  • providing a thin film transistor layer of polycrystalline material on a substrate, the polycrystalline material comprising grain boundaries;
  • providing a sacrificial fluorine containing layer over the polycrystalline thin film layer;
  • annealing the fluorine containing layer at a temperature and for a time period which in combination are effective to drive fluorine from the fluorine containing layer into the polycrystalline thin film layer and incorporate fluorine within the grain boundaries to passivate said grain boundaries;
  • after annealing, etching the sacrificial layer from the polycrystalline thin film layer; and
  • providing a gate dielectric layer and a gate relative to the passivated polycrystalline thin film layer.
  • Referring to FIGS. 1-4 and initially to FIG. 1, a semiconductor wafer fragment in process is indicated generally with reference numeral 10. Such comprises a bulk substrate region 12 and an overlying insulative layer 14. A thin film transistor layer 16 of polycrystalline material is provided relative to composite substrate 12/14. Such will comprise grain boundaries inherent in polycrystalline materials. A typical and preferred material for layer 16 is polysilicon, with other polycrystalline materials, such as germanium and silicon-germanium, also being contemplated.
  • A fluorine containing layer 18 is provided outwardly over polycrystalline thin film layer 16. Layer 18 preferably contains such fluorine as an excess of fluorine in the form of free or loosely associated fluorine atoms. An example and preferred material for layer 18 is WSix provided by chemical vapor deposition utilizing WF6 and SiH4 as precursors. The fluorine from the WF6 precursor will desirably be appreciably incorporated in layer 18 for use as described below. An example process for providing layer 18 by CVD using WF6 and SiH4 in a manner which maximizes incorporated fluorine includes WF6 feed at 3 sccm, Ar at 500 sccm, SiH4 at 300 sccm, T at 400° C. and a pressure of 1 Torr. Alternately by way of example only, fluorine containing layer 18 might predominantly comprise elemental W having incorporated fluorine, such as by utilizing a CVD process also using WF6 as a precursor. Regardless where layer 18 is to predominantly comprise W or a W compound, WF6 is a preferred precursor for providing fluorine within such layer.
  • Referring to FIG. 2, wafer fragment 10 and thereby fluorine containing layer 18 is subjected to a suitable annealing temperature for a time period which in combination are effective to drive fluorine from fluorine containing layer 18 into polycrystalline thin film layer 16. Such fluorine will be incorporated within the grain boundaries to passivate said grain boundaries. The principal mechanism by which such fluorine transports from layer 18 to 16 is understood to be predominantly physical (diffusion), as opposed to by chemical action. Alternately but less preferred, such fluorine displacement from layer 18 to layer 16 might occur by a chemical mechanism. However most preferably, the annealing temperature and time are selected to be sufficiently great to drive fluorine from layer 18 into polycrystalline layer 16, but also sufficiently low to prevent a chemical reaction of layer 18 with layer 16.
  • For example where layer 18 predominantly comprises elemental tungsten, an annealing temperature is preferably less than 700° C. to prevent the top or a substantial portion of layer 16 from being reacted with layer 18 to form WSix. Typical and example preferred annealing temperatures for a WSix or other as-deposited layer 18 which has reaction resistance with respect to polycrystalline material of layer 16 is from about 600° C. to 1000° C. for anywhere from 5 seconds (rapid thermal processing) to greater than one hour. The incorporated fluorine within layer 16 preferably forms Si—F bonds with the dangling bonded silicon atoms inherent at the grain boundaries.
  • Referring to FIG. 3 and after annealing, fluorine containing layer 18 is preferably etched from outwardly of passivated polycrystalline thin film layer 16, thereby being sacrificial. An example etch chemistry where layer 18 predominately comprises WSix is a combination of hydrogen peroxide and ammonium hydroxide.
  • Referring to FIG. 4, subsequently a gate dielectric layer 20 is provided, along with a gate 22 outwardly relative to passivated polycrystalline thin film layer 16. Source, drain, offset, Vt adjust, or other implants would ultimately be provided to produce the desired TFT construction. Such are not shown or otherwise described, as such do not constitute aspects pertinent to the claimed invention.
  • The above described embodiment was described with reference to fluorine containing layer 18 being both sacrificial and provided after thin film transistor layer 16 was provided. FIG. 5 illustrates an alternate embodiment of a wafer fragment 10 a where a fluorine containing layer 18 a is neither sacrificial nor provided after provision of a thin film polycrystalline layer. Like numerals from the first described embodiment are utilized where appropriate, with differences being indicated by the suffix “a” or with different numerals. Here, fluorine containing layer 18 a is provided intermediate underlying insulating layer 14 and overlying thin film polycrystalline layer 16. If fluorine containing layer 18 a were electrically conductive, a fluorine transmissive electrical insulating layer (i.e., a 50-100 Angstroms of SiO2) can be provided intermediate layers 18 a and 16. The selected anneal conditions (for example those described above) will effectively move fluorine atoms from layer 18 a into layer 16 to provide the passivating effect. Layer 18 a would then remain after passivation.
  • Another alternate embodiment wafer fragment 10 b and associated processing is described with reference to FIGS. 6 and 7. Like numerals from the first described embodiment are utilized where appropriate, with differences being indicated with the suffix “b” or with different numerals. FIG. 6 is of the same essential composition as the fragment of FIG. 1, but for provision of a buffering layer 25 intermediate thin film transistor layer 16 and fluorine containing layer 18. Buffering layer 25 can be provided to provide etch selectivity of layer 18 relative to 16, and as may be desired to protect the outer surface of layer 16 relative to contact with layer 18. An example and preferred material for layer 25 is an insulating material, such as SiO2 deposited to a thickness of from about 50 Angstroms to about 200 Angstroms. In such instance however, buffering layer 25 will be transmissive of fluorine atoms from fluorine containing layer 18 during the annealing step.
  • Referring to FIG. 7, fluorine containing layer is illustrated as having been selectively etched relative to buffering layer 25 after driving of the fluorine atoms into layer 16. Buffering layer 25 would typically subsequently be etched, and processing continuing to occur as shown by FIG. 4 to produce a thin film transistor construction.
  • The above described embodiments were with respect to a top-gated thin film transistor construction. FIG. 8 illustrates yet another alternate embodiment whereby a bottom-gated thin film construction is provided. Like numerals from the first described embodiment are utilized where appropriate, with differences being indicated by the suffix “c” or with different numerals. Here, wafer fragment 10 c is illustrated as having a bottom gate 22 c provided relative to an insulating layer 27, such as SiO2. Gate dielectric layer 20 c and thin film transistor layer 16 c are provided outwardly relative to layer 27 and gate 22 c. A fluorine containing layer 18 is provided outwardly of polycrystalline thin film layer 16 c for the annealing step. Also, a buffering layer could be provided intermediate thin film transistor layer 16 c and fluorine containing layer 18.
  • Regardless and in all of the above described embodiments, a fluorine containing layer is provided operatively adjacent a polycrystalline thin film layer in a manner effective to enable an effective annealing temperature and time to transfer fluorine atoms from the fluorine containing layer to the polycrystalline thin film layer. Further and regardless, in each of the above embodiments at some point a transistor gate is provided operatively adjacent the thin film transistor layer. Further, subsequent hydrogen passivation could also be conducted without departing from the principals and scope of the invention.
  • Thin film transistors produced according to the above described embodiment have improved operating characteristics.
  • In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.

Claims (12)

1. A semiconductor construction comprising:
a polycrystalline material having grains and grain boundaries and having fluorine non-uniformly distributed between the grains and the grain boundaries;
a fluorine-containing material operably adjacent the polycrystalline material, the fluorine-containing material comprising tungsten; and
a transistor gate operably adjacent the polycrystalline material.
2. The semiconductor construction of claim 1 wherein the polycrystalline material comprises germanium-silicon.
3. The semiconductor construction of claim 1 wherein the polycrystalline material and the fluorine-containing material are present on a substrate having an insulative layer thereon.
4. The semiconductor construction of claim 3 wherein the insulative layer underlies both the polycrystalline material and the fluorine-containing material.
5. The semiconductor construction of claim 1 wherein the at least some of the fluorine present at the grain boundaries bonds with silicon.
6. The semiconductor construction of claim 1 further comprising a gate dielectric layer overlying the polycrystalline material and the fluorine-containing material.
7. The semiconductor construction of claim 6 wherein the transistor gate overlies the gate dielectric layer.
8. A semiconductor construction comprising:
a passivated polycrystalline material layer, the passivated polycrystalline material layer being formed by a method comprising:
providing a layer of polycrystalline material over a substrate, the polycrystalline material having grains and grain boundaries;
forming a fluorine-containing layer proximate the layer of polycrystalline material; and
transferring fluorine into the grain boundaries from the fluorine-containing layer to form the passivated polycrystalline material layer, the passivated polycrystalline material layer having fewer dangling bonds than would occur had the fluorine present in the passivated layer been provided by implanting.
9. The semiconductor construction of claim 8 wherein the polycrystalline material comprises at least one member of the group consisting of silicon and germanium.
10. The semiconductor construction of claim 8 wherein the passivated polycrystalline layer has fluorine non-uniformly distributed between the grains and the grain boundaries.
11. The semiconductor construction of claim 8 wherein the polycrystalline material comprises silicon and wherein at least some of the fluorine present within the grain boundaries is bonded to Si atoms.
12. The semiconductor construction of claim 8 wherein the passivated polycrystalline material layer is incorporated into a thin film transistor.
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US09/837,645 US6344376B2 (en) 1996-01-31 2001-04-17 Method of forming a thin film transistor
US09/902,277 US6890842B2 (en) 1996-01-31 2001-07-09 Method of forming a thin film transistor
US11/021,651 US7385222B2 (en) 1996-01-31 2004-12-22 Thin film transistors and semiconductor constructions
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110024762A1 (en) * 1996-01-31 2011-02-03 Micron Technology, Inc. Method of Forming a Thin Film Transistor

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5753543A (en) * 1996-03-25 1998-05-19 Micron Technology, Inc. Method of forming a thin film transistor
US6476432B1 (en) 2000-03-23 2002-11-05 Micron Technology, Inc. Structures and methods for enhancing capacitors in integrated circuits
US7406704B2 (en) * 2000-09-08 2008-07-29 Sony Corporation Virtual channel system for web appliance, including interactive television
US7199637B2 (en) * 2003-09-02 2007-04-03 Semiconductor Energy Laboratory Co., Ltd. Rectifier circuit without alternating-current feedback
US20060157613A1 (en) * 2005-01-19 2006-07-20 Adamson Eric E Supersonic aircraft with active lift distribution control for reducing sonic boom
JP2007200976A (en) * 2006-01-24 2007-08-09 Matsushita Electric Ind Co Ltd Method for manufacturing semiconductor device
DE102010038739B4 (en) * 2010-07-30 2018-10-11 Globalfoundries Dresden Module One Llc & Co. Kg A process for producing a semiconductor device with increased stability of a complex material stack by providing fluorine-enriched boundary surfaces
US8878176B2 (en) 2011-08-11 2014-11-04 The Hong Kong University Of Science And Technology Metal-oxide based thin-film transistors with fluorinated active layer
US8921181B2 (en) * 2012-12-27 2014-12-30 Intermolecular, Inc. Flourine-stabilized interface

Citations (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4329706A (en) * 1979-03-01 1982-05-11 International Business Machines Corporation Doped polysilicon silicide semiconductor integrated circuit interconnections
US4354309A (en) * 1978-12-29 1982-10-19 International Business Machines Corp. Method of manufacturing a metal-insulator-semiconductor device utilizing a graded deposition of polycrystalline silicon
US4569697A (en) * 1983-08-26 1986-02-11 Energy Conversion Devices, Inc. Method of forming photovoltaic quality amorphous alloys by passivating defect states
US4613382A (en) * 1981-03-30 1986-09-23 Hitachi, Ltd. Method of forming passivated polycrystalline semiconductors
US4663825A (en) * 1984-09-27 1987-05-12 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US4697333A (en) * 1985-02-20 1987-10-06 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device using amorphous silicon as a mask
US4945065A (en) * 1988-06-02 1990-07-31 Mobil Solar Energy Corporation Method of passivating crystalline substrates
US5021353A (en) * 1990-02-26 1991-06-04 Micron Technology, Inc. Split-polysilicon CMOS process incorporating self-aligned silicidation of conductive regions
US5147820A (en) * 1991-08-26 1992-09-15 At&T Bell Laboratories Silicide formation on polysilicon
US5175119A (en) * 1990-03-19 1992-12-29 Fujitsu Limited Method of producing insulated-gate field effect transistor
US5177569A (en) * 1990-11-19 1993-01-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a two layered structure gate electrode
US5202275A (en) * 1989-03-20 1993-04-13 Hitachi Ltd. Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same
US5212108A (en) * 1991-12-13 1993-05-18 Honeywell Inc. Fabrication of stabilized polysilicon resistors for SEU control
US5273937A (en) * 1988-01-08 1993-12-28 Kabushiki Kaisha Toshiba Metal semiconductor device and method for producing the same
US5278096A (en) * 1991-12-23 1994-01-11 At&T Bell Laboratories Transistor fabrication method
US5320975A (en) * 1992-03-27 1994-06-14 International Business Machines Corporation Method of forming thin film pseudo-planar FET devices and structures resulting therefrom
US5334861A (en) * 1992-05-19 1994-08-02 Motorola Inc. Semiconductor memory cell
US5338398A (en) * 1991-03-28 1994-08-16 Applied Materials, Inc. Tungsten silicide etch process selective to photoresist and oxide
US5350698A (en) * 1993-05-03 1994-09-27 United Microelectronics Corporation Multilayer polysilicon gate self-align process for VLSI CMOS device
US5364803A (en) * 1993-06-24 1994-11-15 United Microelectronics Corporation Method of preventing fluorine-induced gate oxide degradation in WSix polycide structure
US5372860A (en) * 1993-07-06 1994-12-13 Corning Incorporated Silicon device production
US5373170A (en) * 1993-03-15 1994-12-13 Motorola Inc. Semiconductor memory device having a compact symmetrical layout
US5393676A (en) * 1993-09-22 1995-02-28 Advanced Micro Devices, Inc. Method of fabricating semiconductor gate electrode with fluorine migration barrier
US5407870A (en) * 1993-06-07 1995-04-18 Motorola Inc. Process for fabricating a semiconductor device having a high reliability dielectric material
US5411909A (en) * 1993-02-22 1995-05-02 Micron Technology, Inc. Method of forming a planar thin film transistor
US5418393A (en) * 1993-11-29 1995-05-23 Motorola, Inc. Thin-film transistor with fully gated channel region
US5440168A (en) * 1993-02-22 1995-08-08 Ryoden Semiconductor System Engineering Corporation Thin-film transistor with suppressed off-current and Vth
US5441904A (en) * 1993-11-16 1995-08-15 Hyundai Electronics Industries, Co., Ltd. Method for forming a two-layered polysilicon gate electrode in a semiconductor device using grain boundaries
US5523240A (en) * 1990-05-29 1996-06-04 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a thin film transistor with a halogen doped blocking layer
US5552332A (en) * 1995-06-02 1996-09-03 Motorola, Inc. Process for fabricating a MOSFET device having reduced reverse short channel effects
US5605848A (en) * 1995-12-27 1997-02-25 Chartered Semiconductor Manufacturing Pte Ltd. Dual ion implantation process for gate oxide improvement
US5652156A (en) * 1995-04-10 1997-07-29 Taiwan Semiconductor Manufacturing Company Ltd. Layered polysilicon deposition method
US5656529A (en) * 1995-05-11 1997-08-12 Nec Corporation Method for manufacturing highly-integrated capacitor
US5665611A (en) * 1996-01-31 1997-09-09 Micron Technology, Inc. Method of forming a thin film transistor using fluorine passivation
US5683946A (en) * 1995-12-01 1997-11-04 National Science Counsil Method for manufacturing fluorinated gate oxide layer
US5712181A (en) * 1993-07-20 1998-01-27 Lg Semicon Co., Ltd. Method for the formation of polycide gate in semiconductor device
US5726096A (en) * 1993-12-17 1998-03-10 Hyundai Electronics Industries Co., Ltd. Method for forming a tungsten silicide layer in a semiconductor device
US5753543A (en) * 1996-03-25 1998-05-19 Micron Technology, Inc. Method of forming a thin film transistor
US5767558A (en) * 1996-05-10 1998-06-16 Integrated Device Technology, Inc. Structures for preventing gate oxide degradation
US5830802A (en) * 1995-08-31 1998-11-03 Motorola Inc. Process for reducing halogen concentration in a material layer during semiconductor device fabrication
US5854135A (en) * 1997-04-09 1998-12-29 Vanguard International Semiconductor Corporation Optimized dry etching procedure, using an oxygen containing ambient, for small diameter contact holes
US5877074A (en) * 1997-12-09 1999-03-02 Holtek Microelectronics, Inc. Method for improving the electrical property of gate in polycide structure
US5943592A (en) * 1996-06-24 1999-08-24 Sony Corporation Method of making a MIS transistor
US6162716A (en) * 1999-03-26 2000-12-19 Taiwan Semiconductor Manufacturing Company Amorphous silicon gate with mismatched grain-boundary microstructure
US20010002071A1 (en) * 1999-08-24 2001-05-31 Agarwal Vishnu K. Boron incorporated diffusion barrier material
US6373114B1 (en) * 1998-10-23 2002-04-16 Micron Technology, Inc. Barrier in gate stack for improved gate dielectric integrity
US6611032B2 (en) * 1999-06-15 2003-08-26 Micron Technology, Inc. Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures
US6614082B1 (en) * 1999-01-29 2003-09-02 Micron Technology, Inc. Fabrication of semiconductor devices with transition metal boride films as diffusion barriers
US6646456B2 (en) * 1999-04-06 2003-11-11 Micron Technology Inc. Conductive material for integrated circuit fabrication
US6797601B2 (en) * 1999-06-11 2004-09-28 Micron Technology, Inc. Methods for forming wordlines, transistor gates, and conductive interconnects
US6949441B2 (en) * 1997-12-12 2005-09-27 Hyundai Electronics Industries Co., Ltd. Ferroelectric memory device and method of making the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US565529A (en) * 1896-08-11 Dynamo-electric machine
DE281054C (en)
JPS59136926A (en) * 1983-01-25 1984-08-06 Seiko Epson Corp Manufacture of semiconductor device
JPH0124009Y2 (en) * 1984-08-11 1989-07-21
JPS62285470A (en) * 1986-06-04 1987-12-11 Oki Electric Ind Co Ltd Manufacture of semiconductor device
DD281054A1 (en) * 1989-03-30 1990-07-25 Akad Wissenschaften Ddr A process for the passivation of Si devices
US5020275A (en) * 1990-10-15 1991-06-04 Bednarzik Uwe H Watering method and apparatus for plants
JPH06163576A (en) * 1992-11-20 1994-06-10 Nippon Steel Corp Manufacture of semiconductor device
JPH0992835A (en) * 1995-09-22 1997-04-04 Toshiba Corp Insulated gate field-effect transistor and its manufacture

Patent Citations (93)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4354309A (en) * 1978-12-29 1982-10-19 International Business Machines Corp. Method of manufacturing a metal-insulator-semiconductor device utilizing a graded deposition of polycrystalline silicon
US4329706A (en) * 1979-03-01 1982-05-11 International Business Machines Corporation Doped polysilicon silicide semiconductor integrated circuit interconnections
US4613382A (en) * 1981-03-30 1986-09-23 Hitachi, Ltd. Method of forming passivated polycrystalline semiconductors
US4569697A (en) * 1983-08-26 1986-02-11 Energy Conversion Devices, Inc. Method of forming photovoltaic quality amorphous alloys by passivating defect states
US4663825A (en) * 1984-09-27 1987-05-12 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US4697333A (en) * 1985-02-20 1987-10-06 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device using amorphous silicon as a mask
US5273937A (en) * 1988-01-08 1993-12-28 Kabushiki Kaisha Toshiba Metal semiconductor device and method for producing the same
US4945065A (en) * 1988-06-02 1990-07-31 Mobil Solar Energy Corporation Method of passivating crystalline substrates
US5202275A (en) * 1989-03-20 1993-04-13 Hitachi Ltd. Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same
US5021353A (en) * 1990-02-26 1991-06-04 Micron Technology, Inc. Split-polysilicon CMOS process incorporating self-aligned silicidation of conductive regions
US5175119A (en) * 1990-03-19 1992-12-29 Fujitsu Limited Method of producing insulated-gate field effect transistor
US5523240A (en) * 1990-05-29 1996-06-04 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a thin film transistor with a halogen doped blocking layer
US5177569A (en) * 1990-11-19 1993-01-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a two layered structure gate electrode
US5338398A (en) * 1991-03-28 1994-08-16 Applied Materials, Inc. Tungsten silicide etch process selective to photoresist and oxide
US5147820A (en) * 1991-08-26 1992-09-15 At&T Bell Laboratories Silicide formation on polysilicon
US5212108A (en) * 1991-12-13 1993-05-18 Honeywell Inc. Fabrication of stabilized polysilicon resistors for SEU control
US5278096A (en) * 1991-12-23 1994-01-11 At&T Bell Laboratories Transistor fabrication method
US5320975A (en) * 1992-03-27 1994-06-14 International Business Machines Corporation Method of forming thin film pseudo-planar FET devices and structures resulting therefrom
US5334861A (en) * 1992-05-19 1994-08-02 Motorola Inc. Semiconductor memory cell
US5440168A (en) * 1993-02-22 1995-08-08 Ryoden Semiconductor System Engineering Corporation Thin-film transistor with suppressed off-current and Vth
US5411909A (en) * 1993-02-22 1995-05-02 Micron Technology, Inc. Method of forming a planar thin film transistor
US5373170A (en) * 1993-03-15 1994-12-13 Motorola Inc. Semiconductor memory device having a compact symmetrical layout
US5350698A (en) * 1993-05-03 1994-09-27 United Microelectronics Corporation Multilayer polysilicon gate self-align process for VLSI CMOS device
US5407870A (en) * 1993-06-07 1995-04-18 Motorola Inc. Process for fabricating a semiconductor device having a high reliability dielectric material
US5364803A (en) * 1993-06-24 1994-11-15 United Microelectronics Corporation Method of preventing fluorine-induced gate oxide degradation in WSix polycide structure
US5668394A (en) * 1993-06-24 1997-09-16 United Microelectronics Corporation Prevention of fluorine-induced gate oxide degradation in WSi polycide structure
US5372860A (en) * 1993-07-06 1994-12-13 Corning Incorporated Silicon device production
US5712181A (en) * 1993-07-20 1998-01-27 Lg Semicon Co., Ltd. Method for the formation of polycide gate in semiconductor device
US5393676A (en) * 1993-09-22 1995-02-28 Advanced Micro Devices, Inc. Method of fabricating semiconductor gate electrode with fluorine migration barrier
US5441904A (en) * 1993-11-16 1995-08-15 Hyundai Electronics Industries, Co., Ltd. Method for forming a two-layered polysilicon gate electrode in a semiconductor device using grain boundaries
US5418393A (en) * 1993-11-29 1995-05-23 Motorola, Inc. Thin-film transistor with fully gated channel region
US5726096A (en) * 1993-12-17 1998-03-10 Hyundai Electronics Industries Co., Ltd. Method for forming a tungsten silicide layer in a semiconductor device
US5652156A (en) * 1995-04-10 1997-07-29 Taiwan Semiconductor Manufacturing Company Ltd. Layered polysilicon deposition method
US5656529A (en) * 1995-05-11 1997-08-12 Nec Corporation Method for manufacturing highly-integrated capacitor
US5552332A (en) * 1995-06-02 1996-09-03 Motorola, Inc. Process for fabricating a MOSFET device having reduced reverse short channel effects
US5830802A (en) * 1995-08-31 1998-11-03 Motorola Inc. Process for reducing halogen concentration in a material layer during semiconductor device fabrication
US5683946A (en) * 1995-12-01 1997-11-04 National Science Counsil Method for manufacturing fluorinated gate oxide layer
US5605848A (en) * 1995-12-27 1997-02-25 Chartered Semiconductor Manufacturing Pte Ltd. Dual ion implantation process for gate oxide improvement
US20050156240A1 (en) * 1996-01-31 2005-07-21 Sandhu Gurtej S. Thin film transistors and semiconductor constructions
US20110024762A1 (en) * 1996-01-31 2011-02-03 Micron Technology, Inc. Method of Forming a Thin Film Transistor
US5665611A (en) * 1996-01-31 1997-09-09 Micron Technology, Inc. Method of forming a thin film transistor using fluorine passivation
US7825414B2 (en) * 1996-01-31 2010-11-02 Micron Technology, Inc. Method of forming a thin film transistor
US7566907B2 (en) * 1996-01-31 2009-07-28 Micron Technology, Inc. Thin film transistors and semiconductor constructions
US20090047776A1 (en) * 1996-01-31 2009-02-19 Micron Technology, Inc. Method of Forming a Thin Film Transistor
US6001675A (en) * 1996-01-31 1999-12-14 Micron Technology, Inc. Method of forming a thin film transistor
US20070102705A1 (en) * 1996-01-31 2007-05-10 Sandhu Gurtej S Thin film transistors and semiconductor constructions
US6890842B2 (en) * 1996-01-31 2005-05-10 Micron Technology, Inc. Method of forming a thin film transistor
US7452760B2 (en) * 1996-01-31 2008-11-18 Micron Technology, Inc. Thin film transistors and semiconductor constructions
US6238957B1 (en) * 1996-01-31 2001-05-29 Micron Technology, Inc. Method of forming a thin film transistor
US20080237601A1 (en) * 1996-01-31 2008-10-02 Sandhu Gurtej S Transistors and semiconductor constructions
US20010014518A1 (en) * 1996-01-31 2001-08-16 Sandhu Gurtej S. Method of forming a thin film transistor
US20010044173A1 (en) * 1996-01-31 2001-11-22 Sandhu Gurtej S. Method of forming a thin film transistor
US7385222B2 (en) * 1996-01-31 2008-06-10 Micron Technology, Inc. Thin film transistors and semiconductor constructions
US6344376B2 (en) * 1996-01-31 2002-02-05 Micron Technology, Inc. Method of forming a thin film transistor
US6077732A (en) * 1996-03-25 2000-06-20 Micron Technology, Inc. Method of forming a thin film transistor
US5753543A (en) * 1996-03-25 1998-05-19 Micron Technology, Inc. Method of forming a thin film transistor
US5767558A (en) * 1996-05-10 1998-06-16 Integrated Device Technology, Inc. Structures for preventing gate oxide degradation
US6093589A (en) * 1996-05-10 2000-07-25 Integrated Device Technology, Inc. Methods for preventing gate oxide degradation
US5943592A (en) * 1996-06-24 1999-08-24 Sony Corporation Method of making a MIS transistor
US5854135A (en) * 1997-04-09 1998-12-29 Vanguard International Semiconductor Corporation Optimized dry etching procedure, using an oxygen containing ambient, for small diameter contact holes
US5877074A (en) * 1997-12-09 1999-03-02 Holtek Microelectronics, Inc. Method for improving the electrical property of gate in polycide structure
US7053434B2 (en) * 1997-12-12 2006-05-30 Hyundai Electronics Industries Co., Ltd. Ferroelectric memory device and method of making the same
US6949441B2 (en) * 1997-12-12 2005-09-27 Hyundai Electronics Industries Co., Ltd. Ferroelectric memory device and method of making the same
US6373114B1 (en) * 1998-10-23 2002-04-16 Micron Technology, Inc. Barrier in gate stack for improved gate dielectric integrity
US6930363B2 (en) * 1998-10-23 2005-08-16 Micron Technology, Inc. Barrier in gate stack for improved gate dielectric integrity
US6770571B2 (en) * 1998-10-23 2004-08-03 Micron Technology, Inc. Barrier in gate stack for improved gate dielectric integrity
US6562730B2 (en) * 1998-10-23 2003-05-13 Micron Technology, Inc. Barrier in gate stack for improved gate dielectric integrity
US6613654B1 (en) * 1999-01-29 2003-09-02 Micron Technology Inc Fabrication of semiconductor devices with transition metal boride films as diffusion barriers
US6614082B1 (en) * 1999-01-29 2003-09-02 Micron Technology, Inc. Fabrication of semiconductor devices with transition metal boride films as diffusion barriers
US6872639B2 (en) * 1999-01-29 2005-03-29 Micron Technology, Inc. Fabrication of semiconductor devices with transition metal boride films as diffusion barriers
US6162716A (en) * 1999-03-26 2000-12-19 Taiwan Semiconductor Manufacturing Company Amorphous silicon gate with mismatched grain-boundary microstructure
US6781365B2 (en) * 1999-04-06 2004-08-24 Micron Technology, Inc. Conductive material for integrated circuit fabrication
US6870380B2 (en) * 1999-04-06 2005-03-22 Micron Technology Inc Conductive material for integrated circuit fabrication
US6765398B2 (en) * 1999-04-06 2004-07-20 Micron Technology Inc. Conductive material for integrated circuit fabrication
US6906547B2 (en) * 1999-04-06 2005-06-14 Micron Technology Inc. Conductive material for integrated circuit fabrication
US6646456B2 (en) * 1999-04-06 2003-11-11 Micron Technology Inc. Conductive material for integrated circuit fabrication
US7046029B2 (en) * 1999-04-06 2006-05-16 Micron Technology, Inc. Conductive material for integrated circuit fabrication
US6812530B2 (en) * 1999-06-11 2004-11-02 Micron Technology, Inc. Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures
US6797601B2 (en) * 1999-06-11 2004-09-28 Micron Technology, Inc. Methods for forming wordlines, transistor gates, and conductive interconnects
US6611032B2 (en) * 1999-06-15 2003-08-26 Micron Technology, Inc. Methods for forming wordlines, transistor gates, and conductive interconnects, and wordline, transistor gate, and conductive interconnect structures
US20050266624A1 (en) * 1999-08-24 2005-12-01 Agarwal Vishnu K Boron incorporated diffusion barrier material
US6511900B2 (en) * 1999-08-24 2003-01-28 Micron Technology, Inc. Boron incorporated diffusion barrier material
US7084504B2 (en) * 1999-08-24 2006-08-01 Micron Technology, Inc. Boron incorporated diffusion barrier material
US20060261421A1 (en) * 1999-08-24 2006-11-23 Agarwal Vishnu K Boron incorporated diffusion barrier material
US20020030235A1 (en) * 1999-08-24 2002-03-14 Vishnu K. Agarwal Boron incorporated diffusion barrier material
US7271092B2 (en) * 1999-08-24 2007-09-18 Micron Technology, Inc. Boron incorporated diffusion barrier material
US20020001908A1 (en) * 1999-08-24 2002-01-03 Agarwal Vishnu K. Boron incorporated diffusion barrier material
US20010002071A1 (en) * 1999-08-24 2001-05-31 Agarwal Vishnu K. Boron incorporated diffusion barrier material
US20040082156A1 (en) * 1999-08-24 2004-04-29 Agarwal Vishnu K. Boron incorporated diffusion barrier material
US20040080002A1 (en) * 1999-08-24 2004-04-29 Agarwal Vishnu K. Boron incorporated diffusion barrier material
US6635939B2 (en) * 1999-08-24 2003-10-21 Micron Technology, Inc. Boron incorporated diffusion barrier material
US6630391B2 (en) * 1999-08-24 2003-10-07 Micron Technology, Inc. Boron incorporated diffusion barrier material
US6911381B2 (en) * 1999-08-24 2005-06-28 Micron Technology Inc. Boron incorporated diffusion barrier material

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110024762A1 (en) * 1996-01-31 2011-02-03 Micron Technology, Inc. Method of Forming a Thin Film Transistor

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US7825414B2 (en) 2010-11-02
US20010044173A1 (en) 2001-11-22
US5665611A (en) 1997-09-09
US6238957B1 (en) 2001-05-29
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US20110024762A1 (en) 2011-02-03
US6001675A (en) 1999-12-14
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US6890842B2 (en) 2005-05-10
US7566907B2 (en) 2009-07-28

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