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US20090224405A1 - Through via process - Google Patents

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US20090224405A1
US20090224405A1 US12044008 US4400808A US2009224405A1 US 20090224405 A1 US20090224405 A1 US 20090224405A1 US 12044008 US12044008 US 12044008 US 4400808 A US4400808 A US 4400808A US 2009224405 A1 US2009224405 A1 US 2009224405A1
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Prior art keywords
layer
via
plug
contact
substrate
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US12044008
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US8486823B2 (en )
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Wen-Chih Chiou
Chen-Hua Yu
Weng-Jin Wu
Jung-Chih Hu
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Taiwan Semiconductor Manufacturing Co (TSMC) Ltd
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Taiwan Semiconductor Manufacturing Co (TSMC) Ltd
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06541Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Abstract

A through via process is performed on a semiconductor substrate with a contact plug formed in an interlayer dielectric (ILD), and then a via plug is formed in the ILD layer to extend through a portion of the semiconductor substrate, followed forming an interconnection structure electrically connected with the contact plug and the via plug.

Description

    TECHNICAL FIELD
  • [0001]
    The present invention relates to stacked integrated circuits, and particularly to a through via process for wafer-level stacking technology.
  • BACKGROUND
  • [0002]
    Three-dimensional (3D) wafer-to-wafer vertical stack technology seeks to achieve the long-awaited goal of vertically stacking many layers of active IC devices such as processors, programmable devices and memory devices inside a single chip to shorten average wire lengths, thereby reducing interconnect RC delay and increasing system performance. One major challenge of 3D interconnects on a single wafer or in a wafer-to-wafer vertical stack is through-via that provides a signal path for high impedance signals to traverse from one side of the wafer to the other. Through silicon via (TSV) is typically fabricated to provide the through-via filled with a conducting material that pass completely through the layer to contact and connect with the other TSVs and conductors of the bonded layers. Examples of methods forming TSVs after the first interconnect metallization process are described in U.S. Pat. No. 6,642,081 to Patti and U.S. Pat. No. 6,897,125 to Morrow, et al. One disadvantage is that the density of the via is typically less because of etch and design limitations, potentially creating connection, contact, and reliability problems. An additional limitation to current TSV systems and methods is the limited availability for thermal dissipation. Therefore, should there be a desire to design TSVs for thermal dissipation, those TSVs will typically occupy the area for normal design, since the contact and metallization layers are already in place. The article entitled: “Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs”, by Robert S. Patti, Proceedings of the IEEE, pp. 1214-1224, Vol. 94, No. 6, June. 2006, (incorporated herein by reference), presents examples of super-contact processes forming tungsten-filled TSVs before the contact process. The super-contact process may impact precision in photolithography and deposition during the subsequent contact process due to stress induced by the huge tungsten-filled TSV.
  • SUMMARY OF THE INVENTION
  • [0003]
    Embodiments of the present invention include a through via process performed after a contact process before a first-level interconnection process.
  • [0004]
    In one aspect, the present invention provides a through via process including the following steps: providing a semiconductor substrate with an integrated circuit (IC) component formed thereon; forming an interlayer dielectric (ILD) layer on the semiconductor substrate and covering the IC component, forming a contact plug in the ILD layer and electrically connected to the IC component; forming at least one via hole extending through the ILD layer and a portion of the semiconductor substrate; depositing a conductive material layer on the ILD layer to fill the via hole; removing the conductive material layer outside the via hole to expose the conductive material layer and the top of the contact plug, wherein the conductive material layer remaining in the via hole forms a via plug; and forming an interconnection structure comprising a plurality of metal layers formed in a plurality of inter-metal dielectric (IMD) layers, wherein a lowermost metal layer of the interconnection structure is electrically connected to the exposed portions of the contact plug and the via plug.
  • [0005]
    In another aspect, the present invention provides a semiconductor component including a semiconductor substrate with an integrated circuit (IC) component formed thereon, an interlayer dielectric (ILD) layer formed on the semiconductor substrate, a contact plug formed in the ILD layer and electrically connected to the IC component, a via plug formed in the ILD layer and extending through a portion of the semiconductor substrate, and an interconnection structure comprising a plurality of metal layers formed in a plurality of inter-metal dielectric (IMD) layers. The top surfaces of the ILD layer, the via plug and the contact plug are leveled off. A lowermost metal layer of the interconnection structure is electrically connected to the exposed portions of the contact plug and the via plug.
  • [0006]
    In another aspect, the present invention provides a method including the following steps: providing a first wafer with a first semiconductor substrate, a first integrated circuit (IC) component formed on the first semiconductor substrate and an interlayer dielectric (ILD) layer formed on the semiconductor substrate and covering the IC component; successively forming a contact plug and a via plug in the ILD layer; forming an interconnection structure on the ILD layer; providing a second wafer; and bonding the first wafer to the second wafer to form a wafer stack. The contact plug is electrically connected to the IC component, and the via plug extends through a portion of the first semiconductor substrate. The interconnection structure is electrically connected to the contact plug and the via plug respectively.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0007]
    The aforementioned objects, features and advantages of this invention will become apparent by referring to the following detailed description of the preferred embodiments with reference to the accompanying drawings, wherein:
  • [0008]
    FIGS. 1˜10 are cross-sectional diagrams illustrating an exemplary embodiment of a portion of a semiconductor device at stages in an integrated circuit manufacturing process.
  • DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
  • [0009]
    Preferred embodiments of the present invention provide a through via process performed after a contact process before a first-level interconnection process. As used throughout this disclosure, the term “through via” refers to a metal-filled via passing through at least a part of a semiconductor substrate. The through via process of the present invention can be called a through-silicon via (TSV) process when the process is directed to form a metal-filled via passing through a part of a silicon-containing semiconductor substrate. The term “first-level interconnection” refers to a lowermost metal layer patterned in a lowermost inter-metal dielectric (IMD) layer overlying contact structures and transistors.
  • [0010]
    Reference will now be made in detail to the present embodiments, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. In the drawings, the shape and thickness of one embodiment may be exaggerated for clarity and convenience. This description will be directed in particular to elements forming part of, or cooperating more directly with, apparatus in accordance with the present invention. It is to be understood that elements not specifically shown or described may take various forms well known to those skilled in the art. Further, when a layer is referred to as being on another layer or “on” a substrate, it may be directly on the other layer or on the substrate, or intervening layers may also be present.
  • [0011]
    In an exemplary embodiment, FIGS. 1˜10 show cross-sectional views of a portion of a semiconductor device at stages in an integrated circuit manufacturing process. With reference now to FIG. 1, there is shown a cross-sectional diagram of a wafer 100 comprising a semiconductor substrate 10, an IC component 200 processed from the substrate 10, an inter-layer dielectric (ILD) layer 12 overlying the semiconductor substrate 10, and a contact plug 14 formed in the dielectric layer 12 electrically connected with the IC component 200. In detail, the substrate 10 is typically silicon (Si), for example, a silicon substrate with or without an epitaxial layer, or a silicon-on-insulator substrate containing a buried insulator layer. The substrate 10 may also be made of gallium arsenide (GaAs), gallium arsenide-phosphide (GaAsP), indium phosphide (InP), gallium aluminum arsenic (GaAlAs), indium gallium phosphide (InGaP). The IC component 200 may comprise multiple individual circuit elements such as transistors, diodes, resistors, capacitors, inductors, and other active and passive semiconductor devices formed by conventional processes known in the integrated circuit manufacturing art.
  • [0012]
    The ILD layer 12 is formed on the substrate 10 so as to isolate the IC component 200 from a subsequent formation of an interconnection structure. The ILD layer 12 may be a single layer or a multi-layered structure. The ILD layer 12 may be a silicon oxide containing layer formed of doped or undoped silicon oxide by a thermal CVD process or high-density plasma (HDP) process, e.g., undoped silicate glass (USG), phosphorous doped silicate glass (PSG) or borophosphosilicate glass (BPSG). Alternatively, the ILD layer 12 may be formed of doped or P-doped spin-on-glass (SOG), PTEOS, or BPTEOS. Following a dry etching process carried out, a contact hole is formed in the ILD layer 12, and a conductive material layer is deposited to fill the contact hole, forming a contact plug 14. The contact plug 14 may be formed of tungsten, tungsten-based alloy, copper, or copper-based alloy.
  • [0013]
    Referring to FIGS. 2˜4, following planarization, e.g., chemical mechanical planarization (CMP) on the ILD layer 12, a lithographically patterned photoresist layer 16 is provided. A dry etching process is then carried out to form at least one via hole 18 that passes through the ILD layer 12 and extends to reach a predetermined depth of the substrate 10. Then the patterned photoresist layer 16 is stripped.
  • [0014]
    Referring to FIG. 5, a passivation layer 20 is conformally deposited on the wafer 100 to line the sidewalls and bottom of the via holes 18 in order to prevent any conducting material from leaching into any active portions of the circuitry of the wafer 100. The passivation layer 20 may be formed of silicon oxide, silicon nitride, combinations thereof, or the like. A conductive material layer 22 is then deposited on the passivation layer 20 of the wafer 100, as shown in FIG. 6, to fill the via holes 18. The conductive material layer 22 may include a diffusion barrier layer and a metal layer. For example, a diffusion barrier layer is conformally deposited along the bottom and sidewalls of the via hole 18 followed by a metal-fill process, thus providing both an excellent diffusion barrier in combination with good conductivity. The diffusion barrier layer may include, but is not limited to, a refractory material, TiN, TaN, Ta, Ti, TiSN, TaSN, W, WN, Cr, Nb, Co, Ni, Pt, Ru, Pd, Au, CoP, CoWP, NiP, NiWP, mixtures thereof, or other materials that can inhibit diffusion of copper into the ILD layer 12 by means of PVD, CVD, ALD or electroplating. The metal layer may include a low resistivity conductor material selected from the group of conductor materials including, but is not limited to, copper and copper-based alloy. For example, a copper-fill process includes metal seed layer deposition and copper electrochemical plating. Alternatively, the metal layer may comprise various materials, such as tungsten, aluminum, gold, silver, and the like.
  • [0015]
    Referring to FIG. 7, after removing the excess portions of the conductive material layer 22 and the passivation layer 20 outside the via holes 18, either through etching, chemical mechanical polishing (CMP), or the like, the wafer 100 now comprises via plugs 22 a passing through the ILD layer 12 and extending through a portion of the substrate 10.
  • [0016]
    Next, back-end-of-line (BEOL) interconnection technologies are processed on the wafer 100 to fabricate an interconnection structure including a plurality of interconnection layers and inter-metal dielectric (IMD) layers. As illustrated in FIG. 8, a first-level interconnection layer 26 is formed in an IMD layer 24 to electrically connect with the contact plug 14 and the via plugs 22 a respectively. Thereafter, another level interconnection layers and IMD layers are fabricated on the first-level interconnection layer 26, which are omitted in the drawings for clarity and convenience. Embodiments of the present invention use copper-based conductive materials for forming the interconnection layers. The copper-based conductive material is intended to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing minor amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum or zirconium. A standard damascene process may be used with the copper BEOL interconnection. Although the embodiments of the present invention illustrate copper interconnection patterns, the present invention also provides value when using metallic materials excluding copper for BEOL interconnection.
  • [0017]
    Referring to FIG. 9, bonding contacts 28 are formed in an insulating layer 30 overlying a completed top-level interconnect layer and a top-level IMD layer. The insulating layer 30 may be removed or etched to reveal the bonding contacts 28 slightly elevated above the top of insulating layer 30. The bonding contacts 28 may be formed of copper-based conductive materials. The insulating layer 30 can insulate the TC component 200 from any other circuitry or devices in any wafers bonded to the wafer 100.
  • [0018]
    FIG. 10 illustrates the cross-section of the wafer 100 stacked and bonded to another wafer 300. The wafer 300 comprises a substrate 40, an insulating layer 42, an IMD layer 44 and bonding pads 46. The wafers 100 and 300 are bonded together at the bonding contacts 28 and the bonding pads 46 to form a three-dimensional stacked wafer. It should be noted that any number of different devices, components, connectors, and the like, might be integrated into the wafers 100 and 300. The specific devices or lack of devices that may be illustrated herein are not intended to limit the embodiments of the present invention in any way.
  • [0019]
    Compared with existing methods for forming TSV in semiconductor devices, the through via process according to the embodiment of the present invention eliminates the impact on precision of photolithography, etching and deposition during the contact process, and results in advantages of lower through-via Rc, higher through-via density, a minimum need for keep-out zone, routing freedom for interconnection metal layers and better yields.
  • [0020]
    Although the present invention has been described in its preferred embodiments, it is not intended to limit the invention to the precise embodiments disclosed herein. Those skilled in this technology can still make various alterations and modifications without departing from the scope and spirit of this invention. Therefore, the scope of the present invention shall be defined and protected by the following claims and their equivalents.

Claims (15)

  1. 1. A through via process, comprising:
    providing a semiconductor substrate, comprising: an integrated circuit (IC) component formed on said semiconductor substrate; an interlayer dielectric (ILD) layer formed on said semiconductor substrate and covering said IC component, and a contact plug formed in said ILD layer and electrically connected to said IC component;
    forming at least one via hole extending through said ILD layer and a portion of said semiconductor substrate;
    depositing a conductive material layer on said ILD layer to fill said via hole;
    removing said conductive material layer outside the via hole to expose said conductive material layer and the top of said contact plug, wherein said conductive material layer remaining in said via hole forms a via plug; and
    forming an interconnection structure comprising a plurality of metal layers formed in a plurality of inter-metal dielectric (IMD) layers, wherein a lowermost metal layer of said interconnection structure is electrically connected to the exposed portions of said contact plug and said via plug.
  2. 2. The through via process of claim 1, wherein said conductive material layer comprises copper or copper-based alloy.
  3. 3. The through via process of claim 1, wherein said contact plug is formed of tungsten or tungsten-based alloy.
  4. 4. The through via process of claim 1, further comprising: forming a passivation layer lining the bottom and sidewalls of said via hole before depositing said conductive material layer.
  5. 5. The through via process of claim 4, where said passivation layer comprises silicon oxide, silicon nitride, or combinations thereof.
  6. 6. A semiconductor component, comprising:
    a semiconductor substrate including an integrated circuit (IC) component, an interlayer dielectric (ILD) layer formed on said semiconductor substrate;
    a contact plug formed in said ILD layer and electrically connected to said IC component;
    a via plug formed in said ILD layer and extending through a portion of said semiconductor substrate, wherein the top surfaces of said ILD layer, said via plug and said contact plug are leveled off; and
    an interconnection structure comprising a plurality of metal layers formed in a plurality of inter-metal dielectric (IMD) layers, wherein a lowermost metal layer of said interconnection structure is electrically connected to the exposed portions of said contact plug and said via plug.
  7. 7. The semiconductor component of claim 6, wherein said via plug comprises copper or copper-based alloy.
  8. 8. The semiconductor component of claim 6, wherein said contact plug is formed of tungsten or tungsten-based alloy.
  9. 9. The semiconductor component of claim 6, further comprising a passivation layer lining the bottom and sidewalls of said via plug.
  10. 10. The semiconductor component of claim 9, where said passivation layer comprises silicon oxide, silicon nitride, or combinations thereof.
  11. 11. A method, comprising:
    providing a first wafer, comprising: a first semiconductor substrate; a first integrated circuit (IC) component formed on said first semiconductor substrate; and an interlayer dielectric (ILD) layer formed on said semiconductor substrate and covering said IC component;
    successively forming a contact plug and a via plug in said ILD layer, wherein said contact plug is electrically connected to said IC component, and said via plug extends through a portion of said first semiconductor substrate;
    forming an interconnection structure on said ILD layer, wherein said interconnection structure is electrically connected to said contact plug and said via plug respectively;
    providing a second wafer; and
    bonding said first wafer to said second wafer to form a wafer stack.
  12. 12. The method of claim 11, wherein said via plug comprises copper or copper-based alloy.
  13. 13. The method of claim 11, wherein said contact plug is formed of tungsten or tungsten-based alloy.
  14. 14. The method of claim 11, further comprising: forming a passivation layer lining the bottom and sidewalls of said via plug.
  15. 15. The method of claim 14, where said passivation layer comprises silicon oxide, silicon nitride, or combinations thereof.
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US13921032 US20130277844A1 (en) 2008-03-07 2013-06-18 Through via process

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090315154A1 (en) * 2008-06-19 2009-12-24 Micron Technology, Inc. Semiconductor with through-substrate interconnect
US20100213560A1 (en) * 2009-02-24 2010-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for backside illuminated image sensor
US20100220226A1 (en) * 2009-02-24 2010-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Front side implanted guard ring structure for backside illuminated image sensor
US7795134B2 (en) 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US7863187B2 (en) 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7884015B2 (en) 2007-12-06 2011-02-08 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US20110042814A1 (en) * 2009-08-24 2011-02-24 Sony Corporation Semiconductor device and method for production of semiconductor device
US20110042821A1 (en) * 2009-08-21 2011-02-24 Micron Technology, Inc. Vias and conductive routing layers in semiconductor substrates
US7902643B2 (en) 2006-08-31 2011-03-08 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
US7915736B2 (en) 2005-09-01 2011-03-29 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US20110136338A1 (en) * 2009-12-09 2011-06-09 Electronics And Telecommunications Research Institute Method for fabricating semiconductor device
US20110193226A1 (en) * 2010-02-08 2011-08-11 Micron Technology, Inc. Microelectronic devices with through-substrate interconnects and associated methods of manufacturing
US8222139B2 (en) 2010-03-30 2012-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Chemical mechanical polishing (CMP) processing of through-silicon via (TSV) and contact plug simultaneously
WO2012115333A1 (en) * 2011-02-24 2012-08-30 단국대학교 산학협력단 Substrate having penetrating structure and manufacturing method thereof, package device including substrate having penetrating structure and manufacturing method thereof
US20120256150A1 (en) * 2011-04-08 2012-10-11 Micron Technology, Inc. Integrated Circuitry, Methods of Forming Memory Cells, and Methods of Patterning Platinum-Containing Material
US8322031B2 (en) 2004-08-27 2012-12-04 Micron Technology, Inc. Method of manufacturing an interposer
US8481425B2 (en) 2011-05-16 2013-07-09 United Microelectronics Corp. Method for fabricating through-silicon via structure
US8518823B2 (en) 2011-12-23 2013-08-27 United Microelectronics Corp. Through silicon via and method of forming the same
US8525296B1 (en) 2012-06-26 2013-09-03 United Microelectronics Corp. Capacitor structure and method of forming the same
US8609529B2 (en) 2012-02-01 2013-12-17 United Microelectronics Corp. Fabrication method and structure of through silicon via
US8691688B2 (en) 2012-06-18 2014-04-08 United Microelectronics Corp. Method of manufacturing semiconductor structure
US8691600B2 (en) 2012-05-02 2014-04-08 United Microelectronics Corp. Method for testing through-silicon-via (TSV) structures
US8716104B1 (en) 2012-12-20 2014-05-06 United Microelectronics Corp. Method of fabricating isolation structure
US8753981B2 (en) 2011-04-22 2014-06-17 Micron Technology, Inc. Microelectronic devices with through-silicon vias and associated methods of manufacturing
US20140203827A1 (en) * 2013-01-23 2014-07-24 GlobalFoundries, Inc. Integrated circuits and methods of forming the same with embedded interconnect connection to through-semiconductor via
US8822336B2 (en) 2011-06-16 2014-09-02 United Microelectronics Corp. Through-silicon via forming method
US8828745B2 (en) 2011-07-06 2014-09-09 United Microelectronics Corp. Method for manufacturing through-silicon via
US20140264926A1 (en) * 2013-03-12 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method and Apparatus for Back End of Line Semiconductor Device Processing
US8853848B2 (en) 2011-01-24 2014-10-07 Industrial Technology Research Institute Interconnection structure, apparatus therewith, circuit structure therewith
US8884398B2 (en) 2013-04-01 2014-11-11 United Microelectronics Corp. Anti-fuse structure and programming method thereof
US20140332952A1 (en) * 2013-05-09 2014-11-13 United Microelectronics Corp. Semiconductor structure and method for testing the same
US8900996B2 (en) 2012-06-21 2014-12-02 United Microelectronics Corp. Through silicon via structure and method of fabricating the same
US8912844B2 (en) 2012-10-09 2014-12-16 United Microelectronics Corp. Semiconductor structure and method for reducing noise therein
US8916471B1 (en) 2013-08-26 2014-12-23 United Microelectronics Corp. Method for forming semiconductor structure having through silicon via for signal and shielding structure
US9024416B2 (en) 2013-08-12 2015-05-05 United Microelectronics Corp. Semiconductor structure
US9035457B2 (en) 2012-11-29 2015-05-19 United Microelectronics Corp. Substrate with integrated passive devices and method of manufacturing the same
US9048223B2 (en) 2013-09-03 2015-06-02 United Microelectronics Corp. Package structure having silicon through vias connected to ground potential
US9105628B1 (en) * 2012-03-29 2015-08-11 Valery Dubin Through substrate via (TSuV) structures and method of making the same
US9117804B2 (en) 2013-09-13 2015-08-25 United Microelectronics Corporation Interposer structure and manufacturing method thereof
US9123730B2 (en) 2013-07-11 2015-09-01 United Microelectronics Corp. Semiconductor device having through silicon trench shielding structure surrounding RF circuit
US9275933B2 (en) 2012-06-19 2016-03-01 United Microelectronics Corp. Semiconductor device
US9287173B2 (en) 2013-05-23 2016-03-15 United Microelectronics Corp. Through silicon via and process thereof
US9343359B2 (en) 2013-12-25 2016-05-17 United Microelectronics Corp. Integrated structure and method for fabricating the same

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8586472B2 (en) * 2010-07-14 2013-11-19 Infineon Technologies Ag Conductive lines and pads and method of manufacturing thereof
CN103094187B (en) * 2011-10-31 2015-01-21 中芯国际集成电路制造(上海)有限公司 Forming method for silicon through hole
US9520350B2 (en) * 2013-03-13 2016-12-13 Intel Corporation Bumpless build-up layer (BBUL) semiconductor package with ultra-thin dielectric layer
US9147642B2 (en) * 2013-10-31 2015-09-29 Nanya Technology Corporation Integrated circuit device
WO2016161434A1 (en) 2015-04-02 2016-10-06 Nanopac Technologies, Inc. Method for creating through-connected vias and conductors on a substrate
CN106611756A (en) * 2015-10-26 2017-05-03 联华电子股份有限公司 Wafer-to-wafer butt joint structure and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020027293A1 (en) * 2001-06-28 2002-03-07 Fujitsu Limited Three dimensional semiconductor integrated circuit device and method for making the same
US20030193076A1 (en) * 2002-04-11 2003-10-16 Robert Patti Interlocking conductor method for bonding wafers to produce stacked integrated circuits
US6897125B2 (en) * 2003-09-17 2005-05-24 Intel Corporation Methods of forming backside connections on a wafer stack
US7622380B1 (en) * 2003-08-25 2009-11-24 Novellus Systems, Inc. Method of improving adhesion between two dielectric films

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6352923B1 (en) 1999-03-01 2002-03-05 United Microelectronics Corp. Method of fabricating direct contact through hole type
JP4575782B2 (en) 2002-12-20 2010-11-04 インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Method for producing a three-dimensional device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020027293A1 (en) * 2001-06-28 2002-03-07 Fujitsu Limited Three dimensional semiconductor integrated circuit device and method for making the same
US20030193076A1 (en) * 2002-04-11 2003-10-16 Robert Patti Interlocking conductor method for bonding wafers to produce stacked integrated circuits
US6642081B1 (en) * 2002-04-11 2003-11-04 Robert Patti Interlocking conductor method for bonding wafers to produce stacked integrated circuits
US7622380B1 (en) * 2003-08-25 2009-11-24 Novellus Systems, Inc. Method of improving adhesion between two dielectric films
US6897125B2 (en) * 2003-09-17 2005-05-24 Intel Corporation Methods of forming backside connections on a wafer stack

Cited By (71)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8322031B2 (en) 2004-08-27 2012-12-04 Micron Technology, Inc. Method of manufacturing an interposer
US8008192B2 (en) 2005-06-28 2011-08-30 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US7795134B2 (en) 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US9293367B2 (en) 2005-06-28 2016-03-22 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US7863187B2 (en) 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7915736B2 (en) 2005-09-01 2011-03-29 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US9570350B2 (en) 2006-08-31 2017-02-14 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
US9099539B2 (en) 2006-08-31 2015-08-04 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
US7902643B2 (en) 2006-08-31 2011-03-08 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
US9281241B2 (en) 2007-12-06 2016-03-08 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US7884015B2 (en) 2007-12-06 2011-02-08 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US8247907B2 (en) 2007-12-06 2012-08-21 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US7968460B2 (en) 2008-06-19 2011-06-28 Micron Technology, Inc. Semiconductor with through-substrate interconnect
US8404587B2 (en) 2008-06-19 2013-03-26 Micro Technology, Inc. Semiconductor with through-substrate interconnect
US9099457B2 (en) 2008-06-19 2015-08-04 Micron Technology, Inc. Semiconductor with through-substrate interconnect
US9514975B2 (en) 2008-06-19 2016-12-06 Micron Technology, Inc. Semiconductor with through-substrate interconnect
US20090315154A1 (en) * 2008-06-19 2009-12-24 Micron Technology, Inc. Semiconductor with through-substrate interconnect
US9917002B2 (en) 2008-06-19 2018-03-13 Micron Technology, Inc. Semiconductor with through-substrate interconnect
US8531565B2 (en) 2009-02-24 2013-09-10 Taiwan Semiconductor Manufacturing Company, Ltd. Front side implanted guard ring structure for backside illuminated image sensor
US20100213560A1 (en) * 2009-02-24 2010-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for backside illuminated image sensor
US20100220226A1 (en) * 2009-02-24 2010-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Front side implanted guard ring structure for backside illuminated image sensor
US9773828B2 (en) 2009-02-24 2017-09-26 Taiwan Semiconductor Manufacturing Co., Ltd. Image sensor device and method of forming same
US8810700B2 (en) 2009-02-24 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Front side implanted guard ring structure for backside
US9142586B2 (en) 2009-02-24 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for backside illuminated image sensor
US20110042821A1 (en) * 2009-08-21 2011-02-24 Micron Technology, Inc. Vias and conductive routing layers in semiconductor substrates
US9799562B2 (en) 2009-08-21 2017-10-24 Micron Technology, Inc. Vias and conductive routing layers in semiconductor substrates
US8742585B2 (en) 2009-08-24 2014-06-03 Sony Corporation Semiconductor device having a plurality of pads of low diffusible material formed in a substrate
US20110042814A1 (en) * 2009-08-24 2011-02-24 Sony Corporation Semiconductor device and method for production of semiconductor device
US8368222B2 (en) * 2009-08-24 2013-02-05 Sony Corporation Semiconductor device with pad with less diffusible contacting surface and method for production of the semiconductor device
US7998862B2 (en) * 2009-12-09 2011-08-16 Electronics And Telecommunications Research Institute Method for fabricating semiconductor device
US20110136338A1 (en) * 2009-12-09 2011-06-09 Electronics And Telecommunications Research Institute Method for fabricating semiconductor device
US20110193226A1 (en) * 2010-02-08 2011-08-11 Micron Technology, Inc. Microelectronic devices with through-substrate interconnects and associated methods of manufacturing
US8907457B2 (en) 2010-02-08 2014-12-09 Micron Technology, Inc. Microelectronic devices with through-substrate interconnects and associated methods of manufacturing
US8222139B2 (en) 2010-03-30 2012-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Chemical mechanical polishing (CMP) processing of through-silicon via (TSV) and contact plug simultaneously
US8853848B2 (en) 2011-01-24 2014-10-07 Industrial Technology Research Institute Interconnection structure, apparatus therewith, circuit structure therewith
WO2012115333A1 (en) * 2011-02-24 2012-08-30 단국대학교 산학협력단 Substrate having penetrating structure and manufacturing method thereof, package device including substrate having penetrating structure and manufacturing method thereof
US8409960B2 (en) * 2011-04-08 2013-04-02 Micron Technology, Inc. Methods of patterning platinum-containing material
US8835891B2 (en) 2011-04-08 2014-09-16 Micron Technology, Inc. Integrated circuitry, methods of forming memory cells, and methods of patterning platinum-containing material
US8653494B2 (en) 2011-04-08 2014-02-18 Micron Technology, Inc. Integrated circuitry, methods of forming memory cells, and methods of patterning platinum-containing material
US20120256150A1 (en) * 2011-04-08 2012-10-11 Micron Technology, Inc. Integrated Circuitry, Methods of Forming Memory Cells, and Methods of Patterning Platinum-Containing Material
US9343362B2 (en) 2011-04-22 2016-05-17 Micron Technology, Inc. Microelectronic devices with through-silicon vias and associated methods of manufacturing
US8753981B2 (en) 2011-04-22 2014-06-17 Micron Technology, Inc. Microelectronic devices with through-silicon vias and associated methods of manufacturing
US8481425B2 (en) 2011-05-16 2013-07-09 United Microelectronics Corp. Method for fabricating through-silicon via structure
US8822336B2 (en) 2011-06-16 2014-09-02 United Microelectronics Corp. Through-silicon via forming method
US8828745B2 (en) 2011-07-06 2014-09-09 United Microelectronics Corp. Method for manufacturing through-silicon via
US8518823B2 (en) 2011-12-23 2013-08-27 United Microelectronics Corp. Through silicon via and method of forming the same
US8841755B2 (en) 2011-12-23 2014-09-23 United Microelectronics Corp. Through silicon via and method of forming the same
US8609529B2 (en) 2012-02-01 2013-12-17 United Microelectronics Corp. Fabrication method and structure of through silicon via
US9105628B1 (en) * 2012-03-29 2015-08-11 Valery Dubin Through substrate via (TSuV) structures and method of making the same
US8691600B2 (en) 2012-05-02 2014-04-08 United Microelectronics Corp. Method for testing through-silicon-via (TSV) structures
US8691688B2 (en) 2012-06-18 2014-04-08 United Microelectronics Corp. Method of manufacturing semiconductor structure
US9275933B2 (en) 2012-06-19 2016-03-01 United Microelectronics Corp. Semiconductor device
US8900996B2 (en) 2012-06-21 2014-12-02 United Microelectronics Corp. Through silicon via structure and method of fabricating the same
US9312208B2 (en) 2012-06-21 2016-04-12 United Microelectronics Corp. Through silicon via structure
US8525296B1 (en) 2012-06-26 2013-09-03 United Microelectronics Corp. Capacitor structure and method of forming the same
US8912844B2 (en) 2012-10-09 2014-12-16 United Microelectronics Corp. Semiconductor structure and method for reducing noise therein
US9035457B2 (en) 2012-11-29 2015-05-19 United Microelectronics Corp. Substrate with integrated passive devices and method of manufacturing the same
US8716104B1 (en) 2012-12-20 2014-05-06 United Microelectronics Corp. Method of fabricating isolation structure
US20140203827A1 (en) * 2013-01-23 2014-07-24 GlobalFoundries, Inc. Integrated circuits and methods of forming the same with embedded interconnect connection to through-semiconductor via
US9245790B2 (en) * 2013-01-23 2016-01-26 GlobalFoundries, Inc. Integrated circuits and methods of forming the same with multiple embedded interconnect connection to same through-semiconductor via
US9627250B2 (en) * 2013-03-12 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for back end of line semiconductor device processing
US20140264926A1 (en) * 2013-03-12 2014-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method and Apparatus for Back End of Line Semiconductor Device Processing
US8884398B2 (en) 2013-04-01 2014-11-11 United Microelectronics Corp. Anti-fuse structure and programming method thereof
US20140332952A1 (en) * 2013-05-09 2014-11-13 United Microelectronics Corp. Semiconductor structure and method for testing the same
US9287173B2 (en) 2013-05-23 2016-03-15 United Microelectronics Corp. Through silicon via and process thereof
US9123730B2 (en) 2013-07-11 2015-09-01 United Microelectronics Corp. Semiconductor device having through silicon trench shielding structure surrounding RF circuit
US9024416B2 (en) 2013-08-12 2015-05-05 United Microelectronics Corp. Semiconductor structure
US8916471B1 (en) 2013-08-26 2014-12-23 United Microelectronics Corp. Method for forming semiconductor structure having through silicon via for signal and shielding structure
US9048223B2 (en) 2013-09-03 2015-06-02 United Microelectronics Corp. Package structure having silicon through vias connected to ground potential
US9117804B2 (en) 2013-09-13 2015-08-25 United Microelectronics Corporation Interposer structure and manufacturing method thereof
US9343359B2 (en) 2013-12-25 2016-05-17 United Microelectronics Corp. Integrated structure and method for fabricating the same

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