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Method and apparatus for copper electroplating

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US20090065365A1
US20090065365A1 US11853174 US85317407A US2009065365A1 US 20090065365 A1 US20090065365 A1 US 20090065365A1 US 11853174 US11853174 US 11853174 US 85317407 A US85317407 A US 85317407A US 2009065365 A1 US2009065365 A1 US 2009065365A1
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Prior art keywords
substrate
additive
recessed
onto
region
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US11853174
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Ayse Durmus
Ismail Emesh
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ASM NuTool Inc
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ASM NuTool Inc
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    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02Electroplating of selected surface areas
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D17/00Constructional parts, or assemblies thereof, of cells for electrolytic coating
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00Electroplating: Baths therefor
    • C25D3/02Electroplating: Baths therefor from solutions
    • C25D3/38Electroplating: Baths therefor from solutions of copper

Abstract

A method and apparatus for a copper electroplating procedure, wherein a first additive is preferentially adsorbed onto the field region of a substrate and a second additive is preferentially adsorbed onto the surfaces of at least one recessed region of the substrate, is provided. The first additive is more resistive to the electrodeposition relative to the second additive such that the recessed regions are filled at a faster rate than a layer is deposited on the field region.

Description

    FIELD OF THE INVENTION
  • [0001]
    The present invention relates to copper electroplating, and more particularly to a method and apparatus for copper electroplating a substrate in a semiconductor manufacturing process by preferentially adsorbing additives onto the substrate prior to the electroplating procedure.
  • BACKGROUND OF THE INVENTION
  • [0002]
    In today's electronic products, integrated circuit chips are packaged in a planar two-dimensional style in which wire bonding is used for connecting the various chips to the board. Further, miniaturization and performance enhancement will require three-dimensional interconnection schemes whereby various chips are stacked and vertically connected by interconnects drilled through the substrate. The three-dimensional interconnects are shorter between chips than in a two-dimensional configuration, which allows for higher system speed and smaller power consumption. Three-dimensional integration processes bring a new challenge to the semiconductor industry which includes filling large vias and interconnects. While submicron size vias take a couple of minutes to fill, wide vias and interconnects having a depth of up to hundreds microns and/or widths of tens of microns may take hours to fill and large voids may occur. Successfully filling these vias with copper depends on the role of additives and the plating method used.
  • [0003]
    Conventional semiconductor devices generally include a semiconductor substrate, such as a silicon substrate, and a plurality of sequentially formed dielectric interlayers and conductive pathways made of conductive materials. In an integrated circuit, multiple levels of interconnected networks extend laterally with respect to the substrate surface. The interconnects are typically formed by filling in features or cavities etched into the dielectric interlayers by a metallization process such as electrodeposition, for example. Copper, CVD tungsten, and copper alloys are considered preferable materials for filling the vias and interconnects because of their superior electromigration and low resistivity characteristics. Vias formed in adjacent interlayers can be electrically connected using interconnects.
  • [0004]
    Copper electroplating is commonly performed cathodically in a specially formulated electrolyte solution, or plating bath, containing copper ions as well as additives that control the texture, morphology, and plating behavior of the deposited copper layer. The electroplating process typically is performed by immersing a substrate into a plating solution that also contains an anode plate, which can be consumable, disposed therein. The substrate includes a seed layer formed over a barrier layer, and an electrical contact is operatively connected to the seed layer. Deposition of the copper onto the seed layer is initiated when a cathodic potential, with respect to the anode plate, is applied. Typical plating solutions commercially available for plating copper layers contain copper sulfate (CuSO4) as the copper ion source. The plating solution may also have other ingredients such as chloride ions, which have an effect on the adsorption of the additives.
  • [0005]
    The additives added to the electrolyte solution help to deposit a smooth and shiny layer of copper. These additives can be categorized as suppressors, accelerators, levelers, brighteners, grain refiners, wetting agents, stress reducing agents, or the like. The relative size of the accelerator molecules is smaller than the relative size of the suppressor molecules which, in turn, is smaller than the relative size of the leveler molecules. Typical suppressors include, but are not limited to, polyethylene glycol (“PEG”) and polypropylene glycol (“PPG”). Typical accelerators include, but are not limited to, organic disulfides. Typical levelers include, but are not limited to, organic compounds such as Crystal Violent, Janus Green and BTA. The additives play an important role in forming interconnects between adjacent interlayers because filling the vias and trenches in the metallization process requires a bottom-up, void-free filling capability. The additives assist in controlling the rate of electroplating on different surfaces.
  • [0006]
    The additive concentration in the electrolyte solution is a critical parameter in maintaining reliable plating processes. For example, it is known that accelerator molecules are consumed rapidly even when current is not applied. This is due to the catalytic decomposition that takes place at a copper anode surface. For this reason, a costly and complicated system is commonly used for most advanced plating tools in which the accelerator additives are separated from the anode plate by a membrane being disposed between the substrate being processed and the anode plate. The function of the membrane is to allow the copper ions in the electrolyte solution to diffuse through the membrane while preventing direct contact between the accelerator additive molecules and the anode plate. This can be accomplished by having two compartments for the plating bath isolated by the membrane, wherein one compartment is filled with an additive-free electrolyte and containing the anode plate and the other compartment is filled with an electrolyte solution containing additives and also contains the substrate being processed. In addition, because the concentration of the additives is critical during the electroplating process, the electrolyte solution must be continually sampled and tested. The testing apparatus is an expensive piece of equipment for maintaining the proper balance and levels of additives within the electrolyte solution for the above-described complex plating apparatus.
  • [0007]
    Accordingly, an electroplating process that eliminates the need for a membrane separating the anode plate from the additives, which in turn eliminates the need for expensive analysis machinery to maintain the proper concentration of additives, is needed. Further, an electroplating process that reduces the copper film thickness on the field regions that surround the vias and interconnects while filling vias or interconnects is also needed. Additionally, a plating process that reduces the overall cost for the fabrication of copper interconnects by reducing the cost of the subsequent chemical mechanical planarization (“CMP”) procedure is needed.
  • BRIEF SUMMARY OF THE INVENTION
  • [0008]
    In one aspect of the present invention, a method for electroplating a substrate having a field region and at least one recessed region formed therein is provided. The method includes preferentially adsorbing a first additive to surfaces of at least one recessed region. The method also includes preferentially adsorbing a second additive to the field region. The substrate is then immersed into a plating bath to perform an electroplating procedure to electrodeposit copper onto the substrate. The preferentially adsorbed first and second additives cause copper to be electroplated into the recessed regions faster than copper is electrodeposited onto the field region.
  • [0009]
    In another aspect of the present invention, a method for electroplating a substrate is provided. The method includes immersing the substrate into a first tank that contains an electrolyte solution. The electrolyte solution includes a first additive and a second additive. The first additive is preferentially adsorbed onto surfaces of at least one recessed region formed in the substrate, and the second additive is preferentially adsorbed onto a field region of the substrate. The method further includes rinsing excess electrolyte solution from the substrate. After rinsing, the substrate is then immersed into a plating bath for an electroplating procedure, wherein the first additive provides less resistance to electrodeposition of copper than said second additive.
  • [0010]
    In yet another aspect of the present invention, an apparatus for electroplating a substrate having a field region and at least one recessed region formed therein is provided. The apparatus includes a first tank that contains a first additive. The substrate is immersed into the first tank to allow the first additive to be preferentially adsorbed onto the field region or onto surfaces of the at least one recessed region. The apparatus also includes a second tank that contains a second additive. The substrate is immersed into the second tank to allow the second additive to be preferentially adsorbed onto the other of the field region or onto the surfaces of a recessed region. The apparatus further includes a third tank that contains a plating bath. An anode plate is disposed within the plating bath. The substrate is operatively connectable to the anode plate to form an electrical circuit for an electroplating procedure.
  • [0011]
    In yet a further aspect of the present invention, an apparatus for electroplating a substrate having a field region and at least one recessed region formed therein is provided. The apparatus includes a spin-on mechanism configured to preferentially adsorb a first additive onto either the field region or the surfaces of the at least one recessed region. The spin-on mechanism is further configured to preferentially adsorb a second additive onto the other of the field region or the surfaces of the at least one recessed region. The apparatus also includes a tank containing a plating bath into which said substrate is immersable for an electroplating procedure. An anode plate is disposed within the plating bath. The anode plate is operatively connectable to the substrate through the plating bath to form an electrical circuit for performing an electroplating procedure.
  • [0012]
    Advantages of the present invention will become more apparent to those skilled in the art from the following description of the embodiments of the invention which have been shown and described by way of illustration. As will be realized, the invention is capable of other and different embodiments, and its details are capable of modification in various respects. Accordingly, the drawing(s) and description are to be regarded as illustrative in nature and not as restrictive.
  • BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS
  • [0013]
    FIG. 1 is a cross-sectional view of a substrate having two recessed regions;
  • [0014]
    FIG. 2 is an apparatus for a copper electroplating process with preferential adsorption;
  • [0015]
    FIG. 3 is another apparatus for a copper electroplating process with preferential adsorption;
  • [0016]
    FIG. 4 is an embodiment of a copper electroplating process with preferential adsorption;
  • [0017]
    FIG. 5 is another embodiment of a copper electroplating process with preferential adsorption;
  • [0018]
    FIG. 6 is yet another embodiment of a copper electroplating process with preferential adsorption; and
  • [0019]
    FIG. 7 is a schematic of an embodiment of a spin-on apparatus for a copper electroplating procedure.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • [0020]
    In processing semiconductor integrated circuits (“IC”), electroplating often utilizes an electrolyte solution containing copper ions and additives to deposit a layer of copper onto an exposed, electrically conductive surface. The electrically conductive surface may be a seed layer of copper formed by chemical vapor deposition (“CVD”) or physical vapor deposition (“PVD”) onto the surface of the substrate. The electrically conductive layer may be formed by direct plating using a specially formulated electrolyte of copper onto a barrier such as Tantalum Nitride (“TaN”), Tantalum (“Ta”), Titanium Nitride (“TiN), or Ruthenium (“Ru”). The additives assist in providing the deposited layer of copper with particular characteristics such as a smooth surface or a shiny appearance. For example, additives commonly used in copper electroplating include, but are not limited to, suppressors, accelerators, levelers, brighteners, grain refiners, wetting agents, and stress reducing agents. Some of these additives affect the rate of deposition during plating in different regions of the substrate depending upon the type of interaction between the additive and the surface of the substrate to which the additive is adsorbed. Once the copper layer has been electroplated, additional processing is performed on the electroplated surface including, but not limited to, etching and/or polishing to remove a portion of the electroplating deposited on the field region or to provide a more workable copper surface for further processing.
  • [0021]
    In an embodiment, the surface of the substrate being electroplated with copper is substantially flat. In another embodiment, the surface of the substrate being electroplated with copper includes at least one via or interconnect trench. The via or interconnect trench is a recessed structure extending from the surface of the substrate into the thickness thereof. The electroplating processes ideally fills the via or interconnect trench with solid copper without any voids that may adversely affect the conductive properties of the contact plug or interconnect that fills it.
  • [0022]
    Referring to FIG. 1, an exemplary section of a substrate 10 prior to an electrodeposition procedure is shown. The terms “semiconductor wafer,” “substrate,” and/or “wafer” as used herein refers to a substrate as it may exist in any of the various stages of the semiconductor fabrication process including, but not limited to, a bare substrate, as bare substrate having at least one recessed region formed therein, or a substrate having at least one dielectric layer formed upon the substrate in which one of the layers may include copper-filled vias or interconnects. It should be understood by one skilled in the art that the substrate may include multiple layers of dielectric formed therein, wherein the interconnects formed in the different layers are three-dimensionally connected by way of vias. In an embodiment, the substrate 10 is formed of silicon. It should be understood by one skilled in the art that the substrate can also be formed of any other material or compound. The illustrated substrate 10 includes a first recessed region 12 and a second recessed region 14, wherein the recessed regions 12, 14 extend into a portion of the thickness of the substrate 10 from the surface 16 of the substrate 10. The recessed regions 12, 14 being formed through a portion of the thickness of a single dielectric layer are for illustrative purposes only. It should be understood by one skilled in the art that the recessed regions 12, 14 may extend through a portion of a single layer, or, in the alternative, may extend through multiple layers. In the illustrated embodiment, the second recessed region 14 extends into the thickness of the substrate 10 a greater distance than the first recessed region 12, and the width of the opening of the second recessed region 14 is greater than the width of the opening of the first recessed region 12. However, it should be understood by one skilled in the art that the size of the opening and the depth of the illustrated recessed regions 12, 14 are exemplary only, and size of the opening of each recessed region 12, 14 is independent relative to the depth of the same recessed region 12, 14. In an embodiment of a substrate 10 having a plurality of recessed regions, each recessed region has the same sized opening and depth. In another embodiment of a substrate 10 having a plurality of recessed regions, at least one recessed region has a different sized opening and depth than the other recessed regions. The recessed regions 12, 14 may extend into the thickness of the substrate between about zero percent (0%) and one hundred percent (100%) of the thickness of the substrate. In an exemplary embodiment, a recessed region 12, 14 extends into the thickness of the substrate 10 between about five micrometers (5 μm) and about two hundred micrometers (200 μm). In an embodiment, the diameter of the opening of a recessed region 12, 14 is less than about one hundred microns (100 μm).
  • [0023]
    In an embodiment, a barrier layer 18 extends over the entire exposed surface of the recessed regions 12, 14. The barrier layer 18 may be formed of Tantalum/Tantalum-Nitride (Ta/TaN), Tantalum/Ruthenium (Ta/Ru), Titanium Nitride (TiN), or any other material or combination of materials sufficient to prevent diffusion of copper ions from the electroplated layer through the barrier layer 18 into the substrate 10 or any other layer adjacent to the barrier layer 18. A seed layer 20 is deposited onto the barrier layer 18. In an embodiment, the seed layer 20 is formed of copper sputtered onto the barrier layer 18. In another embodiment, the seed layer 20 is deposited onto the barrier layer 18 by way of atomic layer deposition (“ALD”) or any other method sufficient to provide a copper seed layer 20. In yet another embodiment, the seed layer is disposed onto the barrier layer using a specially formulated electrolyte. The field region 22 forms the upper surface of the substrate that extends between, and is adjacent to, the openings of the recessed regions 12, 14. It should be understood by one skilled in the art that the seed layer 20 is not necessary to perform an electroplating procedure. Instead, the electroplating procedure can deposit copper by direct plating onto the barrier layer or onto a seed layer.
  • [0024]
    The recessed regions, formed as vias and/or interconnect trenches, formed through the surface of the substrate provide empty volumes to be filled by a copper electroplating procedure. The recessed regions may be formed through a portion of the thickness of one layer, or the recessed regions may be formed through a portion of more than one layer, such as in three-dimensional integration. These recessed regions may vary in size and shape between each recessed region formed in the substrate. For example, one recessed region formed in a substrate may be a sub-micron-sized via having an opening being less that one micron (<1 μm) across the width of the opening. In another example, a recessed region formed in a substrate may have an opening being between at least one micron (1 μm) and about one hundred microns (100 μm) across the width of the opening. The substrate being electroplated may contain no recessed regions or any number of recessed regions formed therein. Each of the recessed regions may be formed having the same size and shape or each of the recessed regions may be formed having any of a variety of sizes and depths with respect to the other recessed regions formed in the substrate. For example, a recessed region formed through the surface of the substrate or dielectric layer may be very shallow; a recessed region may be formed through the entire thickness of the substrate or dielectric layer; a recessed region may be formed through the entire thickness of one or more dielectric layers; or a recessed region may be formed having any thickness therebetween.
  • [0025]
    A process of the present invention preferentially adsorbs user-determined additives to particular surfaces of the substrate to which a copper layer is later electroplated, wherein the preferential adsorption is performed prior to the substrate being immersed into an electrolyte solution in which an electroplating procedure is performed. Preferential adsorption, or selective adsorption, provides an improved process that causes user-determined additives to be adsorbed to specific regions of a substrate, whereby the selected additives affect the deposition on the particular region to which they are adsorbed during the electroplating procedure. For example, by preferentially adsorbing particular additives to particular surfaces or recessed regions of the substrate prior to an electroplating procedure, the amount of time to fill a recessed region formed in the substrate during electroplating and removing any deposited material on the field region can be substantially less than the amount of time required to fill the same recessed region and subsequently remove deposited material on the field region when previous electroplating techniques known in the art are used. The reduced time required to remove material deposited onto the field region after the electroplating procedure reduces subsequent processing costs. Additionally, by preferentially adsorbing particular additives to particular surfaces or recessed regions of the substrate prior to an electroplating procedure, the amount of copper deposited on the field regions of the substrate when the recessed regions are filled can be significantly less than the amount of copper deposited on the field regions when previous electroplating techniques known in the art are used.
  • [0026]
    The preferential adsorption process eliminates the need for additives to be added to the plating bath because the additives are adsorbed to the substrate prior to the substrate being immersed in the plating bath. While the preferential adsorption process eliminates the need for additives in the plating bath, it should be understood that any additives added to the plating bath to enhance the characteristics of the electrodeposited copper should be substantially non-reactive with respect to the anode plate such that the additives do not adversely affect the performance of the anode plate during an electroplating procedure. Additionally, because particular additives are preferentially adsorbed to the substrate prior to immersion into the electrolyte solution in which the electroplating procedure is performed, the membrane typically used to separate these particular additives from the anode plate is eliminated. Further, continuous sampling, testing, and adjusting the concentration of the particular additives in the electrolyte solution is no longer needed when the particular additives that previously adversely affected the performance of the plating bath, thereby eliminating the expenses associated with the machinery for sampling, testing, and adjusting the concentration of these particular additives in the electrolyte solution.
  • [0027]
    Preferential adsorption includes adsorbing at least one pre-determined additive onto a particular surface, or surfaces, of a substrate prior to the substrate being immersed into an electrolyte solution to be electroplated. It is commonly understood that leveler and suppressor additives typically include large polymeric molecules. When the leveler or suppressor additive molecules adsorb onto the surface of the substrate being processed by electroplating, the leveler and suppressor additive molecules create a relatively high resistance that tends to impede the charge transfer needed for electroplating, thereby substantially reducing the amount of copper electrodeposited onto the surface onto which the leveler or suppressor additive molecules are adsorbed. It is also commonly understood that accelerator additives consist of relatively small molecules, often having a diameter less than one micron (<1 μm). While the accelerator additive molecules also provide a resistance during the electroplating procedure, the resistance due to accelerator additive molecules adsorbed onto a surface is less than the resistance due to leveler or suppressor additive molecules adsorbed onto a similar surface. It is also generally understood that bonds between the nitrogen-containing leveler additive molecules and the copper seed layer are stronger relative to the bonds between sulfur-containing accelerator additive molecules and the copper seed layer. Accordingly, leveler additive molecules effectively displace accelerator additive molecules that may have been previously adsorbed onto a copper seed layer on a substrate.
  • [0028]
    For recessed regions with small sized openings, typically less than about one hundred micrometers (100 μm) in diameter, formed into a substrate, the leveler and suppressor additive molecules are generally too large to diffuse into the opening of the recessed region and instead adsorb onto the field region and the area immediately surrounding the opening of the recessed region, thereby creating a resistive film that impedes electrodeposition of copper onto the field regions surrounding the openings of the recessed regions. On the other hand, the accelerator additive molecules are small enough to diffuse through the small opening of the recessed regions and adsorb onto each surface of the recessed region, whereby the accelerator additive molecules provide less resistance to electrodeposition relative to the leveler additive molecules to aid in the bottom-up filling of the recessed region during the electroplating procedure. Accordingly, during the electroplating procedure, the recessed regions are quickly filled with copper while comparatively less copper is deposited onto the field regions of the substrate. In an exemplary embodiment, an electroplating procedure using a substrate having accelerator additive molecules preferentially adsorbed onto the surfaces of the recessed region and leveler and/or suppressor additive molecules preferentially adsorbed onto the field regions results in the recessed regions being completely filled with copper while a thin film of copper is deposited onto the field region surrounding a recessed region, wherein the thickness of the thin film is less than about forty percent (40%) of the diameter of the opening of the adjacent recessed region. It should be understood by one skilled in the art that the thickness of the copper film deposited on the field region using the preferential adsorption process provided herein should be significantly less relative to the thickness of the copper film deposited on the field region using electrodeposition procedures previously known in the art, thereby reducing the amount of subsequent processing of the substrate to remove the film of copper on the field regions.
  • [0029]
    The copper layer deposited onto the field regions by electroplating is generally removed in a subsequent etching or polishing step. The decreased copper deposited onto the field regions due to the preferential adsorption of large leveler additive molecules onto the field regions with respect to the increased copper deposited into the recessed regions due to the preferential adsorption of relatively small accelerator additive molecules onto the surfaces of the recessed regions reduces the additional costs of subsequent CMP processing of the substrate configured to remove the copper layer deposited on the field region.
  • [0030]
    One method for electroplating a layer of copper onto a substrate having at least one recessed region includes preferentially adsorbing at least one additive onto the substrate prior to immersion of the substrate into an electrolyte solution for copper deposition. In an embodiment, the substrate having at least one recessed region is immersed into a first tank 30, as illustrated in FIG. 2. The first tank 30 includes a solution containing at least one leveler additive and at least one accelerator additive. It should be understood by one skilled in the art that more than one type of accelerator additive can be preferentially adsorbed onto the surfaces of the recessed regions and more than one type of leveler additive can be preferentially adsorbed onto the field regions, but the exemplary embodiments provided herein describe preferentially adsorbing only one type of leveler additive onto the field regions and only one type of accelerator additive onto the surfaces of the recessed regions. The leveler/accelerator solution is continually agitated for equal distribution of the additives in the solution. In an embodiment, the concentration of the leveler additive is between about ten parts per million (10 ppm) and about five hundred parts per million (500 ppm), and the concentration of the accelerator additive is between about one hundred parts per million (100 ppm) and about one thousand parts per million (1000 ppm). In another embodiment, the concentration of the leveler additive is between about one hundred fifty parts per million (150 ppm) to about two hundred fifty parts per million (250 ppm), and the concentration of the accelerator additive is between about four hundred parts per million (400 ppm) and about six hundred parts per million (600 ppm). It should be understood that the ranges provided are exemplary, and that the amount of time it takes to preferentially adsorb sufficient amounts of the leveler and accelerator additives onto the substrate decreases as the concentration increases. The substrate remains immersed in the first tank 30 for a time sufficient to allow the leveler and accelerator additive molecules to adsorb to the seed layer formed on the substrate. In an exemplary embodiment, the substrate is immersed in the first tank for between about ten (10) seconds and about two hundred (200) seconds. It should be understood by one skilled in the art that the amount of time in which the substrate remains immersed in the first tank is dependent upon multiple factors including, but not limited to, concentration of the additives in the solution, surface area to which the additives are to be adsorbed, number of recessed regions formed in the substrate, and relative geometry of the recessed regions. In an embodiment, accelerator additive molecules are preferentially adsorbed onto the surfaces of the recessed regions and leveler additive molecules are preferentially adsorbed onto the field regions of the substrate.
  • [0031]
    Once the substrate is immersed in the first tank a sufficient amount of time to allow the additives to adsorb onto the field regions and onto the surfaces of the recessed regions of the substrate, the substrate is removed from the first tank 30 and placed into a second tank 32 to rinse the substrate, as shown in FIG. 2. In an embodiment, the second tank 32 includes de-ionized water (“DI water”) to remove any excess solution that remained on the substrate from the first tank 30. The second tank 32 may contain any fluid that allows the substrate to be rinsed while keeping the adsorbed additives on the substrate. After rinsing the substrate, the substrate is subsequently spun and dried. The rinse/spin/dry cycle may be performed once or multiple times to ensure excess additives are removed from the substrate. It should be understood by one skilled in the art that the drying procedure may not be necessary when the substrate is processed in an automated, robot-controlled tool.
  • [0032]
    Once the substrate is dry, the substrate having additives adsorbed onto the surface thereof is immersed into a third tank 34, as illustrated in FIG. 2. In an embodiment, the third tank 34 includes a plating bath, or an electrolyte solution, that contains copper ions, typically from copper sulfate (CuSO4), and an anode plate disposed within the solution. In another embodiment, the third tank 34 includes an electrolyte solution containing copper ions in addition to other additives to further enhance the performance of the electroplating procedure or to produce a particular copper finish, such as a suppressor additive or the like. In a further embodiment, the third tank 34 includes an electrolyte solution containing copper ions but does not include an accelerator additive. In yet another embodiment, the third tank 34 includes an electrolyte solution containing copper ions as well as a suppressor additive. It should be understood by one skilled in the art that any additives in the third tank 34 should not affect the performance of the plating bath, and a membrane should not be required to maintain a separation between the anode plate and the additive molecules such that no additional testing or sampling machinery is needed in order to maintain the concentration of the additives within the solution. While in the electrolyte solution, the substrate is operatively connected to an electrical circuit and a copper electroplating procedure is performed. The resulting copper deposit completely fills each of the recessed regions while depositing a very thin film of copper onto the field regions relative to the amount deposited in the recessed regions. It is preferable that the additives adsorbed onto the field regions of the substrate result in less copper deposit thereon while the additives adsorbed onto the surfaces of the recessed region allow the recessed region to be completely filled without voids during the electroplating procedure.
  • [0033]
    In another embodiment, as illustrated in FIG. 3, the substrate is immersed into a first tank 36. The first tank 36 includes a solution containing at least one leveler additive. The leveler additive-containing solution is continually agitated for equal distribution of the additive within the solution. It should be understood by one skilled in the art that the solution in the first tank 36 may also include another type of leveler additive, a suppressor additive, and/or any other additive to be preferentially adsorbed onto the field regions of the substrate to provide a greater resistance to electrodeposition on the field regions relative to the recessed regions. In an embodiment, the concentration of the leveler additive is between about ten parts per million (10 ppm) and about five hundred parts per million (500 ppm). In another embodiment, the concentration of the leveler additive is between about one hundred fifty parts per million (150 ppm) to about two hundred fifty parts per million (250 ppm). It should be understood that the ranges provided are exemplary, and that the amount of time it takes to preferentially adsorb the leveler additive molecules onto the substrate decreases as the concentration increases. The substrate remains immersed in the first tank 36 a sufficient amount of time to allow the leveler additive molecules to be preferentially adsorbed onto the field regions of the substrate.
  • [0034]
    The substrate is subsequently removed from the first tank 36 and immersed in a second tank 37 to be rinsed with DI water to remove un-adsorbed additive molecules, as illustrated in FIG. 3. It should be understood by one skilled in the art that the rinse could be done by immersion, cascade overflow, or any other manner of removing the un-adsorbed additive molecules. The substrate is then immersed in a third tank 38 that includes a solution containing at least one type of accelerator additive. It should be understood by one skilled in the art that the third tank 38 may also include other additives in addition to the accelerator additive, but the additional additives should not prevent the preferential adsorption of the accelerator additive molecules onto the surfaces of the recessed regions formed in the substrate. In an embodiment, the concentration of the accelerator additive is between about one hundred parts per million (100 ppm) and about one thousand parts per million (1000 ppm). In another embodiment, the concentration of the accelerator additive is between about four hundred parts per million (400 ppm) and about six hundred parts per million (600 ppm). It should be understood that the ranges provided are exemplary, and that the amount of time it takes to preferentially adsorb the accelerator additive molecules onto the substrate decreases as the concentration increases. The substrate remains immersed in the third tank 38 from between about ten (10) seconds and about two hundred (200) seconds. The substrate should remain immersed in the third tank 38 a sufficient amount of time to allow the accelerator additive molecules to adsorb onto the surfaces of the recessed regions. In an alternative embodiment, the substrate may be immersed in a first tank containing an accelerator additive for the preferential adsorption of accelerator additive molecules onto the surfaces of recessed regions prior to immersion into a second tank containing a leveler additive for the preferential adsorption of leveler additive molecules onto the field regions of the substrate. It should be understood by one skilled in the art that the substrate may be immersed in any number of tanks containing different additive-containing solutions provided that the process is configured to allow the accelerator additive molecules to be preferentially adsorbed onto the surfaces of each recessed region and leveler additive molecules to be preferentially adsorbed onto the field regions of the substrate.
  • [0035]
    After the substrate has been immersed in the first, second, and third tanks 36, 37, 38, the substrate is placed into a fourth tank 40 to rinse the substrate, as shown in FIG. 3. In an embodiment, the fourth tank 40 includes de-ionized water (“DI water”) to remove any excess solution or additives that were not adsorbed onto the substrate from the first, second, or third tanks 36, 37, 38. The fourth tank 40 may contain any fluid that allows the substrate to be rinsed while keeping the adsorbed additives on the substrate. After rinsing the substrate, the substrate is subsequently spun and dried. The rinse/spin/dry cycle may be performed once or multiple times to ensure excess additives are removed from the substrate. The second and fourth tanks 37, 40 are provided to rinse the substrate prior to being immersed in a subsequent tank to avoid cross-contamination of additives. It should be understood by one skilled in the art that the rinse could be done by immersion, cascade overflow, or any other manner removing the un-adsorbed additive molecules.
  • [0036]
    Once the substrate has been rinsed, the substrate is immersed into a fifth tank 42, as illustrated in FIG. 3. In an embodiment, the fifth tank 42 includes a plating bath, or an electrolyte solution, which contains copper ions, typically from copper sulfate (CUSO4), and an anode plate disposed within the solution. In another embodiment, the fifth tank 42 includes an electrolyte solution containing copper ions in addition to other additives configured to further enhance the electroplating procedure or to produce a particular copper finish. It should be understood by one skilled in the art that the additives in the fifth tank 42 should not affect the performance of the plating bath, and a membrane should not be necessary to maintain a separation between the anode plate and the additive molecules such that no additional testing or sampling machinery is needed in order to maintain the concentration of the additives within the solution. While in the electrolyte solution, the substrate is operatively connected to an electrical circuit and a copper electroplating procedure is performed. The resulting copper deposit completely fills each of the recessed regions while depositing very little, if any, copper onto the field regions of the substrate. It is preferable that the additives adsorbed onto the field regions of the substrate result in less copper deposit thereon while the additives adsorbed onto the surfaces of each recessed region enhances the deposition of copper in each recessed region to be completely filled during the electroplating procedure.
  • [0037]
    It should be understood by one skilled in the art that any number of tanks containing additives can be used to preferentially adsorb a specific additive molecules onto a substrate. It should also be understood by one skilled in the art that the substrate does not need to be dried prior to immersion into the plating bath for electroplating when the substrate is being processed in an automated tool.
  • [0038]
    In yet another embodiment, accelerator additive molecules are preferentially adsorbed onto the surfaces of the recessed regions formed in a substrate by a spin-on technique and leveler additive molecules are preferentially adsorbed onto the field regions of a substrate by a spin-on technique prior to the substrate being immersed in a plating bath. Spin-on techniques, commonly known in the art, include spinning a substrate while dispensing a small volume of solution onto the surface onto which the solution is to be adsorbed, thereby allowing the rotational forces to spread the solution across the entire surface of the substrate and into any recessed regions formed into the substrate. During a spin-on procedure, the substrate is generally rotated at a low speed while the solution is dispensed thereon. Once the solution is distributed across the surface of the substrate, the substrate is spun at a higher speed to remove the excess solution from the surface of the substrate.
  • [0039]
    FIG. 4 illustrates an embodiment of an electroplating process in which additives are preferentially adsorbed onto the substrate by spin-on procedures prior to being immersed into a plating bath for an electroplating procedure. In the first step 50, the substrate is subject to a spin-on procedure in which a small volume of solution containing a leveler additive is dispensed onto the surface of the substrate that is to be subsequently electroplated. The leveler solution is spun-on to preferentially adsorb the leveler additive molecules onto the field regions of the substrate. In the second step 51, the substrate is rinsed to remove the un-adsorbed leveler additive molecules. It should be understood by one skilled in the art that the rinse could be done by spin-on, immersion, cascade overflow, or any other manner of removing the un-adsorbed additive molecules. In the third step 52, the substrate is then subject to another spin-on procedure in which a small volume of solution containing an accelerator additive is dispensed onto the surface to which the leveler-containing solution was previously dispensed. The accelerator-containing solution is spun-on to preferentially adsorb the accelerator additive molecules onto the surfaces of the recessed regions formed into the substrate. In the fourth step 54, the substrate is rinsed with DI water to remove any excess solution that was not removed during the spin-on procedures. It should be understood by one skilled in the art that the rinse could be done by spin-on, immersion, cascade overflow, or any other manner of removing the un-adsorbed additive molecules. Finally, the fifth step 56 involves immersing the substrate into a plating bath for an electroplating procedure for electrodepositing a copper layer onto the substrate.
  • [0040]
    FIG. 5 illustrates another embodiment of an electroplating process in which additives are preferentially adsorbed onto the substrate by spin-on procedures prior to being immersed into a plating bath for an electroplating procedure. In the first step 58, the substrate is subject to a spin-on procedure in which a small volume of solution containing an accelerator additive is dispensed onto the surface of the substrate that is to be subsequently electroplated. The accelerator solution is spun-on to preferentially adsorb the accelerator additive molecules onto the surfaces of the recessed regions of the substrate. In the second step, 59, the substrate is then rinsed to remove the un-adsorbed accelerator molecules. It should be understood by one skilled in the art that the rinse could be done by spin-on, immersion, cascade overflow, or any other manner of removing the un-adsorbed additive molecules. In the third step 60, the substrate is then subject to another spin-on procedure in which a small volume of solution containing a leveler additive is dispensed onto the surface to which the accelerator-containing solution was previously dispensed. The leveler-containing solution is spun-on to preferentially adsorb the leveler additive molecules onto the field regions of the substrate. In the fourth step 62, the substrate is rinsed with DI water to remove any excess solution that was not removed during the spin-on procedures. It should be understood by one skilled in the art that the rinse could be done by spin-on, immersion, cascade overflow, or any other manner of removing the un-adsorbed additive molecules. Finally, the fifth step 64 involves immersing the substrate into a plating bath for an electroplating procedure for electrodepositing a copper layer onto the substrate.
  • [0041]
    It should be understood by one skilled in the art that the first spin-on procedure of the exemplary preferential adsorption processes illustrated in FIGS. 5 and 6 may include a solution containing a leveler additive, an accelerator additive, a suppressor additive, any combination thereof, or a combination including other additives to enhance the quality of copper deposition. It should also be understood by one skilled in the art that the first and/or second spin-on procedure may be repeated any number of times to ensure preferential adsorption of the additives onto the substrate. In an alternative embodiment, the preferential adsorption process may include a single spin-on procedure to preferentially adsorb accelerator additive molecules onto the surfaces of the recessed regions and adsorb leveler and/or suppressor additive molecules onto the field regions of the substrate.
  • [0042]
    FIG. 6 illustrates another embodiment of an electroplating process in which additives are preferentially adsorbed onto the substrate by spin-on procedures prior to being immersed into a plating bath for an electroplating procedure. In the first step 66, the substrate is subject to a spin-on procedure in which a small volume of solution containing an accelerator additive and a leveler additive is dispensed onto the surface of the substrate that is to be subsequently electroplated. The leveler/accelerator solution is spun-on such that the accelerator additive molecules are preferentially adsorbed onto the surfaces of the recessed regions of the substrate and the leveler additive molecules are preferentially adsorbed onto the field regions of the substrate. In the second step 68, the substrate is rinsed with DI water to remove any excess solution that was not removed during the spin-on procedures. Finally, the third step 70 involves immersing the substrate into a plating bath for an electroplating procedure for electrodepositing a copper layer onto the substrate.
  • [0043]
    It should be understood by one skilled in the art that the spin-on procedures use substantially less solution than immersing the substrate into tanks containing the additives. In alternative embodiments, the preferential adsorption procedures may include only immersion tanks, only spin-on procedures, or a combination thereof.
  • [0044]
    FIG. 7 illustrates an exemplary embodiment of an electroplating apparatus 100 for implementing the spin-on techniques discussed above. The electroplating apparatus 100 includes a spin-on mechanism 102 and a tank 104 spaced apart from the spin-on mechanism. In an embodiment, the spin-on mechanism 102 and the tank 104 are located within the same machine. In another embodiment, the spin-on mechanism 102 is disposed within a machine that is separate from the tank 104. The spin-on mechanism 102 includes a plate 106 configured to receive a substrate 108 to be processed. The plate 106 is connected to a shaft 109 that is operatively connected to a motor (not shown). The motor rotates the shaft 109, thereby rotating the plate 106 and substrate 108 in a corresponding manner. A dispensing mechanism 110 is located above the substrate 108. In an embodiment, the dispensing mechanism 110 is in fluid communication with a first reservoir 112 containing a first additive and a second reservoir 114 containing a second additive. It should be understood by one skilled in the art that the dispensing mechanism 110 can be in fluid communication with only one reservoir or a plurality of reservoirs containing additives or other fluids to be dispensed onto the substrate 108. The dispensing mechanism 110 is configured to dispense the first and second additives onto the surface of the substrate 108 as the substrate is rotated. Accordingly, the first and second additives are applied to the substrate 108 using a spin-on process. In one embodiment, the first additive is an accelerator and the second additive is a leveler, per the discussion of FIGS. 4-6 above. However, it should be understood by one skilled in the art that the first and second additives can be any additives to be preferentially adsorbed onto the surface of the substrate by the spin-on technique.
  • [0045]
    Prior to the substrate being transferred to the tank 104 for an electroplating procedure, the dispensing mechanism 110 rinses the substrate to remove the un-adsorbed additive molecules. In an embodiment, the dispensing mechanism 110 is in fluid communication with a DI water source 116, or the substrate can be rinsed in any other manner sufficient to remove any un-adsorbed additive molecules. It should be understood by one skilled in the art that the dispensing mechanism 110 can be configured to dispense each of the additives separately, or the dispensing mechanism 110 can be configured to dispense a combination of additives or other fluids in fluid communication therewith. It should also be understood by one skilled in the art that each additive can be in fluid communication with a separate dispensing mechanism 110 configured to dispense the particular additive onto the substrate 108 within the same spin-on mechanism 102.
  • [0046]
    Once the additives have been adsorbed onto the substrate 108 using a spin-on procedure, the substrate 108 is rinsed before being transported to the tank 104 for an electroplating procedure. As shown in FIG. 7, the tank 104 is filled with a plating bath 118. An anode plate 120 is immersed in the plating bath 118. It should be understood by one skilled in the art that more than one anode plate 120 may be immersed in the plating bath 118. It should also be understood by one skilled in the art that more than one substrate 108 may be processed simultaneously in the plating bath 118. In an embodiment, the plating bath 118 does not contain an accelerator additive. In another embodiment, the plating bath 118 includes a suppressor additive. The anode plate 120 is operatively connected to the substrate 108 to form an electrical circuit through the plating bath 118. The electroplating procedure is performed in the plating bath 118. Once the electroplating procedure has been performed, the substrate 108 is removed from the plating bath 118 and transferred from the electroplating apparatus 100 for further processing. It should be understood by one skilled in the art that the electroplating apparatus 100 can include any number of spin-on mechanisms 102 for preferentially adsorbing different additives onto the substrate 108.
  • [0047]
    The preferential adsorption of additives into the recessed regions and onto the field regions of a substrate provides film with a differential resistivity to charge transfer during the electrodeposition of copper therebetween. In the preferred embodiment, the additives preferentially adsorbed onto the surfaces of the recessed regions forming film that is less resistive to charge transfer during the electrodeposition relative to that film which is formed by additives preferentially adsorbed onto the surfaces of the field regions of the substrate. While the above embodiments are configured to preferentially adsorb accelerator additive molecules onto the recessed regions and leveler additive molecules onto the field regions, it should be understood by one skilled in the art that the additives adsorbed to the different regions in these embodiments illustrate the relative resistance in charge transfer between the different regions of the substrate being processed. The preferential adsorption provides a differential between the resistance to electrodeposition in the recessed region and the resistance to electrodeposition on the field regions. Any additives may be adsorbed onto the surfaces of the recessed regions and the field regions provided the resistance to electrodeposition on the field regions is greater than the resistance to electrodeposition in the recessed regions such that the recessed regions are filled quickly with less copper being deposited on the field regions during an electroplating procedure.
  • [0048]
    While preferred embodiments of the present invention have been described, it should be understood that the present invention is not so limited and modifications may be made without departing from the present invention. The scope of the present invention is defined by the appended claims, and all devices, process, and methods that come within the meaning of the claims, either literally or by equivalence, are intended to be embraced therein.

Claims (24)

1. A method for electroplating a substrate having a field region and at least one recessed region formed therein, said method comprising:
preferentially adsorbing a first additive to surfaces of said at least one recessed region;
preferentially adsorbing a second additive to said field region;
subsequently immersing said substrate into a plating bath; and
performing an electroplating procedure to deposit copper onto said substrate, wherein said preferentially adsorbed first and second additives cause copper to be electroplated into said at least one recessed region faster than copper is electroplated onto said field region.
2. The method of claim 1, wherein preferentially adsorbing said first additive includes immersing said substrate into a tank containing said first additive.
3. The method of claim 2, wherein preferentially adsorbing said second additive includes immersing said substrate into a second tank containing said second additive.
4. The method of claim 1, wherein preferentially adsorbing said first additive includes using a spin-on technique to distribute a first additive-containing solution over said substrate.
5. The method of claim 1, wherein preferentially adsorbing said second additive includes using a spin-on technique to distribute a second additive-containing solution over said substrate.
6. The method of claim 1, wherein said first additive is an accelerator.
7. The method of claim 1, wherein said second additive is a leveler.
8. The method of claim 1, wherein said plating bath includes copper sulfate (CuSO4).
9. The method of claim 8, wherein said plating bath further includes a suppressor additive.
10. The method of claim 8, wherein said plating bath does not include an accelerator additive.
11. The method of claim 1, wherein said substrate is rinsed with de-ionized water prior to being immersed in said plating bath and after preferentially adsorbing said first and second additives.
12. A method for electroplating a substrate comprising:
immersing said substrate into a first tank containing an electrolyte solution, said electrolyte solution including a first additive and a second additive, and said first additive is preferentially adsorbed onto surfaces of at least one recessed region formed in said substrate and said second additive is preferentially adsorbed onto a field region of said substrate;
rinsing excess of said electrolyte solution from said substrate; and
after rinsing, immersing said substrate into a plating bath for an electroplating procedure, wherein said first additive provides less resistance to electrodeposition of copper than said second additive.
13. The method of claim 12, wherein one of said at least one recessed region has an opening measuring less than one micrometer.
14. The method of claim 12, wherein one of said at least one recessed region has an opening measuring at least one micrometer.
15. The method of claim 12, wherein one of said at least one recessed region has an opening measuring less than one micrometer and a second of said at least one recessed region has an opening measuring at least one micrometer.
16. The method of claim 12, wherein said substrate is immersed in said first tank between about 10 seconds and about 200 seconds.
17. The method of claim 12, wherein said plating bath includes at least one additive different than said first additive and said second additive.
18. The method of claim 12 further comprising removing said electrodeposited layer from said field region.
19. An apparatus for electroplating a substrate having a field region and at least one recessed region formed therein, said apparatus comprising:
a first tank containing at least a first additive, wherein said substrate is immersable into said first tank, said first additive configured to be preferentially adsorbed onto one of said field region and surfaces of said at least one recessed region;
a second tank containing at least a second additive, wherein said substrate is immersable into said second tank, said second additive configured to be preferentially adsorbed onto the other of said field region and surfaces of said at least one recessed region; and
a third tank containing a plating bath into which said substrate is immersable for an electroplating procedure, wherein an anode plate is disposed within said plating bath, and said anode plate is operatively connectable to said substrate through said plating bath to form an electrical circuit for said electroplating procedure.
20. The apparatus of claim 19, wherein said first additive provides a film more resistive to electroplating than said second additive.
21. The apparatus of claim 19, wherein said first and second additives are configured to permit electroplating in said at least one recessed region at a faster rate than onto said field region.
22. The apparatus of claim 19, wherein said at least one recessed region has an opening diameter, and said first and second additives are configured such that electroplating produces a thin film on said field region having a thickness less than about 40% of said opening diameter.
23. An apparatus for electroplating a substrate having a field region and at least one recessed region formed therein, said apparatus comprising:
a spin-on mechanism configured to preferentially adsorb a first additive onto one of said field region and surfaces of said at least one recessed region and preferentially adsorb a second additive onto the other of said field region and surfaces of said at least one recessed region; and
a tank containing a plating bath into which said substrate is immersable for an electroplating procedure, wherein an anode plate is disposed within said plating bath, and said anode plate is operatively connectable to said substrate through said plating bath to form an electrical circuit for said electroplating procedure.
24. The apparatus of claim 23, wherein said spin-on mechanism is further configured to rinse said substrate prior to immersing said substrate into said tank.
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Citations (95)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US1416929A (en) * 1921-11-07 1922-05-23 William E Bailey Art of electrolysis
US2540602A (en) * 1946-07-03 1951-02-06 Lockheed Aircraft Corp Method and apparatus for the surface treatment of metals
US2708181A (en) * 1951-05-17 1955-05-10 Indiana Steel & Wire Company I Electroplating process
US2965556A (en) * 1959-04-15 1960-12-20 Struers Chemiske Lab H Apparatus for the electro-mechanical polishing of surfaces
US3328273A (en) * 1966-08-15 1967-06-27 Udylite Corp Electro-deposition of copper from acidic baths
US3448023A (en) * 1966-01-20 1969-06-03 Hammond Machinery Builders Inc Belt type electro-chemical (or electrolytic) grinding machine
US3595069A (en) * 1969-02-14 1971-07-27 Panametrics Ultrasonic sensing system
US4033833A (en) * 1975-10-30 1977-07-05 Western Electric Company, Inc. Method of selectively electroplating an area of a surface
US4808273A (en) * 1988-05-10 1989-02-28 Avantek, Inc. Method of forming completely metallized via holes in semiconductors
US4975159A (en) * 1988-10-24 1990-12-04 Schering Aktiengesellschaft Aqueous acidic bath for electrochemical deposition of a shiny and tear-free copper coating and method of using same
US4978639A (en) * 1989-01-10 1990-12-18 Avantek, Inc. Method for the simultaneous formation of via-holes and wraparound plating on semiconductor chips
US5055425A (en) * 1989-06-01 1991-10-08 Hewlett-Packard Company Stacked solid via formation in integrated circuit systems
US5084071A (en) * 1989-03-07 1992-01-28 International Business Machines Corporation Method of chemical-mechanical polishing an electronic component substrate and polishing slurry therefor
US5096550A (en) * 1990-10-15 1992-03-17 The United States Of America As Represented By The United States Department Of Energy Method and apparatus for spatially uniform electropolishing and electrolytic etching
US5151168A (en) * 1990-09-24 1992-09-29 Micron Technology, Inc. Process for metallizing integrated circuits with electrolytically-deposited copper
US5158860A (en) * 1990-11-01 1992-10-27 Shipley Company Inc. Selective metallization process
US5171412A (en) * 1991-08-23 1992-12-15 Applied Materials, Inc. Material deposition method for integrated circuit manufacturing
US5316974A (en) * 1988-12-19 1994-05-31 Texas Instruments Incorporated Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer
US5466161A (en) * 1993-10-01 1995-11-14 Bourns, Inc. Compliant stacking connector for printed circuit boards
US5516412A (en) * 1995-05-16 1996-05-14 International Business Machines Corporation Vertical paddle plating cell
US5558568A (en) * 1994-10-11 1996-09-24 Ontrak Systems, Inc. Wafer polishing machine with fluid bearings
US5641391A (en) * 1995-05-15 1997-06-24 Hunter; Ian W. Three dimensional microfabrication by localized electrodeposition and etching
US5681215A (en) * 1995-10-27 1997-10-28 Applied Materials, Inc. Carrier head design for a chemical mechanical polishing apparatus
US5714707A (en) * 1996-05-13 1998-02-03 Talon Manufacturing Company, Inc. Process and apparatus for demilitarization of small caliber primed cartridge cases
US5723387A (en) * 1996-07-22 1998-03-03 Industrial Technology Research Institute Method and apparatus for forming very small scale Cu interconnect metallurgy on semiconductor substrates
US5762544A (en) * 1995-10-27 1998-06-09 Applied Materials, Inc. Carrier head design for a chemical mechanical polishing apparatus
US5770095A (en) * 1994-07-12 1998-06-23 Kabushiki Kaisha Toshiba Polishing agent and polishing method using the same
US5773364A (en) * 1996-10-21 1998-06-30 Motorola, Inc. Method for using ammonium salt slurries for chemical mechanical polishing (CMP)
US5772833A (en) * 1993-11-20 1998-06-30 Tokyo Electron Limited Plasma etching apparatus
US5793272A (en) * 1996-08-23 1998-08-11 International Business Machines Corporation Integrated circuit toroidal inductor
US5862605A (en) * 1996-05-24 1999-01-26 Ebara Corporation Vaporizer apparatus
US5897375A (en) * 1997-10-20 1999-04-27 Motorola, Inc. Chemical mechanical polishing (CMP) slurry for copper and method of use in integrated circuit manufacture
US5911619A (en) * 1997-03-26 1999-06-15 International Business Machines Corporation Apparatus for electrochemical mechanical planarization
US5922091A (en) * 1997-05-16 1999-07-13 National Science Council Of Republic Of China Chemical mechanical polishing slurry for metallic thin film
US5976331A (en) * 1998-04-30 1999-11-02 Lucent Technologies Inc. Electrodeposition apparatus for coating wafers
US5985123A (en) * 1997-07-09 1999-11-16 Koon; Kam Kwan Continuous vertical plating system and method of plating
US6013948A (en) * 1995-11-27 2000-01-11 Micron Technology, Inc. Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US6066030A (en) * 1999-03-04 2000-05-23 International Business Machines Corporation Electroetch and chemical mechanical polishing equipment
US6071388A (en) * 1998-05-29 2000-06-06 International Business Machines Corporation Electroplating workpiece fixture having liquid gap spacer
US6090239A (en) * 1998-02-20 2000-07-18 Lsi Logic Corporation Method of single step damascene process for deposition and global planarization
US6121141A (en) * 1998-11-24 2000-09-19 Advanced Micro Devices, Inc. Method of forming a void free copper interconnects
US6217152B1 (en) * 1999-03-30 2001-04-17 Asahi Kogaku Kogyo Kabushiki Kaisha Film member for use in ink-transfer-type printer
US6245676B1 (en) * 1998-02-20 2001-06-12 Nec Corporation Method of electroplating copper interconnects
US6251236B1 (en) * 1998-11-30 2001-06-26 Applied Materials, Inc. Cathode contact ring for electrochemical deposition
US6251235B1 (en) * 1999-03-30 2001-06-26 Nutool, Inc. Apparatus for forming an electrical contact with a semiconductor substrate
US6268660B1 (en) * 1999-03-05 2001-07-31 International Business Machines Corporation Silicon packaging with through wafer interconnects
US20010015321A1 (en) * 1998-10-26 2001-08-23 Reid Jonathan D. Electroplating process for avoiding defects in metal features of integrated circuit devices
US6284121B1 (en) * 1997-10-08 2001-09-04 Novellus Systems, Inc. Electroplating system including additive for filling sub-micron features
US6287968B1 (en) * 1999-01-04 2001-09-11 Advanced Micro Devices, Inc. Method of defining copper seed layer for selective electroless plating processing
US6297140B1 (en) * 1998-01-09 2001-10-02 International Business Machines Corporation Method to plate C4 to copper stud
US6300250B1 (en) * 1999-08-09 2001-10-09 Taiwan Semiconductor Manufacturing Company Method of forming bumps for flip chip applications
US6303014B1 (en) * 1998-10-14 2001-10-16 Faraday Technology Marketing Group, Llc Electrodeposition of metals in small recesses using modulated electric fields
US6315883B1 (en) * 1998-10-26 2001-11-13 Novellus Systems, Inc. Electroplanarization of large and small damascene features using diffusion barriers and electropolishing
US6319831B1 (en) * 1999-03-18 2001-11-20 Taiwan Semiconductor Manufacturing Company Gap filling by two-step plating
US6319384B1 (en) * 1998-10-14 2001-11-20 Faraday Technology Marketing Group, Llc Pulse reverse electrodeposition for metallization and planarization of semiconductor substrates
US6334937B1 (en) * 1998-12-31 2002-01-01 Semitool, Inc. Apparatus for high deposition rate solder electroplating on a microelectronic workpiece
US6346479B1 (en) * 2000-06-14 2002-02-12 Advanced Micro Devices, Inc. Method of manufacturing a semiconductor device having copper interconnects
US6402925B2 (en) * 1998-11-03 2002-06-11 Nutool, Inc. Method and apparatus for electrochemical mechanical deposition
US6413403B1 (en) * 2000-02-23 2002-07-02 Nutool Inc. Method and apparatus employing pad designs and structures with improved fluid distribution
US6433402B1 (en) * 2000-11-16 2002-08-13 Advanced Micro Devices, Inc. Selective copper alloy deposition
US6458696B1 (en) * 2001-04-11 2002-10-01 Agere Systems Guardian Corp Plated through hole interconnections
US6482656B1 (en) * 2001-06-04 2002-11-19 Advanced Micro Devices, Inc. Method of electrochemical formation of high Tc superconducting damascene interconnect for integrated circuit
US6506103B1 (en) * 1999-07-23 2003-01-14 Riken ELID centerless grinding apparatus
US20030015435A1 (en) * 2000-05-11 2003-01-23 Rimma Volodarsky Anode assembly for plating and planarizing a conductive layer
US20030038038A1 (en) * 2001-07-20 2003-02-27 Basol Bulent M. Multi step electrodeposition process for reducing defects and minimizing film thickness
US6548395B1 (en) * 2000-11-16 2003-04-15 Advanced Micro Devices, Inc. Method of promoting void free copper interconnects
US20030089986A1 (en) * 2001-11-13 2003-05-15 Daniele Gilkes Microelectronic device layer deposited with multiple electrolytes
US6566259B1 (en) * 1997-12-02 2003-05-20 Applied Materials, Inc. Integrated deposition process for copper metallization
US20030119311A1 (en) * 2001-07-20 2003-06-26 Basol Bulent M. Planar metal electroprocessing
US6599778B2 (en) * 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
US6610190B2 (en) * 2000-11-03 2003-08-26 Nutool, Inc. Method and apparatus for electrodeposition of uniform film with minimal edge exclusion on substrate
US6620725B1 (en) * 1999-09-13 2003-09-16 Taiwan Semiconductor Manufacturing Company Reduction of Cu line damage by two-step CMP
US6638411B1 (en) * 1999-01-26 2003-10-28 Ebara Corporation Method and apparatus for plating substrate with copper
US6653226B1 (en) * 2001-01-09 2003-11-25 Novellus Systems, Inc. Method for electrochemical planarization of metal surfaces
US20040012090A1 (en) * 2002-07-22 2004-01-22 Basol Bulent M. Defect-free thin and planar film processing
US6709970B1 (en) * 2002-09-03 2004-03-23 Samsung Electronics Co., Ltd. Method for creating a damascene interconnect using a two-step electroplating process
US6709565B2 (en) * 1998-10-26 2004-03-23 Novellus Systems, Inc. Method and apparatus for uniform electropolishing of damascene ic structures by selective agitation
US6750144B2 (en) * 2002-02-15 2004-06-15 Faraday Technology Marketing Group, Llc Method for electrochemical metallization and planarization of semiconductor substrates having features of different sizes
US6756307B1 (en) * 1999-10-05 2004-06-29 Novellus Systems, Inc. Apparatus for electrically planarizing semiconductor wafers
US6762076B2 (en) * 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6846725B2 (en) * 2002-10-17 2005-01-25 Institute Of Microelectronics Wafer-level package for micro-electro-mechanical systems
US6852627B2 (en) * 2003-03-05 2005-02-08 Micron Technology, Inc. Conductive through wafer vias
US6887795B2 (en) * 2000-05-15 2005-05-03 Asm International N.V. Method of growing electrical conductors
US6897148B2 (en) * 2003-04-09 2005-05-24 Tru-Si Technologies, Inc. Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby
US6924224B2 (en) * 2002-10-03 2005-08-02 International Business Machines Corporation Method of forming filled blind vias
US6965045B2 (en) * 2001-12-28 2005-11-15 Samsung Electronics Co., Ltd. Organic metal precursor for use in forming metal containing patterned films
US20060003566A1 (en) * 2004-06-30 2006-01-05 Ismail Emesh Methods and apparatuses for semiconductor fabrication utilizing through-wafer interconnects
US7019402B2 (en) * 2003-10-17 2006-03-28 International Business Machines Corporation Silicon chip carrier with through-vias using laser assisted chemical vapor deposition of conductor
US7067407B2 (en) * 2003-08-04 2006-06-27 Asm International, N.V. Method of growing electrical conductors
US7211174B2 (en) * 2001-01-17 2007-05-01 Novellus Systems, Inc. Method and system to provide electrical contacts for electrotreating processes
US7211186B2 (en) * 2001-01-17 2007-05-01 Novellus Systems, Inc. Method and system to provide electrical contacts for electrotreating processes
US7404886B2 (en) * 2000-08-10 2008-07-29 Novellus Systems, Inc. Plating by creating a differential between additives disposed on a surface portion and a cavity portion of a workpiece
US20080277867A1 (en) * 2007-05-08 2008-11-13 Canon Kabushiki Kaisha Sheet stacking apparatus and sheet stacking control method
US7479213B2 (en) * 2003-12-25 2009-01-20 Ebara Corporation Plating method and plating apparatus
US7615141B2 (en) * 2003-10-03 2009-11-10 University Of Washington Electrochemical micromanufacturing system and method

Patent Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US1416929A (en) * 1921-11-07 1922-05-23 William E Bailey Art of electrolysis
US2540602A (en) * 1946-07-03 1951-02-06 Lockheed Aircraft Corp Method and apparatus for the surface treatment of metals
US2708181A (en) * 1951-05-17 1955-05-10 Indiana Steel & Wire Company I Electroplating process
US2965556A (en) * 1959-04-15 1960-12-20 Struers Chemiske Lab H Apparatus for the electro-mechanical polishing of surfaces
US3448023A (en) * 1966-01-20 1969-06-03 Hammond Machinery Builders Inc Belt type electro-chemical (or electrolytic) grinding machine
US3328273A (en) * 1966-08-15 1967-06-27 Udylite Corp Electro-deposition of copper from acidic baths
US3595069A (en) * 1969-02-14 1971-07-27 Panametrics Ultrasonic sensing system
US4033833A (en) * 1975-10-30 1977-07-05 Western Electric Company, Inc. Method of selectively electroplating an area of a surface
US4808273A (en) * 1988-05-10 1989-02-28 Avantek, Inc. Method of forming completely metallized via holes in semiconductors
US4975159A (en) * 1988-10-24 1990-12-04 Schering Aktiengesellschaft Aqueous acidic bath for electrochemical deposition of a shiny and tear-free copper coating and method of using same
US5316974A (en) * 1988-12-19 1994-05-31 Texas Instruments Incorporated Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer
US4978639A (en) * 1989-01-10 1990-12-18 Avantek, Inc. Method for the simultaneous formation of via-holes and wraparound plating on semiconductor chips
US5084071A (en) * 1989-03-07 1992-01-28 International Business Machines Corporation Method of chemical-mechanical polishing an electronic component substrate and polishing slurry therefor
US5055425A (en) * 1989-06-01 1991-10-08 Hewlett-Packard Company Stacked solid via formation in integrated circuit systems
US5151168A (en) * 1990-09-24 1992-09-29 Micron Technology, Inc. Process for metallizing integrated circuits with electrolytically-deposited copper
US5096550A (en) * 1990-10-15 1992-03-17 The United States Of America As Represented By The United States Department Of Energy Method and apparatus for spatially uniform electropolishing and electrolytic etching
US5158860A (en) * 1990-11-01 1992-10-27 Shipley Company Inc. Selective metallization process
US5171412A (en) * 1991-08-23 1992-12-15 Applied Materials, Inc. Material deposition method for integrated circuit manufacturing
US5466161A (en) * 1993-10-01 1995-11-14 Bourns, Inc. Compliant stacking connector for printed circuit boards
US5772833A (en) * 1993-11-20 1998-06-30 Tokyo Electron Limited Plasma etching apparatus
US5770095A (en) * 1994-07-12 1998-06-23 Kabushiki Kaisha Toshiba Polishing agent and polishing method using the same
US5558568A (en) * 1994-10-11 1996-09-24 Ontrak Systems, Inc. Wafer polishing machine with fluid bearings
US5641391A (en) * 1995-05-15 1997-06-24 Hunter; Ian W. Three dimensional microfabrication by localized electrodeposition and etching
US5516412A (en) * 1995-05-16 1996-05-14 International Business Machines Corporation Vertical paddle plating cell
US5762544A (en) * 1995-10-27 1998-06-09 Applied Materials, Inc. Carrier head design for a chemical mechanical polishing apparatus
US5681215A (en) * 1995-10-27 1997-10-28 Applied Materials, Inc. Carrier head design for a chemical mechanical polishing apparatus
US6013948A (en) * 1995-11-27 2000-01-11 Micron Technology, Inc. Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US5714707A (en) * 1996-05-13 1998-02-03 Talon Manufacturing Company, Inc. Process and apparatus for demilitarization of small caliber primed cartridge cases
US5862605A (en) * 1996-05-24 1999-01-26 Ebara Corporation Vaporizer apparatus
US5723387A (en) * 1996-07-22 1998-03-03 Industrial Technology Research Institute Method and apparatus for forming very small scale Cu interconnect metallurgy on semiconductor substrates
US5793272A (en) * 1996-08-23 1998-08-11 International Business Machines Corporation Integrated circuit toroidal inductor
US5773364A (en) * 1996-10-21 1998-06-30 Motorola, Inc. Method for using ammonium salt slurries for chemical mechanical polishing (CMP)
US5911619A (en) * 1997-03-26 1999-06-15 International Business Machines Corporation Apparatus for electrochemical mechanical planarization
US5922091A (en) * 1997-05-16 1999-07-13 National Science Council Of Republic Of China Chemical mechanical polishing slurry for metallic thin film
US5985123A (en) * 1997-07-09 1999-11-16 Koon; Kam Kwan Continuous vertical plating system and method of plating
US6284121B1 (en) * 1997-10-08 2001-09-04 Novellus Systems, Inc. Electroplating system including additive for filling sub-micron features
US5897375A (en) * 1997-10-20 1999-04-27 Motorola, Inc. Chemical mechanical polishing (CMP) slurry for copper and method of use in integrated circuit manufacture
US6566259B1 (en) * 1997-12-02 2003-05-20 Applied Materials, Inc. Integrated deposition process for copper metallization
US6297140B1 (en) * 1998-01-09 2001-10-02 International Business Machines Corporation Method to plate C4 to copper stud
US6245676B1 (en) * 1998-02-20 2001-06-12 Nec Corporation Method of electroplating copper interconnects
US6090239A (en) * 1998-02-20 2000-07-18 Lsi Logic Corporation Method of single step damascene process for deposition and global planarization
US5976331A (en) * 1998-04-30 1999-11-02 Lucent Technologies Inc. Electrodeposition apparatus for coating wafers
US6071388A (en) * 1998-05-29 2000-06-06 International Business Machines Corporation Electroplating workpiece fixture having liquid gap spacer
US6319384B1 (en) * 1998-10-14 2001-11-20 Faraday Technology Marketing Group, Llc Pulse reverse electrodeposition for metallization and planarization of semiconductor substrates
US6303014B1 (en) * 1998-10-14 2001-10-16 Faraday Technology Marketing Group, Llc Electrodeposition of metals in small recesses using modulated electric fields
US6793796B2 (en) * 1998-10-26 2004-09-21 Novellus Systems, Inc. Electroplating process for avoiding defects in metal features of integrated circuit devices
US20010015321A1 (en) * 1998-10-26 2001-08-23 Reid Jonathan D. Electroplating process for avoiding defects in metal features of integrated circuit devices
US6709565B2 (en) * 1998-10-26 2004-03-23 Novellus Systems, Inc. Method and apparatus for uniform electropolishing of damascene ic structures by selective agitation
US6315883B1 (en) * 1998-10-26 2001-11-13 Novellus Systems, Inc. Electroplanarization of large and small damascene features using diffusion barriers and electropolishing
US6402925B2 (en) * 1998-11-03 2002-06-11 Nutool, Inc. Method and apparatus for electrochemical mechanical deposition
US6676822B1 (en) * 1998-11-03 2004-01-13 Nutool, Inc. Method for electro chemical mechanical deposition
US6121141A (en) * 1998-11-24 2000-09-19 Advanced Micro Devices, Inc. Method of forming a void free copper interconnects
US6251236B1 (en) * 1998-11-30 2001-06-26 Applied Materials, Inc. Cathode contact ring for electrochemical deposition
US6334937B1 (en) * 1998-12-31 2002-01-01 Semitool, Inc. Apparatus for high deposition rate solder electroplating on a microelectronic workpiece
US6287968B1 (en) * 1999-01-04 2001-09-11 Advanced Micro Devices, Inc. Method of defining copper seed layer for selective electroless plating processing
US6638411B1 (en) * 1999-01-26 2003-10-28 Ebara Corporation Method and apparatus for plating substrate with copper
US6066030A (en) * 1999-03-04 2000-05-23 International Business Machines Corporation Electroetch and chemical mechanical polishing equipment
US6268660B1 (en) * 1999-03-05 2001-07-31 International Business Machines Corporation Silicon packaging with through wafer interconnects
US6319831B1 (en) * 1999-03-18 2001-11-20 Taiwan Semiconductor Manufacturing Company Gap filling by two-step plating
US6251235B1 (en) * 1999-03-30 2001-06-26 Nutool, Inc. Apparatus for forming an electrical contact with a semiconductor substrate
US6217152B1 (en) * 1999-03-30 2001-04-17 Asahi Kogaku Kogyo Kabushiki Kaisha Film member for use in ink-transfer-type printer
US6506103B1 (en) * 1999-07-23 2003-01-14 Riken ELID centerless grinding apparatus
US6300250B1 (en) * 1999-08-09 2001-10-09 Taiwan Semiconductor Manufacturing Company Method of forming bumps for flip chip applications
US6620725B1 (en) * 1999-09-13 2003-09-16 Taiwan Semiconductor Manufacturing Company Reduction of Cu line damage by two-step CMP
US6756307B1 (en) * 1999-10-05 2004-06-29 Novellus Systems, Inc. Apparatus for electrically planarizing semiconductor wafers
US6413403B1 (en) * 2000-02-23 2002-07-02 Nutool Inc. Method and apparatus employing pad designs and structures with improved fluid distribution
US20020130034A1 (en) * 2000-02-23 2002-09-19 Nutool Inc. Pad designs and structures for a versatile materials processing apparatus
US20030015435A1 (en) * 2000-05-11 2003-01-23 Rimma Volodarsky Anode assembly for plating and planarizing a conductive layer
US6887795B2 (en) * 2000-05-15 2005-05-03 Asm International N.V. Method of growing electrical conductors
US6346479B1 (en) * 2000-06-14 2002-02-12 Advanced Micro Devices, Inc. Method of manufacturing a semiconductor device having copper interconnects
US7404886B2 (en) * 2000-08-10 2008-07-29 Novellus Systems, Inc. Plating by creating a differential between additives disposed on a surface portion and a cavity portion of a workpiece
US6610190B2 (en) * 2000-11-03 2003-08-26 Nutool, Inc. Method and apparatus for electrodeposition of uniform film with minimal edge exclusion on substrate
US6433402B1 (en) * 2000-11-16 2002-08-13 Advanced Micro Devices, Inc. Selective copper alloy deposition
US6548395B1 (en) * 2000-11-16 2003-04-15 Advanced Micro Devices, Inc. Method of promoting void free copper interconnects
US6653226B1 (en) * 2001-01-09 2003-11-25 Novellus Systems, Inc. Method for electrochemical planarization of metal surfaces
US7211186B2 (en) * 2001-01-17 2007-05-01 Novellus Systems, Inc. Method and system to provide electrical contacts for electrotreating processes
US7211174B2 (en) * 2001-01-17 2007-05-01 Novellus Systems, Inc. Method and system to provide electrical contacts for electrotreating processes
US6458696B1 (en) * 2001-04-11 2002-10-01 Agere Systems Guardian Corp Plated through hole interconnections
US6482656B1 (en) * 2001-06-04 2002-11-19 Advanced Micro Devices, Inc. Method of electrochemical formation of high Tc superconducting damascene interconnect for integrated circuit
US20030038038A1 (en) * 2001-07-20 2003-02-27 Basol Bulent M. Multi step electrodeposition process for reducing defects and minimizing film thickness
US20030119311A1 (en) * 2001-07-20 2003-06-26 Basol Bulent M. Planar metal electroprocessing
US20030089986A1 (en) * 2001-11-13 2003-05-15 Daniele Gilkes Microelectronic device layer deposited with multiple electrolytes
US6856025B2 (en) * 2001-12-19 2005-02-15 International Business Machines Corporation Chip and wafer integration process using vertical connections
US6599778B2 (en) * 2001-12-19 2003-07-29 International Business Machines Corporation Chip and wafer integration process using vertical connections
US6965045B2 (en) * 2001-12-28 2005-11-15 Samsung Electronics Co., Ltd. Organic metal precursor for use in forming metal containing patterned films
US6750144B2 (en) * 2002-02-15 2004-06-15 Faraday Technology Marketing Group, Llc Method for electrochemical metallization and planarization of semiconductor substrates having features of different sizes
US6762076B2 (en) * 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US20040012090A1 (en) * 2002-07-22 2004-01-22 Basol Bulent M. Defect-free thin and planar film processing
US6709970B1 (en) * 2002-09-03 2004-03-23 Samsung Electronics Co., Ltd. Method for creating a damascene interconnect using a two-step electroplating process
US6924224B2 (en) * 2002-10-03 2005-08-02 International Business Machines Corporation Method of forming filled blind vias
US6846725B2 (en) * 2002-10-17 2005-01-25 Institute Of Microelectronics Wafer-level package for micro-electro-mechanical systems
US6852627B2 (en) * 2003-03-05 2005-02-08 Micron Technology, Inc. Conductive through wafer vias
US6897148B2 (en) * 2003-04-09 2005-05-24 Tru-Si Technologies, Inc. Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby
US7067407B2 (en) * 2003-08-04 2006-06-27 Asm International, N.V. Method of growing electrical conductors
US7615141B2 (en) * 2003-10-03 2009-11-10 University Of Washington Electrochemical micromanufacturing system and method
US7019402B2 (en) * 2003-10-17 2006-03-28 International Business Machines Corporation Silicon chip carrier with through-vias using laser assisted chemical vapor deposition of conductor
US7479213B2 (en) * 2003-12-25 2009-01-20 Ebara Corporation Plating method and plating apparatus
US20060003566A1 (en) * 2004-06-30 2006-01-05 Ismail Emesh Methods and apparatuses for semiconductor fabrication utilizing through-wafer interconnects
US20080277867A1 (en) * 2007-05-08 2008-11-13 Canon Kabushiki Kaisha Sheet stacking apparatus and sheet stacking control method

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