US20080277790A1 - Semiconductor Device - Google Patents

Semiconductor Device Download PDF

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US20080277790A1
US20080277790A1 US12166267 US16626708A US2008277790A1 US 20080277790 A1 US20080277790 A1 US 20080277790A1 US 12166267 US12166267 US 12166267 US 16626708 A US16626708 A US 16626708A US 2008277790 A1 US2008277790 A1 US 2008277790A1
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thin
gas
film
layer
tasin
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Han-Choon Lee
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Han-Choon Lee
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846Layer combinations
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562Selective deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855After-treatment introducing at least one additional element into the layer
    • H01L21/76856After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76862Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device having a semiconductor substrate, an interlayer insulating layer formed on the substrate and having a contact hole partially exposing the substrate, and a diffusion barrier formed on the interlayer insulating layer and in the contact hole. The diffusion barrier comprises a plurality of TaSiN thin films. The present invention advantageously provides a semiconductor device with enhanced step coverage and reduced resistivity of a TaSiN layer.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • [0001]
    This application is a divisional of U.S. patent application Ser. No. 11/177,921 (Attorney Docket No. OPP-GZ-2007-0240-US-00), filed Jul. 8, 2005, the contents of which are hereby incorporated by reference. This application also claims priority to and the benefit of Korean Patent Application 10-2004-0053388, filed in the Korean Intellectual Property Office on Jul. 9, 2004, the contents of which are hereby incorporated by reference.
  • BACKGROUND OF THE INVENTION
  • [0002]
    (a) Field of the Invention
  • [0003]
    The present invention relates to a semiconductor device and a method for manufacturing the same. More particularly, the present invention relates to a diffusion barrier that blocks diffusion of metal from a metal line and a method for forming such a diffusion barrier.
  • [0004]
    (b) Description of the Related Art
  • [0005]
    During a process of manufacturing a semiconductor device, a diffusion barrier is frequently formed on an interior wall of a hole such as a contact hole or a via hole, in order to prevent diffusion of a metal such as copper from a metal line into silicon and/or an oxide.
  • [0006]
    Group-II nitrides such as tantalum nitride (TaN), in which nitrogen (N) is contained in a refractory metal such as tantalum (Ta), or group-III nitrides, such as tantalum-silicon-nitride (TaSiN) containing N and silicon (Si) together with Ta, may be used for the diffusion barrier. Among the two groups of nitrides, the group-III nitride containing Si shows better performance.
  • [0007]
    In addition, a TaSiN layer is generally easily deposited, since it is usually deposited by a physical vapor deposition (PVD) method. On the other hand, the TaSiN layer formed by the PVD method shows poor step coverage for a contact hole of a high aspect ratio. In addition, sufficient (poly)silicon remains such that, when PVD TaSiN is used as a diffusion barrier for a copper line, the copper may easily diffuse to form a copper-silicon compound or alloy (CuSi) at the interface of the TaSiN layer and the copper line layer.
  • [0008]
    For such a reasons, research and investigations are conducted into forming the TaSiN layer by chemical vapor deposition (CVD), which may provide better step coverage and a (more) amorphous state for the TaSiN layer. However, according to the CVD method, the substrate has to be heated to a temperature higher than 600° C. in order to obtain a sufficient reaction between the Ta precursor and the other reaction gas(es). Therefore, the method necessarily involves a high temperature, resulting in an increase in surface roughness of the layer, and in particular, a decrease in layer density, thereby causing an agglomeration phenomenon during thermal processing.
  • [0009]
    In addition, due to various residual atoms or other materials included in the Ta precursor, an undesirable amount of impurities may be included in the layer during its deposition, thereby increasing the resistivity of the TaSiN layer.
  • [0010]
    The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention, and therefore, it may contain information that does not form prior art or other information that may be already known to others in this country.
  • SUMMARY OF THE INVENTION
  • [0011]
    The present invention has been made in an effort to provide a semiconductor device having an enhanced diffusion barrier and a manufacturing method thereof.
  • [0012]
    An exemplary semiconductor device according to an aspect of the present invention includes: a semiconductor substrate; an interlayer insulating layer on the substrate and having a contact hole therein partially exposing the substrate; and a diffusion barrier on interlayer insulating layer and in the contact hole, comprising a plurality of TaSiN thin films. The TaSiN thin film may be formed by a reaction of a silicon source gas with an impurity-removed TaN thin film.
  • [0013]
    An exemplary method for manufacturing a semiconductor device according to another aspect of the present invention includes: (a) forming an interlayer insulating layer on a semiconductor substrate, the interlayer insulating layer having a contact hole that partially exposes the substrate; (b) depositing a TaN thin film on the interlayer insulating layer and in the contact hole using a reaction gas containing a Ta precursor and a nitrogen source gas; (c) removing impurities from the TaN thin film; (d) forming a TaSiN thin film by reacting the impurity-removed TaN thin film with a silicon source gas, and (e) repeating steps (a) and (b) at least once to form a diffusion barrier comprising a plurality of TaSiN thin films. In one embodiment, the diffusion barrier (or the TaN thin film) may be formed by an ALD method.
  • [0014]
    In various other embodiments, the Ta precursor may comprise tertbutylimido(trisdiethylamide)tantalum (TBTDET), pentakis(diethylamide)tantalum (PDEAT), pentakis(dimethylamide)tantalum (PDMAT), or pentakis(ethylmethyl-amino)tantalum (PEMAT); NH3 or N2 gas may be used as the nitrogen source gas; step (b) of the method may further comprise heating the substrate a temperature of 170 to 500° C.; in step (c) of the method, the impurities may be removed by plasma processing using a hydrogen containing gas, such as H2, H2+N2 or NH3; the plasma processing may comprise applying a plasma power of 100-400W for 3 to 35 seconds; and/or the silicon source gas may comprise a silane, such as SiH4.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0015]
    FIG. 1A to FIG. 1E are sectional views showing sequential stages of a method for forming a diffusion barrier according to an exemplary embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE EMBODIMENTS
  • [0016]
    An embodiment of the present invention will hereinafter be described in detail with reference to the accompanying drawings.
  • [0017]
    Firstly, a diffusion barrier of a semiconductor device according to an exemplary embodiment of the present invention will hereinafter be described with reference to FIG. 1E.
  • [0018]
    As shown in FIG. 1E, an interlayer insulating layer 11 is formed on a semiconductor substrate 10 such that the substrate 10 may be partially exposed through a contact hole (reference 12 in FIG. 1A). A diffusion barrier 100 composed of multiple layers (i.e., at least two layers, for example, three layers) of TaSiN thin films 14 a, 14 b, and 14 c, is formed on the interlayer insulating layer 11, including in the contact hole 12.
  • [0019]
    In one embodiment, one or more layers of the diffusion barrier 100 is formed by an atomic layer deposition (ALD) method, wherein the respective TaSiN thin films 14 a, 14 b, and 14 c may comprise the reaction product(s) of an impurity-removed TaN thin film and a silicon (Si) source gas. In one implementation, all of the layers of the diffusion barrier 100 comprise atomic layer deposited (ALD) TaSiN. The silicon source gas may comprise a silane of the formula SixHy, where x is an integer of from 1 to 4 and y is 2x+2, and when x is 3 or 4, y may be 2x. In a preferred embodiment, the silicon source gas comprises SiH4.
  • [0020]
    In addition, the impurity-removed TaN thin film may comprise a plasma processed TaN thin film. In one embodiment, the TaN thin film is processed with a plasma comprising a mixture of a hydrogen (H) containing gas and a noble gas. The hydrogen-containing gas may comprise H2, H2+N2 or NH3, and the noble gas may comprise He, Ne, Ar, Xe, or Kr (preferably Ar). The TaN thin film may have a thickness, for example, in a range of from 2 to 100 Å.
  • [0021]
    Hereinafter, a method for forming a diffusion barrier according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 1A to FIG. 1E.
  • [0022]
    As shown in FIG. 1A, the interlayer insulating layer 11 is deposited on the semiconductor substrate 10, and then a contact hole 12 for partially exposing the substrate 10 is formed by patterning the interlayer insulating layer 11 by conventional photolithography and etching.
  • [0023]
    In the stage shown in FIG. 1B, a TaN thin film 13 is deposited on the interlayer insulating layer 11 and in the contact hole 12 at a thickness of 2 to 100 Å, preferably by the ALD method. In the ALD method, reaction gases including a Ta precursor and a nitrogen source gas are injected into a chamber, and then the substrate is heated to a temperature controlled between 170 and 500° C. The Ta precursor may comprise a tantalum compound of the formula Ta(NR2)5 or R′N=Ta(NR2)3, where R and R′ are independently an alkyl, cycloalkyl, alkenyl, cycloalkenyl, or aryl group. Preferably, R is C1-C4 n-alkyl, and R′ is C1-C6 branched alkyl. More specifically, the Ta precursor may comprise one or more members of the group consisting of tert-butylimido(trisdiethylamide)tantalum (TBTDET), penta-kis(diethylamide)tantalum (PDEAT), pentakis(dimethylamide)tantalum (PDMAT), pentakis(ethylmethylamino)tantalum (PEMAT), etc. The Ta precursor is generally thermally decomposed (generally in the presence of the nitrogen source gas) to form the TaN thin film 13. The nitrogen source gas may comprise NH3, N2H4 or N2 (the latter of which may further comprise H2).
  • [0024]
    A lot of impurities are usually contained in the TaN thin film 13 due to various residual materials included in the Ta precursor, particularly from the covalently bound organic (carbon-containing) groups in the preferred Ta precursors. Thereby, the TaN thin film 13 generally has a higher resistivity than is optimal or desired. Therefore, such residual materials should be removed.
  • [0025]
    In the stage shown in FIG. 1C, a hydrogen (H)-containing gas (such as H2, H2+N2, N2H4 or NH3) and a noble gas (such as Ar) are injected into the chamber, and then the TaN thin film 13 is plasma processed, for example under a plasma power of 100-400W for a time sufficient to reduce the carbon content of the TaN film (e.g., a time of from 3-35 seconds). Then, the impurities within the layer and H atoms from the hydrogen-containing gas are believed to react with each other, and resultant volatile chemical compound becomes extracted or exhausted to outside the chamber, such that the impurities are resultantly removed from the layer 13. Therefore, the resistivity of the TaN thin film 13 a becomes lower.
  • [0026]
    Then, in the stage shown in FIG. 1D, the TaSiN thin film 14 a is formed by injecting or otherwise introducing a silicon (Si) source gas into the chamber such that the Si from the Si source gas may react with the TaN thin film 13 a. In a preferred embodiment, SiH4 gas may be used as the silicon source gas.
  • [0027]
    The process for forming the TaSiN thin film 14 a described above with reference to FIG. 1B to FIG. 1D is repeated at least once to form a multiple-layered diffusion layer 100, or until the diffusion barrier may have a desired thickness. As shown in FIG. 1E, the process for forming the TaSiN thin film (e.g., FIGS. 1B to 1D) is repeated twice such that the diffusion barrier 100 may have a triple layer structure of TaSiN thin films 14 a, 14 b, and 14 c. The process for forming the TaSiN thin film may be also repeated more than twice, that is, a few times to a few hundred times, such that the diffusion barrier may have numerous multiples or substantially any number of layers.
  • [0028]
    As described above, according to an embodiment of the present invention, impurities are removed from a TaN thin film by a plasma processing using a gas containing hydrogen (H) atoms, and then a TaSiN thin film is formed by reacting the purified TaN thin film and a gas containing silicon (Si). Therefore, a resistivity of the TaSiN thin film may be lowered.
  • [0029]
    In addition, according to an embodiment of the present invention, a process for forming a TaSiN thin film may be performed at a relatively low temperature by the ALD method, and the TaSiN thin film may be formed to a desired thickness by repeating the process as many times as desired or required. Therefore, such a TaSiN may have an enhanced surface state, and shows enhanced step coverage for a contact hole having a high aspect ratio. Furthermore, the same ALD apparatus and Ta precursor as conventionally used may be used without alteration, and therefore, the method may be easily applied in the field.
  • [0030]
    While this invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims (8)

  1. 1. A semiconductor device comprising:
    a semiconductor substrate;
    an interlayer insulating layer formed on the substrate and having a contact hole partially exposing the substrate; and
    a diffusion barrier formed on the interlayer insulating layer and in the contact hole, comprising a plurality of TaSiN thin films.
  2. 2. The semiconductor device of claim 1, wherein the TaSiN thin films comprise a reaction product of a silicon source gas and an impurity-removed TaN thin film.
  3. 3. The semiconductor device of claim 1, wherein the diffusion barrier comprises an ALD layer.
  4. 4. The semiconductor device of claim 2, wherein the impurity-removed TaN thin film comprises a TaN thin film processed by a plasma comprising a mixture of a hydrogen containing gas and a noble gas.
  5. 5. The semiconductor device of claim 4, wherein the TaN thin film has a thickness of from 2 to 100 Å.
  6. 6. The semiconductor device of claim 4, wherein the hydrogen containing gas comprises a member selected from the group consisting of H2, H2+N2 and NH3.
  7. 7. The semiconductor device of claim 2, wherein the silicon source gas comprises a silane.
  8. 8. The semiconductor device of claim 2, wherein the silicon source gas comprises SiH4.
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US11177921 US7407881B2 (en) 2004-07-09 2005-07-08 Semiconductor device and method for manufacturing the same
US12166267 US20080277790A1 (en) 2004-07-09 2008-07-01 Semiconductor Device

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US20100052167A1 (en) * 2008-08-29 2010-03-04 Oh Joon Seok METAL LINE HAVING A MOxSiy/Mo DIFFUSION BARRIER OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
US20100166982A1 (en) * 2008-12-30 2010-07-01 Oh Joon Seok Metal line of semiconductor device having a diffusion barrier and method for forming the same

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KR100845052B1 (en) 2006-06-07 2008-07-09 주식회사 하이닉스반도체 Semiconductor device and method for fabricating the same
KR20080114056A (en) * 2007-06-26 2008-12-31 주식회사 하이닉스반도체 Line of semiconductor device and method for manufacturing the same
US20110318505A1 (en) * 2008-12-09 2011-12-29 Akiko Yamamoto Method for forming tantalum nitride film and film-forming apparatus for forming the same
CN102623435B (en) * 2011-01-31 2015-02-18 北京泰龙电子技术有限公司 Barrier layer and preparation method thereof
CN102623434B (en) * 2011-01-31 2015-02-18 北京泰龙电子技术有限公司 Diffusion barrier layer and preparation method thereof
JP5824330B2 (en) * 2011-11-07 2015-11-25 ルネサスエレクトロニクス株式会社 The method of manufacturing a semiconductor device and a semiconductor device
US8962473B2 (en) * 2013-03-15 2015-02-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming hybrid diffusion barrier layer and semiconductor device thereof
US8981564B2 (en) * 2013-05-20 2015-03-17 Invensas Corporation Metal PVD-free conducting structures
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KR20170073947A (en) * 2015-12-21 2017-06-29 삼성전자주식회사 Tantalum compound and methods of forming thin film and integrated circuit device

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