US20080265290A1 - Double mesh finfet - Google Patents

Double mesh finfet Download PDF

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US20080265290A1
US20080265290A1 US11/739,420 US73942007A US2008265290A1 US 20080265290 A1 US20080265290 A1 US 20080265290A1 US 73942007 A US73942007 A US 73942007A US 2008265290 A1 US2008265290 A1 US 2008265290A1
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mesh
layer
effect transistor
fin field
formed
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US7453125B1 (en
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Alexander Nielsen
Bernhard Dobler
Georg Georgakos
Ralf Weber
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Infineon Technologies AG
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Infineon Technologies AG
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A multiple gate field-effect transistor is built from an overlapping mesh assembly. The assembly comprises a first layer comprising a semiconductor material formed into at least one fin, a least one source, and at least one drain. The first layer comprises a portion of a first mesh, electrically separated from the rest of the mesh. Similarly, a second layer is formed over the first layer and electrically isolated from the first layer, the second layer being electrically conductive and comprising a gate for the at least one fin of the transistor. The second layer comprises a portion of a second mesh offset from the first mesh and overlapping the first mesh, the second layer of the MuGFET device electrically separated from the rest of the second mesh.

Description

    FIELD OF THE INVENTION
  • The invention relates generally to semiconductor devices, and more specifically in one embodiment to a double mesh array for formation of MuGFET devices.
  • BACKGROUND
  • Semiconductor devices such as transistors and integrated circuits are typically formed on a substrate of a semiconducting material, using processes such as etching, lithography, and ion implantation to form various structures and materials on the substrate. A single field-effect transistor (FET), for example, may require a dozen or more steps to form implanted source and drain regions, an insulating layer, and a gate separated from the channel region by the insulating region.
  • In operation, doped source and drain regions are coupled to a circuit such that a voltage signal applied to the gate region controls the conductivity or resistivity of a channel region physically located between the source and drain regions. The conductivity of the channel region is based on an electric field created by potential applied to the gate, relative to the voltages present at the source and drain. Field effect transistors are sometimes described as being voltage-controlled resistors for this reason, and are used for applications such as amplifiers, signal processing, and control systems.
  • Field effect transistors are also very common in digital logic circuits such as in computer processors, memory, and other digital electronics. The voltage applied to the gate in such applications is typically intended to either turn off the FET completely or turn it on completely, such that the FET operates more like a switch than a variable resistor. For such applications, the switching speed, device size, leakage current, and a variety of other parameters are designed to provide the desired device size and operating characteristics, within the limitations of available technology. It is therefore desirable to control various parameters of field effect transistors to produce field effect transistors suited for various applications.
  • BRIEF DESCRIPTION OF THE FIGURES
  • FIG. 1 illustrates a typical n-type field effect transistor, consistent with the prior art.
  • FIG. 2 illustrates a multiple gate field effect transistor having a fin-type channel region, consistent with the prior art.
  • FIG. 3 illustrates a number of electrical contacts formed to provide source and drain electrical connections for a five-fin MuGFET, consistent with an example embodiment of the invention.
  • FIG. 4 illustrates an improved fin MuGFET structure by using a double mesh, consistent with an example embodiment of the invention.
  • FIG. 5A illustrates the double mesh structure of FIG. 4 filled with contacts, consistent with an example embodiment of the invention.
  • FIG. 5B illustrates a detail view of a theoretical intersection of mesh elements with a contact formed thereon, consistent with an example embodiment of the invention.
  • FIG. 5C illustrates a detail view of a practical intersection of mesh elements with a contact formed thereon, consistent with an example embodiment of the invention.
  • FIG. 6 illustrates use of round resist holes to form a mesh, resulting in intersections that form relatively large contact pads, consistent with an example embodiment of the invention.
  • FIG. 7 illustrates a five-fin multiple gate field effect transistor (MuGFET) device formed from an overlapping mesh assembly, consistent with an example embodiment of the invention.
  • FIG. 8 is a flowchart, illustrating one example method of forming a MuGFET device consistent with an example embodiment of the invention
  • DETAILED DESCRIPTION
  • In the following detailed description of example embodiments of the invention, reference is made to specific example embodiments of the invention by way of drawings and illustrations. These examples are described in sufficient detail to enable those skilled in the art to practice the invention, and serve to illustrate how the invention may be applied to various purposes or embodiments. Other embodiments of the invention exist and are within the scope of the invention, and logical, mechanical, electrical, and other changes may be made without departing from the subject or scope of the present invention. Features or limitations of various embodiments of the invention described herein, however essential to the example embodiments in which they are incorporated, do not limit other embodiments of the invention or the invention as a whole, and any reference to the invention, its elements, operation, and application do not limit the invention as a whole but serve only to define these example embodiments. The following detailed description does not, therefore, limit the scope of the invention, which is defined only by the appended claims.
  • One example embodiment of the invention provides a multiple gate field-effect transistor (MuGFET) built from an overlapping mesh assembly. The assembly comprises a first layer comprising a semiconductor material formed into at least one fin, at least one source, and at least one drain. The first layer comprises a portion of a first mesh, electrically separated from the rest of the mesh. Similarly, a second layer is formed over the first layer and electrically isolated from the first layer, the second layer being electrically conductive and comprising a gate for the at least one fin of the transistor. The second layer comprises a portion of a second mesh offset from the first mesh and overlapping the first mesh, the second layer of the MuGFET device electrically separated from the rest of the second mesh.
  • FIG. 1 illustrates a typical n-type field effect transistor, consistent with the prior art. A semiconductor substrate has a p-type region, such as a silicon substrate doped with boron, as shown at 101. Two n-type semiconductor regions are formed at 102 and 103, such as by ion implantation of a dopant such as phosphorous. These two regions are known as the source and the drain, as one region is used as the source of charge carriers conducted across the channel region, while the other drains the conducted charge carriers. An insulating layer, such as a semiconductor oxide, is formed at 104, separating the channel region of the p-type substrate located between the source 102 and drain 103 from a metal gate 105. The gate is therefore electrically isolated from the source, drain, and channel region of the substrate, and influences conduction across the channel region between the source and drain by an electric field generated as a result of application of voltage to the gate 105.
  • With no voltage applied to the gate, the channel region of the substrate does not conduct, and essentially no electricity is able to flow between the source 102 and the drain 103. Even with application of increasingly large voltage across the source 102 and drain 103, only a small amount of leakage current is able to flow across the channel region unless an excessive voltage known as the breakdown voltage is applied across the source and the drain, and the transistor is destroyed. When a potential is applied to the gate and the source-drain voltage is small, the channel region acts like a resistor that varies in resistance with the applied voltage, enabling the FET to operate essentially as a voltage-controlled resistor. When larger voltages are applied across the source and drain, or when the gate voltage is relatively near the source or drain voltages, the FET will be turned almost completely on or off, acting more like a switch than a resistor as is common in digital electronic applications.
  • FIG. 2 illustrates a field effect transistor having a fin-type channel region, consistent with the prior art. The FET of FIG. 2 is sometimes referred to as a FinFET, as the channel structure resembles a fin. The device of FIG. 2 is a multiple gate FET, or MuGFET, as gate regions are formed on three sides of the fin structure.
  • The MuGFET of FIG. 2 is formed on a substrate 201, such as a doped or undoped silicon substrate or an insulator. A source region 202 and a drain region 203 of the transistor are formed of a doped semiconductor material, such as n-type silicon doped with phosphorous, while the channel region hidden from view under the gate oxide 204 and gate 205 is p-type silicon, doped with boron. The channel region is covered with an insulator material such as silicon oxide, as shown at 204, separating the channel region from the gate 205. The gate structure of this example wraps around three sides of the fin-shaped structure comprising the channel, forming a field effect transistor that appears more like a fin than the flat FET structure of FIG. 1.
  • The FET itself operates much the same as the FET of FIG. 1, except that the gate 205 has sections parallel and close to three different channel regions of the doped silicon material under the insulating gate oxide material 204. The fin therefore operates effectively as having three separate channel regions, each controlled by the same gate 205. The resulting FET structure therefore has a relatively large channel area for the physical size of the FET, meaning that more transistors can be packed into the same area carrying more current that is possible using traditional methods such as that shown in FIG. 1.
  • But, efficiencies gained by very small transistor device sizes can be limited by the need to provide electrical connection to the source, gate, and drain, and can be further limited by the difficulty in forming very small features using modern lithography equipment. In a typical MuGFET as shown in FIG. 2, the source 202 and drain 203 are coupled to contact areas large enough so that metal contacts such as that shown at 206 can be formed. The fin material forming the source and drain regions must therefore be enlarged a certain distance away from the gate region of the MuGFET to provide a suitable landing pad area for the contacts such as 206 to be formed.
  • A more detailed example of a multiple fin MuGFET is shown in FIG. 3, which illustrates a number of electrical contacts formed to provide source and drain electrical connections for a five-fin MuGFET. In this example, the gate shown at 301 extends across five fins 302, each fin parallel to the other fins and perpendicular to the direction of the gate. The fins 302 are in contact with a silicon region having a group of five source contacts, as shown at 303, for both the source and drain sides of the fins. Although the actual fin geometry of the MuGFET of FIG. 3 is relatively small, the contact geometry of the structure shown in FIG. 3 is relatively large, limiting the size advantage gained by use of a FinFET or MuGFET configuration.
  • One example embodiment of the invention seeks to provide an improved multiple fin MuGFET structure by using a double mesh, as shown in FIG. 4. The double mesh is formed such that a first mesh 401 is formed of a series of perpendicular and parallel silicon fins, such as a p-type doped silicon or undoped silicon, and is covered with an oxide layer. The oxide layer is either selectively applied or selectively removed from the first mesh 401, so that some portions of the p-type mesh will remain covered with oxide and be used as the channel region of a MuGFET structure, and other regions of the first mesh will not be covered by oxide and will be doped by an n-type dopant to form the source and drain regions of the same MuGFET structures.
  • A second mesh 402 is then formed over the first mesh and the oxide layer, offset from the first mesh such as is shown in FIG. 4. The second mesh is formed over oxide covered portions of the first mesh, so that the first and second meshes are electrically isolated from one another. The second mesh will serve as the gate for one or more fins of the MuGFET assembly, and in various embodiments is polysilicon, metal, or another substantially conductive material.
  • The double mesh structure of FIG. 4 is then filled with contacts, as shown in FIG. 5. Here, contacts are formed at each intersection of the various elements of the mesh, but in other embodiments are selectively formed at selected intersections of various mesh elements. Although the intersection of the perpendicular mesh segments of the two mesh layers theoretically have square edges as shown in FIG. 5 b, in practice the limits of lithography technology or use of non-square resist mask elements results in a larger intersection area, as shown in FIG. 5 c.
  • One example of use of round resist “holes” to form the mesh, resulting in intersections that form relatively large contact pads, is shown in FIG. 6. In this example, the intersections of the perpendicular mesh elements will be somewhat rounded and not square, resulting in a relatively large intersection area. This provides a large area for a contact to be formed, while leaving the fin structure relatively narrow, resulting in a MuGFET structure having both the desired small overall device size and large contact area.
  • Either before or after the contacts are formed, various parts of the mesh are broken, isolating certain mesh segments. This is performed in one example by use of a trim mask that can be applied to a standardized mesh configuration to form a desired array of MuGFET devices. The isolated mesh segment forms in the example shown in FIG. 7 a five-fin MuGFET, similar to that shown in FIG. 3, but with improved geometry and with the ability to form other MuGFET devices using other mesh segments very near the device of FIG. 7.
  • FIG. 7 shows a first mesh of doped silicon 701, and an offset, overlapping second mesh of a conductor such as metal or polysilicon shown at 702. The second mesh is electrically isolated from the first mesh, such as by oxidizing a thin layer of silicon on the surface of the first mesh or by applying an insulator such as silicon oxide to at least the portions of the first mesh that will overlap with the second mesh before the second mesh is formed.
  • The first mesh 701 has five contact pads formed at junction points of elements of the mesh in one row, forming drain connections, and five contact pads formed at junction points of an adjacent row, forming source connections. In examples where the first mesh is oxidized before formation of the second mesh or where oxide is applied over the entire first mesh, the oxide over the contact areas of the first mesh is removed so that electrical connection to the underlying silicon can be made. The second mesh 702 similarly has a contact pad 704 formed thereon, used as a gate connection.
  • To form the five-fin MuGFET device from the overlapping offset meshes shown in FIG. 7, connections from the device portion of the mesh to other parts of the mesh are broken, such as by using an etch or trim mask, or by other means of breaking the mesh such as laser ablation. Several ablation points are marked with circles in FIG. 7, illustrating points at which the first mesh that forms the source, drain, and channel/fin portions of the MuGFET are separated from the rest of the first mesh as well as the points at which the portion of the second mesh that forms the gate of the MuGFET device is separated from the rest of the second mesh.
  • Each intersection 706 of the first and second mesh layers that is a part of the device isolated by the ablation or separation from the rest of the mesh comprises a MuGFET, having a source, drain, and channel region formed by the first mesh and an electrically isolated gate formed by the second mesh. This method enables formation of relatively dense MuGFET devices, as well as relatively easy customization of the configuration of the FET devices and the number of fins for each device using a standard mask or ablation pattern applied to the standardized mesh configuration.
  • FIG. 8 is a flowchart, illustrating one example method of forming a MuGFET device consistent with an example embodiment of the invention. At 801, a first mesh is formed, and is in some embodiments doped with a p-type material such as boron. This material is then covered in at least some selected areas with an isolating layer such as an oxide layer at 802. In one example, the oxide layer is formed in those portions of the grid elements that are between element intersections, where the overlapping conductive mesh will overlay the first mesh. In another example, the silicon forming the first mesh is oxidized in those portions not masked, forming an oxide layer on the same portions of the first mesh.
  • A second mesh is then formed over the first mesh at 803, similar in pitch but offset from the first mesh as shown in the previous figures such as FIG. 7. The second mesh is made of a conductive material, and is electrically insulated from the first mesh by the oxide layer formed at 802. The isolating oxide layer is then removed from those portions of the first mesh not covered by the second mesh at 804.
  • In a further example, the exposed portions of the first mesh not covered by the oxide layer or by the second mesh are doped with an n-type dopant, forming doped regions of the first mesh that will become the source and drain regions of the formed MuGFET transistor devices. These portions are doped at other times, with other dopants, and selected via other methods in other embodiments.
  • Contacts are then formed at the intersection points of the various meshes at 805, including forming electrical contacts at the intersection points of mesh elements of the first mesh for source and drain connections of electrical devices. Similarly, electrical contacts are formed at intersections of the second mesh layer, to be used as gate connections for transistor devices. In alternate embodiments, the contacts are selectively formed on certain grid intersection points at this time or at another time, depending on the transistor device configuration eventually formed from the overlapping meshes.
  • The portions of the first and second meshes that couple that part of the mesh to be used as a MuGFET device to the remainder of the meshes are then ablated or broken at 806, so that the transistor's various conductive elements are electrically isolated from the rest of the mesh at 807. The portions of the first mesh used to form the fins, the source contacts, and the drain contacts are isolated from the rest of the mesh, and the portions of the second mesh used to form the gate contact and the gate conductors formed over the oxide layers of the transistor fins are isolated from the rest of the second mesh. A single overlapping offset mesh assembly can be used to form a variety of transistor devices from the same mesh assembly in this manner, forming complex electrical circuits or large arrays of transistors. A variety of other mesh orientations and configurations are possible, including perpendicular and angular meshes, meshes of varying sizes, and meshes of varying compositions or materials, all of which are within the scope of the various embodiments of the invention.
  • The overlapping mesh method of device formation illustrated here provides a very dense and regular structure, with the mesh element width and element-to-element distance selected to provide the desired fin size and spacing between source and drain. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that achieve the same purpose, structure, or function may be substituted for the specific embodiments shown. This application is intended to cover any adaptations or variations of the example embodiments of the invention described herein. It is intended that this invention be limited only by the claims, and the full scope of equivalents thereof.

Claims (15)

1. A fin field-effect transistor, comprising:
a substrate;
a first layer comprising a semiconductor material formed into at least one fin, at least one source, and at least one drain, the first layer comprising a portion of a first mesh electrically separated from the rest of the mesh; and
a second layer formed over the first layer and electrically isolated from the first layer, the second layer electrically conductive and comprising a gate for the at least one fin of the transistor, the second layer comprising a portion of a second mesh offset from the first mesh and overlapping the first mesh, the second layer electrically separated from the rest of the second mesh.
2. The fin field-effect transistor of claim 1, wherein the transistor comprises multiple fins, each of the multiple fins comprising a channel of the transistor and each of the fins comprising a part of the first layer, and wherein the second layer further comprises a gate for each of the multiple fins.
3. The fin field-effect transistor of claim 1, wherein the first mesh and the second mesh comprise multiple electrically separated fin field-effect transistors.
4. The fin field-effect transistor of claim 1, wherein at least one of the first and second meshes comprise an intersecting grid of elements, and wherein a contact area is formed on at least one intersection of the grid elements.
5. The fin field-effect transistor of claim 1, wherein a channel portion of the first layer is doped with a first dopant, and the source and drain portions of the first layer are doped with a second dopant.
6. The fin field-effect transistor of claim 1, wherein at least one of the first mesh and the second mesh are formed via an array of resist dots.
7. The fin field-effect transistor of claim 1, wherein the elements of at least one of the first and second mesh are at least partially self-aligning.
8. A fin field-effect transistor mesh assembly, comprising:
a substrate;
a first mesh comprising a grid of intersecting elements, the first mesh comprising a semiconductor material;
a second mesh comprising a grid of intersecting elements offset from the first mesh and overlapping the first mesh, the second mesh comprising a conductive material;
an insulating layer formed on at least a portion of at least the first or second mesh, the insulating layer electrically separating the first mesh from the second mesh; and
a plurality of electrical contacts, the contacts formed on at least one of the first or second meshes at the intersection of intersecting grid elements.
9. The fin field-effect transistor mesh assembly of claim 8, wherein the insulating comprises a silicon oxide layer.
10. The fin field-effect transistor mesh assembly of claim 8, wherein at least one intersection between the first and second meshes forms a FinFET.
11. The fin field-effect transistor mesh assembly of claim 8, wherein a first portion of the first mesh is doped with a first dopant to form a channel region, and second and third portions of the mesh are doped with a second dopant to form source and drain regions.
12. The fin field-effect transistor mesh assembly of claim 8, wherein a contact area is formed on at least one intersection of elements of the first grid or elements of the second grid.
13. The fin field-effect transistor mesh assembly of claim 8, wherein a portion of the first and second meshes is isolated from the rest of the first and second meshes to form an electrically isolated FinFET device.
14. The fin field-effect transistor mesh assembly of claim 13, wherein the separated portion is separated by ablating a portion of the first and second meshes.
15-20. (canceled)
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Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100025767A1 (en) * 2008-08-01 2010-02-04 Kabushiki Kaisha Toshiba Semiconductor device
US20110163417A1 (en) * 2010-01-07 2011-07-07 Globalfoundries Inc. Method to dynamically tune precision resistance
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US8471391B2 (en) 2008-03-27 2013-06-25 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
WO2013106799A1 (en) * 2012-01-13 2013-07-18 Tela Innovations, Inc. Circuits with linear finfet structures
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8549455B2 (en) 2007-08-02 2013-10-01 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US8552508B2 (en) 2008-03-13 2013-10-08 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer
US20130288443A1 (en) * 2011-12-14 2013-10-31 Taiwan Semiconductor Manufacturing Company, Ltd Methods for Reduced Gate Resistance FINFET
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8680626B2 (en) 2007-10-26 2014-03-25 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US8756551B2 (en) 2007-08-02 2014-06-17 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US8863063B2 (en) 2009-05-06 2014-10-14 Tela Innovations, Inc. Finfet transistor circuit
US8921896B2 (en) 2006-03-09 2014-12-30 Tela Innovations, Inc. Integrated circuit including linear gate electrode structures having different extension distances beyond contact
WO2014209509A1 (en) * 2013-06-24 2014-12-31 International Business Machines Corporation Semiconductor device including source/drain formed on bulk and gate channel formed on oxide layer
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8697515B2 (en) * 2012-06-06 2014-04-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a FinFET device
US9000489B2 (en) 2012-10-31 2015-04-07 International Business Machines Corporation Local interconnects for field effect transistor devices

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6989308B2 (en) * 2004-03-11 2006-01-24 International Business Machines Corporation Method of forming FinFET gates without long etches
US7013447B2 (en) * 2003-07-22 2006-03-14 Freescale Semiconductor, Inc. Method for converting a planar transistor design to a vertical double gate transistor design
US7015078B1 (en) * 2003-09-09 2006-03-21 Advanced Micro Devices, Inc. Silicon on insulator substrate having improved thermal conductivity and method of its formation

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100481209B1 (en) * 2002-10-01 2005-04-08 삼성전자주식회사 MOS Transistor having multiple channels and method of manufacturing the same
KR100493059B1 (en) * 2003-04-18 2005-06-02 삼성전자주식회사 Transistor decreasing gate capacitance
KR100699839B1 (en) * 2005-04-21 2007-03-27 삼성전자주식회사 Semiconductor device having multi-channel and Method of manufacturing the same
US7102181B1 (en) * 2005-04-22 2006-09-05 International Business Machines Corporation Structure and method for dual-gate FET with SOI substrate
US7479421B2 (en) * 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7013447B2 (en) * 2003-07-22 2006-03-14 Freescale Semiconductor, Inc. Method for converting a planar transistor design to a vertical double gate transistor design
US7015078B1 (en) * 2003-09-09 2006-03-21 Advanced Micro Devices, Inc. Silicon on insulator substrate having improved thermal conductivity and method of its formation
US6989308B2 (en) * 2004-03-11 2006-01-24 International Business Machines Corporation Method of forming FinFET gates without long etches

Cited By (112)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8946781B2 (en) 2006-03-09 2015-02-03 Tela Innovations, Inc. Integrated circuit including gate electrode conductive structures with different extension distances beyond contact
US10217763B2 (en) 2006-03-09 2019-02-26 Tela Innovations, Inc. Semiconductor chip having region including gate electrode features of rectangular shape on gate horizontal grid and first-metal structures of rectangular shape on at least eight first-metal gridlines of first-metal vertical grid
US9589091B2 (en) 2006-03-09 2017-03-07 Tela Innovations, Inc. Scalable meta-data objects
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US9741719B2 (en) 2006-03-09 2017-08-22 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US9754878B2 (en) 2006-03-09 2017-09-05 Tela Innovations, Inc. Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires
US10186523B2 (en) 2006-03-09 2019-01-22 Tela Innovations, Inc. Semiconductor chip having region including gate electrode features formed in part from rectangular layout shapes on gate horizontal grid and first-metal structures formed in part from rectangular layout shapes on at least eight first-metal gridlines of first-metal vertical grid
US9443947B2 (en) 2006-03-09 2016-09-13 Tela Innovations, Inc. Semiconductor chip including region having integrated circuit transistor gate electrodes formed by various conductive structures of specified shape and position and method for manufacturing the same
US9425272B2 (en) 2006-03-09 2016-08-23 Tela Innovations, Inc. Semiconductor chip including integrated circuit including four transistors of first transistor type and four transistors of second transistor type with electrical connections between various transistors and methods for manufacturing the same
US9425273B2 (en) 2006-03-09 2016-08-23 Tela Innovations, Inc. Semiconductor chip including integrated circuit including at least five gate level conductive structures having particular spatial and electrical relationship and method for manufacturing the same
US9425145B2 (en) 2006-03-09 2016-08-23 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9711495B2 (en) 2006-03-09 2017-07-18 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9336344B2 (en) 2006-03-09 2016-05-10 Tela Innovations, Inc. Coarse grid design methods and structures
US9240413B2 (en) 2006-03-09 2016-01-19 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9859277B2 (en) 2006-03-09 2018-01-02 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US9905576B2 (en) 2006-03-09 2018-02-27 Tela Innovations, Inc. Semiconductor chip including region having rectangular-shaped gate structures and first metal structures
US8952425B2 (en) 2006-03-09 2015-02-10 Tela Innovations, Inc. Integrated circuit including at least four linear-shaped conductive structures having extending portions of different length
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US10230377B2 (en) 2006-03-09 2019-03-12 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8921897B2 (en) 2006-03-09 2014-12-30 Tela Innovations, Inc. Integrated circuit with gate electrode conductive structures having offset ends
US8921896B2 (en) 2006-03-09 2014-12-30 Tela Innovations, Inc. Integrated circuit including linear gate electrode structures having different extension distances beyond contact
US9917056B2 (en) 2006-03-09 2018-03-13 Tela Innovations, Inc. Coarse grid design methods and structures
US10141335B2 (en) 2006-03-09 2018-11-27 Tela Innovations, Inc. Semiconductor CIP including region having rectangular-shaped gate structures and first metal structures
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US10141334B2 (en) 2006-03-09 2018-11-27 Tela Innovations, Inc. Semiconductor chip including region having rectangular-shaped gate structures and first-metal structures
US9673825B2 (en) 2006-03-09 2017-06-06 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US10074640B2 (en) 2007-03-05 2018-09-11 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US9633987B2 (en) 2007-03-05 2017-04-25 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US9424387B2 (en) 2007-03-07 2016-08-23 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9595515B2 (en) 2007-03-07 2017-03-14 Tela Innovations, Inc. Semiconductor chip including integrated circuit defined within dynamic array section
US9910950B2 (en) 2007-03-07 2018-03-06 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US8966424B2 (en) 2007-03-07 2015-02-24 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US8756551B2 (en) 2007-08-02 2014-06-17 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US8549455B2 (en) 2007-08-02 2013-10-01 Tela Innovations, Inc. Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US8759882B2 (en) 2007-08-02 2014-06-24 Tela Innovations, Inc. Semiconductor device with dynamic array sections defined and placed according to manufacturing assurance halos
US8680626B2 (en) 2007-10-26 2014-03-25 Tela Innovations, Inc. Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
US9281371B2 (en) 2007-12-13 2016-03-08 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8951916B2 (en) 2007-12-13 2015-02-10 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US9818747B2 (en) 2007-12-13 2017-11-14 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US8701071B2 (en) 2008-01-31 2014-04-15 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US9202779B2 (en) 2008-01-31 2015-12-01 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US9530734B2 (en) 2008-01-31 2016-12-27 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US8853794B2 (en) 2008-03-13 2014-10-07 Tela Innovations, Inc. Integrated circuit within semiconductor chip including cross-coupled transistor configuration
US8853793B2 (en) 2008-03-13 2014-10-07 Tela Innovations, Inc. Integrated circuit including gate electrode level region including cross-coupled transistors having gate contacts located over inner portion of gate electrode level region and offset gate level feature line ends
US8669594B2 (en) 2008-03-13 2014-03-11 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within at least twelve gate level feature layout channels
US8866197B2 (en) 2008-03-13 2014-10-21 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through another transistor forming gate level feature
US8872283B2 (en) 2008-03-13 2014-10-28 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature
US8816402B2 (en) 2008-03-13 2014-08-26 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate level feature layout channel including single transistor
US8785979B2 (en) 2008-03-13 2014-07-22 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with two inside positioned gate contacts and two outside positioned gate contacts and electrical connection of cross-coupled transistors through same interconnect layer
US8558322B2 (en) 2008-03-13 2013-10-15 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two gate electrodes electrically connected to each other through gate level feature
US8785978B2 (en) 2008-03-13 2014-07-22 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with electrical connection of cross-coupled transistors through same interconnect layer
US8847331B2 (en) 2008-03-13 2014-09-30 Tela Innovations, Inc. Semiconductor chip including region having cross-coupled transistor configuration with offset electrical connection areas on gate electrode forming conductive structures and at least two different inner extension distances of gate electrode forming conductive structures
US8592872B2 (en) 2008-03-13 2013-11-26 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors with two transistors of different type having gate electrodes formed by common gate level feature with shared diffusion regions on opposite sides of common gate level feature
US8772839B2 (en) 2008-03-13 2014-07-08 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer
US8587034B2 (en) 2008-03-13 2013-11-19 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer
US8729606B2 (en) 2008-03-13 2014-05-20 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels
US9871056B2 (en) 2008-03-13 2018-01-16 Tela Innovations, Inc. Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same
US8581303B2 (en) 2008-03-13 2013-11-12 Tela Innovations, Inc. Integrated circuit including cross-coupled trasistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset relationships and electrical connection of cross-coupled transistors through same interconnect layer
US8581304B2 (en) 2008-03-13 2013-11-12 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships
US8575706B2 (en) 2008-03-13 2013-11-05 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level features inner extensions beyond gate electrode
US9081931B2 (en) 2008-03-13 2015-07-14 Tela Innovations, Inc. Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track and gate node connection through single interconnect layer
US9117050B2 (en) 2008-03-13 2015-08-25 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position and offset specifications
US8847329B2 (en) 2008-03-13 2014-09-30 Tela Innovations, Inc. Cross-coupled transistor circuit defined having diffusion regions of common node on opposing sides of same gate electrode track with at least two non-inner positioned gate contacts
US8669595B2 (en) 2008-03-13 2014-03-11 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position, alignment, and offset specifications
US8680583B2 (en) 2008-03-13 2014-03-25 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within at least nine gate level feature layout channels
US9208279B2 (en) 2008-03-13 2015-12-08 Tela Innovations, Inc. Semiconductor chip including digital logic circuit including linear-shaped conductive structures having electrical connection areas located within inner region between transistors of different type and associated methods
US9213792B2 (en) 2008-03-13 2015-12-15 Tela Innovations, Inc. Semiconductor chip including digital logic circuit including at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods
US8729643B2 (en) 2008-03-13 2014-05-20 Tela Innovations, Inc. Cross-coupled transistor circuit including offset inner gate contacts
US8735995B2 (en) 2008-03-13 2014-05-27 Tela Innovations, Inc. Cross-coupled transistor circuit defined on three gate electrode tracks with diffusion regions of common node on opposing sides of same gate electrode track
US9245081B2 (en) 2008-03-13 2016-01-26 Tela Innovations, Inc. Semiconductor chip including digital logic circuit including at least nine linear-shaped conductive structures collectively forming gate electrodes of at least six transistors with some transistors forming cross-coupled transistor configuration and associated methods
US8836045B2 (en) 2008-03-13 2014-09-16 Tela Innovations, Inc. Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track
US10020321B2 (en) 2008-03-13 2018-07-10 Tela Innovations, Inc. Cross-coupled transistor circuit defined on two gate electrode tracks
US8564071B2 (en) 2008-03-13 2013-10-22 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least two different gate level feature extensions beyond contact
US9536899B2 (en) 2008-03-13 2017-01-03 Tela Innovations, Inc. Semiconductor chip including integrated circuit having cross-coupled transistor configuration and method for manufacturing the same
US8742462B2 (en) 2008-03-13 2014-06-03 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position specifications
US8552509B2 (en) 2008-03-13 2013-10-08 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with other transistors positioned between cross-coupled transistors
US8552508B2 (en) 2008-03-13 2013-10-08 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer
US8742463B2 (en) 2008-03-13 2014-06-03 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with outer positioned gate contacts
US8735944B2 (en) 2008-03-13 2014-05-27 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with serially connected transistors
US8569841B2 (en) 2008-03-13 2013-10-29 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with at least one gate level feature extending into adjacent gate level feature layout channel
US8835989B2 (en) 2008-03-13 2014-09-16 Tela Innovations, Inc. Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate electrode placement specifications
US9390215B2 (en) 2008-03-27 2016-07-12 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US9779200B2 (en) 2008-03-27 2017-10-03 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US8759985B2 (en) 2008-03-27 2014-06-24 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US8471391B2 (en) 2008-03-27 2013-06-25 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US8169009B2 (en) * 2008-08-01 2012-05-01 Kabushiki Kaisha Toshiba Semiconductor device
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US20100025767A1 (en) * 2008-08-01 2010-02-04 Kabushiki Kaisha Toshiba Semiconductor device
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8863063B2 (en) 2009-05-06 2014-10-14 Tela Innovations, Inc. Finfet transistor circuit
US9530795B2 (en) 2009-10-13 2016-12-27 Tela Innovations, Inc. Methods for cell boundary encroachment and semiconductor devices implementing the same
US9269702B2 (en) 2009-10-13 2016-02-23 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the same
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US8709882B2 (en) * 2010-01-07 2014-04-29 Globalfoundries Inc. Method to dynamically tune precision resistance
US20110163417A1 (en) * 2010-01-07 2011-07-07 Globalfoundries Inc. Method to dynamically tune precision resistance
US9704845B2 (en) 2010-11-12 2017-07-11 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US8759181B2 (en) * 2011-12-14 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for reduced gate resistance FINFET
US20130288443A1 (en) * 2011-12-14 2013-10-31 Taiwan Semiconductor Manufacturing Company, Ltd Methods for Reduced Gate Resistance FINFET
JP2015506589A (en) * 2012-01-13 2015-03-02 テラ イノヴェイションズ インコーポレイテッド Circuit with a linear FinFET structure
WO2013106799A1 (en) * 2012-01-13 2013-07-18 Tela Innovations, Inc. Circuits with linear finfet structures
CN104303263A (en) * 2012-01-13 2015-01-21 特拉创新公司 Circuits with linear finfet structures
US8957478B2 (en) 2013-06-24 2015-02-17 International Business Machines Corporation Semiconductor device including source/drain formed on bulk and gate channel formed on oxide layer
US9059019B2 (en) 2013-06-24 2015-06-16 International Business Machines Corporation Semiconductor device including source/drain formed on bulk and gate channel formed on oxide layer
WO2014209509A1 (en) * 2013-06-24 2014-12-31 International Business Machines Corporation Semiconductor device including source/drain formed on bulk and gate channel formed on oxide layer

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