US20080264477A1

US20080264477A1 - Methods for manufacturing three-dimensional thin-film solar cells

Info

Publication number: US20080264477A1
Application number: US11/868,489
Authority: US
Inventors: Mehrdad Moslehi
Original assignee: Soltaix Inc
Current assignee: Ob Realty LLC; Beamreach Solar Inc
Priority date: 2006-10-09
Filing date: 2007-10-06
Publication date: 2008-10-30

Abstract

Methods for manufacturing three-dimensional thin-film solar cells 100, using a template. The template comprises a template substrate comprising a plurality of posts and a plurality of trenches between said plurality of posts. The three-dimensional thin-film solar cell substrate is formed by forming a sacrificial layer on the template, subsequently depositing a semiconductor layer, selectively etching the sacrificial layer, and releasing the semiconductor layer from the template. The resulting three-dimensional thin-film solar cell substrate may comprise a plurality of single-aperture unit cells or dual-aperture unit cells. Select portions of the three-dimensional thin-film solar cell substrate are then doped with a first dopant, while other select portions are doped with a second dopant. Next, emitter 525 and base metallization regions 532 are formed.

Description

This application claims the benefit of provisional patent applications 60/828,678 filed on Oct. 9, 2006 and 60/886,303 filed on Jan. 24, 2007, which are hereby incorporated by reference.

FIELD

This disclosure relates in general to the field of photovoltaics and solar cells, and more particularly to methods for manufacturing three-dimensional (3-D) Thin-Film Solar Cells (TFSCs). Even more particularly, the presently disclosed subject matter relates to methods for manufacturing 3-D single-aperture and dual-aperture TFSCs.

DESCRIPTION OF THE RELATED ART

Renewable, high-efficiency, and cost-effective sources of energy are becoming a growing need on a global scale. Increasingly expensive, unreliable, and environmentally-risky fossil fuels and a rising global demand for energy, including electricity, have created the need for alternate, secure, clean, widely available, cost-effective, environmentally-friendly, and renewable forms of energy. Solar photovoltaic (PV) electricity generation using solar cells is uniquely suited to meet the needs of residential, commercial, industrial, and centralized utility applications. Key attributes that make solar energy attractive are the abundant, worldwide, point-of-use supply of sunlight, environmental friendliness, scalability (from milliwatts to megawatts), secure point-of-use generation of solar electricity, and excellent distributed energy economics. The sun provides more energy to the earth in one hour than the annual energy consumption of the entire world. Much of the earth's surface receives a significant amount of annual sun-hours which may be effectively harnessed for clean and secure electricity generation. A key driver for this market pull is a rising public awareness of environmentally-benign technologies. However, due to relatively low solar cell efficiencies (e.g., less than 12% for most thin-film technologies and roughly 12% to 18% for most crystalline silicon solar cell technologies), high costs of raw materials (e.g., silicon for crystalline silicon wafer solar cells) and manufacturing processes, limitations on cost-effective and efficient electrical storage, and a general lack of infrastructure to support solar cell proliferation, to date there has been limited use of this energy solution (currently, electricity generation by solar photovoltaics accounts for less than 0.1% of total worldwide electricity generation).
For commercial applications, cost of energy to the end-user (e.g., in cents/kWh for electricity) should be sufficiently low and comparable to or even better than that from utility grids using conventional electricity generation sources. The solar photovoltaic electricity generation, which currently accounts for less than 0.1% of the global electricity generation, may be substantially expanded if it achieves cost parity with conventional grid electricity. As the costs of solar cells and modules (typically expressed as $/W_p) are reduced, grid-tied solar photovoltaic applications are gaining acceptance at an accelerated pace, making them an attractive option for significant proliferation in electricity generation.
In the price-sensitive solar cell market, two principal technology options exist. On the one hand, crystalline silicon (c-Si) wafers may serve as the basis for solar cell formation (currently accounting for more than 90% of the solar PV market). On the other hand, thin-film (amorphous and polycrystalline) technologies using silicon and other semiconductor absorber materials (such as amorphous silicon, CdTe, or CIGS) may offer significant cost advantages compared to crystalline silicon wafer-based solar cells. These different approaches are at opposite ends of the price-performance scale. Crystalline silicon wafers offer higher performance, but at higher costs (due to the relatively high cost of starting monocrystalline and multicrystalline silicon wafers). Thin-film technologies may offer lower manufacturing costs, but typically at lower performance levels (i.e., lower efficiencies). For both approaches, the price-per-watt typically increases as cell efficiencies rise (due to higher material and/or manufacturing costs).
Due to a rapid annual growth rate of more than 40% during the past ten years and the concurrent demands for silicon material by both semiconductor microelectronics and solar PV industries, the solar PV industry has been experiencing a shortage of polysilicon feedstock supply. The polysilicon feedstock shortage has significantly constrained the solar PV industry growth, particularly during the past several years. In fact, the solar cell industry currently consumes over half of the worldwide production of high-purity polysilicon feedstock. Within the last few years, the contract price of polysilicon has increased from roughly $30/kg to roughly $85/kg, with spot prices exceeding $250/kg. This has led to large increases in the price of monocrystalline and multicrystalline silicon wafers, which now account for roughly half of the total solar module manufacturing cost.
The trend in the mainstream crystalline silicon (c-Si) wafer solar cell industry has been to scale down wafer thicknesses to below 200 microns (in order to reduce the amount of silicon material in grams used per watt of solar cell rated peak power). For example, monocrystalline silicon wafer solar cells are projected to scale down to a thickness of roughly 120 microns by 2012, from a current wafer thickness of roughly 200 microns. Multicrystalline silicon wafer solar cells are projected to scale down to a thickness of roughly 180 microns by 2012, from a current average wafer thickness of roughly 260 microns. This wafer thickness reduction, however, presents additional challenges related to mechanical rigidity, manufacturing yield, and solar cell efficiency. Despite its high cost, crystalline silicon (c-Si) technology still dominates the solar cell market, mainly due to higher efficiencies and synergies with the established microelectronics industry and supply chain. Currently, c-Si accounts for slightly over 90% of the solar cell market (95% when ribbon silicon is included).
Historically, crystalline silicon solar cells have achieved a 20% cost reduction for each doubling of cumulative global cell production (measured in megawatts or MW_pand gigawatts or GW_p). It is projected that through innovative cost reduction and efficiency enhancement methods, the cost of electricity derived from grid-connected rooftop solar photovoltaic modules may become comparable to the cost of electricity purchased from the utility grid in five to ten years. A 2005 survey of the commercially available monocrystalline silicon and multicrystalline silicon solar modules reports the solar module efficiencies then in the range of 9.1% to 16.1%, with a median efficiency value of about 12.5%. Commercial crystalline silicon modules usually show a rapid initial efficiency degradation of 1% to 3% (relative) due to various effects, including photodegradation effects in wafered solar cells (e.g., wafer minority carrier lifetime degradation). Monocrystalline silicon wafer solar cell efficiencies are projected to increase to roughly 20.5% by 2012, from a current efficiency of roughly 16.5% (leading-edge commercially available monocrystalline silicon solar cell and solar module efficiencies are currently about 21.5% and 18%, respectively). Multicrystalline silicon wafer solar cell efficiencies are projected to increase to roughly 18% by 2012, from a current efficiency level of roughly 15.5%.
State-of-the-art crystalline silicon solar cell manufacturing currently uses about 10 grams of high-purity polysilicon feedstock per peak watt (g/W_p), resulting in a polysilicon feedstock material cost of about $0.85/W_p(assuming a polysilicon price of $85/kg). Over the next five years, the projected trends of solar cell wafer thickness reduction (e.g., to less than 200 micron wafers) and a long-term assumed price of about $20/kg for solar-grade polysilicon may reduce the polysilicon feedstock cost (in g/W_p) by about a factor of four to eight to about $0.10/W_pto $0.20/W_p. Thus, any competing solar cell technologies should benchmark their manufacturing cost goals against this reduced raw material cost number. For a given cell efficiency, silicon wafer thickness reduction presents a prime opportunity for solar cell cost reduction by reducing the amount of polysilicon feedstock consumed per watt of peak solar power.
The cost associated with wire saws, amounting to about $0.25/W_pfor current silicon solar cells provides another wafer-related cost component for silicon wafer solar cells. Innovative and cost-effective technologies that eliminate the kerf losses associated with sawing and slicing should further facilitate silicon solar cell cost reductions. It is projected that the wafer-based crystalline silicon solar module manufacturing cost (which is currently on the order of $2.10 per watt to more than $2.70 per watt) may be reduced to the range of roughly $1.50/W_pto $1.80/W_pby the year 2012, in part due to wafer sawing kerf loss reduction to roughly 130 microns by 2012 from the current value of roughly 200 microns. The overall cost reductions for wafer-based crystalline silicon solar cells may come from various sources including: lower cost polysilicon feedstock, thinner wafers, higher cell-level efficiencies, reduced wafer sawing kerf losses, and increased economy of scale or manufacturing volume.
State-of-the-art silicon wafer solar cell fabrication facilities (“solar fabs”) typically produce 125 mm×125 mm up to 156 mm×156 mm solar cells today. The trend in crystalline silicon wafer solar cells is toward thinner and larger wafers. The monocrystalline and cast (as well as ribbon) multicrystalline silicon solar cell wafer thicknesses in leading-edge solar cells used for power generation modules are projected to be reduced to around 150 and 200 microns, respectively, by around 2009-2010. Any cost-effective, high-efficiency, innovative silicon solar cell technology which enables a substantial reduction of the silicon material consumption (e.g., wafer or film thickness) per W_pof cell power compared to the above-mentioned current and projected 2009-2010 numbers may offer significant promise as a viable commercial solar cell technology for solar photovoltaic applications (e.g., residential, commercial, and industrial rooftop as well as large-scale centralized utilities electrical power generation applications).
Higher solar cell efficiencies have favorable effects on the entire solar cell value chain and levelized cost of energy (LCOE in $/kWh) due to reduced material consumption and cost as well as reduced balance-of-system (BOS) costs (e.g., area-related solar module installation and inverter costs). The current mainstream commercial crystalline solar cells provide efficiencies on the order of 14% to 17%. It is expected that the projected crystalline silicon solar cell efficiencies in commercial solar cells may approach around 19% and 17% for monocrystalline and multicrystalline silicon solar cells, respectively, by the year 2009. A key area for new solar cell business opportunities is development of innovative cell structures and simplified process flows which may drive efficiencies up while lowering overall solar cell and module manufacturing costs. For alternative (e.g., thin-film PV) approaches to succeed over the mainstream wafer-based crystalline silicon solar cell technologies, they should provide higher efficiencies at even lower manufacturing costs compared to the projected efficiency and cost numbers for the mainstream wafer-based crystalline silicon solar cells when the new technology is fully commercialized.
Economy-of-scale fab cost reduction associated with high-volume solar fab capacities is a key factor impacting LCOE. The state-of-the-art high-volume solar photovoltaic fabs have annual production capacities on the order of or in excess of 50 MW_pto 100 MW_p(MW_p=1 million W_p). High-volume solar photovoltaic fab capacities are expected to increase substantially to annual production rates of several hundred MW_por even approaching 1 GW_p(GW_p=1 billion W_p) in the coming decade. While very-high-volume solar fabs in the range of 100 MW_pto 1 GW_pshould facilitate longer term cost reductions (including LCOE) through high-volume manufacturing economies of scale, the relatively high initial fab investment costs, which may easily exceed $100M, may impose certain limits on solar photovoltaic fab construction options. Ideally, the preference may be to develop innovative crystalline silicon solar cell designs and simplified manufacturing processes which facilitate substantial manufacturing cost reductions in solar cells and modules even in smaller-scale (and less capital intensive) fabs with modest production volumes (e.g., annual production volumes in the range of 5 MW_pto 50 MW_p). This type of technology would allow for modest-volume solar photovoltaic fabs with modest fab setup and operation costs. Reduced fab setup and operation costs would further facilitate global proliferation of cost-effective solar modules, enabling construction of a multitude of very affordable modest-volume fabs (in contrast to having to set up very expensive high-volume fabs in order to achieve sufficient economy of scale for manufacturing cost reduction). Of course, an innovative solar cell technology that meets the above-mentioned criteria for cost-effective, modest-volume fabs (i.e., meeting the LCOE roadmap requirements even at modest production volumes in low-cost fabs set up for simplified solar cell processing), may also be applicable to very-high-volume (e.g., greater than 100 MW_p) solar fabs. Such solar photovoltaic fabs can take further advantage of the economies of scale associated with increased volume.
Thin-film solar cell (TFSC) technologies (e.g., amorphous silicon, CdTe, and CIGS) require little absorber material (usually much less than 10 microns in thickness) to absorb typical standard “Air Mass 1.5” (AM-1.5) solar illumination due to absorption bands that are well matched to the solar spectrum. The TFSC absorber material may be deposited on inexpensive substrates such as glass or flexible metallic or non-metallic substrates. TFSCs typically offer low cost, reduced module weight, reduced materials consumption, and a capability for using flexible substrates, but are usually much lower in efficiency (e.g., usually 5% to 12%). In the case of prior art thin crystalline silicon films, there are a number of major problems and challenges with the use of flat silicon films (such as epitaxially growth silicon films with thicknesses below 50 microns) for low-cost, high-performance solar cells. These include: relatively low solar module efficiencies (typically 7% to 12%), field degradation of module efficiencies, scarce and expensive absorber materials (e.g., In and Se for CIGS and Te for CdTe), limited validation of system field reliability, and adverse environmental impact of non-silicon technologies such as CIS/CIGS and CdTe.
Prior art FIG. 1 shows process flow 10 for fabricating c-Si TFSCs using planar silicon thin-film absorber layers produced by epitaxial silicon. This prior art TFSC fabrication process flow uses several shadow mask process steps to form the cell structure. The cell absorber is simply a thin planar film of c-Si formed by silicon epitaxial growth processing. The cell uses frontside silicon texturing to improve light trapping and a detached rear aluminum mirror to improve the cell efficiency. Step 12 starts with single-crystal p⁺ CZ silicon. Step 14 involves electrochemical HF etching of silicon to form 2-layer porous silicon comprising a 1 micron top layer with 20% porosity and a 200 nanometer rear layer with greater than 50% porosity. Step 16 involves a hydrogen (H₂) anneal at 1100° C. for 30 minutes. Step 18 involves epitaxial silicon growth at 1100° C. using trichlorosilane or SiHCl₃(deposition rate of 1 micron per minute), forming 2 microns of p⁺⁻Si and 30 microns of p-Si. Step 20 involves frontside surface texturing by wet KOH etching to form upright surface pyramids. Step 22 involves the first shadow mask process, with LPCVD silicon nitride (SiN_x) deposition through a shadow mask to define emitter diffusion windows. Step 24 involves solid source phosphorus diffusion at 830° C. (to achieve 80 Ω/square for the n⁺ doped junction). Step 26 involves the second shadow mask process, with frontside metallization (titanium/Pd/silver grid) by evaporation through shadow mask. Step 28 involves emitter surface passivation by hydrogenated PVD or PECVD SiN_x. Step 30 involves contact frontside busbar by a conductive adhesive. Step 32 involves gluing the cell frontside to MgF₂-coated glass using clear glue. Step 34 involves separating the cell from silicon wafer by mechanical stress. Step 36 involves the third shadow mask process, with backside aluminum metallization using evaporation through shadow mask. Finally, step 38 involves attaching an aluminum reflector at 200 micron spacing from the cell backside.
Prior art FIG. 2 shows another process flow method 40 for fabrication of solar cells on silicon wafers with self-aligned selective emitter and metallization. This prior art process uses laser processing to pattern the top cell dielectric layer while melting the underlying silicon to form the heavily-doped n⁺⁺ emitter contact diffusion regions (after formation of the lightly diffused selective emitter regions by rapid thermal annealing). Step 42 starts with single-crystal p-type silicon. Step 44 involves saw damage removal etch and anisotropic texturing etch in dilute NaOH at 90° C. Step 46 involves spin-on application and drying of phosphorus diffusion source. Step 48 involves rapid thermal annealing to form lightly diffused emitter (80 to 200 Ω/square). Step 50 involves application of backside metal contact by vacuum evaporation or screen printing of aluminum or silver/aluminum alloy, followed by drying. Step 52 involves backside metal sintering/firing (e.g., at 820° C. in oxygen/nitrogen) for a screen-printed contact (fires the metal paste while oxidizing the dielectric to raise its resistance to the metal plating solution). Step 54 involves laser processing to pattern the top dielectric layer while melting the underlying silicon to form the n⁺⁺ contact diffusion region. Step 56 involves dilute HF etch to prepare metal plating surface. Step 58 involves electroless nickel plating at 90° C. for five minutes. Step 60 involves nickel sintering at 350° C. to 450° C. (in nitrogen, argon, or forming gas). Step 62 involves an additional 2 minutes of nickel plating followed by long electroless copper plating to form thick high-conductivity copper film. Step 64 involves flash immersion silver (silver) deposition on copper surface. Finally, step 66 involves edged junction isolation (e.g., using laser grooving, edge cleavage, or plasma etching).
With regard to the prior art crystalline silicon (c-Si) thin-film solar cell (TFSC) technology, there are difficulties associated with sufficient surface texturing of the thin silicon film to reduce surface reflectance losses, while reducing the crystalline silicon film thickness. This places a limit on the minimum flat (co-planar) monocrystalline silicon thickness due to production yield and cell performance (efficiency) considerations. In the case of a flat or co-planar film, it is essential to use surface texturing since the reflectance of an untextured crystalline silicon film is quite excessive (can be greater than 30%) and results in substantial optical reflection losses and degradation of the external quantum efficiency. Thus, reduction of reflectance-induced photon losses in co-planar epitaxial silicon films requires effective surface texturing which itself places a limit on the minimum epitaxial silicon layer thickness. Depending on the film surface texturing requirements and processes, the minimum crystalline silicon layer thickness may be on the order of at least 10 microns (so that the texturing process does not break through any portions of the crystalline silicon layer).
In addition, substantially reduced mean optical path lengths in thin planar crystalline silicon films result in reduced photon absorption, particularly for photons with energies near the infrared bandgap of silicon (800 to 1100 nanometers), resulting in reduced solar cell quantum efficiency (reduced short-circuit current or J_sc). This results in serious degradation of the solar cell efficiency due to reduced cell quantum efficiency and reduced J_sc. For instance, in a co-planar (flat) crystalline silicon absorber layer with thickness of 20 microns, a solar light beam impacting the cell at a near-normal angle would have an effective path length equal to the film thickness, far too short for the solar radiation photons with energies near the infrared bandgap of silicon (i.e., with wavelengths of roughly 800 to 1100 nanometers) to be absorbed effectively in the silicon thin film. In fact, a reduction of the active cell silicon thickness to below roughly 50 microns results in appreciable reduction of J_scand the resulting solar cell efficiency, with this degradation effect rapidly accelerating when the silicon film thickness is reduced below roughly 20 microns. Thus, a co-planar thin crystalline silicon film may also require effective light trapping using both top surface texturing and rear surface back reflection of the light exiting the back surface of the crystalline silicon film in order to create effective optical path lengths equal to a large multiple of the crystalline silicon film thickness.
The prior art technologies using this approach mostly use either back reflection through internal reflection of the light at the crystalline silicon film/silicon substrate, or reflection from a blanket backside contact (such as a back surface field aluminum contact/mirror). The back reflectance provided by these techniques may not be great (e.g., roughly 70% effective near-IR rear reflectance), constraining the performance gain that would have otherwise been achieved by an optimal back reflector. The problem with this approach is that the primary incident beam always passes the crystalline silicon film only once. Any subsequent second passes of the primary incident beam photons are dependent on the back surface reflection.
There is also the problem of lack of rigidity and mechanical support of the thin film during cell and module processing steps. This problem relates to the mechanical strength of a large-area (e.g., 200 mm×200 mm) thin silicon film. It is well known that reducing the large-area crystalline silicon wafer thickness to below 100 microns results in a substantial loss of TFSC substrate mechanical strength/rigidity, and such thin wafers tend to be flexible and very difficult to handle without breakage during cell fabrication process flow.
Large-area, co-planar (flat) crystalline silicon films thinner than, for instance, 50 microns must be properly mounted and supported on a cost-effective support or handle substrate in order to achieve acceptable yield for solar cell and module manufacturing. One approach is to grow and retain the thin epitaxial film on a relatively low-cost (e.g., metallurgical-grade) silicon substrate (over which the epitaxial layer is grown); however, this approach suffers from some inherent problems constraining the ultimate solar cell efficiency. Another approach is to release or lift off the epitaxial silicon film from its (reusable) parent silicon substrate and subsequently place it on a cheaper non-silicon support or handle substrate to provide mechanical strength through the solar cell process flow. This approach may suffer from any thermal coefficient of expansion (TCE) mismatch between the support/handle substrate and silicon film during any high-temperature oxidation and anneal processes, as well as potential contamination of the thin epitaxial silicon film from the non-silicon support substrate (both creating possible manufacturing yield and performance/efficiency degradation problems).
The cost of the monocrystalline silicon film growth process using silicon epitaxy, particularly for thicker epitaxial films with thicknesses in excess of 30 microns is an additional issue which should be addressed. Using a relatively small epitaxial film thickness (in one embodiment, much below 30 microns) may lower the cost of epitaxy to an attractive range. However, this would present various challenges for fabrication of planar silicon thin-film solar cells. As stated, thinner co-planar (flat) epitaxial films (e.g., in the range of much less than 30 microns) produce a number of problems and challenges, including a lack of film mechanical strength, constraints limiting effective surface texturing of thin silicon films for low surface reflectance and reduced optical reflectance losses, relatively short optical path lengths, and reduced cell quantum efficiencies. Effective light trapping is essential for enhanced thin-film c-Si solar cell efficiencies. The requirement for effective light trapping is based on a combination of front surface texturing and back surface mirror, while achieving sufficiently low surface recombination velocities (for high cell efficiencies). This is very difficult to achieve in the co-planar (flat) c-Si thin film solar cells.
High-performance c-Si thin-film solar cells require some patterning steps or patterned processing steps (e.g., for formation of selective emitter, frontside emitter or backside emitter wrap-through metallization contacts, backside base metallization contacts, etc.). These patterning steps are usually achieved using photolithography, screen printing, and/or shadow-mask deposition (e.g., shadow-mask sputtering or evaporation) processes. The use of photolithography and/or screen printing and/or shadow-mask deposition patterning steps usually increases the manufacturing process flow complexity and cost, and may also detrimentally impact the fabrication yield as well as the ultimate achievable solar cell efficiency.
Therefore a need has arisen for a thin-film solar cell (TFSC) which corrects the problems identified above.
Yet a further need exists to address shortcomings of existing mainstream c-Si solar cell technology. This includes reducing the amount of polysilicon feedstock consumed per peak watt of solar power, and eliminating the kerf losses associated with sawing and slicing; thus, substantially reducing the overall solar cell manufacturing cost.
A further need exists for innovative solar cell structures and simplified process flows, increasing cell and module efficiencies while significantly lowering the overall solar cell and module manufacturing costs. A still further need exists for innovative c-Si solar cell designs and simplified self-aligned manufacturing processes which facilitate substantial solar cell and module cost reduction even in fabs with modest production volumes, enabling low to mid-volume solar cell fabs with modest fab setup and operation costs (thus, achieving economies of scale for manufacturing cost reduction at substantially lower fab volumes than the prior art fabs).
A still further need exists to address shortcomings of existing TFSC technology. This includes addressing difficulties associated with sufficient surface texturing of the thin planar silicon films to reduce surface reflectance losses, which currently places a limit on the minimum flat (co-planar) crystalline silicon thickness due to production yield and cell performance considerations. A still further need exists for effective light trapping based on a combination of front surface texturing and back surface mirror, while achieving low surface recombination velocities (for high cell efficiencies).
A still further need exists to address additional shortcomings of existing TFSC technologies. This includes the problem of lack of rigidity and mechanical support of the thin film substrate during cell and module processing steps, thus, necessitating the use of support or handle substrates (made of silicon or another material) for the TFSC substrates. This further includes the cost of the epitaxial silicon film growth process, particularly for thicker epitaxial films required for planar crystalline silicon TFSCs. This further includes the requirement of multiple photolithography and/or screen printing and/or shadow-mask processing/patterning steps which usually increase the manufacturing process flow complexity and cost, and may also detrimentally impact the fabrication yield as well as the ultimate achievable solar cell efficiency.

SUMMARY

In accordance with the present disclosure, methods for manufacturing three-dimensional thin-film solar cells (3-D TFSCs) are provided. The 3-D TFSCs of the disclosed subject matter substantially eliminate or reduce disadvantages and problems associated with previously developed semiconductor wafer-based solar cells as well as TFSCs, both in terms of conversion efficiency as well as cell and module manufacturing costs.
According to one aspect of the disclosed subject matter, there is a provided a method for manufacturing a 3-D TFSC. The method comprises forming a 3-D TFSC substrate using a template. The template comprises a template substrate comprising a plurality of posts and a plurality of trenches between said plurality of posts. The 3-D TFSC substrate is formed by forming a sacrificial layer on the template, subsequently depositing a semiconductor layer, selectively etching the sacrificial layer, and releasing the semiconductor layer from the template. Select portions of the resulting 3-D TFSC substrate are then doped with a first dopant, and other select portions are then doped with a second dopant. Next, emitter and base metallization regions are formed.
More specifically, the top of the resulting 3-D TFSC substrate is selectively (with spatial selectivity) coated with a first dopant. If necessary, this first dopant is then dried and/or cured. The bottom of the resulting 3-D TFSC substrate is selectively (with spatial selectivity) coated with a second dopant. If necessary, this second dopant is then dried and/or cured. Next, emitter and base contact metallization regions are formed. Optionally, the resulting 3-D TFSC may be mounted on a rear mirror for improved light trapping and conversion efficiency.
These and other advantages of the disclosed subject matter, as well as additional novel features, will be apparent from the description provided herein. The intent of this summary is not to be a comprehensive description of the claimed subject matter, but rather to provide a short overview of some of the subject matter's functionality. Other systems, methods, features and advantages here provided will become apparent to one with skill in the art upon examination of the following FIGURES and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the accompanying claims.

BRIEF DESCRIPTIONS OF THE DRAWINGS

The features, nature, and advantages of the disclosed subject matter may become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout and wherein:

FIG. 1 (PRIOR ART) shows a prior art process flow for fabricating crystalline silicon (c-Si) thin-film solar cells (TFSCs) using planar silicon thin-film absorber layers produced by silicon epitaxy;

FIG. 2 (PRIOR ART) shows a prior art process flow for fabrication of solar cells on silicon wafers including self-aligned selective emitter and metallization;

FIG. 3 (PRIOR ART) summarizes the key process steps eliminated by the current disclosure, compared to the prior art;

FIG. 4 summarizes the high-level process flow and the competitive advantages of the current disclosure, compared to the prior art;

FIG. 5 provides another summary of the key features and benefits of the current disclosure;

FIG. 6 shows a top view of an embodiment of a hexagonal-prism TFSC including a square-shaped hexagonal-prism 3-D TFSC substrate with a planar peripheral silicon frame;

FIGS. 7A and 7B show scanning electron microscopic views of two embodiments of a hexagonal-prism 3-D TFSC, without and with a rear base layer, respectively (7A and 7B show the dual-aperture and single-aperture TFSC substrates, respectively);

FIG. 8 provides an overview of the 3-D TFSC substrate and solar cell fabrication process flow;

FIG. 9 shows a view of an embodiment of a template including hexagonal prism posts;

FIGS. 10A and 10B show magnified scanning views (with two different magnifications) of one embodiment of a template including hexagonal prism posts;

FIG. 11 shows a view of an embodiment of a template including staggered (shifted) square prism posts;

FIG. 12 shows a 3-D cross-sectional view of an embodiment of a single-aperture hexagonal-prism 3-D TFSC substrate (i.e., TFSC substrate with an integral base layer), including the substrate rear monolithically (integrally) connected to a substantially flat planar thin semiconductor film;

FIG. 13 shows the Y-Y and Z-Z cross-sectional axes on an embodiment of a hexagonal-prism (honeycomb) 3-D TFSC substrate;

FIG. 14A shows a Y-Y cross-sectional view of an embodiment of a single aperture hexagonal prism 3-D TFSC substrate, while FIG. 14B shows a Z-Z cross-sectional view;

FIGS. 15 through 20 show alternative process flow embodiments for fabricating hexagonal-prism 3-D TFSCs using single-aperture TFSC substrates including rear base layers;

FIG. 21 shows a schematic view of a double-sided coater setup for self-aligned application (coating) of dopant liquid or paste layers on 3-D TFSC substrate hexagonal-prism top ridges and hexagonal-prism rear surface or ridges by roller coating and in-line curing of the applied liquid/paste layers (shown in conjunction with an integrated belt-driven process equipment);

FIG. 22 shows a view of an alternative spray coater and curing setup to perform the same processes as the roller coater and curing setup of FIG. 21;

FIG. 23 shows a view of another alternative setup design using liquid-dip coating or liquid-transfer coating to perform the same processes as the roller coater and curing setup of FIG. 21 and the spray coater and curing setup of FIG. 22;

FIG. 24 shows multiple adjacent hexagonal-prism unit cells, after completion of the TFSC fabrication process and after mounting the cell rear base side onto a rear mirror;

FIGS. 25A through 27A show Y-Y cross-sectional views of a unit cell within an embodiment of a single-aperture hexagonal-prism 3-D TFSC substrate including a rear base layer;

FIGS. 27B through 31 show Y-Y cross-sectional views of an embodiment of a single-aperture hexagonal-prism 3-D TFSC substrate including a rear base layer, and including either a detached or an integrated rear mirror;

FIG. 32 outlines an embodiment of a process flow for fabrication of a template using photolithography patterning;

FIG. 33 shows a top view of an embodiment of a lithography mask design to produce a hexagonal array (honeycomb) pattern;

FIGS. 34 through 37 outline various embodiments of process flows for fabrication of a template using either direct laser micromachining or photolithography patterning;

FIG. 38 shows the Y-Y and Z-Z cross-sectional axes on an embodiment of a hexagonal-prism (honeycomb) 3-D TFSC substrate;

FIGS. 39 and 40 show Y-Y cross-sectional views of an embodiment of a template including through-wafer and within-wafer trenches, respectively;

FIGS. 41 through 47 show Y-Y cross-sectional views of a silicon substrate during the fabrication process flow for making an embodiment of a template based on the process flows of FIG. 36 or FIG. 37;

FIGS. 48 through 52 show Y-Y cross-sectional views of alternative embodiments of templates;

FIGS. 53 and 54 show embodiments of mask designs for patterning a semiconductor (silicon) wafer rear to produce backside openings on a template;

FIG. 55 shows an alternative frontside lithography mask with an array of hexagonal array openings for formation of template trenches and an array of holes for formation of an array of release channels from the template backside to the template frontside;

FIG. 56 shows the frontside patterning mask in FIG. 55 with a backside square array pattern (to be used for backside patterning with relative alignment as shown to the frontside pattern) superimposed for reference;

FIG. 57 shows the backside lithography mask pattern (square array) in FIG. 56 with the frontside mask hexagonal array pattern from FIG. 55 superimposed for reference;

FIGS. 58 through 66 show Y-Y cross-sectional views of a semiconductor (silicon) substrate during the fabrication process flow for making an embodiment of a template based on the process flows of FIG. 36 or FIG. 37;

FIGS. 67 through 75 show Y-Y cross-sectional views of a silicon substrate during the fabrication process flow for making an embodiment of a template based on the process flows of FIG. 36 or FIG. 37;

FIG. 76 and FIGS. 79 through 86 show Y-Y cross-sectional views of a semiconductor (e.g., silicon) substrate during the fabrication process flow for making an embodiment of a template based on the process flows of FIG. 36 or FIG. 37;

FIGS. 77 and 78 show backside lithography mask designs; FIG. 78 shows the relative alignment of the backside square array pattern with respect to the frontside hexagonal array pattern whereas FIG. 77 shows the backside square array pattern used for formation of chemical release channels on the template.

FIGS. 87 and 88 show cross-sectional views of stacked template structures for concurrently fabricating and releasing two hexagonal-prism 3-D TFSC substrates per process pass (FIGS. 87 and 88 show the stacked templates with in-wafer trenches and through-wafer trenches, respectively);

FIGS. 89 and 90 show alternative embodiments of a process flows for fabrication of self-supporting hexagonal prism 3-D TFSC substrates including rear base layers (single-aperture TFSC substrates with single-aperture unit cells);

FIGS. 91 through 95 illustrate Y-Y cross-sectional views of a template with in-wafer trenches and no dielectrics on the template frontside, as it goes through the key process steps to fabricate a hexagonal prism 3-D TFSC substrate (single-aperture TFSC substrate) with a rear base layer; FIGS. 94 and 95 show the released 3-D TFSC substrate with a base layer and the reusable template after the 3-D TFSC substrate release, respectively.

FIGS. 96 through 98 illustrate Y-Y cross-sectional views of the template in FIG. 66 with the rear-to-front release channels, as it goes through the key process steps to fabricate a hexagonal-prism 3-D TFSC substrate (single-aperture TFSC substrate) with a rear base layer (template is made on <100> silicon substrate);

FIGS. 99 through 101 illustrate Y-Y cross-sectional views of the template in FIG. 75 with the rear-to-front release channels, as it goes through the key process steps to fabricate a hexagonal-prism 3-D TFSC substrate (single-aperture TFSC substrate) with a rear base layer (template is made on <110> silicon substrate);

FIGS. 102 through 104 illustrate Y-Y cross-sectional views of the template in FIG. 85 with backside release channels aligned to the bottom of hexagonal-prism trenches, as it goes through the key process steps to fabricate a hexagonal-prism 3-D TFSC substrate with a rear base layer (single-aperture TFSC substrate);

FIGS. 105A through 111C show examples of several embodiments of 3-D polygon-prism TFSC substrates including various prism unit cell geometrical designs and arrangements;

FIGS. 112 through 117 show alternative process flow embodiments for fabricating hexagonal-prism 3-D TFSCs using dual-aperture TFSC substrates without rear base layers;

FIG. 118A shows a schematic Y-Y cross-sectional view of an embodiment of a self-supporting (free-standing) hexagonal-prism dual-aperture 3-D TFSC substrate (without a base layer) including a thin peripheral semiconductor (silicon) frame, before 3-D TFSC fabrication;

FIG. 118B shows a schematic Y-Y cross-sectional view of the 3-D TFSC substrate of FIG. 118A after TFSC fabrication;

FIG. 119A shows a schematic Y-Y cross-sectional view of an embodiment of a self-supporting (free-standing) hexagonal-prism dual-aperture 3-D TFSC substrate including a thick peripheral semiconductor (silicon) frame, before TFSC fabrication;

FIG. 119B shows a schematic Y-Y cross-sectional view of the TFSC substrate of FIG. 119A after cell fabrication;

FIG. 120 shows a top view of an embodiment of a regular (equilateral) hexagonal-prism 3-D TFSC substrate;

FIG. 121 shows a 3-D view of an embodiment of a hexagonal-prism 3-D thin-film semiconductor substrate after release and removal from a template;

FIG. 122A shows a schematic Y-Y cross-sectional view of an embodiment of a dual-aperture hexagonal-prism 3-D TFSC substrate, while FIG. 122B shows a Z-Z cross-sectional view of the same substrate;

FIGS. 123A through 124B show schematic Y-Y cross-sectional views of a single unit cell from a dual-aperture 3-D TFSC substrate within an embodiment of a hexagonal-prism 3-D TFSC fabricated using a 3-D TFSC substrate without a rear base layer;

FIGS. 125A and 125B show Y-Y cross-sectional views of a single unit cell from a dual-aperture 3-D TFSC substrate after mounting the cell onto a rear mirror;

FIGS. 126A through 127 show Y-Y cross-sectional views of multiple unit cells from a dual-aperture 3-D TFSC substrate, after mounting onto a rear mirror (with and without a spacing between the mirror and the rear cell);

FIGS. 128A through 132 show schematic Y-Y cross-sectional views of an embodiment of a hexagonal-prism 3-D TFSC formed on a dual-aperture 3-D TFSC substrate without a rear base layer, with substantially vertical hexagonal-prism sidewalls;

FIGS. 133A and 133B show 3-D views of a single unit cell in a dual-aperture hexagonal-prism 3-D TFSC substrate, before and after self-aligned base and emitter contact metallization, respectively;

FIG. 134 shows multiple adjacent hexagonal-prism unit cells, after completion of the TFSC fabrication process and after mounting the cell rear base side onto a rear mirror;

FIG. 135 shows an embodiment of a process flow for fabrication of self-supporting hexagonal prism 3-D TFSC substrates using layer release processing;

FIGS. 136 through 141 show alternative embodiments of process flows for fabrication of self-supporting hexagonal-prism (as well as other prism array patterns) 3-D TFSC substrates without rear base layers (to form dual-aperture TFSC substrates; i.e., TFSC substrates with top and bottom unit cell openings);

FIGS. 142 through 146 show Y-Y cross-sectional views of the evolution of one prism unit cell of a template with through-wafer trenches, as it goes through several key process steps for fabricating a hexagonal-prism 3-D TFSC substrate (dual-aperture TFSC substrate) without a rear base layer;

FIGS. 147 through 150 illustrate Y-Y cross-sectional views of an embodiment of a template with in-wafer trenches and no dielectric layers on the template frontside or template backside, as it goes through several key process steps for fabricating a hexagonal-prism 3-D TFSC substrate (dual-aperture TFSC substrate) without a rear base layer;

FIGS. 151 through 154 illustrate Y-Y cross-sectional views of an embodiment of a template with through-wafer trenches and no dielectrics on the template frontside, as it goes through several key process steps for fabricating a hexagonal-prism 3-D TFSC substrate (dual-aperture TFSC substrate) without a rear base layer;

FIG. 155 shows a schematic view of a single unit cell from an embodiment of a hexagonal-prism 3-D TFSC substrate for reference including certain TFSC substrate calculations;

FIG. 156 shows a graph of the computed 3-D TFSC substrate hexagonal-prism area ratio (ratio of 3-D cell surface area to the flat cell base area) versus hexagonal-prism aspect ratio (unit cell height to aperture diameter ratio);

FIG. 157 shows a graph of the ratio of the hexagonal-prism TFSC substrate mass to a reference flat semiconductor wafer mass for both types of 3-D honeycomb-prism TFSC substrates (single and dual aperture substrates), versus various ratio of the honeycomb-prism sidewall silicon thickness to the reference flat silicon wafer thickness;

FIG. 158 shows a schematic diagram of ray tracing for solar rays incident on a dual-aperture hexagonal-prism unit cell employing reflective emitter metallization contact;

FIGS. 159 through 162 show various numbers of solar light rays incident at various angles of incidence, demonstrating efficient light trapping characteristics of the current disclosure;

FIG. 163 shows simulated light trapping in a unit cell and short circuit current density versus angle of incidence for various emitter contact metallization embodiments of the solar cell designs of the current disclosure;

FIG. 164 shows Standard Test Condition (STC) cell efficiency and short-circuit current density for the solar cell of the current disclosure versus unit cell prism height;

FIG. 165 shows maximum photocurrent density versus incident angle, also indicating the effect of emitter contact metallization (assuming 100% optical reflectance for emitter contact metal);

FIG. 166 shows a graph of the representative selective emitter phosphorus and 3-D TFSC substrate boron doping profiles in hexagonal-prism 3-D TFSCs of this disclosure, shown with graded boron doping profile to create a built-in electric field;

FIG. 167 serves as a reference FIGURE for calculation of the hexagonal-prism TFSC internal ohmic losses due to the base current along the hexagonal-prism vertical sidewalls;

FIG. 168 shows maximum base resistivity and approximate p-type base doping concentration values for various 3-D honeycomb-prism sidewall film thicknesses in order to limit the base current ohmic losses to less than 0.1%;

FIG. 169 shows various views of silicon frames and silicon frame slivers for the hexagonal-prism TFSCs of the current invention;

FIG. 170 shows a view of series connections of TFSCs in a solar module assembly;

FIG. 171 shows a view of the frontside metallization pattern of a printed-circuit board (PCB) used for solar module assembly using the TFSCs of the current disclosure;

FIGS. 172 and 173 show views of the backside metallization pattern of a PCB used for solar module assembly using the TFSCs of the current disclosure;

FIG. 174A shows an enlarged top view of the frontside of a solar module PCB, showing one of the PCB patterned metallization sites for placement of one of the solar cells of the current disclosure;

FIG. 174B shows an enlarged top view of the backside of a solar module PCB, showing the series connections of the adjacent cells on the PCB;

FIG. 175 shows a cross-sectional view of an embodiment of a solar module structure comprising the TFSCs of the current disclosure and a tempered glass cover;

FIG. 176 shows an embodiment of a process flow for fabrication of solar modules using a tempered glass cover;

FIG. 177 shows a cross-sectional view of an embodiment of a solar module structure comprising the TFSCs of the current disclosure and a coated layer cover;

FIG. 178 shows an embodiment of a process flow for fabrication of solar modules without a tempered glass cover;

FIGS. 179 and 180 show cross-sectional views of a solar glass assembly for building façade applications;

FIG. 181 shows a view of an electrically conductive layer formed on a glass plate to interconnect cells in series for solar glass applications;

FIG. 182 shows an embodiment of a process flow for fabrication of solar modules for solar glass applications;

FIG. 183 serves as a reference FIGURE for calculation of TFSC interconnect ohmic losses; and

FIGS. 184 through 189 show graphs of interconnect (emitter contact metallization) ohmic losses at maximum cell power versus the ratio of emitter contact metal coverage height for various emitter metal sheet resistance values.

DETAILED DESCRIPTION OF THE SPECIFIC EMBODIMENTS

Preferred embodiments of the present disclosure are illustrated in the drawings, like numbers being used to refer to like and corresponding parts of the various drawings. The innovative solar cell designs and technologies of the current disclosure are based on the use of a three-dimensional (3-D), self-supporting, doped (in one embodiment, in-situ-doped) semiconductor thin film, deposited on and released from a reusable crystalline (embodiments include monocrystalline or multicrystalline silicon) semiconductor template.
A preferred semiconductor material for the 3-D TFSC substrate is crystalline silicon (c-Si), although other semiconductor materials may also be used. One embodiment uses monocrystalline silicon as the thin film semiconductor material. Other embodiments use multicrystalline silicon, polycrystalline silicon, microcrystalline silicon, amorphous silicon, porous silicon, and/or a combination thereof. The designs here are also applicable to other semiconductor materials such as germanium, silicon germanium, silicon carbide, a crystalline compound semiconductor, or a combination thereof. Additional applications include copper indium gallium selenide (CIGS) and cadmium telluride semiconductor thin films.
The 3-D TFSC designs and production technologies as well as associated module structures and assembly approaches of this disclosure effectively overcome the above-mentioned problems and challenges and enable cost-reduced fabrication of very-high-efficiency solar cells and modules using self-aligned cell process flows without the use of any photolithography patterning or screen printing or shadow-mask deposition process steps during cell fabrication (i.e., during 3-D TFSC substrate and cell fabrication after fabrication of the reusable 3-D template). The 3-D TFSC technologies of this disclosure are based on the formation of a 3-D prism-array TFSC substrate structure on a low-cost reusable template and its subsequent release and lift-off from the template to form a free-standing, self-supporting 3-D thin-film semiconductor substrate structure.
The current disclosure combines the benefits of TFSC fabrication on a proven high-efficiency crystalline silicon (c-Si) platform. The 3-D c-Si TFSC designs and technologies of this disclosure enable significant advancements in the areas of c-Si solar cell and module efficiency enhancement as well as manufacturing cost reduction. Based on innovative thin-film process steps, dependence on an expensive and constrained silicon wafer supply-chain is eliminated. Some of the unique advantages of the cells designs and technologies of this disclosure which enable achieving ultra-high-efficiency at reduced manufacturing cost are substantial decoupling from the traditional solar PV silicon supply chain, performance enhancement, cost reduction, and reliability improvement.
The disclosed subject matter improves solar cell efficiency by using a 3-D c-Si film as an absorber layer in conjunction with highly efficient light trapping. Use of the crystalline silicon absorber layer leverages known solar cell manufacturing techniques and supply chain, while reducing absorber layer thickness (e.g., reduced by a factor of ten or more compared to silicon wafers used for wafer-based solar cells). The disclosed method and system eliminates or substantially reduces photo-degradation and enhances open-circuit voltage (V_oc) of cells. In addition, the disclosed method and system provides efficient frontside and rear side light-trapping in conjunction with a highly reflective rear mirror for maximum absorption of incident solar flux. Also, the disclosed method and system provides a selective emitter to enhance blue response and external quantum efficiency, with minimal shadowing of the cell and reduced ohmic losses due to a unique folded emitter metallization contact design and improved module assembly.
Manufacturing cost is reduced by decreasing silicon usage (by a significant factor, e.g., 3× to over 10×), with thinner deposited c-Si films also reducing the finished solar module energy payback time to less than 1 to 2 years. Manufacturing cost is further reduced by eliminating wire sawing and related kerf losses associated with mainstream solar cell wafer manufacturing technology. Manufacturing cost is still further reduced by using self-aligned processing without any lithography or patterning steps used during the substrate and cell fabrication process flow, and a reduced number of fabrication process steps, with improved yield and cycle time. Production cost is still further reduced by using a simplified interconnection and cell-module assembly process and lightweight monolithic modules.
Operational reliability is improved by using thinner silicon films, eliminating photo-degradation and reducing temperature coefficients. Operational reliability is further improved by using a simple distributed high-conductance electrical interconnection, minimizing field failures. Operational reliability is still further improved by eliminating module glass cover (for glassless module assembly), thus reducing cost and facilitating field installation and operation. Operational reliability is still further improved by reducing the number of manufacturing process steps and process variations using in-line manufacturing process control.
The current disclosure reduces the solar module cost per watt for the user (by at least 30% to 50%) and cuts balance-of-system (BOS) and installation costs for the integrators and installers. This may offer major benefits to the global grid-tied end-users and solar system installers and integrators. The current disclosure reduces the module integration and installation cost and installed solar cell system cost per W_pfor the user, thereby lowering finished system cost per W_p. The current disclosure increases module efficiency, with higher module efficiency resulting in lower BOS cost. The lower installed solar cell system cost results in reduction of the economic break-even time to a lower fraction of the system lifetime, from roughly ½ to ⅓ for current best-of-breed c-Si solar cell systems to less than ¼ to ⅛ for the embodiments of this disclosure. The current disclosure reduces energy pay-back time (EPBT) from 3 to 7 years for best-of-breed c-Si solar cell systems to less than 1 to 2 years for the embodiments of this disclosure. Reduced EPBT substantially increases the net lifetime energy output (in kWh) for field-installed modules. The cell designs and module assemblies of this disclosure also provide stable degradation-free field operation over an extended time (e.g., 30 to 40 year life of the module), further increasing the net lifetime electrical energy output. Module manufacturing costs are expected to be 30% to 65% lower than that of the leading high-performance c-Si solar cells/modules at the time of market entry. This may shorten the ROI break-even time for the users compared to the current industry roadmap and projections. Further benefits include increased field performance stability and reliability and reduced environmental impact (non-toxic materials and shortened EPBT). Further, the cell and module designs of this disclosure are ideal for grid-tied applications where it is advantageous to maximize electricity generation from a limited building rooftop or façade area.
The absorber silicon film thickness of the current disclosure may be a value in the range of roughly 1 to 30-microns, where a thinner silicon layer is preferred for less material consumption (in one embodiment, in the range of 1 to 10 microns). Even after taking into account the effective surface area increase due to the 3-D geometric structure of the 3-D TFSC substrates, the 3-D TFSC substrates of this disclosure consume substantially less silicon material than the state-of-the-art wafer-based c-Si solar cells. Moreover, there are no sawing or kerf losses. Similarly, there is no requirement for saw damage removal since the 3-D crystalline silicon film is process-ready upon release from the reusable template. This substantially reduces the solar cell cost associated with silicon consumption. The self-supporting 3-D epitaxial silicon thin film is deposited on and released from a low-cost reusable crystalline (monocrystalline or multicrystalline) silicon substrate (template). The template may be reused numerous times before being reconditioned or recycled. The template may even be chosen from the much lower cost metallurgical-grade c-Si since any metallic impurities are prevented from contaminating the 3-D crystalline silicon film.
FIG. 3 summarizes the overall crystalline solar cell fabrication process flow of prior art techniques and highlights the specific steps eliminated by the current disclosure, compared to the prior art. FIG. 4 summarizes the overall cell and module fabrication process flow and the competitive advantages of the current disclosure, compared to the prior art. As highlighted here, the current disclosure enables fabrication of 3-D thin-film solar TFSC substrates and cells, thus, substantially reducing consumption of semiconductor absorber material (e.g., silicon) and the cell and module manufacturing costs. FIG. 5 provides another summary of the benefits of the embodiments of the current disclosure.
The 3-D TFSCs of the disclosed subject matter utilize a 3-D TFSC substrate which has a plurality of unit cell cavities to capture and substantially trap solar light on the substrate frontside, while the substrate backside includes a continuous thin semiconductor layer which is attached to the rear sides of the unit cell cavities.
FIG. 6 shows a top view 100 of a hexagonal-prism 3-D TFSC with a peripheral planar silicon frame 102. The top surface of the frame 102 may also be used as the top 3-D TFSC interconnect and may be used to produce a wrap-through or wrap-around emitter metallization for making contacts to the cell emitter at the bottom of the cell (in module assembly). The frame 102 is metallized, along with the top hexagonal emitter contacts, and is electrically connected to the hexagonal emitter contacts. The frame 102 may have the same thickness as the 3-D TFSC substrate or may be much thicker. In one embodiment, frame width 104 is between 5 and 500 microns. The hexagonal prism 3-D TFSC substrate is composed of hexagonal-prism unit cells 106. In one embodiment, the width 108 of the silicon film forming the sidewalls of the hexagonal prism unit cell is preferably 2 to 30 microns, and more preferably 2 to 10 microns. Typically, there are thousands to millions of hexagonal-prism unit cells 106 on a large-area 3-D TFSC. In one embodiment, frame length (S) 110 ranges from 125 to over 200 millimeters (e.g., 210 mm×210 mm). The hexagonal-prism 3-D TFSC substrates of this disclosure may have a thin silicon frame, a thick silicon frame, or no peripheral frame at all.
FIGS. 7A and 7B show microscopic views of 3-D TFSC substrates of a 3-D TFSC as illustrated in FIG. 6. FIG. 7A shows a view of a dual-aperture TFSC substrate without a base layer whereas FIG. 7B shows a view of a single-aperture TFSC substrate with a base layer.
FIG. 8 provides an overview of the 3-D TFSC substrate and cell fabrication process flow. Focusing on the top of FIG. 8 illustrating the 3-D TFSC substrate fabrication, note that the first step in this process flow uses a pre-fabricated template. The template with a pre-fabricated 3-D trench or groove pattern may be used for formation of 3-D TFSC substrates, which are then used in the formation of 3-D TFSCs, substantially eliminating or reducing disadvantages and problems associated with previously developed TFSCs and the wafer-based crystalline silicon cell technologies. The template is capable of being used numerous times (e.g., tens to hundreds of times) to fabricate numerous 3-D TFSC substrates before being reconditioned or recycled. In one embodiment, the template may be used hundreds of times to fabricate 3-D TFSC substrates before being recycled. The template may be reused for as long as it remains relatively free of dislocations and/or for as long as it maintains an acceptable trench or groove pattern with widths and surface conditions within acceptable control limits (e.g., as gauged by in-line metrology).
FIG. 4 shows a view 120 of a template with hexagonal-prism posts (pillars) 122. A hexagonal-prism 3-D TFSC substrate (not shown) is fabricated by first forming a suitable relatively conformal thin sacrificial layer (in one embodiment, porous silicon) on the template, then filling in the relatively deep trenches 124 between hexagonal-prism posts 122, and subsequently releasing the hexagonal prism 3-D TFSC substrate by selectively etching the sacrificial layer (not shown) deposited between the hexagonal-prism 3-D TFSC substrate and the template. In one embodiment, the template has deep interconnected hexagonal-prism trenches with slightly tapered sidewalls (i.e., larger trench widths near the top of the trenched compared to near the bottom of the trenches. Moreover, the trench widths near the top of the trenches may be made about one to several microns larger than the trench widths near the bottom of the trenches. FIGS. 10A and 10B show magnified views of one embodiment of a template with hexagonal-prism posts 122 and trenches 124. This embodiment was prepared using photolithography and deep reactive-ion etching (DRIE).
Note that the terms “honeycomb” and “hexagonal” are used interchangeably throughout this disclosure. The term “honeycomb” refers to the fact that embodiments of the 3-D TFSC substrates resemble a natural honeycomb.
FIG. 11 shows a view 130 of an alternative embodiment of a template (or master stencil) with staggered square prism posts 132. A square-prism 3-D TFSC substrate (not shown) is formed by first depositing or forming a relatively conformal sacrificial layer (e.g., porous silicon), filling in the trenches 134 between square prism posts 132, and subsequently releasing the 3-D TFSC substrate by selectively etching the sacrificial layer formed between the 3-D TFSC substrate and the template.
FIG. 12 shows a schematic view 140 of a hexagonal-prism single-aperture 142 3-D TFSC substrate with prism sidewalls 144, with the hexagonal-prism 3-D TFSC substrate rear side 146 monolithically connected to a relatively flat planar thin film 148 (rear base layer).
FIG. 13 shows a schematic magnified top view 150 of a regular (equilateral) hexagonal-prism 3-D TFSC substrate showing a plurality of prism unit cells. Each hexagonal unit cell 106 contains hexagonal unit cell boundary points (H₁, H₂, H₃, H₄, H₅, and H₆) 152, 154, 156, 158, 160, 162. FIG. 13 shows the hexagonal-prism 3-D TFSC substrate sidewalls 144; the long diagonal dimension of the unit cell hexagon (d) 164; and the short diagonal dimension of the hexagonal unit cell (h) 166. In one embodiment, the hexagonal-prism 3-D TFSC substrate sidewalls 144 are between 2 and 30 microns thick.
FIG. 14A shows a Y-Y cross-sectional view 170 of the hexagonal-prism single-aperture 3-D TFSC substrate with a rear base layer shown in FIG. 12. FIG. 14B shows a Z-Z cross-sectional view 180 of the hexagonal-prism 3-D TFSC substrate shown in FIG. 12. These FIGURES also show the hexagonal thin silicon walls 144 monolithically attached to the rear base layer 148. Note that the 3-D TFSC substrate has height 172 in both FIGUREs.
FIGS. 15 through 20 show six different process flow embodiments of this disclosure for fabricating single-aperture hexagonal-prism 3-D TFSCs with rear base layers. While these process flow embodiments are outlined for fabricating silicon-based TFSCs, the overall concepts and methodologies may be extended and applied to other homojunction and heterojunction semiconductor materials (such as multicrystalline silicon, polycrystalline silicon, CIGS, etc.). While the process flows shown are for fabrication of 3-D c-Si TFSCs, the embodiments may be easily adjusted and modified to fabricate silicon-based TFSCs using polysilicon, amorphous silicon, and/or multicrystalline silicon films.
FIGS. 15 through 20 show six different process flow embodiments 190, 220, 250, 280, 310, and 340 of this disclosure for fabrication of single-aperture hexagonal-prism 3-D TFSCs with rear base layers (i.e., the honeycomb-prism structures have a monolithically attached thin base layer). These embodiments may use one of the templates described and shown previously. These TFSC substrates may be fabricated using templates with trenches with shallow wider trenches (shoulders) on top of deeper narrower trenches (or using deep trenches with flared out regions on top of the trenches, that is, trench widths larger on the top of the deep trenches compared to the trench widths in the lower sections of the deep trenches). These six embodiments all result in single-aperture hexagonal-prism 3-D TFSCs with self-aligned selective emitter and base diffusion regions in silicon as well as self-aligned emitter and base contact metallization regions. While shown for crystalline silicon (c-Si) cells, the methodologies of these embodiments may also be extended and applied to polysilicon/amorphous silicon as well as non-Si TFSCs. These embodiments include either detached rear mirrors (for instance, mirrors provided by silver-coated copper or silver-coated aluminum pads on solar module printed-circuit boards) or preferably integrated/attached rear mirrors deposited directly on the rear surface of the cell passivation dielectric (e.g., on thermal oxide) layer on the rear base layer. Both the detached and integrated/attached mirrors may also serve as the base interconnect planes (electrically connected to the hexagonal base contact metallization). In one embodiment, the material for a high-reflectivity mirror is silver (alternatively, aluminum may be used).
FIG. 15 shows a process flow 190 for fabrication of single-aperture hexagonal-prism 3-D TFSCs with rear base layers using self-aligned selective plating metallization with boron-doped p⁺⁺ rear base contacts by selective base doping (besides selective emitter doping). This hexagonal-prism 3-D TFSC with rear base layer uses a detached rear mirror (i.e., rear mirror is not an integrated layer directly deposited on the rear base layer). In step 192, cell processing starts with a single-crystal (or multicrystalline or polycrystalline) p-type (for n-type selective emitter), 3-D silicon TFSC substrate (e.g., a 3-D array of honeycomb hexagonal prisms). As with any other cells in this disclosure, the substrate doping polarity may be changed to n-type (for p-type selective emitter). The 3-D honeycomb prism TFSC substrate has open top apertures and no rear apertures (due to the rear base layer). There is a rear relatively flat base silicon layer monolithically and integrally attached to the honeycomb-prism cell. Step 194 involves selectively coating the top ridges of the 3-D honeycomb prisms (in one embodiment, the top 2 to 10 microns) with an n-type dopant source. In one embodiment, this n-type dopant source is phosphorus. Selective coating may be done by self-aligned roller coating using paste/liquid source, liquid-dip coating by dipping in a known liquid source depth, ink-jet coating, or spray coating. Next, the n-type dopant source layer is dried and cured (e.g., by thermal curing at 250° C. to 400° C. or UV irradiation). Step 196 involves selectively filling the rear base troughs on the substrate backside with a p-type liquid/paste dopant source layer. In one embodiment, the p-type dopant source is boron. Selective filling may be done by boron source layer coating (e.g., roller, spin-on, ink-jet, or spray coating) followed by selective etch-back (e.g., by solvent spin-on) to form filled troughs. Next, the p-type dopant source layer is dried and cured (e.g., by thermal curing at 250° C. to 400° C. or UV exposure). Step 198 involves forming self-aligned selective emitter and base regions. The top n⁺⁺p emitter diffusion contact, top aperture n⁺p selective emitter junctions, rear p⁺⁺ base contacts and selectively doped p⁺base regions (the latter are optional) are concurrently formed. This may be done using thermal anneal in a diffusion furnace at 800° C. to 950° C. In one embodiment, the 3-D TFSC substrate is annealed while placed in an in-line diffusion furnace, or with stacks of 3-D TFSC substrates in face-to-face contact to facilitate vapor-phase doping formation of n⁺ emitter and p⁺ base. Step 200 involves surface passivation (oxidation), where a thermal oxide layer is grown, in one embodiment by steam oxidation (e.g., 10 to 200 nanometers at 800° C. to 950° C.). Step 200 may be merged into the prior diffusion step in multi-zone furnace, to be performed sequentially after the selective emitter and base diffusion step. In one embodiment, the diffusion/oxidation steps result in selective emitter and emitter contact sheet resistance values of 80-150 Ω/square and 10-70 Ω/square, respectively. Step 202 involves selective etching of the cured layers in preparation for self-aligned metallization. The dopant source layers are selectively etched (i.e., the n-type coating on top honeycomb prism ridges and the p-type coating in rear filled troughs) with a suitable dielectric etchant (e.g., an HF-based etchant) with high selectivity with respect to thermal oxide. This selectively strips the cured doped and undoped dielectrics on the top and rear portions of the substrate and exposes silicon in those regions, while removing only a small fraction of thermal oxide from other 3-D TFSC substrate regions. Step 204 involves self-aligned metallization (in one embodiment, by plating). The front and rear emitter and base metallized regions are concurrently formed using selective electroplating and/or electroless plating and/or galvanic plating to form single or multilayer high-conductivity metallized regions (silver, aluminum, nickel, titanium, cobalt, tantalum). For instance, the plated metal stack may include a thin (50 to 500 nanometers) barrier and adhesion layer such as nickel (nickel) followed by a relatively thick (2 to 15 microns) layer of high-conductivity metal (silver or copper or aluminum). If a high-conductivity metal other than silver is used for the thick metallization layer, a final flash coat of silver may be used to create a high-reflectivity surface coating in order to improve light reflection and trapping into the 3-D cells (by the emitter metallization contact). Step 206 involves an optional forming-gas anneal. A forming gas anneal may be performed (e.g., 350° C. to 450° C.) to reduce front and rear interconnect resistance values and help with surface/bulk passivation. Step 208 involves mounting honeycomb prism TFSC rear side (base side) onto a highly reflective (diffuse with a rough surface or specular with a smooth surface) rear mirror. This rear mirror may be made of an silver-coated aluminum or copper foil and may also serve as the TFSC base interconnect plane on a printed-circuit board (PCB) in a solar module. Step 210 involves an optional step of depositing a passivation and ARC layer on mounted cells. In one embodiment, this passivation and ARC layer is PVD or PECVD SiN_xwith thickness between 50 and 200 nanometers. Step 212 involves proceeding with packaging the honeycomb prism TFSCs in solar module assembly.
FIG. 16 shows an alternative process flow 220 for fabrication of single-aperture hexagonal-prism 3-D TFSCs with rear base layers using self-aligned selective plating metallization without boron-doped p⁺⁺ rear base contacts by selective base doping. The p⁺⁺ base contact doping is performed by aluminum doping using aluminum from base contact metallization and an anneal (contact firing process). As in FIG. 15, this process flow uses cured phosphorus source layer and a thermal anneal to form the n⁺ phosphorus-doped selective emitter regions and the n⁺⁺ phosphorus-doped emitter contact diffusion regions. This single-aperture hexagonal-prism 3-D TFSC with rear base layer also uses a detached rear mirror (i.e., rear mirror is not an integrated layer directly deposited on the rear base layer). Step 222 (providing a substrate) corresponds to step 192 of FIG. 128; and step 224 (selective coating) corresponds to step 194. Step 226 (selective filling) involves selectively filling the rear base troughs on the TFSC substrate backside with an undoped sealant dielectric (e.g., oxide and/or nitride) using a dielectric liquid/paste source layer. Selective filling may be done by undoped dielectric source layer coating (e.g., roller, spin-on, ink-jet, or spray coating) followed by selective etch-back (e.g., by solvent spin-on) to form filled troughs. Next, the undoped dielectric source layer is dried and cured (e.g., by thermal curing at 250° C. to 400° C. or UV exposure). Step 228 involves self-aligned selective emitter and base. The top n⁺⁺p emitter contact and honeycomb top apertures n+p selective emitter junctions are concurrently formed using thermal anneal at 800° C. to 950° C. In one embodiment, the 3-D TFSC substrate may be annealed while placed in an in-line diffusion furnace, or with stacks of 3-D TFSC substrates in face-to-face contact to facilitate vapor-phase doping formation of n+p selective emitter and n⁺⁺p emitter contact regions. Step 230 (surface passivation oxidation) corresponds to step 200 of FIG. 15. Step 232 involves selective etching of the cured layers in preparation for self-aligned metallization. The dopant source layer (i.e., the n-type coating on top honeycomb prism ridges) and the undoped dielectric filling in rear filled troughs) are selectively etched with a suitable etchant (e.g., an HF etchant) with high selectivity with respect to thermal oxide. This selectively strips the cured dopant source dielectrics on the top and rear portions of the 3-D TFSC substrate and exposes silicon in those regions, while removing only a small fraction of thermal oxide from other 3-D TFSC substrate regions. Step 234 involves self-aligned metallization (embodiments include electroless plating, galvanic plating, and/or electroplating). The rear base aluminum metallized regions are selectively formed by selective electroplating or electroless plating. In one embodiment, this aluminum plating process limited to the rear base regions. Step 236 involves an anneal or firing process to form rear aluminum-doped p⁺ contacts. An optional forming gas anneal (e.g., 350° C. to 450° C.) is performed to reduce interconnect resistance and help with surface/bulk passivation. Step 238 involves self-aligned metallization (plating). A suitable high-conductivity metal such as silver or copper (e.g., 2 to 12 microns) is selectively/concurrently deposited on the top honeycomb ridges (emitter) and rear aluminum-filled troughs (aluminum metallized base contacts) by plating. If necessary, the plating process may first involve selective deposition of a suitable refractory metal barrier and adhesion layer (e.g., 50 to 200 nanometers nickel) followed by the deposition of the thicker higher conductivity metal (silver and/or copper). If necessary, the metallized regions are then flash coated with a thin layer of silver in order to establish a high optical/IR reflectivity (this step may be merged into the prior plating step). If silver is used as the main metallization layer, then the top solver flash coating may not be needed. Step 240 (mounting) corresponds to step 208 of FIG. 15; step 242 (ARC layer) corresponds to step 210; and step 244 (proceeding with packaging) corresponds to step 212.
FIG. 17 shows another alternative process flow 250 for fabrication of hexagonal prism 3-D TFSCs with rear base layers using self-aligned selective plating metallization with boron-doped p⁺⁺ rear base contacts by selective base doping (besides selective emitter doping). This single-aperture hexagonal-prism 3-D TFSC with rear base layer uses an integrated rear mirror which is directly deposited (e.g., silver or aluminum formed by sputtering, evaporation, or another method such as non-selective plating) on the rear base passivation dielectric layer (the rear base passivation layer may be a thermal oxide layer). Optionally, the rear base passivation dielectric (e.g., oxide) layer surface may be treated (e.g., with plasma) to produce a rough dielectric surface (e.g., with an RMS surface roughness in the range of tens to hundreds of nanometers) prior to mirror layer deposition. This may produce a diffuse integrated mirror directly on the rear surface of the rear base layer passivation layer. Alternatively, the TFSC substrate may already be textured as a result of using a textured template, resulting in a diffuse rear mirror.
Step 252 (providing a substrate) corresponds to step 222 of FIG. 16; and step 254 (selective coating) corresponds to step 224. Step 256 involves selectively filling the rear base troughs on the 3-D TFSC substrate backside with p-type (e.g., boron) liquid/paste dopant source. This may be done by boron source layer coating (e.g., roller, spin-on, ink-jet, or spray coating) followed by etch-back (e.g., by solvent spin-on) to form filled troughs. The layer is then dried and cured (using thermal curing at 250° C. to 400° C. or UV exposure). Step 258 involves self-aligned selective emitter and base. The top n⁺⁺p emitter contact, honeycomb top apertures n+p selective emitter junctions, the rear p⁺⁺ base contact and selectively doped p⁺ base regions are concurrently formed using thermal anneal at 800° C. to 950° C. In one embodiment, the 3-D TFSC substrate is annealed while placed in an in-line diffusion furnace, or with stacks of 3-D TFSC substrates in face-to-face contact to facilitate vapor-phase doping formation of n⁺ emitter and p⁺ base. Step 260 (surface passivation oxide) corresponds to step 230 of FIG. 16. Step 262 involves selective etching of the cured layers in preparation for self-aligned metallization. The dopant source layers (i.e., the n-type coating on top honeycomb prism ridges and the p-type coating in rear filled troughs) are selectively etched with a suitable dielectric etchant (e.g., an HF-based etchant) with a relatively high selectivity with respect to thermal oxide. This selectively strips the cured dopant layers on the top and rear portions of the 3-D TFSC substrate and exposes silicon in those regions, while removing only a small fraction of thermal oxide from other 3-D TFSC substrate regions (e.g., thermal oxide coating remains on all selective emitter regions and rear base backside regions outside the base contact area). Step 264 involves an optional plasma treatment step. A plasma treatment process may be performed to roughen the thermal oxide layer on the substrate backside (for integrated diffuse rear mirror). Step 266 involves self-aligned metallization (plating). The front and rear emitter and base metallized regions are concurrently formed using selective electroplating and/or electroless plating and/or galvanic plating to form single or multilayer high-conductivity metallized regions (silver, aluminum, nickel, titanium, cobalt, tantalum). For instance, the plated metal stack may include a thin (50 to 500 nanometers) barrier and adhesion layer such as nickel (nickel) followed by a relatively thick (2 to 15 microns) layer of high-conductivity metal (silver or copper or aluminum). If a high-conductivity metal other than silver is used for the thick metallization layer, a final flash coat of silver may be used to create a high-reflectivity surface coating in order to improve light reflection and trapping into the 3-D cells (by the emitter metallization contact). Step 268 involves an optional forming gas anneal step is (e.g., performed at 350° C. to 450° C.) to reduce front and rear interconnect resistance values and help with surface/bulk passivation. Step 270 involves addition of an integrated rear cell mirror. A thin (e.g., 50 to 1000 nanometers) layer of high-reflectance metal (silver and/or aluminum, among others) is deposited on TFSC substrate backside (e.g., by PVD, non-selective plating, or evaporation). This thin layer also serves as base interconnect plane. Step 272 involves an optional step of depositing an ARC (e.g., 50 to 200 nanometers PVD or PECVD hydrogenated SiN_xor AlO_x) layer on substrate frontside. This step is may be performed either before or after mounting the cells in the module assembly. Step 274 (proceeding with packaging) corresponds to step 244 of FIG. 16.
FIG. 18 shows another alternative process flow 280 for fabrication of single-aperture hexagonal-prism 3-D TFSCs with rear base layers using self-aligned selective plating metallization without boron-doped p⁺⁺ rear base contacts by selective base doping. The p⁺⁺ base contact doping is performed by aluminum doping (aluminum contact firing) using aluminum from base contact metallization and an anneal (firing process). This process flow uses cured phosphorus source layer and a thermal anneal to form the n⁺ phosphorus-doped selective emitter regions and the n⁺⁺ phosphorus-doped emitter contact regions (the latter underneath the cured phosphorus doping layer). This single-aperture hexagonal-prism 3-D TFSC with rear base layer uses an integrated rear mirror which is directly deposited (embodiments include silver and/or aluminum deposited by PVD, evaporation, or non-selective plating) on the rear base passivation dielectric layer. As an option, the rear base passivation dielectric (e.g., oxide) layer surface may be treated (e.g., with plasma) to produce a roughened dielectric surface (e.g., with an RMS surface roughness of roughly tens to hundreds of nanometers) prior to mirror layer deposition. This produces a diffuse integrated mirror directly on the rear surface of the rear base layer passivation layer. Alternatively, the TFSC substrate rear base layer may be pre-textured by a textured template surface (thus, eliminating the need for such plasma treatment). Step 282 (providing a substrate) corresponds to step 252 of FIG. 17; and step 284 (selective coating) corresponds to step 254. Step 286 (selective filling) corresponds to step 226 of FIG. 16; step 288 (self-aligned selective emitter and base) corresponds to step 228 of FIG. 16; step 290 (surface passivation) corresponds to step 230 of FIG. 16; and step 292 (etch) corresponds to step 232 of FIG. 16. Step 294 (optional plasma treatment step as part of self-aligned metallization) corresponds to step 264 of FIG. 17. Step 296 (plating) corresponds to step 234 of FIG. 16; step 298 (anneal) corresponds to step 236 of FIG. 16; and step 300 (plating) corresponds to step 238 of FIG. 16. Step 302 (integrated mirror) corresponds to step 260 of FIG. 17; step 304 (ARC layer) corresponds to step 262 of FIG. 17; and step 306 (proceeding with packaging) corresponds to step 264 of FIG. 17.
FIG. 19 shows another alternative process flow 310 for fabrication of single-aperture hexagonal-prism 3-D TFSCs with rear base layers using self-aligned fire-through metallization with boron-doped p⁺⁺ rear base contacts by selective base doping (besides selective emitter doping). This hexagonal-prism 3-D TFSC with rear base layer uses a detached rear mirror in module assembly (i.e., rear mirror is not an integrated layer directly deposited on the rear base layer). Step 312 (providing a substrate) corresponds to step 252 of FIG. 17; step 314 (selective coating) corresponds to step 254; step 316 (selective filling) corresponds to step 256; and step 318 (self-aligned selective emitter and base) corresponds to step 258. Step 320 involves formation of surface passivation and ARC. The top (emitter phosphorus) dopant source layer, rear (base boron) dopant source layer, and any native oxide are stripped using a suitable etchant (e.g., using HF etchant). A thin oxide layer (e.g., 5 to 100 nanometers) is grown by steam oxidation (e.g., 3 to 300 nanometers at 800° C. to 950° C.). This thermal oxidation step is optional. Next, an ARC layer (e.g., 3 to 100 nanometers hydrogenated SiN_x) is deposited by PECVD or PVD, with passivation layer formed on prism top and sidewalls (coverage on the cell rear is optional). The PECVD or PVD SiN_x(or AlO_x) also provides H passivation of the 3-D TFSC substrate. In one embodiment, the diffusion/oxidation steps result in selective emitter and emitter contact diffusion sheet resistance values of 80-150 Ω/square and 10-70 Ω/square, respectively. Step 322 involves self-aligned metallization (metal coat). The top portions of the honeycomb prisms are selectively coated (to a height equal to or less than the dopant source layer) with metal (in one embodiment, silver) liquid or paste using self-aligned roller, inkjet, liquid dip, or spray coating. Next, this layer is dried and cured (250° C. to 400° C. or UV). The rear base troughs on the substrate backside are then selectively filled with metal liquid or paste (silver and/or aluminum). This may be done by roller, spin-on, ink-jet, or spray coating followed by etch-back (e.g., by solvent spin-on or selective cell backside etchback) to form filled troughs. This layer is then dried and cured (250° C. to 400° C. or UV). Step 324 involves self-aligned metallization (fire-through). The cell front (silver) and rear (aluminum and/or silver) metallized regions are formed by firing through the oxide/PECVD (or PVD) SiN_xlayers. Step 326 involves an optional self-aligned plating metallization step. A layer of silver or copper (e.g., roughly 1 to 5 microns) is selectively/concurrently deposited on the metallized top honeycomb ridges (emitter) and rear honeycomb ridges (base) by plating. If necessary, a refractory metal barrier layer such as nickel may be deposited by plating before copper or silver plating. Next, the metallized regions are flash coated with silver. Step 328 (optional FGA) corresponds to step 268 of FIG. 17. Step 330 (mounting) corresponds to step 240 of FIG. 16. Step 332 (proceeding with packaging) corresponds to step 306 of FIG. 18.
FIG. 20 shows another alternative process flow 340 for fabrication of single-aperture hexagonal-prism 3-D TFSCs with rear base layers using self-aligned fire-through metallization and with boron-doped p⁺⁺ rear base contacts formed by selective base doping (besides selective emitter doping). This hexagonal-prism 3-D TFSC with rear base layer uses an integrated (attached) rear mirror which is directly deposited (e.g., silver or aluminum by PVD or evaporation or non-selective plating) on the rear base passivation dielectric layer. As an option, the rear base passivation dielectric (e.g., oxide) layer surface may be treated (e.g., with plasma) to produce a rough dielectric surface (e.g., with an RMS surface roughness of roughly tens to hundreds of nanometers) prior to mirror layer deposition. This may produce a diffuse integrated mirror directly on the rear surface of the rear base layer passivation layer. Alternatively, a textured TFSC substrate base layer may be formed by using a textured template (thus, eliminating the need for an optional plasma treatment step). Step 342 (providing a substrate) corresponds to step 312 of FIG. 19; step 344 (selective coating) corresponds to step 314; step 346 (selective filling) corresponds to step 316; step 348 (self-aligned emitter and base) corresponds to step 318; and step 350 (surface passivation and ARC) corresponds to step 320. Step 352 involves an optional plasma treatment step to roughen the thermal oxide layer on the substrate backside (for integrated diffuse rear mirror). Step 354 (metal coat) corresponds to step 322 of FIG. 19; step 356 (fire-through) corresponds to step 324; step 358 (optional FGA) corresponds to step 328; and step 360 (plating) corresponds to step 326. The plating and FGA process steps are reversed. Step 362 (integrated mirror) corresponds to step 302 of FIG. 18; and step 364 (proceeding with packaging) corresponds to step 306.
In regard to the n-type (e.g., phosphorus) dopant liquid/paste covering the top portion of the hexagonal ridges, a single furnace anneal process in a diffusion furnace (e.g., at roughly 800° C. to 950° C.) produces more heavily-doped regions with higher surface phosphorus concentrations on the top silicon hexagonal ridges directly in contact with and underneath the cured n-type dopant solid source layer compared to other regions not covered with the cured dopant source layer. The TFSC substrates may be processed with the emitter side facing down through an in-line diffusion furnace. Through vapor-phase transport of the vaporized dopant source to the adjacent frontside regions within the hexagonal prism unit cell cavities, the furnace anneal concurrently dopes the remaining frontside surface regions not covered with the solid dopant source layer with phosphorus with smaller surface concentration (e.g., 1×10¹⁹to 5×10¹⁹cm⁻³), thus, creating self-aligned selective emitter regions. These less heavily doped regions with higher sheet resistance values (in one embodiment, in the range of 100 Ω/square to 150 Ω/square) improve the blue response of the 3-D TFSC, while the more heavily doped honeycomb ridges may minimize the frontside emitter contact resistance of the 3-D TFSC. Similarly, the same furnace anneal process produces more heavily doped p⁺-doped hexagonal prism diffused based contacts for low base contact resistance. For hexagonal-prism 3-D TFSCs with rear base layers, the remaining rear base layer rear surface base regions are less heavily doped on the surface, resulting in selective base doping (and a back-surface field or BSF region).
The above process steps may be performed on integrated in-line process equipment. For example, FIG. 21 shows a view 400 of a setup for performing the two process steps of liquid/paste coating and UV or IR curing prior to furnace anneal, allowing for subsequent formation of selective emitter and base regions after anneal in an in-line diffusion furnace. This integrated in-line process equipment allows for self-aligned formation of dopant liquid or paste coating on the 3-D TFSC substrate hexagonal-prism top ridges and hexagonal-prism rear ridges by roller coating. Roller coating may be performed using an atmospheric-pressure, belt-driven coating and curing equipment integrated in line with a diffusion furnace. In one embodiment, the top ridges are coated with n-type dopant liquid/paste; the rear ridges are coated with p-type dopant liquid/paste.
The 3-D TFSC substrate 402 is shown moving in 404 on input conveyor belt 406. The rotating top rollers 408, with top roller pads 410, apply a controlled downward force to coat the top hexagonal prism ridges with n-type paste. The rotating rear rollers 412, with rear roller pads 414, apply a controlled upward force to coat the rear hexagonal prism ridges with p-type paste. Multilayer materials may be coated on each side of the 3-D TFSC substrate by applying (or flowing) a different liquid or paste material to each roller on the top 408 and/or rear 410 set of rollers. The 3-D TFSC substrate 402 next moves into the curing area where the dopant liquid/paste layers are concurrently formed using a curing lamp 416 which uses IR or UV curing beams 418. The 3-D TFSC substrate 402 is next shown moving out 420 to the output conveyor belt 422, which may move the substrate 402 to an in-line diffusion furnace, where the n⁺ and p⁺ contacts and selective emitter regions are concurrently formed.
A similar roller coater setup may be properly configured and used for applying metal liquid/paste coatings (e.g., silver and/or aluminum liquid or paste sources), curing the metal liquid/paste source, and performing subsequent thermal anneal in an in-line atmospheric furnace (resistively-heated or lam-heated furnace) for fire-through metallization in order to form the emitter and base contact metallization (and whenever applicable, also to form the aluminum-doped p⁺⁺ base contact regions).
FIG. 22 shows a view 430 of an alternative setup design to perform the same processes as the roller coater/curing/furnace setup of FIG. 21. The setup in FIG. 22 may be used for self-aligned formation of dopant source liquid/paste coating on the 3-D TFSC substrate top ridges and hexagonal-prism rear ridges by angled spray coating. This setup also may utilize an in-line atmospheric-pressure coating and curing and diffusion equipment configuration which can be easily integrated with an in-line diffusion furnace. As with the roller coater setup in FIG. 21, multilayer materials may be coated on each side of the substrate by using multiple sets of spray nozzles connected to different liquid sources (not shown here) and applying (or flowing) a different liquid source material to each nozzle on the top and/or rear set of spray nozzles. This is an alternative technique to the roller coating system shown in FIG. 21. In one embodiment, the top ridges are coated with n-type dopant liquid/paste (such as phosphorus); the rear ridges are coated with p-type dopant liquid/paste (such as boron). Referring to FIG. 22, the 3-D TFSC substrate 402 is shown moving in 404 on input conveyor belt 406. Angled nozzles 432 spray n-type dopant liquid onto the surface at a sharp angle with respect to the surface (nozzles cover wafer width). This n-type dopant liquid comes from an n-type liquid dopant source and nozzle reservoir/pump 434. Angled nozzles 436 spray p-type dopant liquid onto the surface at a sharp angle with respect to the surface (nozzles cover wafer width). This p-type dopant liquid comes from a p-type liquid dopant source and nozzle pump 438. The 3-D TFSC substrate 402 next moves into the curing area where the dopant liquid/paste layers are concurrently formed using a curing lamp 416 which uses IR or UV curing beams 418. The 3-D TFSC substrate 402 is next shown moving out 420 to the output conveyor belt 422, which may move the substrate 402 to an in-line diffusion furnace, where the n⁺ and p⁺ contacts and selective emitter regions are concurrently formed.
The angled spray technique limits the vertical height of the liquid/paste coating to a portion of the hexagonal ridges and prevents the liquid source from coating the inner parts of the hexagonal prism cavity sidewalls and/or rears. This type of in-line (or another drive method) processing system may also be used for applying metal source liquid (e.g., silver and/or aluminum source liquid) for fire-through metallization applications as well as applying liquid etchant for selective etching of dielectrics (e.g., oxide and/or solid dopant source layer) from the top and/or rear hexagonal prism ridges.
FIG. 23 shows a view 440 of another alternative setup to perform the same processes as the in-line roller coater/curing setup of FIG. 21 and the in-line spray coater/curing setup of FIG. 22. The setup in FIG. 23 may be used for self-aligned formation of dopant liquid/paste coating on the 3-D TFSC substrate hexagonal top ridges and hexagonal prism rear ridges by liquid-dip coating. This setup also may utilize an in-line atmospheric-pressure coating and curing equipment configuration to be attached to the input stage of an in-line diffusion (or fire-through) furnace.
In one embodiment, the top ridges are coated with n-type dopant liquid/paste (such as phosphorus); the rear ridges are coated with p-type dopant liquid/paste (such as boron). The 3-D TFSC substrate 402 is shown moving in 404 on input conveyor belt 406. Liquid film dispenser containing n-type liquid dopant source 422 applies a controlled thickness n-type liquid dopant film 444. This n-type dopant liquid comes from n-type liquid dopant source and liquid level and depth controller 446. Liquid film dispenser containing p-Type liquid dopant source (with peripheral air levitation) 448 applies a controlled thickness p-type liquid dopant film 450. This p-type dopant liquid comes from p-type liquid dopant source and liquid level and depth controller 452. The 3-D TFSC substrate 402 next moves into the curing area where the dopant liquid/paste layers are concurrently formed using a curing lamp 416 which uses IR or UV curing beams 418. The 3-D TFSC substrate 402 is next shown moving out 420 to the output conveyor belt 422, which may move the substrate 402 to an in-line diffusion furnace, where the n⁺ and p⁺ contacts and selective emitter regions are concurrently formed.
As in the setups in FIGS. 21 and 22, multilayer materials may be coated on each side of the 3-D TFSC substrate by using multiple sets of liquid-dip applicators (not shown here) and applying (or flowing) a different liquid source material to each liquid-dip applicator on the top and/or rear set of applicators. This type of processing system may also be used for applying metal liquid for fire-through metallization as well as applying liquid etchant for selective etching of dielectrics (e.g., oxide and/or solid dopant source layer) from the top and/or rear hexagonal prism ridges.
FIG. 24 shows a 3-D view 500 of multiple adjacent prism unit cells from a regular hexagonal prism TFSC of this disclosure, after cell fabrication, including self-aligned base and emitter contact metallization. The dark region on the top 502 of the unit cell is the self-aligned emitter contact metal; the rear 504 of the unit cell is the self-aligned base contact metal. The prism sidewall surfaces are doped to form the selective emitter junctions (e.g., shallow n⁺p junctions with a junction depth of 0.2 to 0.5 micron in boron-doped silicon base).
FIGS. 25A through 31 show various cross-sectional views of hexagonal-prism unit cells with rear base layers, with detached or integrated/attached rear mirrors. These FIGURES correspond to the cell fabrication process flow embodiments outlined in FIGS. 15-20. The cell doping polarities may be inverted (e.g., phosphorus-doped base and p⁺n selective emitter). While depicted for c-Si cells, this cell structure may also be applied to polysilicon, amorphous silicon, and non-Si absorber TFSCs. The substrates shown have tapered prism sidewalls (narrower emitter and wider base). Alternatively, the substrate may have vertical prism sidewalls.
FIG. 25A shows a Y-Y cross-sectional view 510 of a unit cell within a single-aperture hexagonal-prism 3-D TFSC substrate with a rear base layer (released and removed from its template) before cell fabrication. For subsequent n⁺p selective emitter formation, the hexagonal-prism sidewalls are in-situ-doped with boron to form the base region at the time of 3-D TFSC substrate fabrication. The sidewalls are doped with boron (in one embodiment, at the time of silicon deposition into the template), either uniformly or in a graded profile, more lightly doped at the prism sidewall surface and more heavily doped towards the sidewall vertical center axis. Similarly, the hexagonal-prism rear base layer is in-situ-doped at the time of 3-D TFSC substrate fabrication. The base layer is doped with boron, either uniformly or in a graded profile, more lightly doped at the rear base layer top surface and more heavily doped towards the rear base layer rear surface, creating a built-in back-surface-field effect in the rear base layer, improving the cell performance. The prism top (emitter side) ridges 512 are used for emitter contact diffusion and metal contact formation and the hexagonal troughs 514 for base contact diffusion and buried metal contact formation.
FIG. 25B shows a Y-Y cross-sectional view 520 of a unit cell within the hexagonal prism 3-D TFSC of this disclosure (using the hexagonal prism 3-D TFSC substrate with a rear base layer as shown in FIG. 25A) after self-aligned formation of: selective emitter regions 522 (e.g., less heavily-doped with phosphorus, n⁺ selective emitter on the hexagonal prism sidewall surfaces as shown); heavily-doped emitter contact regions 524 with coverage height L_e 526 (e.g., more heavily-doped with phosphorus, n⁺⁺ doped emitter contact regions on the hexagonal prism top hexagonal ridges as shown); selective base regions 528 on the rear surface of the rear base layer (e.g., less heavily-doped with boron, p⁺ selective base on the rear base layer rear surface as shown); and heavily-doped (boron-doped p⁺⁺) base contact diffusion regions 530 in the rear base layer trenches/troughs (e.g., more heavily-doped with boron, p⁺⁺ doped base contact regions). The cured solid dopant source layers for emitter 525 and base regions 532 are shown as dark segments on the top hexagonal-prism ridges and within the rear base rear filled trenches (troughs), respectively.
FIG. 26A shows a Y-Y cross-sectional view 540 after the cured n-type and p-type dopant layers have been removed and before the thermal diffusion process. FIG. 26B shows a Y-Y cross-sectional view 550 after formation of surface passivation and anti-reflection coating (thermal SiO₂and/or PVD or PECVD SiN_xor AlN_xARC) dielectric layers 552. Note L _e 554 and cured boron doped glass 556. FIG. 27A shows a Y-Y cross-sectional view 560 after formation of emitter 1732 and base 1734 contact metals (silver, aluminum, copper, etc.) by fire-through and/or selective plating. FIG. 27B shows a Y-Y cross-sectional view 570 after the addition of a detached highly reflective rear specular or diffuse mirror 572 (e.g., silver or aluminum coating on a base interconnect plane on a PCB in the solar module assembly; the mirror may contact the rear base contacts as shown).
FIG. 28 shows a Y-Y cross-sectional view 580 after the addition of an integrated/attached highly reflective thin rear specular or diffuse mirror (e.g., a thin layer 572 of silver or aluminum coating deposited by PVD or plating on the rear base layer rear surface as shown; for diffuse mirror, the dielectric layer on the rear base layer rear surface is roughened by a surface roughening process such as a plasma treatment or ion bombardment before mirror metal deposition). Alternatively, the base layer may already be textured by a pre-textured template from which the TFSC substrate is released.
FIG. 29 shows a Y-Y cross-sectional view 590 of the TFSC in FIG. 28 (showing multiple prism unit cells). The TFSC includes an integrated (attached) high-reflectivity rear mirror 572, made of silver or aluminum, which may be deposited (e.g., by PVD or plating or evaporation or another coating technique such as roller or spray coating followed by curing) on the rear passivation oxide (and ARC) layer(s) formed on the rear surface of the rear base layer. Rear mirror 572 is also the base interconnect plane, electrically connecting to the self-aligned hexagonal base contacts 592 (e.g., silver and/or aluminum and/or copper or other metals) on the rear base layer. The rear mirror may be deposited on a smooth or roughened rear base dielectric layer surface (for specular or diffuse mirror, respectively). Again, the base layer may already be textured by a pre-textured template from which the TFSC substrate is released.
FIG. 30 shows a Y-Y cross-sectional view 600 of the TFSC in FIGS. 28 and 29, with multiple prism unit cells shown. The TFSC includes a detached diffuse high-reflectivity rear mirror 602, made of silver or aluminum (mirror coating), placed below the rear surface of the rear base layer. This FIGURE shows the module assembly interconnect plane placed at a spacing of S 604 below the rear surface of the rear base layer, where S may be in the range of 0 (i.e., interconnect plane in contact with the rear base layer rear surface) up to roughly H (where H is the height of the hexagonal prism unit cell and may be in the range of 100 to 500 microns). In this latter structure, the rear mirror is not electrically connected to the base contact metal. Without the integrated mirror, the interconnect plane with a suitable coating (in one embodiment, silver) may serve as a detached rear mirror.
FIG. 31 shows a schematic Y-Y cross-sectional view 610 of the TFSC in FIG. 27A, with multiple prism unit cells shown. The TFSC includes a detached diffuse high-reflectivity rear mirror 612, made of silver or aluminum (mirror coating), placed below the rear surface of the rear base layer. This FIGURE shows the mirror placed at a spacing of S below the rear surface of the rear base layer, where S may be in the range of 0 (i.e., mirror in contact with the rear base layer rear surface) up to roughly H (where H is the height of the hexagonal prism unit cell and may be in the range of 100 to 500 microns). In this structure, the rear mirror is electrically connected to the base contact metal. Thus, the rear mirror shown here also serves as the base interconnect plane.
In the following section, alternative embodiments of process flows for fabricating templates using either lithography and etch techniques or laser micromachining (or laser drilling) are described. The templates are then used and reused numerous times to fabricate the 3-D TFSC substrates with single-aperture or dual-aperture configurations (either with or without rear base silicon layers) for 3-D TFSC fabrication.
Templates may be fabricated using electronic-grade silicon wafers, solar-grade silicon wafers, or lower-cost metallurgical-grade silicon wafers. Moreover, templates made of silicon can be fabricated either using monocrystalline or multicrystalline silicon wafers. The starting template wafer may either be a standard polished wafer (after saw damage removal) or even a lower grade wafer immediately after wire sawing (without saw damage removal). The latter may further reduce the cost of the templates. The relatively low cost of each template is spread over numerous 3-D TFSC substrates, resulting in much lower TFSC substrate and finished module costs compared to the standard state-of-the-art (e.g., 200 microns thick) solar-grade monocrystalline and multicrystalline silicon wafers and associated modules.
For further explaining how a template is fabricated, FIG. 32 shows an embodiment of a process flow 620. The process begins with step 622, where an unpatterned monocrystalline silicon or multicrystalline silicon, either square-shaped or round substrate (e.g., 200 mm×200 mm square or 200-mm round) is provided. The starting template wafer may be a wafer prepared by wire saw either with or without saw damage removal (the latter may further reduce the cost of template). The starting template wafer may also be made of a lower purity (and lower cost) metallurgical-grade silicon. In one embodiment, the substrate is roughly 200 to 800 microns thick. Optionally, step 622 includes performing gettering on a low-cost metallurgical-grade silicon and/or performing a surface texturing etch (e.g., using isotropic acid texturing by a mixture of nitric acid and hydrofluoric acid, or using alkaline texturing in KOH/IPA) to create an optional textured template surface. Step 624 uses photolithography patterning (in one embodiment, using a lower cost contact or proximity aligner/patterning) to produce a prism-array mask pattern such as hexagonal-array pattern in photoresist (i.e., interconnected hexagonal openings in the photoresist layer). The process sequence includes the formation of an oxide and/or nitride (optional) layer, photoresist coating (e.g., spin-on or spray coating) and pre-bake, photolithography exposure through a hexagonal-array mask, and photoresist development and post-bake. One embodiment includes a hard mask layer (SiO₂and/or SiN_x; for example, a thin thermally grown oxide layer can be used as an optional hard mask) below the photoresist (although the process may be performed without the use of any hard mask layer by placing the photoresist coating directly on silicon). When using a hard mask layer, the exposed portions of the hard mask layer are etched after photoresist patterning (thus, forming hexagonal openings). Such etching of the exposed hard mask layer may be simply performed using a wet etchant such as hydrofluoric acid for oxide hard mask. Step 626 involves formation of hexagonal prisms using anisotropic plasma etch; where a high-rate deep reactive ion etch (DRIE) process forms a closely-packed array of deep (e.g., 100 to 400 microns) hexagonal-shaped trenches in silicon. The photoresist and/or oxide and/or nitride hard mask layer(s) are used for pattern transfer from the patterned photoresist layer to silicon. In one embodiment, the deep RIE (DRIE) process parameters are set to produce near-vertical, slightly tapered hexagonal-prism trench sidewalls. In an alternative embodiment, the deep RIE (DRIE) process parameters are set to produce roughly or essentially vertical hexagonal-prism sidewalls. Note that the slightly tapered sidewalls are preferred over the essentially vertical sidewalls. Step 628 involves template surface preparation and cleaning. This process includes stripping the patterned photoresist layer from the substrate. The template substrate is then cleaned in a wet bench prior to subsequent thermal deposition processing to form the TFSC substrates. Such cleaning may involve DRIE-induced polymer removal (using a suitable wet etchant such as a mixture of sulfuric acid and hydrogen peroxide) followed by an isotropic silicon wet etch (such as in a mixture of nitric acid and hydrofluoric acid) in order to isotropically remove a thin layer (e.g., on the order of 10 to 500 nanometers) of silicon from the trench sidewalls and bottoms. This may remove any surface and buried contaminants, such as any surface and embedded metallic and/or polymeric/organic contaminants introduced by the deep RIE (DRIE) process, from the sidewalls and bottoms of the DRIE-produced template trenches. Template processing may complete after a deionized (DI) water rinse and drying. Optionally and if desired, the template wafer may also go through a standard pre-diffusion (or pre-thermal processing) wafer cleaning process such as a so-called RCA wet clean prior to the above-mentioned DI water rinsing and drying. Another optional surface preparation step (either performed instead of or after the wet isotropic silicon etch process) includes performing a short thermal oxidation (e.g., to grow 5 to 100 nanometers of sacrificial silicon dioxide), followed by wet hydrofluoric acid (HF) oxide strip (to remove any residual contaminants from the patterned template). If no optional oxide growth/HF strip is used, an optional dilute HF etch may performed to remove the native oxide layer and to passivate the surface with hydrogen (forming Si—H bonds) in preparation for subsequent 3-D TFSC substrate fabrication. After the completion of step 628, the resulting template may then be used and reused multiple times to fabricate 3-D (e.g. hexagonal-prism) TFSC substrates.
FIG. 33 shows a top view of a lithography exposure mask design 630 which may be used for fabrication of a template, as described in step 624 of process flow 620 above. Dark regions 632 are an opaque coating such as Cr on a transparent mask plate. Light regions 634 are areas where the opaque coating (e.g., Cr) has been etched to allow for exposure of a photoresist layer. In one embodiment, the width of the hexagonal line (L_M) 635 on the mask plate is between 1 and 30 microns, and the diagonal distance between hexagonal prism points (d) 636 or the hexagonal-prism aperture diameter is between 50 and 500 microns.
An alternative embodiment of a process flow 640 for patterning of a template is outlined in FIG. 34, which uses direct laser micromachining instead of photolithography and reactive-ion etch. Step 642 (providing an unpatterned substrate) corresponds to step 622 of FIG. 32. Step 644 involves the use of programmable precision laser micromachining to form the desired periodic array of deep trenches. This process may be performed in a controlled atmospheric ambient based on either physical ablation or a combination of physical ablation and laser-assisted chemical etching. Step 646 (surface preparation and cleaning) corresponds to step 628 of FIG. 32. After the completion of step 646, the resulting template may then be used and reused to fabricate multiple 3-D TFSC substrates.
Another alternative embodiment of a process flow 650 for patterning of a template is outlined in FIG. 35, which uses photolithography and etch to produce through-wafer trenches. Step 652 (providing an unpatterned substrate) corresponds to step 642 in FIG. 134. Step 654 involves forming a silicon dioxide (SiO₂) layer and/or a silicon nitride (SiN_x) layer on both the frontside and backside of the substrate (this step is optional and may not be used). In one embodiment, the SiO₂layer thickness is between 100 and 1000 nanometers. The SiO₂layer is formed by steam oxidation or LPCVD and may be followed by a layer of SiN_xformed by LPCVD or PECVD. In one embodiment, the SiN_xlayer thickness is between 100 and 1000 nanometers. These layers may be formed on both sides of the silicon substrate (as shown in FIG. 34), or only on the substrate frontside or backside. Alternatively, only one layer (either oxide or nitride) may be used. Step 656 (patterning) corresponds to step 624 in FIG. 32; and step 658 (etch) corresponds to step 626. Step 660 involves formation of backside oxide/nitride openings for 3-D TFSC substrate release etching. Photoresist lithography patterning and plasma etch (or wet etch) are used to form a regular array of openings (e.g., a square grid or a line pattern) in oxide/nitride on the substrate backside. These openings may be used during subsequent 3-D TFSC substrate fabrication (for wet etchant access to sacrificial layer from backside). Step 662 (surface preparation and cleaning) corresponds to step 628 in FIG. 32 and may be modified such that the surface preparation and cleaning process does not remove the dielectric layers from the substrate backside. After step 662, the resulting template may then be used to fabricate 3-D TFSC substrates.
Another alternative embodiment of a process flow 670 for fabrication of a template is outlined in FIG. 36, which uses photolithography and etch, enabling fabrication of TFSC substrates with a rear base layer and grooves for formation of self-aligned base contacts. Another alternative embodiment of a process flow 670 for patterning of a template is outlined in FIG. 37, which uses photolithography and etch, enabling fabrication of TFSC substrates with a rear base layer and grooves for formation of self-aligned base contacts. FIGS. 41 through 47 show the Y-Y cross-sectional views of a silicon substrate during the fabrication process flow for making a template based on the process flows of FIG. 36 or FIG. 37. It may be useful to refer to FIGS. 41 through 47 while reviewing the process flow steps of FIGS. 136 and 37.
Referring to FIG. 36, step 672 (providing an unpatterned substrate) corresponds to step 652 in FIG. 35; step 674 (forming oxide and/or nitride layers) corresponds to step 654; step 676 (patterning) corresponds to step 656; and step 678 (etch) corresponds to step 658. Step 680 involves formation of self-aligned shallow trenches which are wider than deep trenches. The self-aligned wider shallow surface trenches are formed by a timed selective isotropic dielectric (hard mask) etch to form hard mask undercuts with known lateral dimension under photoresist, stripping patterned photoresist, and a timed anisotropic silicon RIE to form shallower/wider tapered trenches near surface. Step 682 (formation of backside openings) corresponds to step 660 in FIG. 35; and step 684 (surface preparation and cleaning) corresponds to step 662. After step 682, the resulting template may then be used and reused to fabricate multiple 3-D TFSC substrates. It should be noted that the self-aligned wider shallow trenches (which are wider than the deep trenches) may also be formed as part of the same deep RIE process which forms the deep trenches (i.e., steps 678 and 680 can be merged into a single deep RIE process in a DRIE process equipment), thus, eliminating the need for the above-mentioned timed selective isotropic dielectric hard mask etch to form hard mask undercuts under photoresist (this modified approach may also eliminate the need for the frontside hard mask (i.e., the patterned photoresist layer can be formed directly on the substrate) and further simplify the template fabrication process). This simplified process can be performed by using a DRIE process recipe which first forms the deep hexagonal-prism trenches and subsequently forms the shallow wider trenches (or shoulders) over the deep trenches by performing a less anisotropic (or more isotropic) silicon etch process which primarily affects the upper (topmost) portion of the deep hexagonal-prism trenches. Using this modified approach the sidewall profile of the wider shallow trenches may be slightly or heavily tapered (both are acceptable).
Referring to FIG. 37, step 692 (providing an unpatterned substrate) corresponds to step 672 in FIG. 36. Step 694 involves forming a SiO₂layer and/or a SiN_xlayer on the frontside and optionally on the backside of the substrate. In one embodiment, SiO₂layer thickness is between 100 and 1000 nanometers. The SiO₂layer is formed by steam oxidation or LPCVD followed by a layer of SiN_xformed by LPCVD or PECVD. In one embodiment, the SiN_xlayer thickness is between 100 and 1000 nanometers. The layers are formed either on front or both sides of the silicon substrate. Alternatively, only one layer (oxide or nitride) may be used. Alternatively, a SiO₂layer only on the frontside and a SiN_xlayer only on backside may be formed. Step 696 (patterning) corresponds to step 676 of FIG. 36; step 698 (etch) corresponds to step 678; and step 700 (formation of shallower wider trenches) corresponds to step 680. Again and essentially as described for FIG. 14, the self-aligned wider shallow trenches (which are wider than the deep trenches) may also be formed as part of the same deep RIE process which forms the deep trenches (i.e., steps 198 and 200 can be merged into a single deep RIE process in a DRIE process equipment). Step 702 involves formation of an array of openings on the wafer backside of sufficient depth to connect to at least some portions of the rears (bottoms) of the deep trenches. These openings provide access to at least a portion of each prism unit cell from the substrate backside. These holes are formed by laser drilling (or may be formed using backside lithography and wet or plasma etch) and may be used for 3-D TFSC substrate release etching (for etchant access to sacrificial layer such as for etching the sacrificial porous silicon layer). Step 704 (surface preparation and cleaning) corresponds to step 684 of FIG. 36. After step 704, the resulting template may then be used and reused to fabricate multiple 3-D TFSC substrates.
FIGS. 36 and 37 result in templates which enable subsequent fabrication of 3-D TFSC substrates with rear base layers (e.g., such as flat rear silicon base layers) and interconnected shallow grooves or trenches for formation of self-aligned high-conductivity base contact metallization. These 3-D TFSC substrates may be used for subsequent fabrication of high-efficiency TFSCs with self-aligned base and emitter contacts. The dual-width trenches (or deep trenches with shallower and wider trench shoulders stacked on their top) in the template enable fabrication of self-aligned base metallization contacts beside self-aligned emitter metallization contacts.
In order to better understand the following FIGURES, FIG. 38 is provided to show a top view of a hexagonal prism 3-D TFSC substrate. FIG. 38 shows the reference imaginary Y-Y and Z-Z cross-sectional axes on a hexagonal-prism 3-D TFSC substrate.
FIG. 39 shows a Y-Y cross-sectional view of a template 780 with through-wafer trenches 782 (i.e., trenches formed through the substrate and stopped on backside dielectric). This template 780 may be used to fabricate numerous hexagonal-prism 3-D TFSC substrates, including those without rear base layers (i.e., dual-aperture TFSC substrates).
The template 780 has dimensions of h (horizontal distance between trenches) 784, T_st(trench top width) 786, H (height of the trench) 788, T_sb(trench rear width) 790, and 2θ 792 (where θ is the average sidewall taper angle). Note that because these are through-wafer trenches, H 788 is essentially the same as the silicon thickness of the template substrate. Because the through-wafer trenches 782 produce isolated posts, backside dielectric layer 794 is used and should be sufficiently thick and strong to provide sufficient mechanical support. Backside dielectric layer 794 may be a single dielectric layer such as oxide (or nitride) or a stack of two or more dielectric layers such as oxide/nitride. In one embodiment, backside dielectric layer 794 is composed of a layer of LPCVD Si₃N₄on top of a layer of thin thermal SiO₂. The template 780 contains a frontside etch-stop layer (top hard mask layer) 796. In one embodiment, the top hard mask 796 is composed of a layer of LPCVD Si₃N₄on top of a layer of thin thermal SiO₂. Alternatively, the top hard mask layer 796 may include a single layer instead of a 2-layer stack (e.g., Si₃N₄, SiC_x, etc.). Alternatively, there may be no top hard mask layer (patterned photoresist formed directly on silicon).
FIG. 40 shows a Y-Y cross-sectional view of a template 800 with in-wafer trenches 802. This template 800 may also be used to fabricate numerous hexagonal-prism 3-D TFSC substrates, including those without rear base layers (i.e., dual-aperture TFSC substrates). The trenches are confined within the wafer (within the template substrate) and do not penetrate the entire wafer thickness, leaving remaining wafer thickness R 804; note that for a given template substrate thickness, H 806 is less than H 788 in FIG. 39. Thus, the wafer itself provides sufficient mechanical support without a need for mechanical support from backside dielectrics (thus, eliminating the need for backside dielectrics; backside dielectrics are optional here).
The trenches formed in the templates shown in FIGS. 39 and 40 may have vertical sidewalls or slightly tapered sidewalls (in one embodiment, producing deep trenches with gradually and slightly decreasing trench width moving from the trench top towards the trench bottom). In one embodiment, sidewall angles are in the range of 0° to 100 (preferably in the range of 0° to 1°). Trenches with negative or re-entrant sidewall angles (i.e., trenches with increasing trench width moving from the trench top towards the trench bottom) are not desirable and may cause difficulty with 3-D TFSC substrate release and, therefore, should be avoided.
Both template 780 (FIG. 39) and template 800 (FIG. 40) are made using one of the template process flows outlined in FIGS. 34-36. These flowcharts describe the preferred process steps used for fabricating the templates used for subsequent fabrication of numerous 3-D TFSC substrates.
FIGS. 41 through 47 show one embodiment of a process flow and evolution of a template structure for a template version with in-wafer trenches 800 and design to enable formation of self-aligned base contacts during various stages of the template process flows outlined in FIGS. 34-36.
FIG. 41 shows a Y-Y cross-sectional view 810 after formation of a photoresist frontside pattern 812 on dielectric (oxide) hard mask (backside dielectrics 794 are optional and may not be used). FIG. 42 shows a Y-Y cross-sectional view 820 after anisotropic plasma oxide etch (or isotropic wet oxide etch) through the photoresist frontside pattern 812. FIG. 43 shows a Y-Y cross-sectional view 830 after formation of deep hexagonal-prism trenches using deep RIE (DRIE). FIG. 43 further shows remaining wafer thickness R′ 832 and trench height H′ 834. FIG. 44 shows a Y-Y cross-sectional view 840 after timed selective isotropic hard mask etch (e.g., oxide etch using HF) to form controlled lateral undercuts 842 under patterned photoresist 812 with width W_ox. FIG. 45 shows a Y-Y cross-sectional view 850 after photoresist strip. Note that the top hard mask layer 796 remains and the photoresist layer has been removed. FIG. 46 shows a Y-Y cross-sectional view 860 after anisotropic silicon etch to form wider shallow trenches with controlled height (L) 862 on the top of the narrower and deeper trenches 802. FIG. 47 shows a Y-Y cross-sectional view of a completed template 870 after isotropic oxide etch to strip the top hard mask layer 796 as shown in FIG. 46. While shown here, the backside dielectric layers may also be removed (or may not be used at all). This template 870 may also be used to fabricate numerous hexagonal prism 3-D TFSC substrates. As described before, the combination of deep trenches and wider shallow trenches (top shoulders) may be formed using a single DRIE process sequence (anisotropic deep trench RIE followed by a less anisotropic silicon etch to form the top shoulders), thus, eliminating the need for the top dielectric hard mask layer 796 and the associated process steps reflected in FIGS. 46 and 47.
The following FIGURES (FIGS. 48 to 51) illustrate several alternative embodiments of completed templates.
FIG. 48 shows a Y-Y cross-sectional view of a template 880 with in-wafer trenches 802 without a dielectric top mask layer or a dielectric rear mask layer. FIG. 49 shows a Y-Y cross-sectional view of a template 890 with in-wafer trenches 802 without a dielectric top mask layer or a dielectric rear mask layer, compared to the embodiment shown in FIG. 48. This view also shows template backside holes 892 used to allow for 3-D TFSC substrate release etching. These backside holes 892 may be fabricated using either lithography and etch, or laser micromachining or drilling. FIG. 50 shows a Y-Y cross-sectional view of a template 900 with through-wafer trenches 782 without a top hard mask layer 796 as shown in FIG. 39. FIG. 51 shows a Y-Y cross-sectional view of a template 910 with through-wafer trenches 782 without a top hard mask layer 796, compared to FIG. 50. Note further that the through-wafer trenches 782 in FIG. 51 have wider trenches (top shoulders) with controlled height (L) 862 on the top of the narrower and deeper hexagonal trenches, like the trenches in FIG. 47. However, note that FIG. 51 shows through-wafer trenches 782, whereas FIG. 47 shows within-wafer trenches 802.
For templates with through-wafer trenches, mechanical support may be provided by either using a backside dielectric stack of sufficient strength (such as oxide, nitride, polysilicon, or a combination thereof as described before), or using a backside-bonded silicon wafer. FIG. 52 shows a view of a template 920 with through-wafer trenches and without any frontside dielectrics, suitable for fabrication of hexagonal-prism single-aperture 3-D TFSC substrates with rear base layers. This template 920 includes a mechanical support rear silicon wafer 922 bonded at a bonded interface 924 (e.g., via a dielectric such as oxide or a dielectric stack 926 such as oxide/nitride between the wafers). The mechanical support rear silicon wafer 922 provides wet etchant access to the template trenches through holes 928, which may be created either by laser drilling or reactive ion etching. This template 920 enables fabrication of 3-D TFSC substrates with capability for formation of self-aligned base and emitter contacts during subsequent hexagonal prism 3-D TFSC substrate fabrication. In an alternative embodiment, mechanical support rear silicon wafer 922 may instead be formed by a layer of polysilicon deposited by LPCVD over the backside dielectric (or dielectric stack) 926, thus, eliminating the need for wafer bonding.
FIGS. 53 and 54 show views 930 and 940, respectively, of two examples of mask designs (out of many possible designs), the first one a square-array mask and the second one a line-array mask, which may be used to pattern the template backside to produce backside openings for 3-D TFSC substrate release etching. This patterning is performed only once on each template.
FIG. 53 shows a square-array mask, where each square-array unit cell 932 has a square-array unit cell width 934 and a square array unit cell spacing 936. In one embodiment, both of these are approximately 1 to 5 microns (may be smaller or larger as well). FIG. 54 shows a line-array mask, where the pattern shown is repeated over the entire mask as a periodic array. In one embodiment, the line widths and spaces are all 1 to 10 microns (may be smaller or larger as well). The pattern has a pattern width 942, which in one embodiment is approximately 50 to 500 microns. Other mask patterns (e.g., lines, circles, etc.) enabling etchant access to remove the sacrificial layer may be used instead of square array or orthogonal line array. Alternatively, it is possible to use laser drilling or laser micromachining instead of lithography/etch to create the backside holes/openings for etchant access.
An alternative to the backside patterning outlined in FIGS. 53 and 54 uses a frontside mask to enable release of single-aperture hexagonal-prism 3-D TFSC substrates with flat base layers by providing etchant access pathways from the template frontside.
FIG. 55 shows an alternative frontside hexagonal-prism mask design 950 with center holes 952, shown as white circles on the mask plate. In one embodiment, center holes 952 are roughly 1 to 5 microns in diameter. Note that the hexagonal-prism array design is the same as in FIG. 33. Dark regions 632 are opaque coating (e.g., Cr) on the mask plate. Light regions 634 and 952 are areas to be etched. In one embodiment, the width of the line mask (L_M) 635 is between 1 and 30 microns, and the diagonal distance between hexagonal-prism points (d) 636 is between 50 and 500 microns.
FIG. 56 shows the template frontside mask design 950 shown in FIG. 55, also shown with dotted squares 954 indicating a superimposed image of one embodiment of the backside mask design (in order to see the relative alignment of the frontside mask and backside mask from the frontside mask perspective).
FIG. 57 shows a top view of a template backside mask design 960, with the superimposed image of the hexagonal array of the mask design 950 from FIGS. 55 and 56 shown as gray hexagonal-array pattern in order to see the relative alignment of the frontside mask and backside mask from the backside mask perspective).
FIGS. 58 through 66 show an alternative template version during various stages of the template process flows outlined in FIGS. 36 and 37.
FIG. 58 shows a Y-Y cross-sectional view of an n-type (e.g., phosphorus-doped) [100] silicon substrate 970 after formation of a top hard mask layer 796 and a backside hard mask layer 794 using thermal oxidation. Note that before oxidation, an optional surface texturing wet etch (such as using an acid texturing etch or an alkaline texturing etch) may be performed using a suitable etchant such as KOH in order to texture the silicon surface. FIG. 59 shows the substrate 970 in FIG. 58 after backside lithography to form a patterned photoresist layer 974 comprising an array of square-shaped openings 972 and after wet or anisotropic plasma etching of the backside hard mask layer 794 in the exposed areas. Note that in order to use anisotropic wet etch to form the backside channels, the backside mask square pattern for the substrate 970 backside is properly aligned to produce [111] sidewalls, [110] directed edges, and [211] directed ribs. FIG. 60 shows the substrate 970 in FIG. 59 after anisotropic etching of template from backside using an anisotropic wet etchant (e.g., KOH or TMAH) to form an array of pyramids 976 with square bases and after stripping photoresist layer 974 from template backside. Note the angle 978 of the pyramids 976. In one embodiment, this angle is 35.26°. The backside lithography mask square pattern is properly aligned to produce [111] plane sidewalls 980, [110] directed edges, and [211] directed ribs. FIG. 61 shows the substrate 970 in FIG. 60 after frontside patterning and anisotropic oxide plasma etch (or isotropic oxide wet etch) through patterned resist 812 in preparation for formation of honeycomb-prism trenches and concurrently forming frontside-etched small-diameter release trenches 982, and removing backside oxide layer 794. In one embodiment, the diameter (DR) of the release access trenches 982 is between 1 and 5 microns. FIG. 62 shows the substrate 970 in FIG. 61 after frontside deep silicon RIE. Note that frontside-etched small-diameter trenches 982 connect to the backside release channels 976 through shallower cone-shaped trenches 984 (in one embodiment, at the centers of the hexagonal-prism posts). FIG. 63 shows the substrate 970 in FIG. 62 after timed selective isotropic hard mask (SiO₂) etch to form controlled lateral undercuts 842 under patterned photoresist. FIG. 64 shows the substrate 970 in FIG. 63 after photoresist 812 strip, with oxide hard mask 796 remaining. FIG. 65 shows the substrate 970 in FIG. 64 after anisotropic silicon reactive-ion etch to form wider trenches with controlled height (L) 862 on top of the narrower and deeper hexagonal-prism within-wafer trenches 802. FIG. 66 shows the substrate 970 in FIG. 65 after isotropic oxide etch to strip top oxide 796. After this step an optional timed silicon wet etch may be performed in HNA or TMAH to remove about 5 to 500 nanometers of silicon to remove any DRIE-induced trench sidewall damage and/or polymeric/metallic contamination. At this point, the substrate 970 may serve as a reusable template for formation of 3-D TFSC substrates. Again as described before, the combination of deep trenches and wider shallow trenches (top shoulders) may be formed using a single DRIE process sequence (anisotropic deep trench RIE followed by a less anisotropic silicon etch to form the top shoulders), thus, eliminating the need for the top dielectric hard mask layer 796 and the associated process steps reflected in FIGS. 64 and 65. This alternative process flow also eliminates the need for the oxide hard mask (thus, photoresist can be applied directly on silicon for frontside and backside patterning steps).
FIGS. 67 through 75 show a template version during various stages of the template fabrication process flow outlined in FIGS. 36 and 37. FIGS. 67 through 75 are substantially similar to FIGS. 58 through 66, except the initial silicon substrate is an n-type [110] substrate 990, which results in backside release channels 992 in the shape of rectangular trenches with vertical sidewalls, rather than pyramids. The resulting substrate 990 shown in FIG. 75 may serve as a reusable template for formation of 3-D TFSC substrates. Again as described before, the combination of deep trenches and wider shallow trenches (top shoulders) may be formed using a single DRIE process sequence (anisotropic deep trench RIE followed by a less anisotropic silicon etch to form the top shoulders), thus, eliminating the need for the top dielectric hard mask layer 796 and the associated process steps reflected in FIGS. 72 and 73. This alternative process flow also eliminates the need for the oxide hard mask (thus, photoresist can be applied directly on silicon for frontside and backside patterning steps).
Another approach to implement the template release channels is to place them on the template substrate backside such that they connect to the bottoms of the hexagonal-prism deep trenches (instead of tops of the posts or pillars as shown before). FIGS. 76 and 79 through 86 show a template version (with the release channels connected to the bottoms of the deep trenches) during various stages of the template process flows outlined in FIGS. 36 and 37. This embodiment uses a backside lithography mask design as shown in FIG. 77 (other types of backside mask patterns for backside release channels are also possible). FIG. 78 shows the backside lithography mask shown in FIG. 77, with the frontside hexagonal-prism array mask pattern shown as a superimposed gray pattern for reference (to show the relative alignment of the frontside and backside masks patterns).
FIG. 76 is substantially similar to FIG. 58 above, showing an initial n-type (e.g., phosphorus doped) [100] substrate 970. FIG. 79 is substantially similar to FIG. 59 above, except the mask design aligns backside release channels 994 with the bottoms of deep prism trenches 802 to be formed. FIG. 80 shows the substrate 970 shown in FIG. 79 after anisotropic wet etching (e.g., using anisotropic alkaline etching such as KOH-based etching) of the template backside to form an array of pyramids with square bases (note that the anisotropic etching may also be performed using anisotropic reactive ion etching and the backside openings may be circular or other shapes instead of square-shaped). FIG. 81 shows the substrate 970 in FIG. 80 after frontside patterning and after wet oxide etch through patterned resist in preparation for formation of deep trenches. This also removes the backside oxide layer 794. FIG. 82 shows the substrate 970 in FIG. 81 after formation of hexagonal-prism trenches 802 using deep RIE (DRIE). Note that the bottoms of prism trenches 802 essentially align with the backside release channel holes 994. FIG. 83 shows the substrate 970 in FIG. 82 after timed selective isotropic hard mask (in one embodiment SiO₂) wet etch to form controlled lateral undercuts 842 under patterned photoresist. FIG. 84 shows the substrate 970 in FIG. 83 after top photoresist 812 strip using a photoresist stripper. FIG. 85 shows the substrate 970 in FIG. 84 after anisotropic silicon etch (using the oxide layer as a hard mask) to form wider trenches (top shoulders) with controlled height (L) 862 on top of the narrower and deeper hexagonal-prism within-wafer trenches 802. FIG. 86 shows the substrate 970 in FIG. 85 after isotropic oxide etch to strip top oxide 796. After this step an optional timed isotropic silicon wet etch may be performed in HNA or TMAH (or another suitable isotropic silicon wet etchant) to etch approximately 5 to 500 nanometers of silicon to remove any DRIE-induced trench sidewall contaminants (such as metallic and/or polymeric contaminants) and surface damage. At this point, the substrate 970 may serve as a template for formation of 3-D TFSC substrates. Again as described before, the combination of deep trenches and wider shallow trenches (top shoulders) may be formed using a single DRIE process sequence (anisotropic deep trench RIE followed by a less anisotropic or more isotropic silicon plasma etch to form the top shoulders), thus, eliminating the need for the top dielectric hard mask layer 796 and the associated process steps reflected in FIGS. 83 and 84. This alternative process flow also eliminates the need for the oxide hard mask (thus, photoresist can be applied directly on silicon for frontside and backside patterning steps).
Various embodiments of the templates shown earlier may be used to produce one hexagonal-prism (or other prism geometries) 3-D TFSC substrate per process pass. It is also possible to fabricate templates which are capable of producing two hexagonal-prism 3-D TFSC substrates concurrently per process pass (thus, doubling the 3-D TFSC substrate fabrication throughput). FIGS. 87 and 88 show cross-sectional views of two such templates capable of doubling the hexagonal-prism 3-D TFSC substrate production throughput.
FIG. 87 shows a Y-Y cross-sectional view of a stacked template structure 1000 for fabricating two hexagonal prism 3-D TFSC substrates per process pass. FIG. 87 shows a template structure 1000 with in-wafer trenches 802. Note the similarity to the template 800 in FIG. 40. Template structure 1000 is made of two similar templates, a top template 1002 and a rear template 1004, which are first fabricated based on one of the embodiments outlined before and then bonded together backside to backside (e.g., using direct thermal bonding of the wafer backsides or thermal bonding of dielectric layers formed on the wafer backsides) at a backside interface 1006. Note that the dielectric hard masks on the template frontsides may not be present (they are optional for subsequent use of the templates for TFSC substrate fabrication). FIG. 88 shows Y-Y cross-sectional view of an alternative stacked template structure 1010 for concurrently fabricating two hexagonal-prism 3-D TFSC substrates per process pass. FIG. 88 shows a template structure 1010 with through-wafer trenches 782. Note the similarity to the template 780 in FIG. 39. Template structure 1010 is made of two similar templates, a top template 1012 and a rear template 1014, which are first fabricated based on one of the embodiments outlined before and then bonded together backside to backside (e.g., either through direct bonding of the substrate backsides or using thermal bonding of dielectric layers formed on the wafer backsides) at a backside interface 1006. Note that the dielectric hard masks on the template frontsides may not be present (they are optional for subsequent use of the templates for TFSC substrate fabrication).
While FIGS. 87 and 88 show representative stacked template structures suitable for higher throughput fabrication of hexagonal-prism dual-aperture 3-D TFSC substrates without rear base layers, it is also possible to make stacked template structures for fabrication of hexagonal prism 3-D TFSC substrates with rear base layers. This may be done by first fabricating the suitable individual templates based on one of the process flow embodiments shown in FIGS. 36 and 37, corresponding to the template structure shown in FIG. 47 (this one shown with in-wafer trenches; it is also possible to fabricate templates with through-wafer trenches such as the structures shown in FIG. 51 or FIG. 52). Assuming we use a pair of templates with the structure shown in FIG. 47 (or a template structure with wider and shallow trenches or shoulders stacked on top of the deep trenches), these templates are then processed to create a series of large lateral/radial microchannels in conjunction with an array of holes/openings which communicate with the rears of trenches. The two templates are then bonded together backside-to-backside (e.g., by thermal bonding of the backside surfaces together). The radial/lateral microchannels sandwiched between the bonded wafers extend all the way to the periphery of the stacked/bonded templates and provide easy access for the wet etchant to reach the sacrificial layer (e.g., porous silicon formed by anodic etching of monocrystalline or microcrystalline silicon layer) in each template in order to selectively remove the sacrificial layer in each template and to release the embedded hexagonal-prism 3-D TFSC substrates from the top and rear templates in the stack (thus, concurrently forming two hexagonal-prism 3-D TFSC substrates per process pass). The microchannels on the template backsides may be formed before template bonding by laser ablation or a combination of lithography and etch. The microchannels are sufficiently large to allow for easy movement of wet etchant and etch byproducts between the inner portions of the wafers in the bonded stack and the peripheral openings of the microchannels in the middle of the bonded stack.
The templates described above may be used to fabricate 3-D TFSC substrates for use in 3-D TFSCs.
FIGS. 89 and 90 show two different process flow embodiments for fabricating hexagonal-prism dual-aperture 3-D TFSC substrates with rear base layers (using a suitable template such as the one shown in FIG. 47). FIG. 89 depicts an embodiment of a process flow 1100 using layer release processing. This flow is based on the use of Ge_xSi_1-xsacrificial layer deposition and blanket or selective in-situ-doped epitaxial silicon deposition. The resulting hexagonal-prism unit cells have open apertures on prism top and are terminated at the rear with a rear base layer (in one embodiment, a relatively flat thin silicon layer). Again, the process flow of this embodiment may be easily adjusted in order to use polysilicon, amorphous silicon, or a non-silicon crystalline or polycrystalline/amorphous silicon material. In step 1102, a patterned honeycomb-prism template is provided. This template has already been processed to form an embedded array of trenches along with shallower/wider trenches (or trench shoulders) stacked on top of narrower/deeper trenches (see FIG. 47). There is no dielectric layer on the template frontside, and there is a patterned oxide and/or nitride dielectric layer (or stack) with openings left on the template backside. In step 1104, a multi-layer blanket epitaxy is performed in an epitaxial reactor, including the following in-situ process steps. First, H₂bake or GeH₄/H₂bake is used for in-situ surface cleaning. Next, a thin Ge_xSi_1-xepitaxial layer is deposited (in one embodiment, on the top only). In one embodiment, this layer is between 10 and 1000 nanometers. Next, a doped silicon epitaxial layer is deposited on the top only. In one embodiment, this layer is p-type, boron-doped and between 1 and 30 microns thick. The in-situ doping (boron doping) profile may be flat or graded. In case of grading, boron doping concentration is gradually increased during the deposition of the silicon epitaxial layer, with a lower concentration at the beginning and a higher concentration towards the end of the epitaxial growth process. This graded base doping may provide a field-assisted drift component for efficient collection of photo-generated carriers, substantially reducing the impact of recombination losses. It also reduces base sheet resistance and ohmic losses. The silicon epitaxial layer thickness is set such that the deep trenches are fully filled with silicon while the shallow (wider) trenches (top trench shoulders) receive epitaxy on their sidewalls and their central regions are left with self-aligned shallow hexagonal troughs. In step 1106, the 3-D TFSC substrate is released. A highly selective isotropic wet or dry etch of Ge_xSi_1-xis performed, with very high selectivity with respect to silicon. In one embodiment, a mixture of hydrofluoric acid, nitric acid and acetic acid (HNA) is used to selectively etch the Ge_xSi_1-xlayer. Alternatively, a mixture of ammonia, peroxide, and water (NH₄OH+H₂O₂+H₂O) may be used. The wet etchant selectively removes the sacrificial Ge_xSi_1-xlayer by reaching the sacrificial layer through the template backside dielectric openings. This process releases the hexagonal prism 3-D TFSC substrate, which may then be used for subsequent 3-D TFSC fabrication. Note that the template backside openings may be formed directly in silicon backside without a need for the backside dielectric.
FIG. 90 depicts an embodiment of a process flow 1110 for fabrication of self-supporting hexagonal-prism single-aperture 3-D thin-film polysilicon or amorphous silicon TFSC substrates with rear base layers made of polysilicon or amorphous silicon using layer release processing, without the use of epitaxial silicon processing. The amorphous silicon or polysilicon layer may be optionally crystallized using laser crystallization as part of the flow. This process flow uses a dielectric sacrificial layer such as SiO₂(deposited using LPCVD or thermally grown) in conjunction with conformal amorphous silicon or polysilicon deposition for the silicon absorber layer. Step 1112 (providing a substrate) corresponds to step 1102 in FIG. 89. Step 1114 involves depositing a conformal sacrificial layer (or a layer stack). First, a thin layer of a sacrificial material is deposited by conformal layer formation (LPCVD or thermal oxidation). In one embodiment, the sacrificial material is SiO₂, with a thickness of between 50 and 2000 nanometers. This sacrificial oxide layer conformally covers the hexagonal-prism trench walls and the template frontside. If subsequent laser crystallization is used, step 1114 also includes depositing a thin nitride layer by LPCVD. In one embodiment, this nitride layer is Si₃N₄, with a thickness between 100 and 1000 nanometers. The sacrificial layer may be made of porous silicon instead of oxide and/or nitride. Step 1116 involves deposition of a blanket silicon layer using conformal deposition. In one embodiment, this blanket silicon layer may be amorphous silicon or polysilicon, p-type in-situ doped with boron, having a thickness between 1 and 30 microns. Note that the silicon thickness is set such that the deep trenches are fully filled with silicon while the shallow (wider) near-surface trenches receive silicon on sidewalls, and their central regions are left with self-aligned relatively shallow hexagonal troughs or trenches. Step 1118 involves depositing an optional thin silicon nitride dielectric layer on top by LPCVD or PECVD to serve as a protective cap for silicon layer. In one embodiment, this layer is between 100 and 1000 nanometers. Step 1120 involves 3-D TFSC substrate release. In one embodiment and when using a silicon dioxide sacrificial layer, hydrofluoric acid (HF) is used to etch the oxide sacrificial layer. In another embodiment and when using a porous silicon sacrificial layer, a mixture of ammonia, peroxide, and water (NH₄OH+H₂O₂+H₂O) or a mixture of hydrogen peroxide and hydrofluoric acid (H₂O₂+HF) or a suitable composition of tri-methyl-ammonium-hydroxide (TMAH) may be used. The etch composition and temperature may be adjusted to achieve maximum etch selectivity for porous silicon with respect to silicon. This process releases the hexagonal-prism 3-D TFSC substrate. Note that the wet etchant selectively removes the sacrificial Ge_xSi_1-xlayer (or porous silicon sacrificial layer) by reaching the sacrificial layer through the template backside dielectric openings (note that backside openings may be formed directly in the template substrate backside without using any dielectric on the template backside). This process releases the hexagonal-prism 3-D TFSC substrate from the template. An optional step 1122 involves laser crystallization of the released 3-D thin-film amorphous silicon or polysilicon substrate to form a large-grain polysilicon microstructure. The silicon nitride layer surrounding silicon serves as protective cap. The nitride layer is then selectively stripped. The hexagonal-prism 3-D TFSC substrate may then be used for subsequent 3-D TFSC fabrication.
FIGS. 91 through 95 illustrate Y-Y cross-sectional views of a template 870 (see FIG. 47) with in-wafer hexagonal-prism trenches 802 and no dielectrics on the template frontside and an optional backside layer 794 (the template may be fabricated without any frontside and backside dielectric layers), as it goes through the key process steps to fabricate a hexagonal-prism single-aperture 3-D TFSC substrate with a rear base layer. Again, the flow used for this fabrication process flow is based on one of the embodiments outlined earlier.
FIG. 91 shows a view 1130 after deposition of the thin (e.g., 200 to 2000 nanometers thick) sacrificial layer 1138 (epitaxial Ge_xSi_1-xor porous silicon or another suitable material) and the in-situ-doped (boron-doped for p-type base) epitaxial silicon layer 1140. The epitaxial silicon deposition process fills the trenches (void-free trench fill) while leaving relatively shallow troughs (trenches) near the top. This may be done by stopping the epitaxial deposition process after the deeper/narrower trenches are fully filled with epitaxial silicon and before filling of the wider/shallower trenches on the template frontside (thus, forming the shallower troughs with height (L) 1132 and width (W_m) 1134 in conjunction with the top epitaxial silicon layer of thickness (W_f) 1136. FIG. 92 shows a view 1150 of the template in FIG. 91 after highly selective etching of the sacrificial layer 1138, thus allowing for release and removal of the 3-D TFSC substrate 1140 from the template. FIGS. 93 and 94 illustrate Y-Y cross-sectional views 1160 and 1180 of the released substrate 1140 from FIG. 92. The released substrate 1140 has a base side 1162, an emitter side 1164. The substrate 1140 has dimensions of T_st 786 (silicon sidewall thickness near the base side of the hexagonal-prism vertical sidewalls), T_sb 790 (silicon sidewall thickness near the emitter side of the hexagonal-prism vertical sidewalls), hexagonal-prism height 1170, and tapered hexagonal-prism TFSC substrate sidewalls 1172. Referring to the view 1160 in FIG. 93, the base side 1162 is shown on the top and the emitter side 1164 is shown on the bottom (TFSC substrate as released from the template). In the view 1180 in FIG. 94, the base side 1162 is shown on the bottom and the