US20080248625A1 - Methods for enhancing trench capacitance and trench capacitor - Google Patents
Methods for enhancing trench capacitance and trench capacitor Download PDFInfo
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- US20080248625A1 US20080248625A1 US12/120,535 US12053508A US2008248625A1 US 20080248625 A1 US20080248625 A1 US 20080248625A1 US 12053508 A US12053508 A US 12053508A US 2008248625 A1 US2008248625 A1 US 2008248625A1
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- 238000000034 method Methods 0.000 title claims abstract description 68
- 239000003990 capacitor Substances 0.000 title claims abstract description 15
- 230000002708 enhancing effect Effects 0.000 title abstract description 4
- 238000001020 plasma etching Methods 0.000 claims abstract description 52
- 238000000151 deposition Methods 0.000 claims abstract description 15
- 239000004020 conductor Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 32
- 125000006850 spacer group Chemical group 0.000 claims description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 6
- 238000012545 processing Methods 0.000 abstract description 7
- 239000000463 material Substances 0.000 description 18
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 238000013459 approach Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 8
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 4
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- -1 Ta2O5 Chemical class 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000000313 electron-beam-induced deposition Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000007737 ion beam deposition Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910002113 barium titanate Inorganic materials 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052914 metal silicate Inorganic materials 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
- H01L29/945—Trench capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
Definitions
- the invention relates generally to memory fabrication, and more particularly, to methods for enhancing trench capacitance and a trench capacitor so formed.
- Capacitance enhancement is essential for trench technology scaling.
- the trench is formed in a bottle shape to increase the surface area.
- This approach requires a sacrificial collar, and is susceptible to trench merging.
- the bottle shape approach also requires extra process steps.
- hemispherical silicon grains (HSG) are formed on a sidewall of the trench to increase its surface area.
- This approach also requires a sacrificial collar and extra process steps, and further, narrows the trench.
- Use of new high dielectric constant materials such as aluminum oxide or hafnium oxide
- This approach requires new materials and presents numerous integration issues. It is therefore desired to have a capacitance enhancement without adding process complexity and cost.
- a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor.
- the rough sidewall enhances trench capacitance without increasing processing complexity or cost.
- a first aspect of the invention provides a method of forming a trench capacitor, the method comprising: forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor.
- a second aspect of the invention provides a trench capacitor comprising: a deep trench in a substrate; a first electrode in the substrate; a second electrode in the deep trench; and a dielectric between the first and the second electrodes, wherein the deep trench has sidewalls with roughness having an average amplitude of less than approximately 5 nanometers.
- a third aspect of the invention provides a method comprising: forming a trench having a dielectric layer therein; and first reactive ion etching (RIE) the dielectric layer in the trench to form a micro-mask on a bottom surface of the trench.
- RIE reactive ion etching
- FIGS. 1-5 show one embodiment of a method according to the invention.
- FIGS. 6-10 show another embodiment of a method according to the invention.
- FIGS. 1-5 show one embodiment of a method of forming a trench capacitor 100 ( FIG. 5 ) in a semiconductor-on-insulator (SOI) substrate 102
- FIGS. 6-10 show another embodiment of a method of forming a trench capacitor 200 ( FIG. 10 ) in bulk substrate 202 .
- processing begins with SOI substrate 102 including a substrate 104 , a buried insulator layer 106 (e.g., silicon oxide (SiO 2 )) and a semiconductor layer 108 (e.g., silicon (Si), germanium (Ge), silicon germanium (SiGe), etc.).
- SOI substrate 102 has a pad layer 110 and a hardmask 112 .
- Pad layer 110 may include any now known or later developed pad layer materials such as a silicon nitride (Si 3 N 4 ) layer and a silicon oxide (SiO 2 ) layer (not individually shown).
- Hardmask 112 may include any now known or later developed hardmask material such as tetraethyl orthosilicate, Si(OC 2 H 5 ) 4 (TEOS) based silicon oxide (SiO 2 ).
- a portion or entire semiconductor substrate 102 may be strained.
- semiconductor layer 108 may be strained.
- FIG. 2 shows forming a first (upper) portion 120 of a trench 122 .
- First portion 120 may be formed, for example, by patterning hard mask 112 and etching, e.g., using a reaction ion etch (RIE), through hard mask 112 , pad layer 110 , semiconductor layer 108 , buried insulator layer 106 and perhaps slightly into substrate 104 .
- FIG. 2 also shows depositing a dielectric layer 124 in first portion 120 .
- RIE reaction ion etch
- “Depositing” may include any now known or later developed techniques appropriate for the material to be deposited, e.g., chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating and evaporation.
- CVD chemical vapor deposition
- LPCVD low-pressure CVD
- PECVD plasma-enhanced CVD
- SACVD semi-
- dielectric layer 124 may include silicon nitride (Si 3 N 4 ); however, other materials may also be employed. Dielectric layer 124 is conformally deposited to cover the top, bottom and sidewalls of first portion 120 of trench 122 .
- FIGS. 3-4 show performing a RIE including a first stage 130 ( FIG. 3 ) and a second stage 140 ( FIG. 4 ).
- first stage RIE 130 etches dielectric layer 124 ( FIG. 2 ) and forms a micro-mask 132 on a bottom surface 134 of first portion 120 of trench 122 .
- first stage RIE 130 includes a non-uniform RIE; however, this may not always be necessary.
- First stage RIE 130 also forms a spacer 136 within first portion 120 , which protects semiconductor layer 108 and buried insulator layer 106 from undesired attack and doping.
- first stage RIE 130 removes dielectric layer 124 on bottom surface 134 of trench 122 , forming spacer 136 .
- the process conditions of first stage RIE 130 are designed such that a micro mask 132 is created in substrate 104 after spacer 136 is formed.
- FIG. 4 shows performing second stage RIE 140 to form a second portion 142 of trench 122 , i.e., into substrate 104 , having a rough sidewall 144 .
- Rough sidewall 144 is formed based on micro-mask 132 .
- Rough sidewall 144 has dimensions of a nanometer scale. For example, rough sidewall 144 may have an average amplitude of less than approximately 5 nanometers.
- Second stage RIE 140 etches substrate 104 to complete deep trench formation. Micro-mask 132 produced in first stage RIE 130 produces a rough sidewall 144 , as shown in FIG. 4 .
- First and second RIE stages 130 , 140 are performed in a single process chamber.
- the process conditions include approximately 50 milliTorr (mT) pressure, approximately 300 standard cubic centimeters (sccm) hydrogen bromide (HBr), approximately 75 sccm ammonia (NF 3 ), approximately 5 sccm oxygen (O 2 ) and a power configuration that removes dielectric layer 124 ( FIG. 2 ) in the form of silicon nitride at trench bottom surface 134 and at the same time creates micro mask 132 .
- a second stage 140 may include several steps to etch deep trench 122 .
- the process conditions for the first three parts of the second stage may have the same pressure (approximately 150 mT), same HBr flow rate (approximately 300 sccm), same NF 3 flow rate (approximately 36 sccm), same high frequency power (500 W), and different O 2 flow rates (from approximately 33 to approximately 23 sccm), and different low frequency power (from approximately 1200 W to approximately 1500 W).
- the same pressure (approximately 200 mT), same HBr flow rate (approximately 300 sccm), same NF 3 flow rate (approximately 32 sccm), same high frequency power (approximately 500 W), same low frequency power (approximately 1800 W), and different O 2 flow rates (approximately 17 sccm and approximately 18 sccm) may be used.
- FIG. 5 shows finalizing steps for forming trench capacitor 100 .
- any remaining hardmask 112 ( FIG. 4 ) may be stripped at this or later stage.
- an outer electrode 160 can be formed from substrate 104 as-is or a buried plate 162 (phantom line) can optionally be formed in substrate 104 .
- buried plate 162 may include a portion of substrate 104 which is heavily doped. Buried plate 162 may be formed by any conventional process, such as gas phase doping, liquid phase doping, plasma doping, plasma immersion ion implantation, outdiffusion doping from a solid film such as arsenic doped silicate glass (ASG), or any combination thereof, which are all well known in the art.
- ASG arsenic doped silicate glass
- Spacer 136 protects SOI layer 108 and BOX layer 106 from undesired doping during the formation of buried plate 162 .
- Buried plate 162 is self-aligned to spacer 136 .
- FIG. 5 also shows depositing a node dielectric 150 that follows the contours of rough sidewall 144 .
- Node dielectric 150 may include any now known or later developed insulator appropriate for forming a trench capacitor 100 , e.g., silicon oxide, silicon nitride, silicon oxynitride, high-k material having a relative permittivity above about 10, or any combination of these materials.
- metal oxides such as Ta 2 O 5 , BaTiO 3 , HfO 2 , ZrO 2 , Al 2 O 3
- FIG. 5 also shows filling trench 122 with a conductor 164 to form an inner electrode 166 .
- Inner electrode 166 may include, for example, amorphous silicon, polycrystalline silicon (hereinafter “polysilicon”), germanium, silicon germanium, a metal (e.g., tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum), a conducting metallic compound material (e.g., tungsten silicide, tungsten nitride, titanium nitride, tantalum nitride, ruthenium oxide, cobalt silicide, nickel silicide), or any suitable combination of these materials.
- Inner electrode 166 material may further include dopants.
- inner electrode 166 material includes doped polysilicon.
- a planarization process such as chemically mechanical polishing (CMP) is performed, rendering inner electrode 166 co-planar with pad layer 110 .
- CMP chemically mechanical polishing
- Methods for forming node dielectric 150 and inner electrode 164 material include but are not limited to thermal oxidation, chemical oxidation, thermal nitridation, atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD), sub-atmospheric chemical vapor deposition (SACVD), rapid thermal chemical vapor deposition (RTCVD), limited reaction processing CVD (LRPCVD), ultrahigh vacuum chemical vapor deposition (UHVCVD), metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), physical vapor deposition, sputtering, plating, evaporation, ion beam deposition, electron beam deposition and/or laser assisted deposition.
- ALD atomic layer deposition
- LPCVD low-pressure chemical vapor deposition
- PECVD plasma enhanced chemical vapor deposition
- HDPCVD high density plasma chemical vapor deposition
- FIGS. 6-10 show another embodiment of a method of forming a trench capacitor 200 ( FIG. 10 ) in bulk substrate 202 .
- processing begins with a bulk substrate 202 .
- Substrate 204 may include any of the materials listed above relative to substrate 104 ( FIGS. 1-5 ).
- Substrate 202 has a pad layer 210 and a hardmask 212 thereover.
- Pad layer 210 and hardmask 212 may include any of the materials listed above relative to pad layer 110 and hard mask 112 ( FIGS. 1-5 ).
- a portion or entire semiconductor substrate 204 may be strained.
- FIG. 7 shows forming a first (upper) portion 220 of a trench 222 .
- First portion 220 may be formed, for example, by patterning hard mask 212 and etching, e.g., using a RIE, through hard mask 212 and pad layer 210 into substrate 204 .
- First portion 220 may extend into substrate 204 to a depth of, for example, approximately 1 um.
- FIG. 7 also shows depositing (as described above) a dielectric layer 224 in first portion 222 .
- dielectric layer 224 may include silicon nitride (Si 3 N 4 ); however, other materials may also be employed.
- Dielectric layer 224 is conformally deposited to cover the top, bottom and sidewall of first portion 220 of trench 222 .
- FIGS. 8-9 show performing a RIE including a first stage 230 ( FIG. 8 ) and a second stage 240 ( FIG. 9 ).
- first stage RIE 230 etches dielectric layer 224 ( FIG. 7 ) and forms a micro-mask 232 on a bottom surface 234 of first portion 220 ( FIG. 7 ) of trench 222 ( FIG. 7 ).
- first stage RIE 230 includes a non-uniform RIE; however, this may not always be necessary.
- First stage RIE 230 also forms a spacer 236 within first portion 220 . Spacer 236 protects a sidewall of first portion 220 from undesired attack and doping.
- first stage RIE 230 removes dielectric layer 224 on bottom surface 234 of trench 222 , forming spacer 236 .
- the process conditions of first stage RIE 230 are designed such that a micro-mask 232 is created in substrate 204 after spacer 236 is formed.
- FIG. 9 shows performing second stage RIE 240 to form a second portion 242 of trench 222 having a rough sidewall 244 .
- Rough sidewall 244 is formed based on micro-mask 232 ( FIG. 8 ). As described above, rough sidewall 244 has dimensions of a nanometer scale. For example, rough sidewall 244 may have an average amplitude of less than approximately 5 nanometers.
- Second stage RIE 240 further etches substrate 204 to complete deep trench formation. Micro-mask 232 produced in first stage RIE 230 helps produce a rough sidewall 244 , as shown in FIG. 9 .
- First and second RIE stages 230 , 240 are performed in a single process chamber. The same RIE process conditions as described above may be employed.
- FIG. 10 shows finalizing steps for forming trench capacitor 200 .
- Trench capacitor 200 may include, among other things, rough sidewall 244 , a node dielectric 250 , an inner electrode 266 , an outer electrode 260 (e.g., including a buried plate 262 (phantom line)).
- the above-described RIE process may be employed to form micro-mask 132 , 232 alone.
- a trench 122 , 222 having a dielectric layer 124 , 224 , e.g., silicon nitride, therein is formed, and a first RIE 130 , 230 is performed on dielectric layer 124 , 224 in trench 122 , 222 to form micro-mask 132 , 232 on bottom surface 134 , 234 of trench 122 , 222 .
- First RIE 130 , 230 forms a spacer 136 , 236 on a sidewall of trench 122 , 222 , and may be a non-uniform etch.
- a second RIE 140 , 240 shown in FIGS. 4 and 9 , may also be provided to extend trench 122 , 222 into substrate 104 , 204 to form a deep trench below spacer 136 , 236 .
- the rough trench sidewall 144 , 244 has nanometer scale roughness, e.g., having an average amplitude of less than approximately 5 nanometers.
- First RIE 130 , 230 and second RIE 140 , 240 may occur in a single process chamber.
- the above-described methods integrate the dielectric spacer 136 , 236 RIE process with deep trench 142 , 242 etch process, which eliminates conventional dedicated spacer RIE and post-clean processes, and therefore significantly saves process time. Furthermore, the above-described embodiments remove the need to dedicate equipment to dielectric spacer RIE and thus reduce the cost associated with equipment investment and maintenance. In addition, an approximately 12-15% trench capacitance enhancement is achieved through rough sidewall 144 , 244 by increasing the trench surface area. Furthermore, the above-described methods have advanced scalability because the roughness on trench sidewall is in the nano-scale. The merging trench issue in conventional trench widening approaches is eliminated. Finally, the above-described methods are fully compatible with existing trench processes. No exotic materials and processes are needed to enhance trench capacitance.
- trench capacitor 100 , 200 includes deep trench 122 , 222 in substrate 104 , 204 ; first electrode 160 , 260 in substrate 104 , 204 , second electrode 166 , 266 in deep trench 122 , 222 , and dielectric 150 , 250 between the first and the second electrodes.
- deep trench 122 , 222 has rough sidewall 144 , 244 with roughness having an average amplitude of approximately 5 nanometers, which is significantly smaller than conventional devices.
- a spacer 136 , 236 may be disposed in an upper portion 120 , 220 of deep trench 122 , 222 .
- First electrode 160 , 260 may include buried plate 162 , 262 in substrate 104 , 204 , which is self-aligned to spacer 136 , 236 .
- Capacitance can be enhanced by forming a bottle-shape in the lower trench section, roughening the sidewalls of the lower trench section by forming hemispherical silicon grains (HSG) thereon, or by any other suitable conventional trench capacitance enhancement method.
- HSG hemispherical silicon grains
- the method as described above is used in the fabrication of integrated circuit chips.
- the resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form.
- the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections).
- the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as portion of either (a) an intermediate product, such as a motherboard, or (b) an end product.
- the end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
Abstract
Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost.
Description
- This patent application is a divisional of U.S. patent application Ser. No. 11/468,472, filed Aug. 30, 2006, currently pending.
- 1. Technical Field
- The invention relates generally to memory fabrication, and more particularly, to methods for enhancing trench capacitance and a trench capacitor so formed.
- 2. Background Art
- Capacitance enhancement is essential for trench technology scaling. There are a variety of techniques to increase a surface area of trenches to increase capacitance. In one approach, the trench is formed in a bottle shape to increase the surface area. This approach, however, requires a sacrificial collar, and is susceptible to trench merging. The bottle shape approach also requires extra process steps. In another approach, hemispherical silicon grains (HSG) are formed on a sidewall of the trench to increase its surface area. This approach also requires a sacrificial collar and extra process steps, and further, narrows the trench. Use of new high dielectric constant materials (such as aluminum oxide or hafnium oxide) has also been proposed, but this approach requires new materials and presents numerous integration issues. It is therefore desired to have a capacitance enhancement without adding process complexity and cost.
- Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost.
- A first aspect of the invention provides a method of forming a trench capacitor, the method comprising: forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor.
- A second aspect of the invention provides a trench capacitor comprising: a deep trench in a substrate; a first electrode in the substrate; a second electrode in the deep trench; and a dielectric between the first and the second electrodes, wherein the deep trench has sidewalls with roughness having an average amplitude of less than approximately 5 nanometers.
- A third aspect of the invention provides a method comprising: forming a trench having a dielectric layer therein; and first reactive ion etching (RIE) the dielectric layer in the trench to form a micro-mask on a bottom surface of the trench.
- The illustrative aspects of the present invention are designed to solve the problems herein described and/or other problems not discussed.
- These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings that depict various embodiments of the invention, in which:
-
FIGS. 1-5 show one embodiment of a method according to the invention. -
FIGS. 6-10 show another embodiment of a method according to the invention. - It is noted that the drawings of the invention are not to scale. The drawings are intended to depict only typical aspects of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements between the drawings.
- Turning to drawings,
FIGS. 1-5 show one embodiment of a method of forming a trench capacitor 100 (FIG. 5 ) in a semiconductor-on-insulator (SOI)substrate 102, andFIGS. 6-10 show another embodiment of a method of forming a trench capacitor 200 (FIG. 10 ) inbulk substrate 202. - As shown in
FIG. 1 , in one embodiment, processing begins withSOI substrate 102 including asubstrate 104, a buried insulator layer 106 (e.g., silicon oxide (SiO2)) and a semiconductor layer 108 (e.g., silicon (Si), germanium (Ge), silicon germanium (SiGe), etc.).SOI substrate 102 has apad layer 110 and ahardmask 112.Pad layer 110 may include any now known or later developed pad layer materials such as a silicon nitride (Si3N4) layer and a silicon oxide (SiO2) layer (not individually shown). Hardmask 112 may include any now known or later developed hardmask material such as tetraethyl orthosilicate, Si(OC2H5)4 (TEOS) based silicon oxide (SiO2).Substrate 104 may include, for example, silicon, germanium, silicon germanium, silicon carbide, and those consisting essentially of one or more III-V compound semiconductors having a composition defined by the formula AlX1GaX2InX3AsY1PY2NY3SbY4, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 being the total relative mole quantity). Other suitable substrates include, for example, 1′-VI compound semiconductors having a composition ZnA1CdA2SeB1TeB2, where A1, A2, B1, and B2 are relative proportions each greater than or equal to zero and A1+A2+B1+B2=1 (1 being a total mole quantity). Furthermore, a portion orentire semiconductor substrate 102 may be strained. For example,semiconductor layer 108 may be strained. -
FIG. 2 shows forming a first (upper) portion 120 of a trench 122. First portion 120 may be formed, for example, by patterninghard mask 112 and etching, e.g., using a reaction ion etch (RIE), throughhard mask 112,pad layer 110,semiconductor layer 108, buriedinsulator layer 106 and perhaps slightly intosubstrate 104.FIG. 2 also shows depositing adielectric layer 124 in first portion 120. “Depositing” may include any now known or later developed techniques appropriate for the material to be deposited, e.g., chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating and evaporation. In one embodiment,dielectric layer 124 may include silicon nitride (Si3N4); however, other materials may also be employed.Dielectric layer 124 is conformally deposited to cover the top, bottom and sidewalls of first portion 120 of trench 122. -
FIGS. 3-4 show performing a RIE including a first stage 130 (FIG. 3 ) and a second stage 140 (FIG. 4 ). InFIG. 3 , first stage RIE 130 etches dielectric layer 124 (FIG. 2 ) and forms amicro-mask 132 on abottom surface 134 of first portion 120 of trench 122. In one embodiment, first stage RIE 130 includes a non-uniform RIE; however, this may not always be necessary. First stage RIE 130 also forms aspacer 136 within first portion 120, which protectssemiconductor layer 108 and buriedinsulator layer 106 from undesired attack and doping. In other words, first stage RIE 130 removesdielectric layer 124 onbottom surface 134 of trench 122, formingspacer 136. The process conditions of first stage RIE 130 are designed such that amicro mask 132 is created insubstrate 104 afterspacer 136 is formed. -
FIG. 4 shows performing second stage RIE 140 to form a second portion 142 of trench 122, i.e., intosubstrate 104, having arough sidewall 144.Rough sidewall 144 is formed based on micro-mask 132.Rough sidewall 144 has dimensions of a nanometer scale. For example,rough sidewall 144 may have an average amplitude of less than approximately 5 nanometers.Second stage RIE 140etches substrate 104 to complete deep trench formation. Micro-mask 132 produced in first stage RIE 130 produces arough sidewall 144, as shown inFIG. 4 . First andsecond RIE stages rough sidewall 144 is shown in Table 1. Other RIE processes are also possible and within the scope of the invention. -
TABLE 1 Stab Time Stab Time Time Time Stab Time Time Time 60 10 60 20 20 30 60 120 300 Press 50 50 150 150 150 150 200 200 200 High 0 400 0 500 500 500 0 500 500 RF Low 0 600 0 1200 1350 1500 0 1800 1800 RF HBr 300 300 300 300 300 300 300 300 300 NF3 75 75 36 36 36 36 32 32 32 O2 5 5 32.5 32.5 27.5 23 17 17 18 BP Ctr 10 10 10 10 10 10 10 10 10 BP Edge 40 40 40 40 40 40 40 40 40 Nitride breakthrough step - In a
first stage 130, the process conditions include approximately 50 milliTorr (mT) pressure, approximately 300 standard cubic centimeters (sccm) hydrogen bromide (HBr), approximately 75 sccm ammonia (NF3), approximately 5 sccm oxygen (O2) and a power configuration that removes dielectric layer 124 (FIG. 2 ) in the form of silicon nitride at trenchbottom surface 134 and at the same time createsmicro mask 132. Asecond stage 140 may include several steps to etch deep trench 122. The process conditions for the first three parts of the second stage may have the same pressure (approximately 150 mT), same HBr flow rate (approximately 300 sccm), same NF3 flow rate (approximately 36 sccm), same high frequency power (500 W), and different O2 flow rates (from approximately 33 to approximately 23 sccm), and different low frequency power (from approximately 1200 W to approximately 1500 W). In the last two parts of the second stage, the same pressure (approximately 200 mT), same HBr flow rate (approximately 300 sccm), same NF3 flow rate (approximately 32 sccm), same high frequency power (approximately 500 W), same low frequency power (approximately 1800 W), and different O2 flow rates (approximately 17 sccm and approximately 18 sccm) may be used. There may be stabilization processes between two neighboring etchings. -
FIG. 5 shows finalizing steps for formingtrench capacitor 100. For example, any remaining hardmask 112 (FIG. 4 ) may be stripped at this or later stage. Furthermore, anouter electrode 160 can be formed fromsubstrate 104 as-is or a buried plate 162 (phantom line) can optionally be formed insubstrate 104. In this case, buriedplate 162 may include a portion ofsubstrate 104 which is heavily doped. Buriedplate 162 may be formed by any conventional process, such as gas phase doping, liquid phase doping, plasma doping, plasma immersion ion implantation, outdiffusion doping from a solid film such as arsenic doped silicate glass (ASG), or any combination thereof, which are all well known in the art.Spacer 136 protectsSOI layer 108 andBOX layer 106 from undesired doping during the formation of buriedplate 162. Buriedplate 162 is self-aligned to spacer 136.FIG. 5 also shows depositing anode dielectric 150 that follows the contours ofrough sidewall 144.Node dielectric 150 may include any now known or later developed insulator appropriate for forming atrench capacitor 100, e.g., silicon oxide, silicon nitride, silicon oxynitride, high-k material having a relative permittivity above about 10, or any combination of these materials. Examples of high-k material include but are not limited to metal oxides such as Ta2O5, BaTiO3, HfO2, ZrO2, Al2O3, or metal silicates such as HfSixOy or HfSixOyNz, where x, y, and z represent relative proportions, each greater than or equal to zero and x+y+z=1 (1 being the total relative mole quantity). -
FIG. 5 also shows filling trench 122 with a conductor 164 to form an inner electrode 166. Inner electrode 166 may include, for example, amorphous silicon, polycrystalline silicon (hereinafter “polysilicon”), germanium, silicon germanium, a metal (e.g., tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum), a conducting metallic compound material (e.g., tungsten silicide, tungsten nitride, titanium nitride, tantalum nitride, ruthenium oxide, cobalt silicide, nickel silicide), or any suitable combination of these materials. Inner electrode 166 material may further include dopants. In one embodiment, inner electrode 166 material includes doped polysilicon. In one embodiment, a planarization process such as chemically mechanical polishing (CMP) is performed, rendering inner electrode 166 co-planar withpad layer 110. - Methods for forming
node dielectric 150 and inner electrode 164 material include but are not limited to thermal oxidation, chemical oxidation, thermal nitridation, atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD), sub-atmospheric chemical vapor deposition (SACVD), rapid thermal chemical vapor deposition (RTCVD), limited reaction processing CVD (LRPCVD), ultrahigh vacuum chemical vapor deposition (UHVCVD), metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), physical vapor deposition, sputtering, plating, evaporation, ion beam deposition, electron beam deposition and/or laser assisted deposition. -
FIGS. 6-10 show another embodiment of a method of forming a trench capacitor 200 (FIG. 10 ) inbulk substrate 202. The process is substantially similar to that described above. As shown inFIG. 6 , processing begins with abulk substrate 202.Substrate 204 may include any of the materials listed above relative to substrate 104 (FIGS. 1-5 ).Substrate 202 has apad layer 210 and ahardmask 212 thereover.Pad layer 210 andhardmask 212 may include any of the materials listed above relative to padlayer 110 and hard mask 112 (FIGS. 1-5 ). A portion orentire semiconductor substrate 204 may be strained. -
FIG. 7 shows forming a first (upper) portion 220 of a trench 222. First portion 220 may be formed, for example, by patterninghard mask 212 and etching, e.g., using a RIE, throughhard mask 212 andpad layer 210 intosubstrate 204. First portion 220 may extend intosubstrate 204 to a depth of, for example, approximately 1 um.FIG. 7 also shows depositing (as described above) adielectric layer 224 in first portion 222. In one embodiment,dielectric layer 224 may include silicon nitride (Si3N4); however, other materials may also be employed.Dielectric layer 224 is conformally deposited to cover the top, bottom and sidewall of first portion 220 of trench 222. -
FIGS. 8-9 show performing a RIE including a first stage 230 (FIG. 8 ) and a second stage 240 (FIG. 9 ). InFIG. 8 ,first stage RIE 230 etches dielectric layer 224 (FIG. 7 ) and forms a micro-mask 232 on abottom surface 234 of first portion 220 (FIG. 7 ) of trench 222 (FIG. 7 ). In one embodiment,first stage RIE 230 includes a non-uniform RIE; however, this may not always be necessary.First stage RIE 230 also forms aspacer 236 within first portion 220.Spacer 236 protects a sidewall of first portion 220 from undesired attack and doping. In other words,first stage RIE 230 removesdielectric layer 224 onbottom surface 234 of trench 222, formingspacer 236. The process conditions offirst stage RIE 230 are designed such that a micro-mask 232 is created insubstrate 204 afterspacer 236 is formed. -
FIG. 9 shows performingsecond stage RIE 240 to form a second portion 242 of trench 222 having arough sidewall 244.Rough sidewall 244 is formed based on micro-mask 232 (FIG. 8 ). As described above,rough sidewall 244 has dimensions of a nanometer scale. For example,rough sidewall 244 may have an average amplitude of less than approximately 5 nanometers.Second stage RIE 240further etches substrate 204 to complete deep trench formation.Micro-mask 232 produced infirst stage RIE 230 helps produce arough sidewall 244, as shown inFIG. 9 . First and second RIE stages 230, 240 are performed in a single process chamber. The same RIE process conditions as described above may be employed. -
FIG. 10 shows finalizing steps for formingtrench capacitor 200. Each of these processes may be as described above relative toFIG. 5 .Trench capacitor 200 may include, among other things,rough sidewall 244, anode dielectric 250, aninner electrode 266, an outer electrode 260 (e.g., including a buried plate 262 (phantom line)). - In another embodiment, shown in
FIGS. 1-3 and 5-8, the above-described RIE process may be employed to form micro-mask 132, 232 alone. In this case, a trench 122, 222 having adielectric layer first RIE dielectric layer bottom surface First RIE spacer second RIE FIGS. 4 and 9 , may also be provided to extend trench 122, 222 intosubstrate spacer rough trench sidewall First RIE second RIE - The above-described methods integrate the
dielectric spacer rough sidewall - In one embodiment,
trench capacitor substrate first electrode substrate second electrode 166, 266 in deep trench 122, 222, and dielectric 150, 250 between the first and the second electrodes. As noted above, deep trench 122, 222 hasrough sidewall spacer First electrode plate substrate - It is understood that optionally, other trench capacitance enhancements can be performed before or after the above-described methods. Capacitance can be enhanced by forming a bottle-shape in the lower trench section, roughening the sidewalls of the lower trench section by forming hemispherical silicon grains (HSG) thereon, or by any other suitable conventional trench capacitance enhancement method. The combination of two or more of these conventional approaches, such as the combination of bottling and HSG with the teachings of the invention, can be performed.
- The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as portion of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
- The foregoing description of various aspects of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of the invention as defined by the accompanying claims.
Claims (14)
1. A method of forming a trench capacitor, the method comprising:
forming a first portion of a trench;
depositing a dielectric layer in the first portion;
performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall;
depositing a node dielectric; and
filling the trench with a conductor.
2. The method of claim 1 , further comprising forming a buried plate in the second portion of the trench.
3. The method of claim 1 , wherein the etching in the first stage includes a non-uniform reactive ion etch.
4. The method of claim 1 , wherein the dielectric layer includes silicon nitride.
5. The method of claim 1 , wherein the etching, including the first stage and the second stage, occurs in a single process chamber.
6. The method of claim 1 , wherein the rough sidewall has dimensions of a nanometer scale.
7. The method of claim 6 , wherein the rough sidewall has an average amplitude of less than approximately 5 nanometers.
8. A method comprising:
forming a trench having a dielectric layer therein; and
first reactive ion etching (RIE) the dielectric layer in the trench to form a micro-mask on a bottom surface of the trench.
9. The method of claim 8 , wherein the first RIE forms a spacer on a sidewall of the trench.
10. The method of claim 8 , wherein the first RIE is non-uniform.
11. The method of claim 8 , further comprising a second reactive ion etching (RIE) to extend the trench into a substrate to form a deep trench below the spacer.
12. The method of claim 11 , wherein the second RIE forms the trench with nanometer scale roughness on a trench sidewall.
13. The method of claim 12 , wherein the roughness on the trench sidewall has an average amplitude of less than approximately 5 nanometers.
14. The method of claim 12 , wherein the first RIE and the second RIE occur in a single process chamber.
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080001196A1 (en) * | 2006-06-28 | 2008-01-03 | International Business Machines Corporation | Trench capacitors and memory cells using trench capacitors and method of fabricating same |
US20110165747A1 (en) * | 2010-01-07 | 2011-07-07 | Hynix Semiconductor Inc. | Semiconductor apparatus and fabrication method thereof |
US20110201161A1 (en) * | 2010-02-15 | 2011-08-18 | International Business Machines Corporation | Method of forming a buried plate by ion implantation |
US20120108068A1 (en) * | 2010-11-03 | 2012-05-03 | Texas Instruments Incorporated | Method for Patterning Sublithographic Features |
US8299515B2 (en) | 2011-02-08 | 2012-10-30 | International Business Machines Corporation | Method of forming deep trench capacitor |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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US7977172B2 (en) * | 2008-12-08 | 2011-07-12 | Advanced Micro Devices, Inc. | Dynamic random access memory (DRAM) cells and methods for fabricating the same |
US8482111B2 (en) | 2010-07-19 | 2013-07-09 | Tessera, Inc. | Stackable molded microelectronic packages |
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KR20230009025A (en) | 2021-07-08 | 2023-01-17 | 주식회사 키파운드리 | Method of Deep Trench Etching with Scallop Profile |
Citations (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4533430A (en) * | 1984-01-04 | 1985-08-06 | Advanced Micro Devices, Inc. | Process for forming slots having near vertical sidewalls at their upper extremities |
US4942137A (en) * | 1989-08-14 | 1990-07-17 | Motorola, Inc. | Self-aligned trench with selective trench fill |
US4999312A (en) * | 1988-08-18 | 1991-03-12 | Hyundai Electronics Industries Co., Ltd. | Doping method using an oxide film and a nitride film on the trench wall to manufacture a semiconductor device and the manufactured device |
US5254503A (en) * | 1992-06-02 | 1993-10-19 | International Business Machines Corporation | Process of making and using micro mask |
US5444013A (en) * | 1994-11-02 | 1995-08-22 | Micron Technology, Inc. | Method of forming a capacitor |
US5605600A (en) * | 1995-03-13 | 1997-02-25 | International Business Machines Corporation | Etch profile shaping through wafer temperature control |
US5891807A (en) * | 1997-09-25 | 1999-04-06 | Siemens Aktiengesellschaft | Formation of a bottle shaped trench |
US5930585A (en) * | 1996-07-23 | 1999-07-27 | International Business Machines Corporation | Collar etch method to improve polysilicon strap integrity in DRAM chips |
US6066566A (en) * | 1998-01-28 | 2000-05-23 | International Business Machines Corporation | High selectivity collar oxide etch processes |
US6074954A (en) * | 1998-08-31 | 2000-06-13 | Applied Materials, Inc | Process for control of the shape of the etch front in the etching of polysilicon |
US6448131B1 (en) * | 2001-08-14 | 2002-09-10 | International Business Machines Corporation | Method for increasing the capacitance of a trench capacitor |
US20020132422A1 (en) * | 2001-03-13 | 2002-09-19 | Infineon Technologies North America Corp. | Method of deep trench formation with improved profile control and surface area |
US6455369B1 (en) * | 2000-08-18 | 2002-09-24 | Infineon Technologies Ag | Method for fabricating a trench capacitor |
US6495411B1 (en) * | 2000-07-13 | 2002-12-17 | Promos Technology Inc. | Technique to improve deep trench capacitance by increasing surface thereof |
US20030068867A1 (en) * | 2001-09-04 | 2003-04-10 | Matthias Forster | Method for fabricating a trench capacitor for a semiconductor memory |
US20040095896A1 (en) * | 2002-11-14 | 2004-05-20 | Chudzik Michael P. | Silicon nitride island formation for increased capacitance |
US6743727B2 (en) * | 2001-06-05 | 2004-06-01 | International Business Machines Corporation | Method of etching high aspect ratio openings |
US20040219798A1 (en) * | 2003-05-02 | 2004-11-04 | Nanya Technology Corporation | Deep trench self-alignment process for an active area of a partial vertical cell |
US20050118777A1 (en) * | 2003-10-31 | 2005-06-02 | Henry Bernhardt | Trench capacitor structure and process for applying a covering layer and a mask for trench etching processes in semiconductor substrates |
US7332392B2 (en) * | 2006-04-11 | 2008-02-19 | United Microelectronics Corp. | Trench-capacitor DRAM device and manufacture method thereof |
US7396762B2 (en) * | 2006-08-30 | 2008-07-08 | International Business Machines Corporation | Interconnect structures with linear repair layers and methods for forming such interconnection structures |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5895740A (en) * | 1996-11-13 | 1999-04-20 | Vanguard International Semiconductor Corp. | Method of forming contact holes of reduced dimensions by using in-situ formed polymeric sidewall spacers |
DE10038378A1 (en) * | 2000-08-07 | 2002-02-28 | Infineon Technologies Ag | Process for the production of capacitor electrodes |
US6555430B1 (en) * | 2000-11-28 | 2003-04-29 | International Business Machines Corporation | Process flow for capacitance enhancement in a DRAM trench |
US6620675B2 (en) * | 2001-09-26 | 2003-09-16 | International Business Machines Corporation | Increased capacitance trench capacitor |
US6849529B2 (en) * | 2002-10-25 | 2005-02-01 | Promos Technologies Inc. | Deep-trench capacitor with hemispherical grain silicon surface and method for making the same |
DE10339989B4 (en) * | 2003-08-29 | 2008-04-17 | Advanced Micro Devices, Inc., Sunnyvale | A method of making a conformal spacer adjacent to a gate electrode structure |
US6806138B1 (en) * | 2004-01-21 | 2004-10-19 | International Business Machines Corporation | Integration scheme for enhancing capacitance of trench capacitors |
US7223669B2 (en) * | 2004-06-16 | 2007-05-29 | International Business Machines Corporation | Structure and method for collar self-aligned to buried plate |
US20050285175A1 (en) * | 2004-06-23 | 2005-12-29 | International Business Machines Corporation | Vertical SOI Device |
-
2006
- 2006-08-30 US US11/468,472 patent/US7560360B2/en not_active Expired - Fee Related
-
2008
- 2008-05-14 US US12/120,535 patent/US20080248625A1/en not_active Abandoned
Patent Citations (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4533430A (en) * | 1984-01-04 | 1985-08-06 | Advanced Micro Devices, Inc. | Process for forming slots having near vertical sidewalls at their upper extremities |
US4999312A (en) * | 1988-08-18 | 1991-03-12 | Hyundai Electronics Industries Co., Ltd. | Doping method using an oxide film and a nitride film on the trench wall to manufacture a semiconductor device and the manufactured device |
US4942137A (en) * | 1989-08-14 | 1990-07-17 | Motorola, Inc. | Self-aligned trench with selective trench fill |
US5254503A (en) * | 1992-06-02 | 1993-10-19 | International Business Machines Corporation | Process of making and using micro mask |
US5444013A (en) * | 1994-11-02 | 1995-08-22 | Micron Technology, Inc. | Method of forming a capacitor |
US5605600A (en) * | 1995-03-13 | 1997-02-25 | International Business Machines Corporation | Etch profile shaping through wafer temperature control |
US5930585A (en) * | 1996-07-23 | 1999-07-27 | International Business Machines Corporation | Collar etch method to improve polysilicon strap integrity in DRAM chips |
US5891807A (en) * | 1997-09-25 | 1999-04-06 | Siemens Aktiengesellschaft | Formation of a bottle shaped trench |
US6066566A (en) * | 1998-01-28 | 2000-05-23 | International Business Machines Corporation | High selectivity collar oxide etch processes |
US6074954A (en) * | 1998-08-31 | 2000-06-13 | Applied Materials, Inc | Process for control of the shape of the etch front in the etching of polysilicon |
US6495411B1 (en) * | 2000-07-13 | 2002-12-17 | Promos Technology Inc. | Technique to improve deep trench capacitance by increasing surface thereof |
US6455369B1 (en) * | 2000-08-18 | 2002-09-24 | Infineon Technologies Ag | Method for fabricating a trench capacitor |
US20020132422A1 (en) * | 2001-03-13 | 2002-09-19 | Infineon Technologies North America Corp. | Method of deep trench formation with improved profile control and surface area |
US6544838B2 (en) * | 2001-03-13 | 2003-04-08 | Infineon Technologies Ag | Method of deep trench formation with improved profile control and surface area |
US6743727B2 (en) * | 2001-06-05 | 2004-06-01 | International Business Machines Corporation | Method of etching high aspect ratio openings |
US6448131B1 (en) * | 2001-08-14 | 2002-09-10 | International Business Machines Corporation | Method for increasing the capacitance of a trench capacitor |
US20030068867A1 (en) * | 2001-09-04 | 2003-04-10 | Matthias Forster | Method for fabricating a trench capacitor for a semiconductor memory |
US20040095896A1 (en) * | 2002-11-14 | 2004-05-20 | Chudzik Michael P. | Silicon nitride island formation for increased capacitance |
US20040219798A1 (en) * | 2003-05-02 | 2004-11-04 | Nanya Technology Corporation | Deep trench self-alignment process for an active area of a partial vertical cell |
US20050118777A1 (en) * | 2003-10-31 | 2005-06-02 | Henry Bernhardt | Trench capacitor structure and process for applying a covering layer and a mask for trench etching processes in semiconductor substrates |
US7332392B2 (en) * | 2006-04-11 | 2008-02-19 | United Microelectronics Corp. | Trench-capacitor DRAM device and manufacture method thereof |
US7396762B2 (en) * | 2006-08-30 | 2008-07-08 | International Business Machines Corporation | Interconnect structures with linear repair layers and methods for forming such interconnection structures |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080001196A1 (en) * | 2006-06-28 | 2008-01-03 | International Business Machines Corporation | Trench capacitors and memory cells using trench capacitors and method of fabricating same |
US7709320B2 (en) * | 2006-06-28 | 2010-05-04 | International Business Machines Corporation | Method of fabricating trench capacitors and memory cells using trench capacitors |
US7888722B2 (en) | 2006-06-28 | 2011-02-15 | International Business Machines Corporation | Trench capacitors and memory cells using trench capacitors |
US20110165747A1 (en) * | 2010-01-07 | 2011-07-07 | Hynix Semiconductor Inc. | Semiconductor apparatus and fabrication method thereof |
US20110201161A1 (en) * | 2010-02-15 | 2011-08-18 | International Business Machines Corporation | Method of forming a buried plate by ion implantation |
US8133781B2 (en) | 2010-02-15 | 2012-03-13 | International Business Machines Corporation | Method of forming a buried plate by ion implantation |
US20120108068A1 (en) * | 2010-11-03 | 2012-05-03 | Texas Instruments Incorporated | Method for Patterning Sublithographic Features |
US8728945B2 (en) * | 2010-11-03 | 2014-05-20 | Texas Instruments Incorporated | Method for patterning sublithographic features |
US8299515B2 (en) | 2011-02-08 | 2012-10-30 | International Business Machines Corporation | Method of forming deep trench capacitor |
Also Published As
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US7560360B2 (en) | 2009-07-14 |
US20080122030A1 (en) | 2008-05-29 |
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