US20080237572A1 - Forming a type i heterostructure in a group iv semiconductor - Google Patents
Forming a type i heterostructure in a group iv semiconductor Download PDFInfo
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- US20080237572A1 US20080237572A1 US11/728,890 US72889007A US2008237572A1 US 20080237572 A1 US20080237572 A1 US 20080237572A1 US 72889007 A US72889007 A US 72889007A US 2008237572 A1 US2008237572 A1 US 2008237572A1
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- 239000004065 semiconductor Substances 0.000 title description 4
- 230000004888 barrier function Effects 0.000 claims abstract description 55
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 15
- 229910006990 Si1-xGex Inorganic materials 0.000 claims abstract description 14
- 229910007020 Si1−xGex Inorganic materials 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 13
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 11
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 11
- AXQKVSDUCKWEKE-UHFFFAOYSA-N [C].[Ge].[Si] Chemical compound [C].[Ge].[Si] AXQKVSDUCKWEKE-UHFFFAOYSA-N 0.000 claims abstract description 8
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- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- KAJBHOLJPAFYGK-UHFFFAOYSA-N [Sn].[Ge].[Si] Chemical compound [Sn].[Ge].[Si] KAJBHOLJPAFYGK-UHFFFAOYSA-N 0.000 claims abstract description 5
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- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 2
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- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
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- 230000015572 biosynthetic process Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
- H01L29/151—Compositional structures
- H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
- H01L29/155—Comprising only semiconductor materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
Definitions
- CMOS complementary metal oxide semiconductor
- QW quantum well transistors fabricated from extreme high mobility materials such as, but not limited to, indium antimonide (InSb), indium gallium arsenide (InGaAs) and indium arsenide (InAs).
- transistors are formed using Group IV materials such as germanium (Ge).
- Group IV materials such as germanium (Ge).
- Ge germanium
- MOSFETs complementary-channel metal oxide semiconductor field effect transistors
- FIG. 1 is a cross section view of a device structure in accordance with an embodiment of the present invention.
- FIG. 2 is a band diagram of a structure in accordance with an embodiment of the present invention.
- FIG. 3 is a flow diagram of a method in accordance with an embodiment of the present invention.
- Type I heterostructure channels may be formed in Group IV materials to form CMOS devices. While the scope of the present invention is not limited in this regard, in some implementations a channel may be formed including a Group IV material such as germanium (Ge). For example, in some embodiments a silicon germanium carbon (SiGe(C))-based alloy may be used in a channel region of MOSFET devices. Note that the element in the internal parenthesis (i.e., carbon) is optional.
- the higher bandgap of SiGe(C) and especially positive band offsets for both conduction and valence band edges allows formation of buried channel QWs for both n-channel MOSFETs (NMOS) and p-channel MOSFETs (PMOS). Accordingly, conventional CMOS processing to complete a gate stack may be implemented. Furthermore, presence of a SiGe(C) layer may also provide higher thermal stability for a stack and minimized dopant diffusion for ultra-shallow junctions.
- nMOSFETs and pMOSFETs may be formed on common Ge channels. Such devices may be realized as transport in a high mobility channel may be possible with modulation doping. Furthermore, reduced short channel effect (SCE) within a QW may be realized by raising the bandgap and quantum confinement. Furthermore, a sub-band may be populated with lower effective mass. Still further, n-type dopant diffusions may be reduced to form ultra-shallow junctions and furthermore, compressive strain may be induced in a Ge layer to increase effective electron mass, which improves PMOS performance and lowers electron and hole mobility mismatch.
- SCE short channel effect
- FIG. 1 shown is a cross section view of a device structure 10 in accordance with an embodiment of the present invention.
- structure 10 may be used to form NMOS or PMOS devices on a substrate 30 .
- substrate 30 may be a high resistivity n or p-type ( 100 ) off-oriented Si substrate, although the scope of the present invention is not limited in this regard.
- buffer layer 34 may be a graded silicon germanium tin (SiGe(Sn)) layer. Note again that the element in the internal parenthesis (i.e., tin) is optional. Buffer layer 34 may be formed via an ultra-high vacuum chemical vapor deposition (UHVCVD) or reduced pressure chemical vapor deposition (RPCVD), or another such process. In some embodiments, buffer layer 34 may be formed in a graded manner with increasing Ge concentration from its interface with underlying substrate 30 . As an example, the buffer ramp rates may be in the range of approximately 10-20% per micron of SiGe growth.
- UHVCVD ultra-high vacuum chemical vapor deposition
- RPCVD reduced pressure chemical vapor deposition
- buffer layer 34 may be achieved by wafer bonding or an equivalent process.
- buffer layer 34 may be a buried oxide.
- the thickness of buffer layer 34 may vary depending on deposition method. For grading it may be 10 microns; for bonding onto a buried oxide, the oxide could be of any thickness (e.g., 100-1000 angstroms ( ⁇ )).
- a lower barrier layer 38 may be formed on buffer layer 34 .
- Lower barrier layer 38 may be formed of a higher bandgap material than a quantum well layer to be formed thereon.
- Lower barrier layer 38 may be formed of silicon germanium (Si 1-x Ge x ), in one embodiment.
- Lower barrier layer 38 may be of sufficient thickness to provide a potential barrier to charge carriers in the transistor stack.
- lower barrier layer 38 may have a thickness of between approximately 100 ⁇ -250 ⁇ . In other embodiments, lower barrier layer 38 may be between approximately 2-5 microns ( ⁇ m).
- a quantum well layer 40 may be formed over lower barrier layer 38 .
- Quantum well layer 40 may be formed of multiple materials having both smaller and larger bandgaps than that of lower barrier layer 38 .
- quantum well layer 40 may be formed of a lower QW barrier layer 41 , a QW channel layer 42 , and an upper QW barrier layer 43 .
- lower QW barrier layer 41 may be formed by a pseudomorphic growth of a tensile strained silicon germanium carbon (Si 1-y Ge y (C)) layer, where the germanium content (y) may be lower than the germanium content (x) of barrier layer 38 .
- a compressive strained germanium layer may be pseudomorphically grown to form QW channel layer 42 .
- an upper QW barrier layer 43 which may be formed of silicon germanium carbon (Si 1-z Ge z (C)), whose Ge content (z), may be equal to y or lower, may be formed.
- Quantum well layer 40 may be of sufficient thickness to provide adequate channel conductance. In some embodiments, quantum well layer 40 may be between approximately 10-50 nanometers (nm). Quantum well layer 40 may provide high electron mobility and velocity for NMOS devices, and also may provide high hole mobility and velocity for PMOS devices, both compared to a Si-based device.
- a quantum well in accordance with an embodiment may be formed on a high Ge content silicon germanium on insulator substrate. Yet in other embodiments a quantum well may be grown on a strain compensated silicon germanium tin allow buffer to favor the tensile strain introduction to the QW barrier layers.
- spacer layer 44 optionally may be formed over quantum well layer 40 to provide tensile strain.
- Spacer layer 44 may be a Si 1-x Ge x spacer layer. Spacer layer 44 may provide for carrier confinement and remote ion scattering reduction as well as reduced interaction between a doping layer and a two dimensional electron gas (2DEG) formed inside the channel (i.e., the channel of quantum well layer 40 ). In various embodiments, spacer layer 44 may be approximately 20 ⁇ to 30 ⁇ thick.
- a gate stack may then be formed above this spacer layer 44 .
- a doping layer may be formed over spacer layer 44 .
- Doping layer 46 may be delta-doped, modulation doped and/or combinations thereof.
- doping layer 46 may be a modulation delta-doped layer having a thickness of approximately 3 ⁇ -5 ⁇ .
- doping may be implemented using arsenic (As) or phosphorus (P) impurities.
- doping may be boron (B).
- barrier layer 48 may be formed over doping layer 46 to complete the device stack or layer.
- barrier layer 48 may be an Si 1-x Ge x barrier layer.
- Barrier layer 48 may have a thickness of between approximately 50 ⁇ -500 ⁇ , and may be a Schottky barrier layer for gate control.
- a contact layer 52 may be present to act as a contact layer to provide source and drain contacts with low contact resistance and may be formed of Si 1-x Ge x , in various embodiments.
- contact layer 52 may be n+doped, while for a PMOS device, contact layer 52 may be p+doped.
- Contact layer 52 may be between approximately 30 ⁇ -300 ⁇ thick.
- a fully completed device may further include source and drain electrodes.
- a dielectric material may be formed on barrier layer 48 over which a gate electrode may be formed.
- a gate recess etch may be performed within upper barrier layer 48 to form a gate recess on which the dielectric layer and gate electrode may be formed.
- a Schottky junction may be formed through which a gate electrode may control quantum well layer 40 .
- devices may be formed using a high electron mobility material to form high electron mobility transistors (HEMTs) or high hole mobility transistors (HHMTs) having high speed and low power consumption.
- HEMTs high electron mobility transistors
- HHMTs high hole mobility transistors
- Such devices may have dimensions less than approximately 50 nm with a switching frequency of approximately 562 gigahertz (GHz).
- GHz gigahertz
- Such devices may be able to operate at between approximately 0.5-1.0 volts without significant reduction of drive current.
- embodiments may provide lower gate delay at a gate length than a silicon based device.
- the band diagram illustrates, via the top line a conduction band (i.e., E C ) and via the lower line a valence band (i.e., E V ).
- the lower barrier layer which may be silicon germanium (i.e., Si 1-x Ge x ) may be formed.
- a lower QW barrier layer which may be formed of tensile strain silicon germanium carbon (Si 1-y Ge y (C)) may be formed.
- this barrier layer has a higher bandgap than the buffer layer over which it is formed.
- the compressive strain germanium QW channel layer may be formed which has a smaller bandgap than both the buffer and barrier layers.
- an upper tensile strained silicon germanium carbon (Si 1-z Ge z (C)) barrier layer may be formed that may, in some embodiments have the same bandgap as the lower QW barrier layer.
- an optional tensile strained silicon layer may be formed over the upper QW barrier layer which has a higher bandgap than the other layers.
- method 100 may begin by forming a buffer layer over a Si substrate (block 110 ).
- the buffer layer may be graded SiGe(Sn).
- a lower barrier layer e.g., of Si 1-x Ge x , may be formed (block 120 ).
- a QW layer which may be formed of a tensile strain Si 1-y Ge y (C) lower QW barrier layer, a compressive strain Ge QW channel layer, and a tensile strain Si 1-x Ge x (C) upper QW barrier layer, is formed over the lower barrier layer (block 130 ). Then a spacer layer may be formed over the quantum well (QW) channel layer (block 140 ). Next, a modulation delta-doped layer may be formed (block 150 ). To complete the device stack, an upper barrier layer may be formed over the doped layer (block 160 ). Then a contact layer of Si 1-x Ge x may be formed over the barrier layer (block 170 ).
- source and drains of a device may be formed, and further a gate electrode may be formed on a dielectric layer formed over the contact layer. While shown with this particular implementation in the embodiment of FIG. 3 , the scope of the present invention is not limited in this regard.
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Abstract
Description
- A variety of electronic and optoelectronic devices can be enabled by developing thin film relaxed lattice constant III-V semiconductors on elemental silicon (Si) substrates. Surface layers capable of achieving the performance advantages of III-V materials may host a variety of high performance electronic devices such as complementary metal oxide semiconductor (CMOS) and quantum well (QW) transistors fabricated from extreme high mobility materials such as, but not limited to, indium antimonide (InSb), indium gallium arsenide (InGaAs) and indium arsenide (InAs).
- Other transistors are formed using Group IV materials such as germanium (Ge). However, such transistors have poor n-channel properties, i.e., surface channel properties are poor due to high interface state density near conduction band edges and these devices are unable to form quantum wells. Furthermore, such Ge transistors typically cannot be integrated into complementary-channel metal oxide semiconductor field effect transistors (MOSFETs) using standard complementary CMOS process flows.
-
FIG. 1 is a cross section view of a device structure in accordance with an embodiment of the present invention. -
FIG. 2 is a band diagram of a structure in accordance with an embodiment of the present invention. -
FIG. 3 is a flow diagram of a method in accordance with an embodiment of the present invention. - In various embodiments, Type I heterostructure channels may be formed in Group IV materials to form CMOS devices. While the scope of the present invention is not limited in this regard, in some implementations a channel may be formed including a Group IV material such as germanium (Ge). For example, in some embodiments a silicon germanium carbon (SiGe(C))-based alloy may be used in a channel region of MOSFET devices. Note that the element in the internal parenthesis (i.e., carbon) is optional. The higher bandgap of SiGe(C) and especially positive band offsets for both conduction and valence band edges allows formation of buried channel QWs for both n-channel MOSFETs (NMOS) and p-channel MOSFETs (PMOS). Accordingly, conventional CMOS processing to complete a gate stack may be implemented. Furthermore, presence of a SiGe(C) layer may also provide higher thermal stability for a stack and minimized dopant diffusion for ultra-shallow junctions.
- Accordingly, in various embodiments nMOSFETs and pMOSFETs may be formed on common Ge channels. Such devices may be realized as transport in a high mobility channel may be possible with modulation doping. Furthermore, reduced short channel effect (SCE) within a QW may be realized by raising the bandgap and quantum confinement. Furthermore, a sub-band may be populated with lower effective mass. Still further, n-type dopant diffusions may be reduced to form ultra-shallow junctions and furthermore, compressive strain may be induced in a Ge layer to increase effective electron mass, which improves PMOS performance and lowers electron and hole mobility mismatch.
- Referring now to
FIG. 1 , shown is a cross section view of adevice structure 10 in accordance with an embodiment of the present invention. As shown inFIG. 1 ,structure 10 may be used to form NMOS or PMOS devices on asubstrate 30. In various embodiments,substrate 30 may be a high resistivity n or p-type (100) off-oriented Si substrate, although the scope of the present invention is not limited in this regard. - As shown in
FIG. 1 , next abuffer layer 34 may be formed onsubstrate 30. In various embodiments,buffer layer 34 may be a graded silicon germanium tin (SiGe(Sn)) layer. Note again that the element in the internal parenthesis (i.e., tin) is optional.Buffer layer 34 may be formed via an ultra-high vacuum chemical vapor deposition (UHVCVD) or reduced pressure chemical vapor deposition (RPCVD), or another such process. In some embodiments,buffer layer 34 may be formed in a graded manner with increasing Ge concentration from its interface withunderlying substrate 30. As an example, the buffer ramp rates may be in the range of approximately 10-20% per micron of SiGe growth. In this way, increasing Ge concentration is realized such that at a top portion, the layer may have a Ge concentration of at least approximately 80%, in some embodiments. Alternately,buffer layer 34 may be achieved by wafer bonding or an equivalent process. In still other embodiments,buffer layer 34 may be a buried oxide. In some embodiments, the thickness ofbuffer layer 34 may vary depending on deposition method. For grading it may be 10 microns; for bonding onto a buried oxide, the oxide could be of any thickness (e.g., 100-1000 angstroms (Å)). - A
lower barrier layer 38 may be formed onbuffer layer 34.Lower barrier layer 38 may be formed of a higher bandgap material than a quantum well layer to be formed thereon.Lower barrier layer 38 may be formed of silicon germanium (Si1-xGex), in one embodiment.Lower barrier layer 38 may be of sufficient thickness to provide a potential barrier to charge carriers in the transistor stack. In one embodiment,lower barrier layer 38 may have a thickness of between approximately 100 Å-250 Å. In other embodiments,lower barrier layer 38 may be between approximately 2-5 microns (μm). - Referring still to
FIG. 1 , aquantum well layer 40 may be formed overlower barrier layer 38.Quantum well layer 40 may be formed of multiple materials having both smaller and larger bandgaps than that oflower barrier layer 38. In one embodiment,quantum well layer 40 may be formed of a lowerQW barrier layer 41, a QW channel layer 42, and an upperQW barrier layer 43. In one embodiment, lowerQW barrier layer 41 may be formed by a pseudomorphic growth of a tensile strained silicon germanium carbon (Si1-yGey(C)) layer, where the germanium content (y) may be lower than the germanium content (x) ofbarrier layer 38. Above this lowerQW barrier layer 41, a compressive strained germanium layer may be pseudomorphically grown to form QW channel layer 42. In turn, over QW channel layer 42 an upperQW barrier layer 43, which may be formed of silicon germanium carbon (Si1-zGez(C)), whose Ge content (z), may be equal to y or lower, may be formed.Quantum well layer 40 may be of sufficient thickness to provide adequate channel conductance. In some embodiments,quantum well layer 40 may be between approximately 10-50 nanometers (nm).Quantum well layer 40 may provide high electron mobility and velocity for NMOS devices, and also may provide high hole mobility and velocity for PMOS devices, both compared to a Si-based device. In other embodiments, a quantum well in accordance with an embodiment may be formed on a high Ge content silicon germanium on insulator substrate. Yet in other embodiments a quantum well may be grown on a strain compensated silicon germanium tin allow buffer to favor the tensile strain introduction to the QW barrier layers. - As further shown in
FIG. 1 , aspacer layer 44 optionally may be formed overquantum well layer 40 to provide tensile strain.Spacer layer 44 may be a Si1-xGex spacer layer.Spacer layer 44 may provide for carrier confinement and remote ion scattering reduction as well as reduced interaction between a doping layer and a two dimensional electron gas (2DEG) formed inside the channel (i.e., the channel of quantum well layer 40). In various embodiments,spacer layer 44 may be approximately 20 Å to 30 Å thick. - A gate stack may then be formed above this
spacer layer 44. A doping layer may be formed overspacer layer 44.Doping layer 46 may be delta-doped, modulation doped and/or combinations thereof. For example, in oneembodiment doping layer 46 may be a modulation delta-doped layer having a thickness of approximately 3 Å-5 Å. For an NMOS device, doping may be implemented using arsenic (As) or phosphorus (P) impurities. As for a PMOS device, doping may be boron (B). - Referring still to
FIG. 1 , anupper barrier layer 48 may be formed overdoping layer 46 to complete the device stack or layer. In one embodiment,barrier layer 48 may be an Si1-xGex barrier layer.Barrier layer 48 may have a thickness of between approximately 50 Å-500 Å, and may be a Schottky barrier layer for gate control. - As further shown in
FIG. 1 , acontact layer 52 may be present to act as a contact layer to provide source and drain contacts with low contact resistance and may be formed of Si1-xGex, in various embodiments. For an NMOS device,contact layer 52 may be n+doped, while for a PMOS device,contact layer 52 may be p+doped.Contact layer 52 may be between approximately 30 Å-300 Å thick. - While not shown in
FIG. 1 , a fully completed device may further include source and drain electrodes. Furthermore, a dielectric material may be formed onbarrier layer 48 over which a gate electrode may be formed. Note that a gate recess etch may be performed withinupper barrier layer 48 to form a gate recess on which the dielectric layer and gate electrode may be formed. Thus a Schottky junction may be formed through which a gate electrode may controlquantum well layer 40. - Accordingly, in various embodiments devices may be formed using a high electron mobility material to form high electron mobility transistors (HEMTs) or high hole mobility transistors (HHMTs) having high speed and low power consumption. Such devices may have dimensions less than approximately 50 nm with a switching frequency of approximately 562 gigahertz (GHz). Such devices may be able to operate at between approximately 0.5-1.0 volts without significant reduction of drive current. Furthermore, embodiments may provide lower gate delay at a gate length than a silicon based device.
- Referring now to
FIG. 2 , shown is a band diagram of a structure in accordance with an embodiment of the present invention. As shown inFIG. 2 , the band diagram illustrates, via the top line a conduction band (i.e., EC) and via the lower line a valence band (i.e., EV). Beginning at the left-hand side ofFIG. 2 , the lower barrier layer, which may be silicon germanium (i.e., Si1-xGex) may be formed. Over this layer, a lower QW barrier layer, which may be formed of tensile strain silicon germanium carbon (Si1-yGey(C)) may be formed. As shown, this barrier layer has a higher bandgap than the buffer layer over which it is formed. In turn, the compressive strain germanium QW channel layer may be formed which has a smaller bandgap than both the buffer and barrier layers. Over the QW channel layer, an upper tensile strained silicon germanium carbon (Si1-zGez(C)) barrier layer may be formed that may, in some embodiments have the same bandgap as the lower QW barrier layer. Then, as shown inFIG. 2 , an optional tensile strained silicon layer may be formed over the upper QW barrier layer which has a higher bandgap than the other layers. - Referring now to
FIG. 3 , shown is a flow diagram of a method in accordance with an embodiment of the present invention. As shown inFIG. 3 ,method 100 may begin by forming a buffer layer over a Si substrate (block 110). As described above, in some embodiments the buffer layer may be graded SiGe(Sn). Next, a lower barrier layer, e.g., of Si1-xGex, may be formed (block 120). Next, a QW layer, which may be formed of a tensile strain Si1-yGey(C) lower QW barrier layer, a compressive strain Ge QW channel layer, and a tensile strain Si1-xGex(C) upper QW barrier layer, is formed over the lower barrier layer (block 130). Then a spacer layer may be formed over the quantum well (QW) channel layer (block 140). Next, a modulation delta-doped layer may be formed (block 150). To complete the device stack, an upper barrier layer may be formed over the doped layer (block 160). Then a contact layer of Si1-xGex may be formed over the barrier layer (block 170). Of course, from this contact layer, source and drains of a device may be formed, and further a gate electrode may be formed on a dielectric layer formed over the contact layer. While shown with this particular implementation in the embodiment ofFIG. 3 , the scope of the present invention is not limited in this regard. - While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
Claims (14)
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