US20080207002A1 - Method of removing graphitic and/or fluorinated organic layers from the surface of a chip passivation layer having si-containing compounds - Google Patents

Method of removing graphitic and/or fluorinated organic layers from the surface of a chip passivation layer having si-containing compounds Download PDF

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US20080207002A1
US20080207002A1 US11/679,247 US67924707A US2008207002A1 US 20080207002 A1 US20080207002 A1 US 20080207002A1 US 67924707 A US67924707 A US 67924707A US 2008207002 A1 US2008207002 A1 US 2008207002A1
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passivation layer
graphitic
plasma
chip
organic layers
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US7938976B2 (en
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Kang-Wook Lee
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GlobalFoundries Inc
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International Business Machines Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02082Cleaning product to be cleaned

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  • the present invention pertains to the provision of reliable flip chip plastic or organic semiconductor packages, and to a method of producing the packages. More specifically, the present invention is directed to the removal of graphitic and/or fluorinated organic layers from a semiconductor chip passivation layer surface in the instance that a chip passivation layer includes Si-containing materials, whereby the treated chip is employed to make a flip chip plastic package, providing for an increase in the yield or output thereof.
  • the surface of an advanced semiconductor chip is typically provided with solder balls and a passivation layer.
  • the passivation layer may be constituted of silicon nitride, a polyimide, a photosensitive polyimide, or of a benzocyclobutane polymer, whereas the solder balls may consist of a Pb and Sn alloy or a Pb-free alloy, whereby the major metallic component of the latter is tin (Sn).
  • Sn tin
  • the most recently employed semiconductor chips have a tendency to be equipped with Pb-free solder balls in order to protect the environment.
  • the surface of a polymer passivation layer which is provided, includes a graphitic organic layer and/or a fluorinated organic layer.
  • FC-PBGA flip chip plastic ball grid array
  • a chip is placed onto and electrically connected with a laminate, in which flux is employed in the flip chip-joining step, and the subsequently formed residue is ordinarily cleaned with DI water.
  • a graphitic layer and/or a fluorinated layer which is present on the surface of a chip passivation layer, render the post-chip joint cleaning process difficult to implement, whereby a certain level of organotin residue, which is formed during chip joining process remains in an uncleaned condition.
  • the gap which remains between a chip and a laminate in an FC-PBGA package, is filled with an underfill material in order to reinforce the mechanical and electrical strength and operational integrity of the FC-PBGA package.
  • the underfill-chip interface evidences a tendency to delaminate in the presence of some level of organotin residue. In that instance, the delamination frequently leads to an extrusion of solder so as to form a tin bridge between adjacent solder balls, thereby resulting in electrical shorts.
  • the presence of a graphitic layer on a chip passivation layer can also cause electrical shorts, inasmuch as it is electrically conductive in nature.
  • Oxygen (O 2 ) plasma can readily remove a graphitic and/or fluorinated organic layer.
  • O 2 plasma processes create SiO 2 particles on a photosensitive polyimide (PSPI) and a poly (benzocyclobutane-siloxane) (BCB) since they contain silane compounds.
  • N 2 plasma can remove graphitic and/or fluorinated layers without creating SiO 2 particles or SnOx/organotin on PSPI or BCB.
  • a combination of a high-power and a low-pressure re-deposits Sn/SnOx/organotin onto the polymer surface.
  • the best condition for an N 2 plasma is to employ a low-power (100-200 W) and a high-pressure (500-750 mTorr).
  • a wafer is treated with N 2 plasma to eliminate graphitic and/or fluorinated layers, and then followed by a typical process to prepare chips.
  • FIG. 1 a illustrates an XPS spectrum on the surface of a chip passivation layer that includes both graphitic and fluorinated layers;
  • FIG. 1 b illustrates an XPS spectrum on the chip passivation layer surface treated with N 2 gas plasma
  • FIG. 2 a illustrates a high-resolution C1s spectrum corresponding to FIG. 1 a ;
  • FIG. 2 b illustrates a high-resolution C1s spectrum corresponding to FIG. 1 b.
  • FIG. 1 a shows a high-resolution spectrum of C1s XPS that demonstrates a typical graphitic layer, which has been formed on polyimide.
  • FIG. 1 b clearly demonstrates the XPS, which indicates a decrease of F;
  • FIG. 2 b represents the high-resolution spectrum of C1s clearly evidencing the disappearance of the graphitic layer after treatment with N 2 plasma under low-power and high-pressure conditions, as set forth hereinabove, i.e., at a power of about 100-200 W, and a high-pressure of about 500-750 mTorr.
  • the N 2 plasma is employed in an etching process on the passivation layer, hereby etching the layer to a depth of about 1-100 nm, and preferably 5-20 nm.

Abstract

A method for removing undesirable contaminants from a chip passivation layer surface without creating SiO2 particles on the passivation layer, wherein the undesirable contaminants include graphitic layers and fluorinated layers. The use of N2 plasma with optimized plasma parameters can remove through etching both the graphitic and fluorinated organic layers. The best condition for the N2 plasma treatment is to use a relatively low-power within the range of 100-200 W and a relatively high vacuum pressure of N2 in the range of 500-750 mTorr.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention pertains to the provision of reliable flip chip plastic or organic semiconductor packages, and to a method of producing the packages. More specifically, the present invention is directed to the removal of graphitic and/or fluorinated organic layers from a semiconductor chip passivation layer surface in the instance that a chip passivation layer includes Si-containing materials, whereby the treated chip is employed to make a flip chip plastic package, providing for an increase in the yield or output thereof.
  • The surface of an advanced semiconductor chip is typically provided with solder balls and a passivation layer. Generally, the passivation layer may be constituted of silicon nitride, a polyimide, a photosensitive polyimide, or of a benzocyclobutane polymer, whereas the solder balls may consist of a Pb and Sn alloy or a Pb-free alloy, whereby the major metallic component of the latter is tin (Sn). The most recently employed semiconductor chips have a tendency to be equipped with Pb-free solder balls in order to protect the environment. In the process of producing the Pb-free solder balls, the surface of a polymer passivation layer, which is provided, includes a graphitic organic layer and/or a fluorinated organic layer.
  • In a process of manufacturing flip chip plastic ball grid array (FC-PBGA), a chip is placed onto and electrically connected with a laminate, in which flux is employed in the flip chip-joining step, and the subsequently formed residue is ordinarily cleaned with DI water. However, a graphitic layer and/or a fluorinated layer, which is present on the surface of a chip passivation layer, render the post-chip joint cleaning process difficult to implement, whereby a certain level of organotin residue, which is formed during chip joining process remains in an uncleaned condition.
  • The gap, which remains between a chip and a laminate in an FC-PBGA package, is filled with an underfill material in order to reinforce the mechanical and electrical strength and operational integrity of the FC-PBGA package. The underfill-chip interface evidences a tendency to delaminate in the presence of some level of organotin residue. In that instance, the delamination frequently leads to an extrusion of solder so as to form a tin bridge between adjacent solder balls, thereby resulting in electrical shorts. In addition thereto, the presence of a graphitic layer on a chip passivation layer can also cause electrical shorts, inasmuch as it is electrically conductive in nature.
  • 2. Discussion of the Prior Art
  • In view of the above-mentioned difficulties, it, thus, becomes necessary to remove the graphitic layer and/or fluorinated polymer layer in order to be able to obtain a clean polymer passivation layer surface, whereby the resultant clean passivation layer surface provides a reliable FC-PBGA electronic package. Oxygen (O2) plasma can readily remove a graphitic and/or fluorinated organic layer. However, O2 plasma processes create SiO2 particles on a photosensitive polyimide (PSPI) and a poly (benzocyclobutane-siloxane) (BCB) since they contain silane compounds. It is well known that O2 plasma on a polymer with silane organic compounds cumulates SiO2 particles on the polymer surface since the plasma forms SiO2 while the polymer is etched. The use of a N2 and H2 mixture gas tends to leave some graphitic layers since H2 plasma reduces organic molecules.
  • SUMMARY OF THE INVENTION
  • Accordingly, there is a need in the technology to be able to remove a graphitic organic layer and/or a fluorinated organic layer without creating SiO2 particles.
  • Pursuant to the invention, there is provided a simple technique for removing undesirable contaminants from the surface of a chip passivation layer, wherein such undesirable contaminants may include graphitic layers and fluorinated organic layers, and which the chip passivation layer can consist of polyimide, PSPI, BCB, and the like.
  • In connection with the foregoing, N2 plasma can remove graphitic and/or fluorinated layers without creating SiO2 particles or SnOx/organotin on PSPI or BCB. A combination of a high-power and a low-pressure re-deposits Sn/SnOx/organotin onto the polymer surface. The best condition for an N2 plasma is to employ a low-power (100-200 W) and a high-pressure (500-750 mTorr). A wafer is treated with N2 plasma to eliminate graphitic and/or fluorinated layers, and then followed by a typical process to prepare chips.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 a illustrates an XPS spectrum on the surface of a chip passivation layer that includes both graphitic and fluorinated layers;
  • FIG. 1 b illustrates an XPS spectrum on the chip passivation layer surface treated with N2 gas plasma;
  • FIG. 2 a illustrates a high-resolution C1s spectrum corresponding to FIG. 1 a; and
  • FIG. 2 b illustrates a high-resolution C1s spectrum corresponding to FIG. 1 b.
  • DETAILED DESCRIPTION OF THE INVENTION
  • As shown in FIG. 1 a, the XPS spectrum of a semiconductor chip prior to the treatment with N2 plasma, which evidences a considerable amount of F and graphitic layers. FIG. 2 a shows a high-resolution spectrum of C1s XPS that demonstrates a typical graphitic layer, which has been formed on polyimide.
  • A chip with a graphitic and fluorinated layer was treated with N2 plasma. FIG. 1 b clearly demonstrates the XPS, which indicates a decrease of F; FIG. 2 b represents the high-resolution spectrum of C1s clearly evidencing the disappearance of the graphitic layer after treatment with N2 plasma under low-power and high-pressure conditions, as set forth hereinabove, i.e., at a power of about 100-200 W, and a high-pressure of about 500-750 mTorr. The N2 plasma is employed in an etching process on the passivation layer, hereby etching the layer to a depth of about 1-100 nm, and preferably 5-20 nm.
  • While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but to fall within the spirit and scope of the appended claims.

Claims (3)

1. A method for removing contaminants including graphitic and/or fluorinated organic layers from a surface of semiconductor chip passivation layer having Si-containing compounds, said method comprising subjecting said surface to an N2 plasma etching process under a low-power within a range of about 100-200 W and a high-pressure within a range of about 500-750 mTorr.
2. A method as claimed in claim 1, wherein said N2 plasma etches the surface of said chip passivation layer to a depth of within about 1-100 nm.
3. A method as claimed in claim 1, wherein said N2 plasma-etching process is implemented on semiconductor wafers which are subsequently processed to form a plurality of said chips.
US11/679,247 2007-02-27 2007-02-27 Method of removing graphitic and/or fluorinated organic layers from the surface of a chip passivation layer having Si-containing compounds Expired - Fee Related US7938976B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107803507A (en) * 2017-09-28 2018-03-16 河南亚龙金刚石制品股份有限公司 A kind of quick method for removing residual cobalt in diamond compact glomerocryst layer

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020162736A1 (en) * 2001-05-02 2002-11-07 Advanced Micro Devices, Inc. Method of forming low resistance vias
US6605480B2 (en) * 2001-11-28 2003-08-12 Chipmos Technologies Inc. Wafer level packaging for making flip-chips
US6649531B2 (en) * 2001-11-26 2003-11-18 International Business Machines Corporation Process for forming a damascene structure
US20040219797A1 (en) * 2001-12-05 2004-11-04 Masanobu Honda Plasma etching method and plasma etching unit
US20050161834A1 (en) * 2001-09-14 2005-07-28 Cowens Marvin W. Adhesion by plasma conditioning of semiconductor chip
US20090137129A1 (en) * 2005-08-22 2009-05-28 Hitachi Chemical Dupont Microsystems Ltd. Method for manufacturing semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020162736A1 (en) * 2001-05-02 2002-11-07 Advanced Micro Devices, Inc. Method of forming low resistance vias
US20050161834A1 (en) * 2001-09-14 2005-07-28 Cowens Marvin W. Adhesion by plasma conditioning of semiconductor chip
US6649531B2 (en) * 2001-11-26 2003-11-18 International Business Machines Corporation Process for forming a damascene structure
US6605480B2 (en) * 2001-11-28 2003-08-12 Chipmos Technologies Inc. Wafer level packaging for making flip-chips
US20040219797A1 (en) * 2001-12-05 2004-11-04 Masanobu Honda Plasma etching method and plasma etching unit
US20090137129A1 (en) * 2005-08-22 2009-05-28 Hitachi Chemical Dupont Microsystems Ltd. Method for manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107803507A (en) * 2017-09-28 2018-03-16 河南亚龙金刚石制品股份有限公司 A kind of quick method for removing residual cobalt in diamond compact glomerocryst layer

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