US20080191359A1 - Panel, semiconductor device and method for the production thereof - Google Patents
Panel, semiconductor device and method for the production thereof Download PDFInfo
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- US20080191359A1 US20080191359A1 US11/677,774 US67777407A US2008191359A1 US 20080191359 A1 US20080191359 A1 US 20080191359A1 US 67777407 A US67777407 A US 67777407A US 2008191359 A1 US2008191359 A1 US 2008191359A1
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- semiconductor
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- semiconductor components
- panel
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Definitions
- the application relates to a panel, a semiconductor device and method for the production thereof.
- Semiconductor components such as semiconductor chips, are normally used in the form of a semiconductor device.
- the semiconductor device normally provides an internal rewiring extending between the doped regions of the semiconductor material of the semiconductor component and the external contacts of the semiconductor device in order to simplify the electrical access to the semiconductor chip.
- the semiconductor device may have a housing that protects the semiconductor component against damage.
- the internal rewiring and the housing influence the electrical power and thermal capacity, the so-called performance of the semiconductor device.
- a panel may comprise a baseplate with an upper first metallic layer and a multiplicity of a vertical semiconductor components.
- the vertical semiconductor components in each case may comprise a first side with a first load electrode and a control electrode and an opposite second side with a second load electrode.
- the second side of the semiconductor components is in each case mounted on the metallic layer of the baseplate.
- the semiconductor components can be arranged in such a way that edge sides of adjacent semiconductor components are separated from one another.
- a second metallic layer can be arranged in separating regions between the semiconductor components.
- a method for the production of a panel may comprise the following features.
- a multiplicity of vertical semiconductor components are provided, wherein the semiconductor components in each case comprise a first side with a first load electrode and a control electrode and an opposite second side with a second load electrode, wherein the second sides of the semiconductor components are arranged on a metallic layer in such a way that edge sides of adjacent semiconductor components are separated from one another by means of separating regions, and the second sides are electrically connected to the metallic layer.
- At least one metal is deposited onto the metallic layer in the separating regions between the semiconductor components, with the result that the edge sides of the semiconductor components are covered by the deposited metal.
- FIG. 1 shows a cross section of a panel with a multiplicity of semiconductor components
- FIG. 2 shows a cross section of the panel from FIG. 1 with rear side rewiring
- FIG. 3 shows a plan view of the panel from FIG. 2 .
- FIG. 4 shows a cross section of a semiconductor device according to a first embodiment
- FIG. 5 shows a perspective view of the semiconductor device from FIG. 4 .
- FIG. 6 a shows a perspective view of a semiconductor device according to a second embodiment with a first external contact area arrangement
- FIG. 6 b shows a perspective view of a semiconductor device according to a second embodiment with a second external contact area arrangement
- FIG. 7 shows a cross section of a panel according to a third embodiment
- FIG. 8 shows a cross section of a panel according to a fourth embodiment
- FIG. 9 shows a cross section of a panel according to a fifth embodiment
- FIG. 10 shows the production of a multiplicity of semiconductor components from the panel from FIG. 9 .
- FIG. 11 shows the production of a rear side rewiring of the semiconductor components from FIG. 10 .
- FIG. 12 shows a semiconductor device according to a sixth embodiment
- FIG. 13 shows a semiconductor device according to a seventh embodiment
- FIG. 14 shows a semiconductor device according to a eighth embodiment
- FIG. 15 shows a semiconductor device according to a ninth embodiment
- FIG. 16 shows a plan view of the semiconductor device from FIG. 15 .
- FIG. 17 shows a semiconductor device according to a tenth embodiment.
- FIGS. 1 to 5 show the production of a panel 10 , which is singulated in order to produce a plurality of semiconductor devices 11 .
- FIGS. 6 a and 6 b in each case show a semiconductor device 12 produced by means of a panel.
- the semiconductor device 12 differs from the semiconductor device 11 through the arrangement of the external contact areas 13 .
- FIGS. 7 and 8 in each case show a panel according to further embodiments.
- FIGS. 9 to 11 show the production of a panel according to one embodiment and FIGS. 12 to 17 show semiconductor devices which can be produced by means of the panel from FIG. 11 .
- FIG. 1 shows a cross section of a panel 10 having a baseplate 14 in the form of a carrier 14 with an upper metallic layer and a multiplicity of semiconductor components 15 .
- the carrier 14 is a metallic plate, in particular a copper plate.
- the semiconductor components 15 are in each case a vertical semiconductor component, in particular a vertical power transistor in the form of a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor).
- the semiconductor component 15 may be an IGBT (Isolated Gate Bipolar Transistor) or a BJT (Bipolar Junction Transistor) or a diode.
- the semiconductor component 15 has a first side 16 with a first load electrode 17 and a control electrode 18 and an opposite second side 19 with a second load electrode 20 .
- the electrodes 17 , 18 and 20 in each case have the form of a contact area.
- the first load electrode 17 and also the second load electrode 20 are in each case large-area contacts.
- the control electrode is a small-area contact.
- the two electrodes 17 , 18 on the first side 16 are electrically insulated from one another.
- the first load electrode 17 is designated as source
- the control electrode 18 is designated as gate
- the second load electrode 20 is designated as drain, since the semiconductor component 15 is a MOSFET.
- a multiplicity of the semiconductor components 15 are provided.
- the second side 19 of the semiconductor components 15 is arranged on the metallic surface 24 of the carrier 14 in such a way that the edge sides 21 of adjacent semiconductor components 15 are separated from one another by means of separating regions 22 .
- the second side 19 is electrically connected to the metallic surface 24 of the carrier 14 .
- individual semiconductor components 15 are mounted onto the carrier 14 .
- the second side 19 of the semiconductor components 15 is mounted on the upper metallic layer of the carrier 14 .
- the semiconductor components 15 are arranged in such a way that the edge sides 21 of adjacent semiconductor components 15 are separated from one another by means of separating regions 22 .
- the semiconductor components 15 are arranged in columns and rows, with the result that the separating regions 22 have sawing tracks.
- the sawing tracks are represented by a broken line in the figures.
- the second side 19 or the second load electrode 20 of the semiconductor components 15 is mounted on the surface 24 of the copper plate 14 by means of a diffusion solder connection 23 .
- the semiconductor components can be mounted onto the carrier by means of a soft solder connection.
- a layer of a diffusion solder is deposited on the second load electrode 19 .
- the plate 14 is heated to a temperature lying above the melting point of the diffusion solder.
- the second side 19 of the semiconductor component 15 is pressed onto the surface of the carrier 14 , said surface comprising copper.
- the diffusion solder melts and reacts with the material of the surface of the plate 14 , intermetallic phases being formed. Said intermetallic phases have a higher melting point than the melting point of the diffusion solder. Consequently, the boundary between the second side 19 of the semiconductor component 15 and the plate 14 solidifies and forms the diffusion solder connection 23 .
- Said diffusion solder connection thus has a higher melting point than the melting point of the diffusion solder. Consequently, further semiconductor components 15 can be mounted on the plate 14 without the diffusion solder connections 23 that have already been produced melting again. A multiplicity of semiconductor components 15 can thus be reliably mounted on the plate 14 piece by piece.
- FIG. 2 shows a cross section of the panel 10 from FIG. 1 with rear side rewiring 25 .
- at least one metal 26 is deposited onto the plate 14 , in particular into the separating regions between the semiconductor components 15 .
- the metal 26 may be copper or a copper alloy.
- the metal 26 is built up layer by layer and forms a layer 27 of the panel 10 .
- the layer 27 is cohesively connected to the edge margins and edge sides of the semiconductor components 15 .
- the deposition is carried out in such a way that the separating regions 22 are essentially filled by the deposited metal. This may be implemented by the setting of the deposition duration.
- the edge sides 21 of the semiconductor component 15 are sealed by the metal layer 27 . Consequently, there is no need to use a plastic composition for protection against air and moisture.
- the layer 27 is deposited in order to provide a rear side rewiring.
- the semiconductor components 15 are vertical components in which contact areas are arranged on two opposite sides 16 , 19 of the component 15 .
- a rewiring structure is provided for making contact with the two sides 16 , 19 of the component 15 , with the result that all the contact areas can be acted on from a single side of the semiconductor component 15 .
- the layer 27 has at least one metal that is deposited directly on the surface 24 of the plate 14 and is electrically connected to the plate 14 .
- the plate 14 is electrically connected to the second load electrode 19 by means of the diffusion solder connection 23 .
- the second load electrode 19 can therefore be acted on electrically from the opposite side 16 of the semiconductor component 15 via the plate 14 and via the layer 27 .
- the layer 27 is built up layer by layer by the deposition until at least regions of the surface 28 of the layer 27 are essentially coplanar with the first load electrode 17 and with the control electrode 18 , in particular until at least regions of the surface 28 of the layer 27 are essentially coplanar with the outer surface of the first load electrode 17 and the control electrode 18 .
- the layer 27 is produced by means of electrodeposition.
- the potential of the electrolytic cell is connected to the plate 14 . Consequently, the metal is deposited principally on the plate 14 . Hardly any metal or even no metal is deposited onto the first load electrode 17 and the control electrode 18 during the deposition method.
- the metal layer 27 is deposited with a thickness d that is greater than the height h of the semiconductor component 15 .
- the surface 28 of the metal layer 27 lies above the outer surface 29 of the first load electrode 17 and the control electrode 18 .
- This side of the panel 10 is then planarized. This may be carried out by grinding away, such as CMP (chemical mechanical polishing).
- the panel 10 therefore has a plate 14 on which a metallic layer 27 is deposited.
- the semiconductor components 15 are embedded in said metallic layer 27 .
- the panel 10 has no plastic housing composition since the metal layer 27 is arranged directly on the edge sides 20 of the semiconductor components 15 .
- FIG. 3 shows a plan view of the panel 10 from FIG. 2 .
- FIG. 3 illustrates the arrangement of the semiconductor components 15 and also the arrangement of the electrodes 17 , 18 on the first side 16 of the semiconductor components.
- the semiconductor components 15 are arranged in columns and rows and are separated from one another by means of the separating regions 22 .
- the separating regions 22 in each case provide a sawing track.
- the smaller control electrode 18 is in strip form and the larger first load electrode 17 is rectangular.
- FIG. 4 shows a semiconductor device 30 produced by the separation of the panel from FIGS. 2 and 3 .
- the panel 10 is separated along the sawing tracks in the separating regions 22 . This may be carried out by means of sawing by a laser.
- a rewiring element 31 is produced for each semiconductor component 15 and a semiconductor device is produced.
- the semiconductor device 30 has no plastic housing composition since the edge sides 20 and the second side 20 of the semiconductor component 15 are covered with the metal 26 of the metal layer 27 and with the plate 14 .
- the metal layer 27 provides a sealing of the edge sides of the semiconductor component 15 .
- the semiconductor device 30 has a rewiring element 31 extending from the second side 19 of the semiconductor component 15 as far as the first side 16 .
- the rewiring element 31 therefore provides a rear side rewiring.
- the rewiring element 31 comprises a baseplate 32 , which is arranged on the second side 19 of the semiconductor component 15 and which projects beyond the edge sides 20 , and comprises an edge 33 , which is approximately perpendicular to the baseplate 32 and cohesively connected to the edge sides 21 of the semiconductor component 15 .
- the rewiring element 31 therefore has a pedestal form, the inner surface of the base and of the walls being cohesively connected to the semiconductor component 15 .
- the outer surfaces 34 of the rewiring element 31 are outer surfaces of the semiconductor device 30 .
- the outer dimensions of the semiconductor device 30 are only somewhat greater than the outer dimensions of the semiconductor component 15 .
- the semiconductor device 30 is a chip sized package.
- the surface 29 of the first load electrode 17 and of the control electrode 18 and the surface 28 of the metal layer 27 provide the external contact areas 13 of the semiconductor device 30 .
- Said external contact areas 13 are surface-mountable.
- the first load electrode 17 and the control electrode 18 have a metal layer having a thickness of above 30 ⁇ m, above 50 ⁇ m or above 100 ⁇ m.
- solder balls are applied on said surfaces. The solder balls provide the external contacts of the semiconductor device.
- the first load electrode 17 and the control electrode have copper pillars that form the external contact areas of the semiconductor device 30 .
- the smaller control electrode 18 may have a single pillar, while the larger first load electrode 18 has a plurality of pillars.
- the semiconductor device 11 is therefore a so-called “power chip sized package” (PowerCSP).
- PowerCSP power chip sized package
- the metallic sheathing provides the rewiring of the chip rear side electrode of the power MOSFET, which simultaneously serves as an external contact region.
- the heights of the chip front sides and of the chip rear side contact regions within said “chip sized package” can thus be coordinated precisely with one another.
- the coordination between separate die attach layer and front side contacts can therefore be avoided.
- any desired amounts of one or more metals, for example copper can be integrated within the “power chip sized package”. As a result, the thermal short- and long-time capacity of the device is flexibly set and optimized.
- FIGS. 5 , 6 a and 6 b show three embodiments of the external contact areas 13 .
- the surface 29 of the width of the edge or of the walls 33 of the rewiring element 31 is essentially coplanar with the outer surface 29 of the first load electrode 17 and the control electrode 18 at all four edge sides 20 of the semiconductor component 15 .
- This common plane is shown with the reference symbol 30 .
- the outer surface 29 of the rewiring structure 31 is therefore ring-shaped. This structure is produced during the planarization of the upper side of the panel 10 .
- the planarization may be effected by grinding away or by setting the deposition duration.
- the surface 29 provides the drain terminal of the semiconductor device 11 . This arrangement has the advantage that a larger contact area is provided.
- Said semiconductor device 11 can be mounted on a multilayer circuit board in which the rewiring of the source electrode 17 and gate electrode 18 and the drain electrode 20 can be arranged on different planes and thereby be electrically insulated from one another.
- the rewiring of the source electrode 17 and the gate electrode 18 can be led under the rewiring of the outer drain electrode 20 .
- FIGS. 6 a and 6 b in each case show a semiconductor device 12 according to one embodiment, said semiconductor device having a semiconductor component 15 and a rewiring element 41 .
- the walls 42 or the edges of the rewiring element 41 are structured, with the result that the outer surface 43 of the wall thickness 42 alongside only two opposite edge sides 20 of the semiconductor component 15 are essentially coplanar with the outer surface 29 of the first load electrode 17 and the control electrode 18 .
- the surfaces 44 of the remaining two sides 45 of the rewiring element 41 lie in a plane below the surface 43 and therefore do not provide an external contact area.
- the surfaces 43 of the two opposite walls 42 provide external contact areas, in particular the drain terminal.
- the rewiring element 41 has a U-shape in which the two opposite higher sides 42 provide the legs of the U-shape.
- the source electrode contact area 17 and the gate electrode contact area 18 are in each case in strip form.
- the longitudinal sides of the higher edge sides 42 of the rewiring element 41 are approximately perpendicular to the longitudinal sides of the strip-type source electrode contact area 17 and gate electrode contact area 18 .
- the longitudinal sides of the higher edge sides 42 of the rewiring element 41 are arranged approximately parallel to the longitudinal sides of the strip-type source electrode contact area 17 and gate electrode contact area 18 .
- This arrangement enables a plurality of semiconductor devices to be electrically coupled in parallel with one another since the semiconductor devices 12 can be mounted alongside one another on strip-type contact areas on the circuit board.
- the strip-type contact areas on the circuit board in each case provide a common contact for a type of semiconductor device contact area.
- the source contact area of a plurality of semiconductor devices is mounted on a single strip-type contact area on the circuit board, which provides a common supply contact.
- This semiconductor device 12 from FIG. 6 a and FIG. 6 b can be mounted on a single-layer circuit board since it is possible to lead the rewiring of the first load electrode 17 and of the control electrode 18 on the surface of the circuit board under the two short edge sides 42 of the rewiring element 41 , since said short edge sides 42 are not in contact with the circuit board.
- the semiconductor device 12 with an external contact area arrangement according to FIG. 6 a or FIG. 6 b is also produced by the production of a panel 10 as described above.
- the surface of the metal layer 27 is structured in order to produce strip-type elevated regions at two opposite edge sides 20 of the semiconductor components 15 of the panel 10 .
- the metal layer 27 is deposited with a thickness such that the surface 28 of the metal layer is essentially coplanar with the surface 29 of the first load electrode 17 and the control electrode 18 .
- the deposited metal layer can be planarized.
- a mask is then applied and structured so as to leave free the surface 28 alongside two opposite sides of the respective semiconductor components of the panel 10 . These uncovered regions are etched and the depressions produced in the process extend in each case between two adjacent semiconductor components. After the removal of the mask, strip-type elevations and depressions in the surface of the metal layer 27 of the panel 10 are uncovered. After the sawing along the sawing tracks, semiconductor devices 12 are produced which in each case have a U-shaped rewiring element 41 comprising a baseplate 40 composed of the carrier 14 and two opposite edges.
- FIGS. 7 and 8 in each case show a panel 10 according to a third and fourth exemplary embodiment, respectively.
- the panel 50 from FIG. 7 differs from the panel 10 from FIGS. 1 to 6 by virtue of the carrier 14 and the construction of the external contact areas 13 .
- the carrier 14 has a lower ceramic substrate 51 and an upper metallic layer 52 , in particular a copper layer.
- the carrier 14 is a so-called DCB substrate, a direct copper bond substrate.
- the panel 50 is produced in the manner already described above.
- the semiconductor components 15 are mounted on the top side 24 of the copper layer 52 by means of a diffusion solder connection 23 .
- a metal layer 27 is electrodeposited onto the carrier 50 into the separating regions 22 .
- the external contact areas 13 of the panel 50 have a layer 53 composed of a solder-wettable material and a soft solder layer 54 .
- the solder-wettable layer 53 is arranged on the surface 28 of the metal layer and also on the surface 29 of the first load electrode 17 and the control electrode 18 .
- the solder layer 54 is arranged on the solder-wettable layer 53 .
- the solder-wettable layer 53 essentially comprises Ni-2% P.
- the solder-wettable layer 53 may have Ni.
- the solder layer 54 may have an Sn-based soft solder, a lead-free solder or a diffusion solder, such as Sn—Ag, Au—Sn or In—Ag.
- a diffusion solder layer may have a plurality of layers.
- solder-wettable layer 53 and the solder layer 54 are deposited onto the panel. This may be carried out galvanically or by means of sputtering or vapor deposition.
- a carrier 14 which has a ceramic plate coated with a metallic layer on the two large-area sides.
- Said carrier can be produced by means of a so-called “direct copper bond” method.
- the outer surface of the baseplate of the rewiring element of the semiconductor device is a metallic layer.
- An additional heat sink can be mounted on said surface in a simple manner without the heat sink being electrically connected to the second load electrode 20 .
- the metallic layer of the carrier 14 may be provided by other electrically conductive materials, such as carbon for example.
- FIG. 8 shows a cross section of a panel 60 according to the fourth embodiment.
- the panel 60 differs by virtue of the structure of the edge sides 20 of the semiconductor component 15 and also the structure of the metal layer 27 .
- the edge sides 20 of the semiconductor components 15 in each case have an electrically insulating layer 61 produced by the oxidation of the surface of the edge sides 20 .
- the electrical insulation of the metal layer 27 from the semiconductor material of the body of the semiconductor component 15 is thereby increased.
- the metal layer 27 additionally has a seed layer 63 arranged onto the surface 24 of the plate 14 and also on the surface of the insulation layer 62 .
- the seed layer 63 may be applied by means of sputtering, vapor deposition or galvanically or chemically.
- a seed layer may be used in order to increase the adhesion between the plate and the metal layer 27 and/or between the edge sides 20 of the semiconductor component 15 and the metal layer.
- FIGS. 9 to 11 show a panel 70 according to a fifth embodiment.
- the panel 70 has a baseplate or a carrier in the form of a rear side metallization.
- the panel 70 also differs by virtue of its size, which corresponds approximately to the size of the semiconductor wafer from which the semiconductor components are separated.
- FIGS. 12 to 17 show devices with semiconductor components 15 which are produced by means of the panel 70 .
- FIG. 9 shows a panel 70 having a semiconductor wafer 71 with a rear side metallization 72 , which serves as a baseplate.
- the semiconductor wafer 71 has a multiplicity of semiconductor component positions 73 which are in each case doped correspondingly and have a front side metallization 74 , with the result that each position 73 provides a semiconductor component 15 .
- each device position 73 provides a vertical power MOSFET.
- the semiconductor component positions 73 are arranged in columns and rows and separated from adjacent semiconductor component positions 73 by means of sawing tracks 81 .
- the sawing tracks 81 are represented by a broken line.
- the front side metallization 74 provides a first load electrode 17 and a control electrode 18 , which are electrically insulated from one another by means of a passivation layer 75 .
- the rear side 76 of the semiconductor wafer 71 has a metal layer 77 extending over the entire rear side 76 .
- the metal layer 77 simultaneously forms the rear side metallization 72 and a carrier.
- the components 15 of the semiconductor component positions 73 are therefore electrically connected to the rear side metallization 72 and the metal layer 77 .
- the rear side metallization 72 is deposited onto the wafer.
- the rear side metallization may have a known composition and may have a known layer sequence composed of different metals.
- the second sides 19 of the semiconductor component positions 73 are directly connected to the metal layer 77 and are not mounted on the metal layer 77 or on the carrier by means of an additional layer, such as soft solder or diffusion solder.
- the semiconductor components 15 are separated from the semiconductor wafer 71 by means of a laser. This is shown schematically by the arrows. The separating lines are arranged in the sawing tracks 81 . As illustrated in FIG. 10 , the semiconductor components 15 are separated from the semiconductor wafer 71 from the top side 78 of the semiconductor wafer 71 in such a way that the metal layer 77 is not cut.
- the first metal layer 77 extends between singulated semiconductor components 15 .
- the multiplicity of semiconductor components 15 is therefore arranged on a single first metal layer 77 and electrically connected to said first metal layer 77 .
- the metal layer 77 therefore provides a carrier.
- the edge sides 21 of adjacent semiconductor components 15 are separated from one another by means of separating regions 79 having a width B.
- the surface 81 of the metal layer 77 is uncovered in the separating regions 79 .
- a second metallic layer 80 is electrodeposited in the separating regions 79 between adjacent semiconductor components 15 as described above. This method is illustrated in FIG. 11 .
- the separating regions 79 are filled by the second metallic layer 80 , with the result that the second metallic layer 80 has a thickness which at least approximately corresponds to the height of the semiconductor component 15 .
- the surface 86 of the metallic layer 80 may exceed the surface of the first side 78 of the semiconductor wafer 71 or the surface of the front side metallization 78 .
- the surface 86 is then planarized, with the result that the surface 87 of the second metallic layer 80 and the surface of the first load electrode and the control electrode are essentially coplanar.
- the rear side metallization 72 and the second metallic layer 80 provide a rear side rewiring, with the result that the second load electrode 20 on the rear side 19 of the semiconductor components 15 can be acted on electrically from the top side 16 of the semiconductor component 15 .
- the metal of the rear side metallization 72 may be the metal of the deposited second metallic layer 80 .
- the second metallic layer 80 and the rear side metallization may have different metals.
- the rear side metallization may have copper or aluminum, for example, and the second electrodeposited layer may have Au, Au, Sn, Ni, Ag, Al, Cu or An-Ag, for example.
- the panel 70 therefore has a metal layer 77 formed from the rear side metallization 72 , and a multiplicity of semiconductor components 15 embedded in the second deposited metallic layer 80 .
- the areal size of the panel 70 corresponds to the size of the semiconductor wafer 71 .
- the panel 70 is separated along the sawing tracks 81 .
- the sawing tracks are arranged in the separating regions 79 which are filled by the second metallic layer 80 .
- the second metallic layer 80 is therefore separated.
- the separation is carried out in such a way that after the separation, a layer 82 of the second metallic layer 80 remains on the edge sides 21 of the semiconductor components 15 .
- the width of the second sawing track 81 b is narrower than the width B of the separating regions 79 .
- the singulation of the semiconductor components 15 from the panel 70 in order to produce semiconductor devices 83 may be carried out by means of a laser or by means of sawing.
- the method for the production of a rear side rewiring by electrodeposition at the wafer level is suitable for power semiconductors, which are becoming thinner and thinner, so that it is perfectly conceivable for the semiconductor to make up only a fraction of the metallization thickness. Since the method enables two or more semiconductors lying alongside one another on a metallization to be introduced into the housing as one device, which has the consequence of identical electrical properties of the semiconductors, high-precision filters, trimming circuits and amplifiers, for example, can be realized by means of this method. Electrical circuits in which identical electrical properties are required have hitherto been realized with sorted individual devices, which is complicated and expensive.
- FIG. 12 shows a semiconductor device 83 according to a sixth exemplary embodiment, which is singulated from the panel 70 from FIG. 11 .
- the semiconductor device 83 has a vertical semiconductor component 15 with a front side metallization 79 and a rear side rewiring 84 having a first metallic layer 77 and a second metallic layer 82 .
- the first metallic layer is arranged on the rear side or on the second side 19 of the semiconductor component 15 .
- the second metallic layer 82 is arranged on the edge sides 21 of the semiconductor component 15 and cohesively connected to the edge sides.
- the surface 86 of the second metallic layer 82 provides the external contact area of the second load electrode 20 in an exemplary embodiment that is not shown.
- the semiconductor device 83 furthermore has external contacts 84 , which are solder balls in this embodiment.
- the semiconductor device 83 is mounted onto a circuit carrier 85 , which may be a circuit board for example, by means of the external contacts.
- the circuit carrier 85 may be an organic or ceramic substrate, silicon or a semiconductor chip.
- the external contacts 84 are arranged on the first load electrode 17 , on the control electrode 18 and also on the surface 86 of the second metallic layer 82 .
- a semiconductor device which has at least two semiconductor components. At least one of the semiconductor components 15 has a metallic sheathing 91 which completely covers the edge sides 21 and the second side 19 and partly covers the first side.
- an insulation and/or passivation layer is arranged between the metallic sheathing 81 and the semiconductor component material.
- the metallic sheathing may form a shielding against electromagnetic interference fields, be operatively connected to a heat sink or form a connecting element for electrically connecting a rear side electrode of the semiconductor chip to an external contact of the semiconductor chip on the top side.
- FIG. 13 shows a semiconductor device 90 according to a seventh embodiment, which has two semiconductor components 15 , each of which is a vertical power semiconductor component.
- the two semiconductor components 15 are arranged alongside one another.
- a single first metallic layer 77 extends between the two semiconductor components 15 and projects beyond the outer edges of the rear sides of the two semiconductor components.
- the semiconductor device 90 also has a second metallic layer 80 which covers the edge sides 21 of the two semiconductor components and fills the separating region 79 between the semiconductor components 15 .
- the edge sides 21 of the two semiconductor components 15 are embedded in a common second metallic layer 80 .
- At least two semiconductor components 15 have a common metallic sheathing which completely covers the edge sides 21 and the second side 19 and partly covers the first side 16 of said semiconductor components 15 .
- the second metallic layer 80 electrically connects the second load electrodes 20 of the two semiconductor components 15 to one another.
- the surface of the second metallic layer 80 is approximately coplanar with the surface of the front side metallization 78 .
- the surface 86 of the second metallic layer 80 therefore has an outer rectangular ring and a centrally arranged strip extending between two opposite sides of the ring.
- the first load electrodes 17 , the control electrodes 18 and regions 86 of the sheathing which are essentially coplanar with the first load electrode 17 and the control electrode 18 form external contact areas 87 of the semiconductor device.
- Said external contact areas 87 may be surface-mountable external contacts.
- Said external contact areas 87 can be electrically connected to a printed circuit board or a circuit board 85 by means of contact elements 84 such as solder balls, flip-chip contacts or bonding wires.
- the material of the contact areas 87 is chosen correspondingly depending on the type of contact-making.
- the semiconductor device 90 having two semiconductor components 15 arranged alongside one another can be produced by means of the panel according to FIG. 11 .
- the panel 70 is separated in a first direction through every second sawing track 81 and is separated in a second direction, which is perpendicular to the first direction, into each sawing track 81 .
- the semiconductor device 90 with two semiconductor components 15 arranged alongside one another, which is illustrated in FIG. 13 is produced in this way.
- the panel 70 can also be separated in order to produce semiconductor devices having more than two semiconductor components 15 .
- FIG. 14 shows a semiconductor device 100 according to an eighth embodiment, which has two semiconductor components 15 and also two additional semiconductor bodies 101 .
- One of the two additional semiconductor bodies 101 is arranged alongside an outer edge side 21 of one of the two semiconductor components 15 .
- the semiconductor bodies 101 are in each case a part of a semiconductor component 15 which has been produced by sawing from a semiconductor component 15 of the semiconductor wafer 71 .
- An outer edge side 102 of the semiconductor body is therefore free from the second metallic layer 80 since this surface was originally situated within the semiconductor bodies of the semiconductor component 15 .
- the rear side 19 of the semiconductor bodies 101 is covered with the metal layer 77 of the rear side metallization 71 and the further inner edge sides 21 are embedded in the second metallic deposited layer 80 .
- the device 101 is separated from the wafer in sawing tracks 103 which are arranged within the area of a semiconductor component 15 .
- This has the advantage that the sawing tolerances are enlarged since the saw blade does not have to fit within the narrow first separating region 79 . Consequently, a wider saw blade can be used and the sawing can be carried out more reliably. Larger deviations in the positioning of the saw blade can also be afforded tolerance without the semiconductor device 101 being damaged.
- FIG. 15 and FIG. 16 show a semiconductor device 110 according to a ninth embodiment, which has two stacked semiconductor devices 83 , 111 .
- FIG. 15 shows a cross section and FIG. 16 a plan view of the semiconductor device 110 .
- the lower semiconductor device 83 has a metal coating on the rear side 19 and on the edge sides 21 of the semiconductor component 15 , which metal coating is formed from the rear side metallization 71 and the second metallic layer 80 .
- the semiconductor device 83 according to the exemplary embodiment of FIG. 12 may be the lower semiconductor device 83 of the stack. Semiconductor devices according to further exemplary embodiments described herein may also be used instead of said device 83 .
- the upper semiconductor device 111 has a front side 112 with contact areas 113 , but no metal coating on the rear side 19 and on the edge sides 21 of the semiconductor component.
- the rear side 114 of the semiconductor device 83 is arranged on a system carrier 85 .
- the top side 115 of the semiconductor device 83 is remote from the system carrier.
- the upper semiconductor device 111 is arranged on the top side 115 of the lower semiconductor device 83 by means of solder balls 84 .
- the solder balls 84 are arranged directly between the contact areas 113 of the upper semiconductor device 111 and the contact areas 17 , 18 or the surface 87 of the second metallic layer 82 of the lower semiconductor device 83 .
- the upper semiconductor device 111 is therefore electrically connected to the lower semiconductor device 83 by means of the solder balls 84 .
- the plan view of the semiconductor device 110 which can be seen in FIG. 16 , shows that the lower semiconductor device 83 is rectangular and the upper semiconductor device 111 is square.
- the length of the sides of the upper semiconductor device is approximately the length of the short side of the lower semiconductor device 83 .
- the outer regions 116 , 117 of the two opposite sides of the lower semiconductor device 83 are therefore not covered by the upper semiconductor device 111 .
- the uncovered outer regions 116 , 117 of the first side or front side 16 have contact areas 118 which are freely accessible.
- the lower semiconductor device 83 is electrically connected to the circuit carrier 85 by means of bonding wires 119 extending between the contact areas 118 of the front side 16 of the lower semiconductor device 83 and contact areas 88 of the circuit carrier 85 .
- FIG. 17 shows a semiconductor device 120 according to a tenth embodiment, which has a single semiconductor component 15 .
- the rear side 19 and the edge sides 21 of the semiconductor component 15 are sheathed with a metal coating 121 formed from the rear side metallization 72 and the second deposited metallic layer 80 .
- the rear side 19 is mounted on a circuit carrier 85 by means of the metallic layer 77 of the rear side metallization 72 .
- the rear side 19 can be mounted on a heat sink.
- the heat dissipation from the semiconductor component 15 into the heat sink is improved owing to the metallic sheathing 121 .
- the contact areas 17 , 18 and also the metallic coating 121 are electrically connected to contact areas 88 of the circuit carrier 85 by means of bonding wires 122 .
- the surfaces 87 of the edge layers 82 of the second deposited metallic layer 80 may serve as contact areas.
- contact areas of a different material may be provided on the surface 87 .
- Said material is selected so as to produce an improved contact to the material of the bonding wire.
- Said semiconductor device 120 provides an improved dissipation of heat for applications in which no chip island is available.
Abstract
Description
- This application claims priority to
German application number 10 2007 007 142.8 filed Feb. 9, 2007, the contents of which is hereby incorporated by reference in its entirety. - The application relates to a panel, a semiconductor device and method for the production thereof.
- Semiconductor components, such as semiconductor chips, are normally used in the form of a semiconductor device. The semiconductor device normally provides an internal rewiring extending between the doped regions of the semiconductor material of the semiconductor component and the external contacts of the semiconductor device in order to simplify the electrical access to the semiconductor chip. Furthermore, the semiconductor device may have a housing that protects the semiconductor component against damage.
- The internal rewiring and the housing influence the electrical power and thermal capacity, the so-called performance of the semiconductor device.
- According to an embodiment, a panel may comprise a baseplate with an upper first metallic layer and a multiplicity of a vertical semiconductor components. The vertical semiconductor components in each case may comprise a first side with a first load electrode and a control electrode and an opposite second side with a second load electrode. The second side of the semiconductor components is in each case mounted on the metallic layer of the baseplate. The semiconductor components can be arranged in such a way that edge sides of adjacent semiconductor components are separated from one another. A second metallic layer can be arranged in separating regions between the semiconductor components.
- According to a further embodiment, a method for the production of a panel may comprise the following features. A multiplicity of vertical semiconductor components are provided, wherein the semiconductor components in each case comprise a first side with a first load electrode and a control electrode and an opposite second side with a second load electrode, wherein the second sides of the semiconductor components are arranged on a metallic layer in such a way that edge sides of adjacent semiconductor components are separated from one another by means of separating regions, and the second sides are electrically connected to the metallic layer. At least one metal is deposited onto the metallic layer in the separating regions between the semiconductor components, with the result that the edge sides of the semiconductor components are covered by the deposited metal.
-
FIG. 1 shows a cross section of a panel with a multiplicity of semiconductor components, -
FIG. 2 shows a cross section of the panel fromFIG. 1 with rear side rewiring, -
FIG. 3 shows a plan view of the panel fromFIG. 2 , -
FIG. 4 shows a cross section of a semiconductor device according to a first embodiment, -
FIG. 5 shows a perspective view of the semiconductor device fromFIG. 4 , -
FIG. 6 a shows a perspective view of a semiconductor device according to a second embodiment with a first external contact area arrangement, -
FIG. 6 b shows a perspective view of a semiconductor device according to a second embodiment with a second external contact area arrangement, -
FIG. 7 shows a cross section of a panel according to a third embodiment, -
FIG. 8 shows a cross section of a panel according to a fourth embodiment, -
FIG. 9 shows a cross section of a panel according to a fifth embodiment, -
FIG. 10 shows the production of a multiplicity of semiconductor components from the panel fromFIG. 9 , -
FIG. 11 shows the production of a rear side rewiring of the semiconductor components fromFIG. 10 , -
FIG. 12 shows a semiconductor device according to a sixth embodiment, -
FIG. 13 shows a semiconductor device according to a seventh embodiment, -
FIG. 14 shows a semiconductor device according to a eighth embodiment, -
FIG. 15 shows a semiconductor device according to a ninth embodiment, -
FIG. 16 shows a plan view of the semiconductor device fromFIG. 15 , and -
FIG. 17 shows a semiconductor device according to a tenth embodiment. -
FIGS. 1 to 5 show the production of apanel 10, which is singulated in order to produce a plurality ofsemiconductor devices 11.FIGS. 6 a and 6 b in each case show asemiconductor device 12 produced by means of a panel. Thesemiconductor device 12 differs from thesemiconductor device 11 through the arrangement of theexternal contact areas 13.FIGS. 7 and 8 in each case show a panel according to further embodiments. -
FIGS. 9 to 11 show the production of a panel according to one embodiment andFIGS. 12 to 17 show semiconductor devices which can be produced by means of the panel fromFIG. 11 . - In the figures, identical elements are shown with the same reference symbol.
-
FIG. 1 shows a cross section of apanel 10 having abaseplate 14 in the form of acarrier 14 with an upper metallic layer and a multiplicity ofsemiconductor components 15. In this embodiment, thecarrier 14 is a metallic plate, in particular a copper plate. In this embodiment, thesemiconductor components 15 are in each case a vertical semiconductor component, in particular a vertical power transistor in the form of a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Thesemiconductor component 15 may be an IGBT (Isolated Gate Bipolar Transistor) or a BJT (Bipolar Junction Transistor) or a diode. Thesemiconductor component 15 has afirst side 16 with afirst load electrode 17 and acontrol electrode 18 and an oppositesecond side 19 with asecond load electrode 20. Theelectrodes first load electrode 17 and also thesecond load electrode 20 are in each case large-area contacts. The control electrode is a small-area contact. The twoelectrodes first side 16 are electrically insulated from one another. In this embodiment, thefirst load electrode 17 is designated as source, thecontrol electrode 18 is designated as gate and thesecond load electrode 20 is designated as drain, since thesemiconductor component 15 is a MOSFET. - A multiplicity of the
semiconductor components 15 are provided. Thesecond side 19 of thesemiconductor components 15 is arranged on themetallic surface 24 of thecarrier 14 in such a way that theedge sides 21 ofadjacent semiconductor components 15 are separated from one another by means of separatingregions 22. Thesecond side 19 is electrically connected to themetallic surface 24 of thecarrier 14. - In this first embodiment,
individual semiconductor components 15 are mounted onto thecarrier 14. In particular, thesecond side 19 of thesemiconductor components 15 is mounted on the upper metallic layer of thecarrier 14. Thesemiconductor components 15 are arranged in such a way that theedge sides 21 ofadjacent semiconductor components 15 are separated from one another by means of separatingregions 22. Thesemiconductor components 15 are arranged in columns and rows, with the result that theseparating regions 22 have sawing tracks. The sawing tracks are represented by a broken line in the figures. - The
second side 19 or thesecond load electrode 20 of thesemiconductor components 15 is mounted on thesurface 24 of thecopper plate 14 by means of adiffusion solder connection 23. In a further embodiment, the semiconductor components can be mounted onto the carrier by means of a soft solder connection. - In order to produce the
diffusion solder connection 23, a layer of a diffusion solder is deposited on thesecond load electrode 19. In order to mount thesemiconductor component 15 on theplate 14, theplate 14 is heated to a temperature lying above the melting point of the diffusion solder. Thesecond side 19 of thesemiconductor component 15 is pressed onto the surface of thecarrier 14, said surface comprising copper. The diffusion solder melts and reacts with the material of the surface of theplate 14, intermetallic phases being formed. Said intermetallic phases have a higher melting point than the melting point of the diffusion solder. Consequently, the boundary between thesecond side 19 of thesemiconductor component 15 and theplate 14 solidifies and forms thediffusion solder connection 23. Said diffusion solder connection thus has a higher melting point than the melting point of the diffusion solder. Consequently,further semiconductor components 15 can be mounted on theplate 14 without thediffusion solder connections 23 that have already been produced melting again. A multiplicity ofsemiconductor components 15 can thus be reliably mounted on theplate 14 piece by piece. -
FIG. 2 shows a cross section of thepanel 10 fromFIG. 1 withrear side rewiring 25. In order to produce the rear side rewiring, at least onemetal 26 is deposited onto theplate 14, in particular into the separating regions between thesemiconductor components 15. Themetal 26 may be copper or a copper alloy. Themetal 26 is built up layer by layer and forms alayer 27 of thepanel 10. Thelayer 27 is cohesively connected to the edge margins and edge sides of thesemiconductor components 15. The deposition is carried out in such a way that the separatingregions 22 are essentially filled by the deposited metal. This may be implemented by the setting of the deposition duration. The edge sides 21 of thesemiconductor component 15 are sealed by themetal layer 27. Consequently, there is no need to use a plastic composition for protection against air and moisture. - The
layer 27 is deposited in order to provide a rear side rewiring. Thesemiconductor components 15 are vertical components in which contact areas are arranged on twoopposite sides component 15. A rewiring structure is provided for making contact with the twosides component 15, with the result that all the contact areas can be acted on from a single side of thesemiconductor component 15. Thelayer 27 has at least one metal that is deposited directly on thesurface 24 of theplate 14 and is electrically connected to theplate 14. Theplate 14 is electrically connected to thesecond load electrode 19 by means of thediffusion solder connection 23. Thesecond load electrode 19 can therefore be acted on electrically from theopposite side 16 of thesemiconductor component 15 via theplate 14 and via thelayer 27. - The
layer 27 is built up layer by layer by the deposition until at least regions of thesurface 28 of thelayer 27 are essentially coplanar with thefirst load electrode 17 and with thecontrol electrode 18, in particular until at least regions of thesurface 28 of thelayer 27 are essentially coplanar with the outer surface of thefirst load electrode 17 and thecontrol electrode 18. - In this embodiment, the
layer 27 is produced by means of electrodeposition. The potential of the electrolytic cell is connected to theplate 14. Consequently, the metal is deposited principally on theplate 14. Hardly any metal or even no metal is deposited onto thefirst load electrode 17 and thecontrol electrode 18 during the deposition method. - In an embodiment that is not shown, the
metal layer 27 is deposited with a thickness d that is greater than the height h of thesemiconductor component 15. Thesurface 28 of themetal layer 27 lies above theouter surface 29 of thefirst load electrode 17 and thecontrol electrode 18. This side of thepanel 10 is then planarized. This may be carried out by grinding away, such as CMP (chemical mechanical polishing). - The
panel 10 therefore has aplate 14 on which ametallic layer 27 is deposited. Thesemiconductor components 15 are embedded in saidmetallic layer 27. Thepanel 10 has no plastic housing composition since themetal layer 27 is arranged directly on the edge sides 20 of thesemiconductor components 15. -
FIG. 3 shows a plan view of thepanel 10 fromFIG. 2 .FIG. 3 illustrates the arrangement of thesemiconductor components 15 and also the arrangement of theelectrodes first side 16 of the semiconductor components. Thesemiconductor components 15 are arranged in columns and rows and are separated from one another by means of the separatingregions 22. The separatingregions 22 in each case provide a sawing track. Thesmaller control electrode 18 is in strip form and the largerfirst load electrode 17 is rectangular. -
FIG. 4 shows asemiconductor device 30 produced by the separation of the panel fromFIGS. 2 and 3 . Thepanel 10 is separated along the sawing tracks in the separatingregions 22. This may be carried out by means of sawing by a laser. As a result, arewiring element 31 is produced for eachsemiconductor component 15 and a semiconductor device is produced. Thesemiconductor device 30 has no plastic housing composition since the edge sides 20 and thesecond side 20 of thesemiconductor component 15 are covered with themetal 26 of themetal layer 27 and with theplate 14. Themetal layer 27 provides a sealing of the edge sides of thesemiconductor component 15. Thesemiconductor device 30 has arewiring element 31 extending from thesecond side 19 of thesemiconductor component 15 as far as thefirst side 16. Therewiring element 31 therefore provides a rear side rewiring. - The
rewiring element 31 comprises abaseplate 32, which is arranged on thesecond side 19 of thesemiconductor component 15 and which projects beyond the edge sides 20, and comprises anedge 33, which is approximately perpendicular to thebaseplate 32 and cohesively connected to the edge sides 21 of thesemiconductor component 15. Therewiring element 31 therefore has a pedestal form, the inner surface of the base and of the walls being cohesively connected to thesemiconductor component 15. The outer surfaces 34 of therewiring element 31 are outer surfaces of thesemiconductor device 30. The outer dimensions of thesemiconductor device 30 are only somewhat greater than the outer dimensions of thesemiconductor component 15. Thesemiconductor device 30 is a chip sized package. - The
surface 29 of thefirst load electrode 17 and of thecontrol electrode 18 and thesurface 28 of themetal layer 27 provide theexternal contact areas 13 of thesemiconductor device 30. Saidexternal contact areas 13 are surface-mountable. Thefirst load electrode 17 and thecontrol electrode 18 have a metal layer having a thickness of above 30 μm, above 50 μm or above 100 μm. In a further embodiment (not shown), solder balls are applied on said surfaces. The solder balls provide the external contacts of the semiconductor device. In a further embodiment (not shown), thefirst load electrode 17 and the control electrode have copper pillars that form the external contact areas of thesemiconductor device 30. Thesmaller control electrode 18 may have a single pillar, while the largerfirst load electrode 18 has a plurality of pillars. - The
semiconductor device 11 is therefore a so-called “power chip sized package” (PowerCSP). The metallic sheathing provides the rewiring of the chip rear side electrode of the power MOSFET, which simultaneously serves as an external contact region. The heights of the chip front sides and of the chip rear side contact regions within said “chip sized package” can thus be coordinated precisely with one another. The coordination between separate die attach layer and front side contacts can therefore be avoided. Moreover, by means of the electrodeposited sheathing, any desired amounts of one or more metals, for example copper, can be integrated within the “power chip sized package”. As a result, the thermal short- and long-time capacity of the device is flexibly set and optimized. -
FIGS. 5 , 6 a and 6 b show three embodiments of theexternal contact areas 13. InFIG. 5 , thesurface 29 of the width of the edge or of thewalls 33 of therewiring element 31 is essentially coplanar with theouter surface 29 of thefirst load electrode 17 and thecontrol electrode 18 at all fouredge sides 20 of thesemiconductor component 15. This common plane is shown with thereference symbol 30. Theouter surface 29 of therewiring structure 31 is therefore ring-shaped. This structure is produced during the planarization of the upper side of thepanel 10. The planarization may be effected by grinding away or by setting the deposition duration. Thesurface 29 provides the drain terminal of thesemiconductor device 11. This arrangement has the advantage that a larger contact area is provided. - Said
semiconductor device 11 can be mounted on a multilayer circuit board in which the rewiring of thesource electrode 17 andgate electrode 18 and thedrain electrode 20 can be arranged on different planes and thereby be electrically insulated from one another. The rewiring of thesource electrode 17 and thegate electrode 18 can be led under the rewiring of theouter drain electrode 20. -
FIGS. 6 a and 6 b in each case show asemiconductor device 12 according to one embodiment, said semiconductor device having asemiconductor component 15 and arewiring element 41. Thewalls 42 or the edges of therewiring element 41 are structured, with the result that theouter surface 43 of thewall thickness 42 alongside only two opposite edge sides 20 of thesemiconductor component 15 are essentially coplanar with theouter surface 29 of thefirst load electrode 17 and thecontrol electrode 18. Thesurfaces 44 of the remaining twosides 45 of therewiring element 41 lie in a plane below thesurface 43 and therefore do not provide an external contact area. Thesurfaces 43 of the twoopposite walls 42 provide external contact areas, in particular the drain terminal. - The
rewiring element 41 has a U-shape in which the two oppositehigher sides 42 provide the legs of the U-shape. The sourceelectrode contact area 17 and the gateelectrode contact area 18 are in each case in strip form. - In the embodiment of
FIG. 6 a, the longitudinal sides of the higher edge sides 42 of therewiring element 41 are approximately perpendicular to the longitudinal sides of the strip-type sourceelectrode contact area 17 and gateelectrode contact area 18. - In contrast thereto, in the embodiment of
FIG. 6 b, the longitudinal sides of the higher edge sides 42 of therewiring element 41 are arranged approximately parallel to the longitudinal sides of the strip-type sourceelectrode contact area 17 and gateelectrode contact area 18. This arrangement enables a plurality of semiconductor devices to be electrically coupled in parallel with one another since thesemiconductor devices 12 can be mounted alongside one another on strip-type contact areas on the circuit board. The strip-type contact areas on the circuit board in each case provide a common contact for a type of semiconductor device contact area. By way of example, the source contact area of a plurality of semiconductor devices is mounted on a single strip-type contact area on the circuit board, which provides a common supply contact. - This
semiconductor device 12 fromFIG. 6 a andFIG. 6 b can be mounted on a single-layer circuit board since it is possible to lead the rewiring of thefirst load electrode 17 and of thecontrol electrode 18 on the surface of the circuit board under the two short edge sides 42 of therewiring element 41, since said short edge sides 42 are not in contact with the circuit board. - The
semiconductor device 12 with an external contact area arrangement according toFIG. 6 a orFIG. 6 b is also produced by the production of apanel 10 as described above. After the deposition of themetal layer 27, the surface of themetal layer 27 is structured in order to produce strip-type elevated regions at two opposite edge sides 20 of thesemiconductor components 15 of thepanel 10. In one embodiment, themetal layer 27 is deposited with a thickness such that thesurface 28 of the metal layer is essentially coplanar with thesurface 29 of thefirst load electrode 17 and thecontrol electrode 18. In a further step, the deposited metal layer can be planarized. - A mask is then applied and structured so as to leave free the
surface 28 alongside two opposite sides of the respective semiconductor components of thepanel 10. These uncovered regions are etched and the depressions produced in the process extend in each case between two adjacent semiconductor components. After the removal of the mask, strip-type elevations and depressions in the surface of themetal layer 27 of thepanel 10 are uncovered. After the sawing along the sawing tracks,semiconductor devices 12 are produced which in each case have aU-shaped rewiring element 41 comprising abaseplate 40 composed of thecarrier 14 and two opposite edges. -
FIGS. 7 and 8 in each case show apanel 10 according to a third and fourth exemplary embodiment, respectively. - The
panel 50 fromFIG. 7 differs from thepanel 10 fromFIGS. 1 to 6 by virtue of thecarrier 14 and the construction of theexternal contact areas 13. Thecarrier 14 has a lowerceramic substrate 51 and an uppermetallic layer 52, in particular a copper layer. Thecarrier 14 is a so-called DCB substrate, a direct copper bond substrate. Thepanel 50 is produced in the manner already described above. Thesemiconductor components 15 are mounted on thetop side 24 of thecopper layer 52 by means of adiffusion solder connection 23. Ametal layer 27 is electrodeposited onto thecarrier 50 into the separatingregions 22. In this embodiment, theexternal contact areas 13 of thepanel 50 have alayer 53 composed of a solder-wettable material and asoft solder layer 54. The solder-wettable layer 53 is arranged on thesurface 28 of the metal layer and also on thesurface 29 of thefirst load electrode 17 and thecontrol electrode 18. Thesolder layer 54 is arranged on the solder-wettable layer 53. The solder-wettable layer 53 essentially comprises Ni-2% P. The solder-wettable layer 53 may have Ni. Thesolder layer 54 may have an Sn-based soft solder, a lead-free solder or a diffusion solder, such as Sn—Ag, Au—Sn or In—Ag. A diffusion solder layer may have a plurality of layers. - The solder-
wettable layer 53 and thesolder layer 54 are deposited onto the panel. This may be carried out galvanically or by means of sputtering or vapor deposition. - In an embodiment that is not shown, a
carrier 14 is provided which has a ceramic plate coated with a metallic layer on the two large-area sides. Said carrier can be produced by means of a so-called “direct copper bond” method. The outer surface of the baseplate of the rewiring element of the semiconductor device is a metallic layer. An additional heat sink can be mounted on said surface in a simple manner without the heat sink being electrically connected to thesecond load electrode 20. - The metallic layer of the
carrier 14 may be provided by other electrically conductive materials, such as carbon for example. -
FIG. 8 shows a cross section of apanel 60 according to the fourth embodiment. Thepanel 60 differs by virtue of the structure of the edge sides 20 of thesemiconductor component 15 and also the structure of themetal layer 27. The edge sides 20 of thesemiconductor components 15 in each case have an electrically insulatinglayer 61 produced by the oxidation of the surface of the edge sides 20. The electrical insulation of themetal layer 27 from the semiconductor material of the body of thesemiconductor component 15 is thereby increased. - The
metal layer 27 additionally has a seed layer 63 arranged onto thesurface 24 of theplate 14 and also on the surface of theinsulation layer 62. The seed layer 63 may be applied by means of sputtering, vapor deposition or galvanically or chemically. A seed layer may be used in order to increase the adhesion between the plate and themetal layer 27 and/or between the edge sides 20 of thesemiconductor component 15 and the metal layer. -
FIGS. 9 to 11 show apanel 70 according to a fifth embodiment. In this embodiment, thepanel 70 has a baseplate or a carrier in the form of a rear side metallization. Thepanel 70 also differs by virtue of its size, which corresponds approximately to the size of the semiconductor wafer from which the semiconductor components are separated. -
FIGS. 12 to 17 show devices withsemiconductor components 15 which are produced by means of thepanel 70. -
FIG. 9 shows apanel 70 having asemiconductor wafer 71 with arear side metallization 72, which serves as a baseplate. Thesemiconductor wafer 71 has a multiplicity of semiconductor component positions 73 which are in each case doped correspondingly and have afront side metallization 74, with the result that eachposition 73 provides asemiconductor component 15. In this embodiment, eachdevice position 73 provides a vertical power MOSFET. The semiconductor component positions 73 are arranged in columns and rows and separated from adjacent semiconductor component positions 73 by means of sawing tracks 81. The sawing tracks 81 are represented by a broken line. - The
front side metallization 74 provides afirst load electrode 17 and acontrol electrode 18, which are electrically insulated from one another by means of apassivation layer 75. Therear side 76 of thesemiconductor wafer 71 has ametal layer 77 extending over the entirerear side 76. Themetal layer 77 simultaneously forms therear side metallization 72 and a carrier. Thecomponents 15 of the semiconductor component positions 73 are therefore electrically connected to therear side metallization 72 and themetal layer 77. Therear side metallization 72 is deposited onto the wafer. The rear side metallization may have a known composition and may have a known layer sequence composed of different metals. - In contrast to the exemplary embodiments of
FIGS. 1 to 8 , thesecond sides 19 of the semiconductor component positions 73 are directly connected to themetal layer 77 and are not mounted on themetal layer 77 or on the carrier by means of an additional layer, such as soft solder or diffusion solder. - The
semiconductor components 15 are separated from thesemiconductor wafer 71 by means of a laser. This is shown schematically by the arrows. The separating lines are arranged in the sawing tracks 81. As illustrated inFIG. 10 , thesemiconductor components 15 are separated from thesemiconductor wafer 71 from thetop side 78 of thesemiconductor wafer 71 in such a way that themetal layer 77 is not cut. Thefirst metal layer 77 extends betweensingulated semiconductor components 15. The multiplicity ofsemiconductor components 15 is therefore arranged on a singlefirst metal layer 77 and electrically connected to saidfirst metal layer 77. Themetal layer 77 therefore provides a carrier. The edge sides 21 ofadjacent semiconductor components 15 are separated from one another by means of separatingregions 79 having a width B. Thesurface 81 of themetal layer 77 is uncovered in the separatingregions 79. - A second
metallic layer 80 is electrodeposited in the separatingregions 79 betweenadjacent semiconductor components 15 as described above. This method is illustrated inFIG. 11 . The separatingregions 79 are filled by the secondmetallic layer 80, with the result that the secondmetallic layer 80 has a thickness which at least approximately corresponds to the height of thesemiconductor component 15. After the deposition, thesurface 86 of themetallic layer 80 may exceed the surface of thefirst side 78 of thesemiconductor wafer 71 or the surface of thefront side metallization 78. Thesurface 86 is then planarized, with the result that thesurface 87 of the secondmetallic layer 80 and the surface of the first load electrode and the control electrode are essentially coplanar. - The
rear side metallization 72 and the secondmetallic layer 80 provide a rear side rewiring, with the result that thesecond load electrode 20 on therear side 19 of thesemiconductor components 15 can be acted on electrically from thetop side 16 of thesemiconductor component 15. The metal of therear side metallization 72 may be the metal of the deposited secondmetallic layer 80. As an alternative, the secondmetallic layer 80 and the rear side metallization may have different metals. The rear side metallization may have copper or aluminum, for example, and the second electrodeposited layer may have Au, Au, Sn, Ni, Ag, Al, Cu or An-Ag, for example. - The
panel 70 therefore has ametal layer 77 formed from therear side metallization 72, and a multiplicity ofsemiconductor components 15 embedded in the second depositedmetallic layer 80. The areal size of thepanel 70 corresponds to the size of thesemiconductor wafer 71. - The
panel 70 is separated along the sawing tracks 81. The sawing tracks are arranged in the separatingregions 79 which are filled by the secondmetallic layer 80. The secondmetallic layer 80 is therefore separated. The separation is carried out in such a way that after the separation, alayer 82 of the secondmetallic layer 80 remains on the edge sides 21 of thesemiconductor components 15. The width of the second sawing track 81 b is narrower than the width B of the separatingregions 79. The singulation of thesemiconductor components 15 from thepanel 70 in order to producesemiconductor devices 83 may be carried out by means of a laser or by means of sawing. - The method for the production of a rear side rewiring by electrodeposition at the wafer level is suitable for power semiconductors, which are becoming thinner and thinner, so that it is perfectly conceivable for the semiconductor to make up only a fraction of the metallization thickness. Since the method enables two or more semiconductors lying alongside one another on a metallization to be introduced into the housing as one device, which has the consequence of identical electrical properties of the semiconductors, high-precision filters, trimming circuits and amplifiers, for example, can be realized by means of this method. Electrical circuits in which identical electrical properties are required have hitherto been realized with sorted individual devices, which is complicated and expensive.
-
FIG. 12 shows asemiconductor device 83 according to a sixth exemplary embodiment, which is singulated from thepanel 70 fromFIG. 11 . Thesemiconductor device 83 has avertical semiconductor component 15 with afront side metallization 79 and arear side rewiring 84 having a firstmetallic layer 77 and a secondmetallic layer 82. The first metallic layer is arranged on the rear side or on thesecond side 19 of thesemiconductor component 15. The secondmetallic layer 82 is arranged on the edge sides 21 of thesemiconductor component 15 and cohesively connected to the edge sides. Thesurface 86 of the secondmetallic layer 82 provides the external contact area of thesecond load electrode 20 in an exemplary embodiment that is not shown. - The
semiconductor device 83 furthermore hasexternal contacts 84, which are solder balls in this embodiment. Thesemiconductor device 83 is mounted onto acircuit carrier 85, which may be a circuit board for example, by means of the external contacts. Thecircuit carrier 85 may be an organic or ceramic substrate, silicon or a semiconductor chip. Theexternal contacts 84 are arranged on thefirst load electrode 17, on thecontrol electrode 18 and also on thesurface 86 of the secondmetallic layer 82. - A semiconductor device is also provided which has at least two semiconductor components. At least one of the
semiconductor components 15 has a metallic sheathing 91 which completely covers the edge sides 21 and thesecond side 19 and partly covers the first side. - In an embodiment that is not shown, an insulation and/or passivation layer is arranged between the
metallic sheathing 81 and the semiconductor component material. - The metallic sheathing may form a shielding against electromagnetic interference fields, be operatively connected to a heat sink or form a connecting element for electrically connecting a rear side electrode of the semiconductor chip to an external contact of the semiconductor chip on the top side.
-
FIG. 13 shows asemiconductor device 90 according to a seventh embodiment, which has twosemiconductor components 15, each of which is a vertical power semiconductor component. The twosemiconductor components 15 are arranged alongside one another. A single firstmetallic layer 77 extends between the twosemiconductor components 15 and projects beyond the outer edges of the rear sides of the two semiconductor components. Thesemiconductor device 90 also has a secondmetallic layer 80 which covers the edge sides 21 of the two semiconductor components and fills the separatingregion 79 between thesemiconductor components 15. The edge sides 21 of the twosemiconductor components 15 are embedded in a common secondmetallic layer 80. - In this embodiment, at least two
semiconductor components 15 have a common metallic sheathing which completely covers the edge sides 21 and thesecond side 19 and partly covers thefirst side 16 of saidsemiconductor components 15. - The second
metallic layer 80 electrically connects thesecond load electrodes 20 of the twosemiconductor components 15 to one another. In this embodiment, the surface of the secondmetallic layer 80 is approximately coplanar with the surface of thefront side metallization 78. Thesurface 86 of the secondmetallic layer 80 therefore has an outer rectangular ring and a centrally arranged strip extending between two opposite sides of the ring. - The
first load electrodes 17, thecontrol electrodes 18 andregions 86 of the sheathing which are essentially coplanar with thefirst load electrode 17 and thecontrol electrode 18 formexternal contact areas 87 of the semiconductor device. Saidexternal contact areas 87 may be surface-mountable external contacts. Saidexternal contact areas 87 can be electrically connected to a printed circuit board or acircuit board 85 by means ofcontact elements 84 such as solder balls, flip-chip contacts or bonding wires. The material of thecontact areas 87 is chosen correspondingly depending on the type of contact-making. - The
semiconductor device 90 having twosemiconductor components 15 arranged alongside one another can be produced by means of the panel according toFIG. 11 . In order to produce thesemiconductor device 90, thepanel 70 is separated in a first direction through everysecond sawing track 81 and is separated in a second direction, which is perpendicular to the first direction, into each sawingtrack 81. Thesemiconductor device 90 with twosemiconductor components 15 arranged alongside one another, which is illustrated inFIG. 13 , is produced in this way. Thepanel 70 can also be separated in order to produce semiconductor devices having more than twosemiconductor components 15. -
FIG. 14 shows asemiconductor device 100 according to an eighth embodiment, which has twosemiconductor components 15 and also twoadditional semiconductor bodies 101. One of the twoadditional semiconductor bodies 101 is arranged alongside anouter edge side 21 of one of the twosemiconductor components 15. Thesemiconductor bodies 101 are in each case a part of asemiconductor component 15 which has been produced by sawing from asemiconductor component 15 of thesemiconductor wafer 71. Anouter edge side 102 of the semiconductor body is therefore free from the secondmetallic layer 80 since this surface was originally situated within the semiconductor bodies of thesemiconductor component 15. Therear side 19 of thesemiconductor bodies 101 is covered with themetal layer 77 of therear side metallization 71 and the further inner edge sides 21 are embedded in the second metallic depositedlayer 80. - The
device 101 is separated from the wafer in sawingtracks 103 which are arranged within the area of asemiconductor component 15. This has the advantage that the sawing tolerances are enlarged since the saw blade does not have to fit within the narrowfirst separating region 79. Consequently, a wider saw blade can be used and the sawing can be carried out more reliably. Larger deviations in the positioning of the saw blade can also be afforded tolerance without thesemiconductor device 101 being damaged. -
FIG. 15 andFIG. 16 show asemiconductor device 110 according to a ninth embodiment, which has two stackedsemiconductor devices FIG. 15 shows a cross section andFIG. 16 a plan view of thesemiconductor device 110. - The
lower semiconductor device 83 has a metal coating on therear side 19 and on the edge sides 21 of thesemiconductor component 15, which metal coating is formed from therear side metallization 71 and the secondmetallic layer 80. Thesemiconductor device 83 according to the exemplary embodiment ofFIG. 12 may be thelower semiconductor device 83 of the stack. Semiconductor devices according to further exemplary embodiments described herein may also be used instead of saiddevice 83. - The
upper semiconductor device 111 has afront side 112 withcontact areas 113, but no metal coating on therear side 19 and on the edge sides 21 of the semiconductor component. - The
rear side 114 of thesemiconductor device 83 is arranged on asystem carrier 85. Thetop side 115 of thesemiconductor device 83 is remote from the system carrier. Theupper semiconductor device 111 is arranged on thetop side 115 of thelower semiconductor device 83 by means ofsolder balls 84. Thesolder balls 84 are arranged directly between thecontact areas 113 of theupper semiconductor device 111 and thecontact areas surface 87 of the secondmetallic layer 82 of thelower semiconductor device 83. Theupper semiconductor device 111 is therefore electrically connected to thelower semiconductor device 83 by means of thesolder balls 84. - The plan view of the
semiconductor device 110, which can be seen inFIG. 16 , shows that thelower semiconductor device 83 is rectangular and theupper semiconductor device 111 is square. The length of the sides of the upper semiconductor device is approximately the length of the short side of thelower semiconductor device 83. Theouter regions lower semiconductor device 83 are therefore not covered by theupper semiconductor device 111. The uncoveredouter regions front side 16 havecontact areas 118 which are freely accessible. Thelower semiconductor device 83 is electrically connected to thecircuit carrier 85 by means ofbonding wires 119 extending between thecontact areas 118 of thefront side 16 of thelower semiconductor device 83 andcontact areas 88 of thecircuit carrier 85. -
FIG. 17 shows asemiconductor device 120 according to a tenth embodiment, which has asingle semiconductor component 15. Therear side 19 and the edge sides 21 of thesemiconductor component 15 are sheathed with ametal coating 121 formed from therear side metallization 72 and the second depositedmetallic layer 80. - The
rear side 19 is mounted on acircuit carrier 85 by means of themetallic layer 77 of therear side metallization 72. Therear side 19 can be mounted on a heat sink. The heat dissipation from thesemiconductor component 15 into the heat sink is improved owing to themetallic sheathing 121. Thecontact areas metallic coating 121 are electrically connected to contactareas 88 of thecircuit carrier 85 by means ofbonding wires 122. Thesurfaces 87 of the edge layers 82 of the second depositedmetallic layer 80 may serve as contact areas. As an alternative, contact areas of a different material may be provided on thesurface 87. Said material is selected so as to produce an improved contact to the material of the bonding wire. Saidsemiconductor device 120 provides an improved dissipation of heat for applications in which no chip island is available. -
- 10 Panel
- 11 First semiconductor device
- 12 Second semiconductor device
- 13 External contact areas
- 14 Carrier
- 15 Semiconductor component
- 16 First side
- 17 First load electrode
- 18 Control electrode
- 19 Second side
- 20 Second load electrode
- 21 Edge side
- 22 Separating region
- 23 Diffusion solder connection
- 24 Surface of the carriers
- 25 Rear side rewiring
- 26 Metal
- 27 Metallic layer
- 28 Surface of the metallic layer
- 29 Surface of the first load electrode and control electrode
- 30 Common plane
- 31 Rewiring element
- 32 Baseplate
- 33 Edge
- 34 Surface of the rewiring element
- 40 Baseplate
- 41 Second rewiring element
- 42 Edge of the second rewiring element
- 43 Surface of two sides of the second rewiring element
- 44 Surface of the remaining two sides of the second rewiring element
- 45 Edge
- 50 Second panel
- 51 Ceramic substrate
- 52 Upper metallic layer
- 53 Solder-wettable layer
- 54 Solder layer
- 60 Third panel
- 61 Insulating layer
- 62 Seed layer
- 70 Panel
- 71 Semiconductor wafer
- 72 Rear side metallization
- 73 Device position
- 74 Front side metallization
- 75 Passivation layer
- 76 Rear side of the semiconductor wafer
- 77 Metal layer
- 78 Top side of the semiconductor wafer
- 79 Separating region
- 80 Second electrodeposited layer
- 81 Sawing track
- 82 Edge layer
- 83 Semiconductor device
- 84 External contact
- 85 Circuit carrier
- 86 Surface of the second metallic layer
- 87 External contact area
- 88 Contact area of the circuit carrier
- 90 Semiconductor device
- 100 Semiconductor device
- 101 Semiconductor body
- 102 Outer edge side of the semiconductor body
- 110 Semiconductor device
- 111 Stacked semiconductor device
- 112 Front side of the stacked semiconductor device
- 113 Contact area
- 114 Rear side of the stacked semiconductor device
- 115 Top side of the lower semiconductor device
- 116 Uncovered region of the lower semiconductor device
- 117 Uncovered region of the lower semiconductor device
- 118 Contact area of the lower semiconductor device
- 119 Bonding wire
- 120 Semiconductor device
- 121 Metallic coating
- 122 Bonding wire
Claims (68)
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US12/828,327 US8164173B2 (en) | 2007-02-09 | 2010-07-01 | Panel, semiconductor device and method for the production thereof |
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DE102007007142A DE102007007142B4 (en) | 2007-02-09 | 2007-02-09 | Benefits, semiconductor device and method for their production |
DEDE102007007142.8 | 2007-02-09 | ||
DE102007007142 | 2007-02-09 |
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US12/828,327 Division US8164173B2 (en) | 2007-02-09 | 2010-07-01 | Panel, semiconductor device and method for the production thereof |
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US20080191359A1 true US20080191359A1 (en) | 2008-08-14 |
US7772693B2 US7772693B2 (en) | 2010-08-10 |
Family
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US11/677,774 Expired - Fee Related US7772693B2 (en) | 2007-02-09 | 2007-02-22 | Panel, semiconductor device and method for the production thereof |
US12/828,327 Active US8164173B2 (en) | 2007-02-09 | 2010-07-01 | Panel, semiconductor device and method for the production thereof |
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US12/828,327 Active US8164173B2 (en) | 2007-02-09 | 2010-07-01 | Panel, semiconductor device and method for the production thereof |
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Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090085195A1 (en) * | 2007-09-28 | 2009-04-02 | Houle Sabina J | Method of Making Microelectronic Package Using Integrated Heat Spreader Stiffener Panel and Microelectronic Package Formed According to the Method |
US20100078783A1 (en) * | 2008-09-30 | 2010-04-01 | Infineon Technologies Ag | Device including two mounting surfaces |
US20110163440A1 (en) * | 2010-01-07 | 2011-07-07 | Infineon Technologies Ag | Semiconductor device |
CN102842556A (en) * | 2011-06-21 | 2012-12-26 | 万国半导体(开曼)股份有限公司 | Semiconductor component with dual surfaces exposed and manufacturing method of semiconductor component |
US20130026615A1 (en) * | 2011-07-28 | 2013-01-31 | Yuping Gong | Double-side exposed semiconductor device and its manufacturing method |
US20130105977A1 (en) * | 2011-10-27 | 2013-05-02 | Infineon Technologies Ag | Electronic Device and Method for Fabricating an Electronic Device |
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DE102014101076B4 (en) * | 2013-01-30 | 2019-11-21 | Infineon Technologies Ag | Process for the production of semiconductor devices |
US10818635B2 (en) * | 2018-04-23 | 2020-10-27 | Deca Technologies Inc. | Fully molded semiconductor package for power devices and method of making the same |
US20230197663A1 (en) * | 2021-12-20 | 2023-06-22 | Infineon Technologies Ag | Method of processing a semiconductor wafer, semiconductor die, and method of producing a semiconductor module |
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Publication number | Priority date | Publication date | Assignee | Title |
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US9318473B2 (en) * | 2012-04-20 | 2016-04-19 | Infineon Technologies Ag | Semiconductor device including a polymer disposed on a carrier |
DE102016101801B4 (en) | 2016-02-02 | 2021-01-14 | Infineon Technologies Ag | LOAD CONNECTION OF A POWER SEMICONDUCTOR ELEMENT, POWER SEMICONDUCTOR MODULE WITH IT AND MANUFACTURING PROCESS FOR IT |
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Citations (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4348253A (en) * | 1981-11-12 | 1982-09-07 | Rca Corporation | Method for fabricating via holes in a semiconductor wafer |
US5465009A (en) * | 1992-04-08 | 1995-11-07 | Georgia Tech Research Corporation | Processes and apparatus for lift-off and bonding of materials and devices |
US5637922A (en) * | 1994-02-07 | 1997-06-10 | General Electric Company | Wireless radio frequency power semiconductor devices using high density interconnect |
US5705848A (en) * | 1995-11-24 | 1998-01-06 | Asea Brown Boveri Ag | Power semiconductor module having a plurality of submodules |
US5786636A (en) * | 1993-09-29 | 1998-07-28 | Fuji Electric Co., Ltd. | Semiconductor device and method of fabricating same |
US5939755A (en) * | 1995-06-08 | 1999-08-17 | Kabushiki Kaisha Toshiba | Power IC having high-side and low-side switches in an SOI structure |
US6133634A (en) * | 1998-08-05 | 2000-10-17 | Fairchild Semiconductor Corporation | High performance flip chip package |
US6306680B1 (en) * | 1999-02-22 | 2001-10-23 | General Electric Company | Power overlay chip scale packages for discrete power devices |
US20020027276A1 (en) * | 2000-09-04 | 2002-03-07 | Noriaki Sakamoto | Circuit device and method of manufacturing the same |
US6582990B2 (en) * | 2001-08-24 | 2003-06-24 | International Rectifier Corporation | Wafer level underfill and interconnect process |
US6624522B2 (en) * | 2000-04-04 | 2003-09-23 | International Rectifier Corporation | Chip scale surface mounted device and process of manufacture |
US6677669B2 (en) * | 2002-01-18 | 2004-01-13 | International Rectifier Corporation | Semiconductor package including two semiconductor die disposed within a common clip |
US20040021216A1 (en) * | 2002-07-08 | 2004-02-05 | Futoshi Hosoya | Semiconductor device |
US20040061221A1 (en) * | 2002-07-15 | 2004-04-01 | International Rectifier Corporation | High power MCM package |
US20060087026A1 (en) * | 2004-10-01 | 2006-04-27 | Jianjun Cao | Audio amplifier assembly |
US7271470B1 (en) * | 2006-05-31 | 2007-09-18 | Infineon Technologies Ag | Electronic component having at least two semiconductor power devices |
US7304372B2 (en) * | 2005-09-21 | 2007-12-04 | International Rectifier Corporation | Semiconductor package |
US7626262B2 (en) * | 2006-06-14 | 2009-12-01 | Infineon Technologies Ag | Electrically conductive connection, electronic component and method for their production |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5019535A (en) * | 1989-03-28 | 1991-05-28 | General Electric Company | Die attachment method using nonconductive adhesive for use in high density interconnected assemblies |
DE10308928B4 (en) * | 2003-02-28 | 2009-06-18 | Siemens Ag | Method for producing self-supporting contacting structures of a non-insulated component |
US7757392B2 (en) * | 2006-05-17 | 2010-07-20 | Infineon Technologies Ag | Method of producing an electronic component |
US7476978B2 (en) * | 2006-05-17 | 2009-01-13 | Infineon Technologies, Ag | Electronic component having a semiconductor power device |
DE102006047761A1 (en) * | 2006-10-06 | 2008-04-10 | Infineon Technologies Ag | Semiconductor component and method for its production |
US7880280B2 (en) * | 2007-02-16 | 2011-02-01 | Infineon Technologies Ag | Electronic component and method for manufacturing an electronic component |
US8410590B2 (en) * | 2008-09-30 | 2013-04-02 | Infineon Technologies Ag | Device including a power semiconductor chip electrically coupled to a leadframe via a metallic layer |
-
2007
- 2007-02-09 DE DE102007007142A patent/DE102007007142B4/en not_active Expired - Fee Related
- 2007-02-22 US US11/677,774 patent/US7772693B2/en not_active Expired - Fee Related
-
2010
- 2010-07-01 US US12/828,327 patent/US8164173B2/en active Active
Patent Citations (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4348253A (en) * | 1981-11-12 | 1982-09-07 | Rca Corporation | Method for fabricating via holes in a semiconductor wafer |
US5465009A (en) * | 1992-04-08 | 1995-11-07 | Georgia Tech Research Corporation | Processes and apparatus for lift-off and bonding of materials and devices |
US5786636A (en) * | 1993-09-29 | 1998-07-28 | Fuji Electric Co., Ltd. | Semiconductor device and method of fabricating same |
US5637922A (en) * | 1994-02-07 | 1997-06-10 | General Electric Company | Wireless radio frequency power semiconductor devices using high density interconnect |
US5939755A (en) * | 1995-06-08 | 1999-08-17 | Kabushiki Kaisha Toshiba | Power IC having high-side and low-side switches in an SOI structure |
US5705848A (en) * | 1995-11-24 | 1998-01-06 | Asea Brown Boveri Ag | Power semiconductor module having a plurality of submodules |
US6133634A (en) * | 1998-08-05 | 2000-10-17 | Fairchild Semiconductor Corporation | High performance flip chip package |
US6306680B1 (en) * | 1999-02-22 | 2001-10-23 | General Electric Company | Power overlay chip scale packages for discrete power devices |
US6624522B2 (en) * | 2000-04-04 | 2003-09-23 | International Rectifier Corporation | Chip scale surface mounted device and process of manufacture |
US6767820B2 (en) * | 2000-04-04 | 2004-07-27 | International Rectifier Corporation | Chip scale surface mounted device and process of manufacture |
US6890845B2 (en) * | 2000-04-04 | 2005-05-10 | International Rectifier Corporation | Chip scale surface mounted device and process of manufacture |
US20020027276A1 (en) * | 2000-09-04 | 2002-03-07 | Noriaki Sakamoto | Circuit device and method of manufacturing the same |
US6582990B2 (en) * | 2001-08-24 | 2003-06-24 | International Rectifier Corporation | Wafer level underfill and interconnect process |
US6677669B2 (en) * | 2002-01-18 | 2004-01-13 | International Rectifier Corporation | Semiconductor package including two semiconductor die disposed within a common clip |
US20040021216A1 (en) * | 2002-07-08 | 2004-02-05 | Futoshi Hosoya | Semiconductor device |
US20040061221A1 (en) * | 2002-07-15 | 2004-04-01 | International Rectifier Corporation | High power MCM package |
US20060087026A1 (en) * | 2004-10-01 | 2006-04-27 | Jianjun Cao | Audio amplifier assembly |
US7304372B2 (en) * | 2005-09-21 | 2007-12-04 | International Rectifier Corporation | Semiconductor package |
US7271470B1 (en) * | 2006-05-31 | 2007-09-18 | Infineon Technologies Ag | Electronic component having at least two semiconductor power devices |
US7626262B2 (en) * | 2006-06-14 | 2009-12-01 | Infineon Technologies Ag | Electrically conductive connection, electronic component and method for their production |
Cited By (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090085195A1 (en) * | 2007-09-28 | 2009-04-02 | Houle Sabina J | Method of Making Microelectronic Package Using Integrated Heat Spreader Stiffener Panel and Microelectronic Package Formed According to the Method |
US8067256B2 (en) * | 2007-09-28 | 2011-11-29 | Intel Corporation | Method of making microelectronic package using integrated heat spreader stiffener panel and microelectronic package formed according to the method |
US20100078783A1 (en) * | 2008-09-30 | 2010-04-01 | Infineon Technologies Ag | Device including two mounting surfaces |
US8138587B2 (en) * | 2008-09-30 | 2012-03-20 | Infineon Technologies Ag | Device including two mounting surfaces |
US20110163440A1 (en) * | 2010-01-07 | 2011-07-07 | Infineon Technologies Ag | Semiconductor device |
CN102130027A (en) * | 2010-01-07 | 2011-07-20 | 英飞凌科技股份有限公司 | Semiconductor device |
DE102010061573B4 (en) | 2010-01-07 | 2018-07-12 | Infineon Technologies Ag | Method for producing a semiconductor component |
US8426251B2 (en) * | 2010-01-07 | 2013-04-23 | Infineon Technologies Ag | Semiconductor device |
CN102842556A (en) * | 2011-06-21 | 2012-12-26 | 万国半导体(开曼)股份有限公司 | Semiconductor component with dual surfaces exposed and manufacturing method of semiconductor component |
US8450152B2 (en) * | 2011-07-28 | 2013-05-28 | Alpha & Omega Semiconductor, Inc. | Double-side exposed semiconductor device and its manufacturing method |
US20130026615A1 (en) * | 2011-07-28 | 2013-01-31 | Yuping Gong | Double-side exposed semiconductor device and its manufacturing method |
US20130105977A1 (en) * | 2011-10-27 | 2013-05-02 | Infineon Technologies Ag | Electronic Device and Method for Fabricating an Electronic Device |
US9406646B2 (en) * | 2011-10-27 | 2016-08-02 | Infineon Technologies Ag | Electronic device and method for fabricating an electronic device |
WO2014035504A3 (en) * | 2012-05-30 | 2014-05-30 | Ipg Photonics Corporation | Laser ablation process for manufacturing submounts for laser diode and laser diode units |
KR20150016528A (en) * | 2012-05-30 | 2015-02-12 | 아이피지 포토닉스 코포레이션 | Laser ablation process for manufacturing submounts for laser diode and laser diode units |
CN104584343A (en) * | 2012-05-30 | 2015-04-29 | Ipg光子公司 | Laser ablation process for manufacturing submounts for laser diode and laser diode units |
US20160352070A1 (en) * | 2012-05-30 | 2016-12-01 | Ipg Photonics Corporation | Laser ablation process for manufacturing submounts for laser diodes and laser diode units |
KR102069724B1 (en) * | 2012-05-30 | 2020-01-23 | 아이피지 포토닉스 코포레이션 | Laser ablation process for manufacturing submounts for laser diode and laser diode units |
DE102014101076B4 (en) * | 2013-01-30 | 2019-11-21 | Infineon Technologies Ag | Process for the production of semiconductor devices |
US10818635B2 (en) * | 2018-04-23 | 2020-10-27 | Deca Technologies Inc. | Fully molded semiconductor package for power devices and method of making the same |
US20230197663A1 (en) * | 2021-12-20 | 2023-06-22 | Infineon Technologies Ag | Method of processing a semiconductor wafer, semiconductor die, and method of producing a semiconductor module |
Also Published As
Publication number | Publication date |
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US8164173B2 (en) | 2012-04-24 |
US7772693B2 (en) | 2010-08-10 |
DE102007007142A1 (en) | 2008-08-21 |
US20100264523A1 (en) | 2010-10-21 |
DE102007007142B4 (en) | 2008-11-13 |
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