US20080182432A1 - Interposer for connecting plurality of chips and method for manufacturing the same - Google Patents
Interposer for connecting plurality of chips and method for manufacturing the same Download PDFInfo
- Publication number
- US20080182432A1 US20080182432A1 US11/756,634 US75663407A US2008182432A1 US 20080182432 A1 US20080182432 A1 US 20080182432A1 US 75663407 A US75663407 A US 75663407A US 2008182432 A1 US2008182432 A1 US 2008182432A1
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- Prior art keywords
- interposer
- chip
- disposed
- connective
- substrate
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Links
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- 238000004519 manufacturing process Methods 0.000 title 1
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052814 silicon oxide Inorganic materials 0.000 description 10
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- 229910052737 gold Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
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Images
Classifications
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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Definitions
- the invention is related to an interposer, and particularly to an interposer capable of connecting several chips and reducing the size of a package having the interposer therein.
- FIG. 1 is a schematic diagram of a conventional package 10 .
- FIG. 1 shows a package 10 having a package substrate 12 and two chips 14 , 16 respectively disposed on each surface thereof.
- the chips 14 , 16 have a plurality of respective contact pads 14 A, 14 B, 16 A, 16 B, which are electrically connected to a plurality of contact pads 20 disposed on a surface of the package substrate 12 through a plurality of wires 18 and 22 respectively.
- a package material (not shown) is formed covering the chips 14 , 16 , the contact pads 14 A, 14 B, 16 A, 16 B, the wires 18 , 22 , and the contact pad 20 disposed on the surface of the package substrate 12 .
- the package 10 is mounted on a print circuit board by bumps (not shown) or leads (not shown) of various sizes to form an electronic system with other active or passive elements to be utilized in consumer electronic devices.
- the distance between the chips 14 and 16 of the package 10 will be reduced to decrease the area of the package 10 .
- the reduced distance between the chips 14 and 16 results in problems, such as raising the difficulty and complexity in wiring, or electromagnetic interference between the chips 14 and 16 .
- an interposer for connecting a plurality of chips.
- the interposer has a connective substrate, at least a through via positioned in the connective substrate, and at least a first chip and a second chip.
- the connective substrate has a first surface and a second surface.
- the first chip is electrically connected to the first surface
- the second chip is electrically connected to the second surface. Both the first chip and the second chip are flip-chips.
- the through via acts as a connector and electrically connects the first surface and the second surface of the connective substrate.
- the present invention further provides a method of forming an interposer.
- a connective substrate having a first surface and a second surface is provided.
- the first surface includes at least a first dielectric layer, at least a first interconnection, and at least a first contact pad.
- An adhesive layer is provided to bond the first surface to a carrier.
- At least a through hole is formed on the second surface, and the through hole penetrates the connective substrate.
- a conductive layer is formed to fill the through via and to form a through via connecting the first surface and the second surface.
- at least a second dielectric layer, at least a second interconnection, and at least a second contact pad are formed on the second surface of the connective substrate.
- the second interconnection and the second contact pad are electrically connected to the first interconnection and the first contact pad on the first surface.
- the first surface and the wafer carrier are separated.
- the interposer of the present invention is capable of connecting two or more chips, or other components requiring signal transmission.
- the use of the interposer reduces the area of the package and the size of the electronic systems or barebones having the interposer therein.
- the interposer is used for several types of packages. Therefore, the interposer overcomes the wiring difficulty and increases the yield of the packaging.
- FIG. 1 is a schematic diagram of a conventional package.
- FIGS. 2-10 are schematic diagrams illustrating a method of forming an interposer according to a preferred embodiment of the present invention.
- FIG. 11 is a schematic diagram illustrating the interposer for connecting a plurality of chips according to another preferred embodiment of the present invention.
- FIG. 12 further discloses the interposers of the present invention connecting three chips according to a preferred embodiment of the present embodiment.
- FIG. 13 is a schematic diagram illustrating the interposer connecting several chips in vertical and horizontal directions according to a preferred embodiment of the present invention.
- FIGS. 2-10 are schematic diagrams illustrating a method of forming an interposer according to a preferred embodiment of the present invention.
- a connective substrate 30 such as a wafer
- the connective substrate 30 has a first surface 32 and a second surface 34 .
- a silicon oxide layer 36 , at least a dielectric layer, and at least a conductive layer is formed on the first surface 32 , and several processes, including deposition, lithography, and etching processes, are performed to form at least an interconnection embedded through the dielectric layer and at least an exposed contact pad for electrical connection.
- FIG. 2 only shows a double-layered interconnection for illustration, but single-layered or multi-layered interconnections are allowable.
- a plurality of the first dielectric layers 38 and a plurality of first interconnections 42 , 42 embedded through the first dielectric layers 38 are formed on the first surface 32 .
- a protective layer 44 is formed to cover the first dielectric layers 38 and the first interconnections 42 , 44 , and to expose a plurality of first contact pads 46 .
- the silicon oxide layer 36 acts as a preventable and stress buffer layer, and has at least an opening 48 for electrical connection between the first surface 32 and the second surface 34 .
- the thickness, critical dimension, and pattern layout of the first interconnection 40 , 42 may be modified depending on requirements.
- the interconnections 40 , 42 preferably have a thickness of 0.5 micrometers ( ⁇ m) and a critical dimension of at least 10 ⁇ m.
- the material of the first interconnections 40 , 42 includes AlCu, Cu, Al, Au, or other material of low-resistance to reduce signal loss during signal transmission.
- a wafer carrier 50 and an adhesive layer 52 are provided.
- the adhesive layer 52 bonds the first surface 32 having the first dielectric layer 38 , the first interconnections 40 , 42 and the first contact pad 46 thereon to the wafer carrier 50 .
- a thinning process for example a CMP process, is performed on the second surface 34 to reduce the thickness of the connective substrate 38 . Additionally, the thinning process is optionally performed depending on the thickness of the connective substrate 30 .
- the thinning process is not limited to the CMP process illustrated in the present embodiment, and other methods capable of reducing the thickness of the substrate or wafer are allowable.
- a silicon oxide layer 54 is deposited on the second surface 34 of the connective substrate 34 .
- the silicon oxide layer 54 may act as a preventable and stress buffer layer.
- a lithography and etching process is performed on the second surface 34 to remove a part of the silicon oxide layer 54 and form a through hole 56 in the connective substrate 30 , wherein the first interconnection 42 acts as an etch stop layer.
- a conductive layer 58 is formed to fill the through hole 56 .
- a seed layer 60 of Cu is formed on the silicon oxide layer 54 and a surface of the through hole 56 by sputtering.
- an electroplating process is performed to form a conductive layer 58 of Cu on a surface of the seed layer 56 .
- a planarization process is performed to remove a part of the conductive layer 58 and the Cu seed layer 60 disposed on the surface of the silicon oxide layer 54 . Therefore, a through via 62 is formed.
- the material of the conductive layer 56 or the through via 62 may also include AlCu, Al, or Au.
- the method of forming the through via 62 is not limited to sputtering, electroplating, or the CMP processes illustrated in the present embodiment, and other processes known by those skilled in the art to stuff the through via 56 and form the through via 62 are allowable.
- At least a dielectric layer and at least a conductive layer are formed on the second surface 34 .
- interconnections are defined and embedded through the dielectric layer.
- a double-layered interconnection is illustrated in the present embodiment, but other types of interconnections are allowable.
- a plurality of second dielectric layers 64 and a plurality of second interconnections 66 , 68 embedded through the second dielectric layer 64 are formed on the second surface 32 of the connective substrate 30 .
- a protective layer 70 is formed on the second dielectric layers 64 and the second interconnections 66 , 68 , to expose a plurality of second contact pads 72 .
- the first interconnection 42 on the first surface 32 is electrically connected to the second interconnection 66 on the second surface 34 by the through via 62 disposed in the connective substrate 30 for signal transmission.
- the thickness, critical dimension, and pattern layout of the second interconnection 66 , 68 may be modified depending on requirements.
- the second interconnections 66 , 68 preferably have a thickness of 0.5 ⁇ m and a critical dimension of at least 10 ⁇ m.
- the material of the second interconnections 66 , 68 includes AlCu, Cu, Al, Au, or other material of low-resistance to reduce signal loss during signal transmission.
- a plurality of second under bump metallurgies 74 are respectively formed on a surface of a plurality of second contact pads 72 .
- the second under bump metallurgies 74 may be formed optionally on the second contact pads 72 .
- the position and quantity of the second under bump metallurgies 74 depend on the size of the intended chip and connection types between the under bump metallurgies 74 and the intended chip(s). For the same reason, if a flip-chip is intended to connect the first surface 32 , a plurality of first under bump metallurgies (not shown) may be respectively formed on a surface of the first contact pads 46 .
- the adhesive layer 52 is removed without impairing any elements on the first surface 32 .
- the first surface 32 and the wafer carrier 50 (not shown) are separated and an interposer 76 of the present invention is formed.
- the interposer 76 is formed and capable of connecting several chips. Please refer to FIG. 11 , which is a schematic diagram illustrating the interposer for connecting a plurality of chips according to another preferred embodiment of the present invention. Components with substantially the same functions are identified by the same reference numeral for the sake of simplicity.
- the interposer 76 includes a connective substrate 30 having a first surface 32 and a second surface 34 , and a through via 62 disposed in the connective substrate 30 .
- the interposer 76 further includes the silicon oxide layer 36 , the first dielectric layer 38 , the first interconnections 40 , 42 , the first contact pads 46 , and the protective layer 44 disposed on the first surface 32 .
- first chip (IC 1 ) 78 which is a flip-chip, is disposed on the first surface 32 .
- the first chip 78 is electrically connected to the first surface 32 by the first under bump metallurgies 80 , and a plurality of first bumps 82 sandwiched between the first under bump metallurgies 80 and the first chip 78 .
- the interposer 78 also has the silicon oxide 54 , the second dielectric layer 64 , the second interconnections 66 , 68 , and the second contact pads 72 , and the protective layer 70 on the second surface 34 .
- At least a second chip (IC 2 ) 84 which is a flip-chip, is electrically connected to the second surface 34 by the second under bump metallurgies 74 and a plurality of second bumps 86 sandwiched between the second under bump metallurgies 74 and the second chip 84 .
- the through via 62 acts as a connector electrically connecting the first interconnection 42 on the first surface 32 and the second interconnection 66 on the second surface 34 . Consequently, the first chip 78 and the second chip 84 are electrically connected by the through via 62 .
- the present embodiment only shows a through via 62 in FIG. 11 for illustration, but the present invention is not limited to this. The quantity and the position of the through via 62 may be modified depending on requirements of the products.
- FIG. 12 further discloses the interposers of the present invention connecting three chips according to a preferred embodiment of the present embodiment.
- a first interposer 96 is sandwiched between a first chip (IC 1 ) 90 and a second chip (IC 2 ) 92
- a second interposer 98 is sandwiched between the second chip 92 and a third chip (IC 3 ) 94 .
- the chips 90 , 92 , 94 are flip-chips. Consequently, signals may be transmitted among three chips 90 , 92 , 94 through the first interposer 96 and the second interposer 98 .
- the use of the interposer is not limited to those shown in FIG.
- FIG. 13 is a schematic diagram illustrating the interposer connecting several chips in vertical and horizontal directions according to another preferred embodiment of the present invention.
- a first chip (IC 1 ) 102 and a second chip (IC 2 ) 104 are electrically connected by an interposer 100 in the vertical direction. Both the first chip 102 and the second chip 104 are flip-chips.
- a third chip (IC 3 ) 106 , a fourth chip (IC 4 ) 108 , a fifth chip (IC 5 ) 110 , and a sixth chip (IC 6 ) 112 are electrically connected to either surface of the interposer 110 by a plurality of wires 114 in a horizontal direction.
- the present invention uses double-layered interconnections for illustration, but other types of interconnections with single-layer or multi-layered structures are allowable.
- the aforementioned embodiments only connect a flip-chip to each surface of the interposer.
- the interposer may be modified with different sizes and pattern layouts for electrically connecting two or more flip-chips on the first surface or the second surface of the interposer.
- the material of the protective layer, the first dielectric layer on the first surface, and the second dielectric layer on the second surface may include silicon oxide, silicon nitride, or other materials having isolation property.
- the interposer and the connected chips may be regarded as a module.
- the module may be mounted on a package substrate and covered by a package material.
- the module also connects to a print circuit board and other passive or active elements by bumps or wires for composing a complete electronic system.
- the interposer of the present invention electrically connects the chips on the first surface and the second surface by the through via.
- the interposer may also connect two or more chips for signal transmission. Therefore, the area of the package having the interposer and the connected chips therein may be reduced. Furthermore, the interposer may be used in several types of packages and overcome the difficulty in wiring of the prior art.
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Abstract
The invention discloses an interposer used for connecting a plurality of chips. The interposer includes a connective substrate and at least a through via disposed in the connective substrate. The connective substrate has a first surface and a second surface. The through via acts as a connector, and is electrically connected to the first surface and the second surface. The first surface and the second surface are electrically connected to at least a first chip and a second chip respectively. In addition, the first chip and the second chip are electrically connected by the through via.
Description
- 1. Field of the Invention
- The invention is related to an interposer, and particularly to an interposer capable of connecting several chips and reducing the size of a package having the interposer therein.
- 2. Description of the Prior Art
- In recent years, consumer electronic devices have become smaller and lighter. In addition, high performance, high speed, large capacity, multi-functionality, and less electrical consumption are desired goals promoting technical development of these electric products.
- Please refer to
FIG. 1 , which is a schematic diagram of aconventional package 10.FIG. 1 shows apackage 10 having apackage substrate 12 and twochips chips respective contact pads contact pads 20 disposed on a surface of thepackage substrate 12 through a plurality ofwires 18 and 22 respectively. A package material (not shown) is formed covering thechips contact pads wires 18, 22, and thecontact pad 20 disposed on the surface of thepackage substrate 12. Thepackage 10 is mounted on a print circuit board by bumps (not shown) or leads (not shown) of various sizes to form an electronic system with other active or passive elements to be utilized in consumer electronic devices. - Since consumer electrical devices are tending towards miniaturization, the distance between the
chips package 10 will be reduced to decrease the area of thepackage 10. However, the reduced distance between thechips chips - It is therefore a primary objective of the present invention to provide an interposer for connecting a plurality of chips to overcome the abovementioned wiring difficulty.
- According to the present invention, an interposer for connecting a plurality of chips is provided. The interposer has a connective substrate, at least a through via positioned in the connective substrate, and at least a first chip and a second chip. The connective substrate has a first surface and a second surface. The first chip is electrically connected to the first surface, and the second chip is electrically connected to the second surface. Both the first chip and the second chip are flip-chips. The through via acts as a connector and electrically connects the first surface and the second surface of the connective substrate.
- The present invention further provides a method of forming an interposer. Initially, a connective substrate having a first surface and a second surface is provided. The first surface includes at least a first dielectric layer, at least a first interconnection, and at least a first contact pad. An adhesive layer is provided to bond the first surface to a carrier. At least a through hole is formed on the second surface, and the through hole penetrates the connective substrate. A conductive layer is formed to fill the through via and to form a through via connecting the first surface and the second surface. Afterwards, at least a second dielectric layer, at least a second interconnection, and at least a second contact pad are formed on the second surface of the connective substrate. In addition, the second interconnection and the second contact pad are electrically connected to the first interconnection and the first contact pad on the first surface. Then, the first surface and the wafer carrier are separated.
- The interposer of the present invention is capable of connecting two or more chips, or other components requiring signal transmission. The use of the interposer reduces the area of the package and the size of the electronic systems or barebones having the interposer therein. The interposer is used for several types of packages. Therefore, the interposer overcomes the wiring difficulty and increases the yield of the packaging.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
-
FIG. 1 is a schematic diagram of a conventional package. -
FIGS. 2-10 are schematic diagrams illustrating a method of forming an interposer according to a preferred embodiment of the present invention. -
FIG. 11 is a schematic diagram illustrating the interposer for connecting a plurality of chips according to another preferred embodiment of the present invention. -
FIG. 12 further discloses the interposers of the present invention connecting three chips according to a preferred embodiment of the present embodiment. -
FIG. 13 is a schematic diagram illustrating the interposer connecting several chips in vertical and horizontal directions according to a preferred embodiment of the present invention. - Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings, in which components with substantially the same functions are identified by the same reference numeral for the sake of simplicity. It should be noted, however, that the present invention is in no way limited to the following illustrative embodiments.
- Please refer to
FIGS. 2-10 .FIGS. 2-10 are schematic diagrams illustrating a method of forming an interposer according to a preferred embodiment of the present invention. As shown inFIG. 2 , aconnective substrate 30, such as a wafer, is provided. Theconnective substrate 30 has afirst surface 32 and asecond surface 34. Asilicon oxide layer 36, at least a dielectric layer, and at least a conductive layer is formed on thefirst surface 32, and several processes, including deposition, lithography, and etching processes, are performed to form at least an interconnection embedded through the dielectric layer and at least an exposed contact pad for electrical connection. For simplicity of description,FIG. 2 only shows a double-layered interconnection for illustration, but single-layered or multi-layered interconnections are allowable. As shown inFIG. 2 , a plurality of the firstdielectric layers 38 and a plurality offirst interconnections dielectric layers 38 are formed on thefirst surface 32. Aprotective layer 44 is formed to cover the firstdielectric layers 38 and thefirst interconnections first contact pads 46. Thesilicon oxide layer 36 acts as a preventable and stress buffer layer, and has at least anopening 48 for electrical connection between thefirst surface 32 and thesecond surface 34. The thickness, critical dimension, and pattern layout of thefirst interconnection first interconnections interconnections first interconnections - As shown in
FIG. 3 , awafer carrier 50 and anadhesive layer 52, such as a piece of tape or other substance for temporary bonding, are provided. Theadhesive layer 52 bonds thefirst surface 32 having the firstdielectric layer 38, thefirst interconnections first contact pad 46 thereon to thewafer carrier 50. As shown inFIG. 4 , a thinning process, for example a CMP process, is performed on thesecond surface 34 to reduce the thickness of theconnective substrate 38. Additionally, the thinning process is optionally performed depending on the thickness of theconnective substrate 30. The thinning process is not limited to the CMP process illustrated in the present embodiment, and other methods capable of reducing the thickness of the substrate or wafer are allowable. - Referring to
FIG. 5 , asilicon oxide layer 54 is deposited on thesecond surface 34 of theconnective substrate 34. Thesilicon oxide layer 54 may act as a preventable and stress buffer layer. A lithography and etching process is performed on thesecond surface 34 to remove a part of thesilicon oxide layer 54 and form a throughhole 56 in theconnective substrate 30, wherein thefirst interconnection 42 acts as an etch stop layer. Referring toFIG. 6 , aconductive layer 58 is formed to fill the throughhole 56. In the present embodiment, aseed layer 60 of Cu is formed on thesilicon oxide layer 54 and a surface of the throughhole 56 by sputtering. Then, an electroplating process is performed to form aconductive layer 58 of Cu on a surface of theseed layer 56. As shown inFIG. 7 , a planarization process is performed to remove a part of theconductive layer 58 and theCu seed layer 60 disposed on the surface of thesilicon oxide layer 54. Therefore, a through via 62 is formed. The material of theconductive layer 56 or the through via 62 may also include AlCu, Al, or Au. The method of forming the through via 62 is not limited to sputtering, electroplating, or the CMP processes illustrated in the present embodiment, and other processes known by those skilled in the art to stuff the through via 56 and form the through via 62 are allowable. - Afterwards, at least a dielectric layer and at least a conductive layer are formed on the
second surface 34. Through the lithography and etching processes, interconnections are defined and embedded through the dielectric layer. For simplicity of description, a double-layered interconnection is illustrated in the present embodiment, but other types of interconnections are allowable. As shown inFIG. 8 , a plurality of second dielectric layers 64 and a plurality ofsecond interconnections second dielectric layer 64 are formed on thesecond surface 32 of theconnective substrate 30. Aprotective layer 70 is formed on the second dielectric layers 64 and thesecond interconnections second contact pads 72. It should be noted that thefirst interconnection 42 on thefirst surface 32 is electrically connected to thesecond interconnection 66 on thesecond surface 34 by the through via 62 disposed in theconnective substrate 30 for signal transmission. The thickness, critical dimension, and pattern layout of thesecond interconnection second interconnections second interconnections second interconnections - As shown in
FIG. 9 , a plurality of second underbump metallurgies 74 are respectively formed on a surface of a plurality ofsecond contact pads 72. The second underbump metallurgies 74 may be formed optionally on thesecond contact pads 72. The position and quantity of the second underbump metallurgies 74 depend on the size of the intended chip and connection types between theunder bump metallurgies 74 and the intended chip(s). For the same reason, if a flip-chip is intended to connect thefirst surface 32, a plurality of first under bump metallurgies (not shown) may be respectively formed on a surface of thefirst contact pads 46. - Please refer to
FIG. 10 . Theadhesive layer 52 is removed without impairing any elements on thefirst surface 32. Thus, thefirst surface 32 and the wafer carrier 50 (not shown) are separated and aninterposer 76 of the present invention is formed. - Hereinafter, the
interposer 76 is formed and capable of connecting several chips. Please refer toFIG. 11 , which is a schematic diagram illustrating the interposer for connecting a plurality of chips according to another preferred embodiment of the present invention. Components with substantially the same functions are identified by the same reference numeral for the sake of simplicity. Theinterposer 76 includes aconnective substrate 30 having afirst surface 32 and asecond surface 34, and a through via 62 disposed in theconnective substrate 30. Theinterposer 76 further includes thesilicon oxide layer 36, thefirst dielectric layer 38, thefirst interconnections first contact pads 46, and theprotective layer 44 disposed on thefirst surface 32. Furthermore, at least a first chip (IC1) 78, which is a flip-chip, is disposed on thefirst surface 32. Thefirst chip 78 is electrically connected to thefirst surface 32 by the first underbump metallurgies 80, and a plurality offirst bumps 82 sandwiched between the first underbump metallurgies 80 and thefirst chip 78. Theinterposer 78 also has thesilicon oxide 54, thesecond dielectric layer 64, thesecond interconnections second contact pads 72, and theprotective layer 70 on thesecond surface 34. At least a second chip (IC2) 84, which is a flip-chip, is electrically connected to thesecond surface 34 by the second underbump metallurgies 74 and a plurality ofsecond bumps 86 sandwiched between the second underbump metallurgies 74 and thesecond chip 84. It should be noted that the through via 62 acts as a connector electrically connecting thefirst interconnection 42 on thefirst surface 32 and thesecond interconnection 66 on thesecond surface 34. Consequently, thefirst chip 78 and thesecond chip 84 are electrically connected by the through via 62. The present embodiment only shows a through via 62 inFIG. 11 for illustration, but the present invention is not limited to this. The quantity and the position of the through via 62 may be modified depending on requirements of the products. - Please refer to
FIG. 12 .FIG. 12 further discloses the interposers of the present invention connecting three chips according to a preferred embodiment of the present embodiment. As shown inFIG. 12 , afirst interposer 96 is sandwiched between a first chip (IC1) 90 and a second chip (IC2) 92, and asecond interposer 98 is sandwiched between thesecond chip 92 and a third chip (IC3) 94. Thechips chips first interposer 96 and thesecond interposer 98. However, the use of the interposer is not limited to those shown inFIG. 11 and 12 , in which the interposers connect the flip-chips and transmit signals vertically. The interposer of the present invention may also connect the chips in vertical and horizontal directions. Please refer toFIG. 13 , which is a schematic diagram illustrating the interposer connecting several chips in vertical and horizontal directions according to another preferred embodiment of the present invention. A first chip (IC1) 102 and a second chip (IC2) 104 are electrically connected by an interposer 100 in the vertical direction. Both thefirst chip 102 and thesecond chip 104 are flip-chips. Additionally, a third chip (IC3) 106, a fourth chip (IC4) 108, a fifth chip (IC5) 110, and a sixth chip (IC6) 112 are electrically connected to either surface of theinterposer 110 by a plurality ofwires 114 in a horizontal direction. - The present invention uses double-layered interconnections for illustration, but other types of interconnections with single-layer or multi-layered structures are allowable. The aforementioned embodiments only connect a flip-chip to each surface of the interposer. In addition, the interposer may be modified with different sizes and pattern layouts for electrically connecting two or more flip-chips on the first surface or the second surface of the interposer. Furthermore, the material of the protective layer, the first dielectric layer on the first surface, and the second dielectric layer on the second surface may include silicon oxide, silicon nitride, or other materials having isolation property.
- The interposer and the connected chips may be regarded as a module. The module may be mounted on a package substrate and covered by a package material. The module also connects to a print circuit board and other passive or active elements by bumps or wires for composing a complete electronic system.
- According to the above, the interposer of the present invention electrically connects the chips on the first surface and the second surface by the through via. The interposer may also connect two or more chips for signal transmission. Therefore, the area of the package having the interposer and the connected chips therein may be reduced. Furthermore, the interposer may be used in several types of packages and overcome the difficulty in wiring of the prior art.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.
Claims (16)
1. An interposer for connecting a plurality of chips, the interposer comprising:
a connective substrate having a first surface and a second surface;
at least a first chip disposed on the first surface, wherein the first chip is a flip-chip;
at least a second chip disposed on the second surface, wherein the second chip is a flip-chip; and
at least a through via positioned in the connective substrate to connect the first surface and the second surface.
2. The interposer of claim 1 , wherein the first surface further comprises:
a plurality of first dielectric layers disposed on the first surface;
a plurality of first interconnections respectively embedded through the plurality of first dielectric layers;
a plurality of first contact pads respectively disposed on a surface of the plurality of first dielectric layers, the plurality of first contact pads electrically connected to the plurality of first interconnections respectively;
a plurality of first under bump metallurgies respectively disposed on a surface of the plurality of first contact pads; and
a plurality of first bumps sandwiched between the first chip and the plurality of first under bump metallurgies for electrical connectivity between the first chip and the first surface.
3. The interposer of claim 1 , wherein the second surface further comprises:
a plurality of second dielectric layers disposed on the first surface;
a plurality of second interconnections respectively embedded through the plurality of second dielectric layers;
a plurality of second contact pads respectively disposed on a surface of the plurality of second dielectric layers, the plurality of second contact pads electrically connected to the plurality of second interconnections respectively;
a plurality of second under bump metallurgies respectively disposed on a surface of the plurality of second contact pads; and
a plurality of second bumps sandwiched between the second chip and the plurality of second under bump metallurgies for electrical connectivity between the second chip and the second surface.
4. The interposer of claim 2 , wherein the first interconnections comprise AlCu alloy, Cu, Al, or Au.
5. The interposer of claim 3 , wherein the second interconnections comprise AlCu alloy, Cu, Al, or Au.
6. The interposer of claim 1 , further comprising at least a third chip electrically connected to the first surface or the second surface of the connective substrate by wires.
7. The interposer of claim 2 , wherein a critical dimension of each first interconnection is greater than 10 micrometers.
8. The interposer of claim 3 , wherein a critical dimension of each second interconnection is greater than 10 micrometers.
9. A method of forming an interposer, comprising:
providing a connective substrate having a first surface and a second surface, the connective substrate further comprising at least a first dielectric layer, at least a first interconnection and at least a first contact pad disposed on the first surface;
providing an adhesive layer to bond the first surface to a wafer carrier;
forming at least a through hole on the second surface of the connective substrate;
forming a conductive layer to fill the through hole and forming a through via between the first surface and the second surface;
forming at least a second dielectric layer, at least a second interconnection, and at least a second contact pad on the second surface of the connective substrate, wherein the through via electrically connects the second interconnection and the second contact pad; and
separating the first surface and the wafer carrier.
10. The method of claim 9 , further comprising:
forming a stress buffer layer on the second surface of the connective substrate after the first surface is bonded to the wafer carrier.
11. The method of claim 9 , further comprising
forming a protective layer covering the second dielectric layer and the second interconnection and exposing the second contact pad, after the second dielectric layer, the second interconnection, and the second contact pad are formed on the second surface of the connective substrate.
12. The method of claim 9 , wherein a thinning process is optionally performed on the second surface of the connective substrate after the first surface of the connective substrate is bonded to the wafer carrier.
13. The method of claim 9 , wherein forming the through via further comprises:
performing an electroplating process to form the conductive layer covering the second surface and filling the through hole; and
performing a planarization process to remove a part of the conductive layer on the second surface of the connective substrate and form the through via.
14. An interposer for connecting chips, comprising:
a connective substrate having a first surface and a second surface;
at least a first chip disposed on the first surface and electrically connected to the first surface; and
at least a second chip disposed on the second surface and electrically connected to the second surface.
15. The interposer of claim 14 , further comprising at least a through via disposed in the connective substrate for electrical connectivity between the first surface and the second surface.
16. The interposer of claim 14 , further comprising at least a third chip electrically connected to the first surface or the second surface by wires.
Priority Applications (1)
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US12/273,550 US7987588B2 (en) | 2007-01-29 | 2008-11-19 | Interposer for connecting plurality of chips and method for manufacturing the same |
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TW096103230A TWI363414B (en) | 2007-01-29 | 2007-01-29 | Interposer for connecting a plurality of chips and method for manufacturing the same |
TW096103230 | 2007-01-29 |
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US12/273,550 Division US7987588B2 (en) | 2007-01-29 | 2008-11-19 | Interposer for connecting plurality of chips and method for manufacturing the same |
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US20080182432A1 true US20080182432A1 (en) | 2008-07-31 |
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US12/273,550 Active 2028-08-29 US7987588B2 (en) | 2007-01-29 | 2008-11-19 | Interposer for connecting plurality of chips and method for manufacturing the same |
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US12/273,550 Active 2028-08-29 US7987588B2 (en) | 2007-01-29 | 2008-11-19 | Interposer for connecting plurality of chips and method for manufacturing the same |
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Cited By (7)
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US20100264516A1 (en) * | 2007-11-07 | 2010-10-21 | Stats Chippac, Ltd. | Method of Forming an Inductor on a Semiconductor Wafer |
CN103378017A (en) * | 2012-04-24 | 2013-10-30 | 辉达公司 | High density 3D package |
US20150216030A1 (en) * | 2012-01-20 | 2015-07-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-Dimensional Integrated Circuit Structures and Methods of Forming the Same |
US9234034B2 (en) | 2008-05-13 | 2016-01-12 | Novimmune S.A. | Methods of treating autoimmune diseases using anti-IL6/IL-6R complex antibodies |
US9853015B1 (en) * | 2016-12-15 | 2017-12-26 | Powertech Technology Inc. | Semiconductor device with stacking chips |
US9929484B1 (en) * | 2016-12-20 | 2018-03-27 | General Electric Company | Electrical connector design for isolating electrical contacts in medical devices |
US20220238328A1 (en) * | 2021-01-26 | 2022-07-28 | Tokyo Electron Limited | Localized stress regions for three-dimension chiplet formation |
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US9396242B2 (en) | 2011-04-11 | 2016-07-19 | Salesforce.Com, Inc. | Multi-master data replication in a distributed multi-tenant system |
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US20060186524A1 (en) * | 2005-02-18 | 2006-08-24 | Fujitsu Limited | Semiconductor device |
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US6181569B1 (en) * | 1999-06-07 | 2001-01-30 | Kishore K. Chakravorty | Low cost chip size package and method of fabricating the same |
JP4444435B2 (en) * | 2000-03-06 | 2010-03-31 | ソニーケミカル&インフォメーションデバイス株式会社 | Printed wiring board and method for manufacturing printed wiring board |
-
2007
- 2007-01-29 TW TW096103230A patent/TWI363414B/en not_active IP Right Cessation
- 2007-06-01 US US11/756,634 patent/US20080182432A1/en not_active Abandoned
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Patent Citations (1)
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US20060186524A1 (en) * | 2005-02-18 | 2006-08-24 | Fujitsu Limited | Semiconductor device |
Cited By (14)
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US8309452B2 (en) * | 2007-11-07 | 2012-11-13 | Stats Chippac, Ltd. | Method of forming an inductor on a semiconductor wafer |
US20130015555A1 (en) * | 2007-11-07 | 2013-01-17 | Stats Chippac, Ltd. | Method of Forming an Inductor on a Semiconductor Wafer |
US20100264516A1 (en) * | 2007-11-07 | 2010-10-21 | Stats Chippac, Ltd. | Method of Forming an Inductor on a Semiconductor Wafer |
US9337141B2 (en) * | 2007-11-07 | 2016-05-10 | Stats Chippac, Ltd. | Method of forming an inductor on a semiconductor wafer |
US10759862B2 (en) | 2008-05-13 | 2020-09-01 | Novimmune, S.A. | Anti-IL-6/IL-6R antibodies and methods of use thereof |
US9234034B2 (en) | 2008-05-13 | 2016-01-12 | Novimmune S.A. | Methods of treating autoimmune diseases using anti-IL6/IL-6R complex antibodies |
US11613582B2 (en) | 2008-05-13 | 2023-03-28 | Novimmune S.A. | Anti-IL-6/IL-6R antibodies and methods of use thereof |
US20150216030A1 (en) * | 2012-01-20 | 2015-07-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-Dimensional Integrated Circuit Structures and Methods of Forming the Same |
US9686852B2 (en) * | 2012-01-20 | 2017-06-20 | Taiwan Semicondcutor Manufacturing Company, Ltd. | Multi-dimensional integrated circuit structures and methods of forming the same |
CN103378017A (en) * | 2012-04-24 | 2013-10-30 | 辉达公司 | High density 3D package |
US9853015B1 (en) * | 2016-12-15 | 2017-12-26 | Powertech Technology Inc. | Semiconductor device with stacking chips |
US9929484B1 (en) * | 2016-12-20 | 2018-03-27 | General Electric Company | Electrical connector design for isolating electrical contacts in medical devices |
US20220238328A1 (en) * | 2021-01-26 | 2022-07-28 | Tokyo Electron Limited | Localized stress regions for three-dimension chiplet formation |
US11721551B2 (en) * | 2021-01-26 | 2023-08-08 | Tokyo Electron Limited | Localized stress regions for three-dimension chiplet formation |
Also Published As
Publication number | Publication date |
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US20090064496A1 (en) | 2009-03-12 |
TWI363414B (en) | 2012-05-01 |
TW200832664A (en) | 2008-08-01 |
US7987588B2 (en) | 2011-08-02 |
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