US20080164609A1 - Injection molded solder ball method - Google Patents

Injection molded solder ball method Download PDF

Info

Publication number
US20080164609A1
US20080164609A1 US11/620,900 US62090007A US2008164609A1 US 20080164609 A1 US20080164609 A1 US 20080164609A1 US 62090007 A US62090007 A US 62090007A US 2008164609 A1 US2008164609 A1 US 2008164609A1
Authority
US
United States
Prior art keywords
solder
cavity
solder ball
microns
mold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/620,900
Inventor
Peter A. Gruber
Barry A. Hochlowski
David T. Naugle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US11/620,900 priority Critical patent/US20080164609A1/en
Publication of US20080164609A1 publication Critical patent/US20080164609A1/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HOCHLOWSKI, BARRY A., NAUGLE, DAVID T., GRUBER, PETER A.
Priority to US12/543,811 priority patent/US7955966B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05671—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11003—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
    • H05K2203/0113—Female die used for patterning or transferring, e.g. temporary substrate having recessed pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0338—Transferring metal or conductive material other than a circuit pattern, e.g. bump, solder, printed component

Definitions

  • the present invention relates to a method for making solder balls that can be used to bump semiconductor wafers.
  • the solder balls can be made using an injection molded soldering process.
  • Solder bumping of semiconductor wafers is undergoing rapid evolution. Whereas past methods of evaporation, plating and paste screening have been the historical technologies, requirements such as alloy flexibility (especially for lead-free (Pb-free) alloys) and cost reductions are driving the industry towards two emerging new technologies. Included in these technologies are ball placement and injection molded solder, otherwise known as Controlled Collapse Chip Connection New Process (C4NP). This methodology focuses on using injection molded solder for significantly improving ball placement technology.
  • C4NP Controlled Collapse Chip Connection New Process
  • solder paste is deposited into cavities in a silicon mold. This paste is later reflowed to produce solder balls.
  • this methodology possesses the same drawback that results from any paste application, namely voiding and volume reduction from paste to solder.
  • Voiding is a well known problem when solder paste is used. As the small solder particles agglomerate, trapping flux voids is a frequent effect. These voids in the solder balls can potentially weaken the mechanical strength of these solder balls in their interconnect applications.
  • volume reduction from paste to solder limits how closely certain sized cavities can be placed in an array, and this limits the upper range of solder bump sizes at a given pitch or spacing.
  • the present invention can, in at least one embodiment, provide a method for making a solder ball, which includes: providing a mold comprising at least one cavity, filling the at least one cavity with a molten solder, cooling the molten solder, and reflowing the solder to form at least one solder ball.
  • the present invention can also provide a solder ball made by the above method.
  • the present invention can, in at least one further embodiment, provide a method for forming a solder bump on a semiconductor, which includes: providing a mold comprising at least one cavity, filling the at least one cavity with a molten solder, cooling the molten solder, reflowing the solder to form at least one solder ball, aligning the at least one cavity with at least one receiving pad, heating to cause the at least one solder ball to flow from the at least one cavity to the at least one receiving pad in order to form at least one solder bump, and removing the mold.
  • the present invention can also provide a semiconductor wafer comprising a solder bump made by the above method.
  • FIG. 1A is an illustrative representation of a side view of a filled injection molder solder (IMS) mold plate having round or hemispherical cavities;
  • IMS injection molder solder
  • FIG. 1B is an illustrative representation of a top view of a filled IMS mold plate having round or hemispherical cavities
  • FIG. 2A is an illustrative representation of a side view of a filled IMS mold plate having pyramidal cavities
  • FIG. 2B is an illustrative representation of a top view of a filled IMS mold plate having pyramidal cavities
  • FIG. 3A is an illustrative representation of a side view of reflowed solder balls in an IMS mold plate having round or hemispherical cavities;
  • FIG. 3B is an illustrative representation of a top view of reflowed solder balls in an IMS mold plate having round or hemispherical cavities;
  • FIG. 5 is an illustrative representation of a side view of a silicon wafer containing wetting pads that are patterned to provide receiving pads for solder balls.
  • FIG. 6 is an illustrative representation of a side view of the wafer configuration of FIG. 5 wherein solder balls have been placed on the receiving pads.
  • FIG. 7 is an illustrative representation of a side view of the wafer configuration of FIG. 5 , wherein solder balls have been placed on the receiving pads in an oxide reducing atmosphere to enhance the solder wetting of the pads.
  • the present invention provides a method of making solder balls that can be used in semiconductor applications, particularly solder balls that can be used in bumping semiconductor wafers.
  • the solder balls can be made using an injection molding soldering (IMS) process, wherein molten solder is deposited in a mold cavity followed by reflowing the solder to produce the solder balls.
  • IMS injection molding soldering
  • solder ball refers to a ball of solder material made according to processes disclosed herein.
  • solder ball includes material in any phase, including material that is in the solid or molten state.
  • the term further includes solder material that is spherical or substantially spherical in shape.
  • the diameter of solder balls made according to processes can range from, for example, about 25 microns to about 500 microns, such as from about 50 microns to about 150 microns.
  • solder material may, for example, include Sn, and Pb, as well as alloys containing at least one of Sn and/or Pb such as, for example, SnPb, SnCu, SnAg, SnAgCu, SnCuBi, and SnAgCuBi.
  • preferred materials include for leaded solders Sn63Pb37, Pb97Sn3 and for lead-free solders SnCu0.7, SnAg3.5, SnAg3.8Cu0.7.
  • any of the above-listed materials may be present in its substantially pure form, wherein the material is essentially free of other materials such as solder paste.
  • Solder balls can be produced by using an injection molding soldering (IMS) process, which includes providing a mold plate or sheet containing one or more cavities into which a molten solder material (such one or more of the above-listed materials) is deposited.
  • IMS injection molding soldering
  • the cavities of the mold plate or sheet are filled with the molten solder material as shown, for example, in FIGS. 1A-B and 2 A-B.
  • the solder material is allowed to cool and solidify after which it is allowed to reflow to form solder balls, as shown, for example in FIGS. 3A-B and 4 A-B.
  • reflow may be accomplished in flux or other oxide reducing environment.
  • the solder balls are a higher temperature Pb97Sn3 alloy, then reflowing in hydrogen is possible, since this environment has oxide reducing properties above about 300° C.
  • the solder is an Sn63Pb37 alloy, such as standard Sn63Pb37 with a melting temp of about 183° C., or a lead-free alloy such as SnCu0.7, such as a common SnCu0.7 alloy with a melting temp of about 227° C., then liquid flux or a formic acid vapor would be appropriate environments for reflow.
  • fill and reflow can occur almost simultaneously. This can occur if the solder filling process is done in a very low oxygen environment. As soon as the constraining effect of the IMS solder fill head passes a row of filled cavities, the solder therein immediately “balls up” or becomes spherical. This occurs due to surface tension affecting the unoxidized solder.
  • cavities are not limited, examples of cavity shapes include round or hemispherical (such as is shown in FIGS. 1A-B and 3 A-B) and pyramidal (such as is shown in FIGS. 2A-B and 4 A-B).
  • the cavities can, for example, be etched into the mold plate or sheet using, for example, a precision etching process, such as an isotropic etching process.
  • the diameter of cavities can, for example, range from about 25 microns to about 500 microns, such as from about 50 microns to about 150 microns.
  • the depth to diameter aspect ratio of the cavities can, for example, range from about 1 ⁇ 4 to about 1 ⁇ 2.
  • the arrangement of cavities in a mold plate or sheet is not limited.
  • the cavities can be arranged in a manner that mirrors the arrangement of solder receiving pads on a final substrate or wafer.
  • the cavities can also be arranged in an array in which they are evenly spaced in one or more dimensions (such as a two-dimensional array of evenly spaced cavities).
  • solder balls can be formed, removed, and then rearrayed into the desired configuration.
  • the present invention can provide a method for making solder balls where they are formed in a different configuration (for example, a more densely packed configuration) than the configuration in which they are finally arrayed.
  • Materials used for the mold plate or sheet can include glass, metal, graphite, and silicon as well as polymer materials such as polyimide sheets.
  • a glass or metal mold plate or sheet may be preferred.
  • cavities are pyramidal in shape such as is shown in FIGS. 2A-B and 4 A-B
  • a silicon mold plate or sheet may be preferred, the pyramidal shape being produced by anisotropic etching in ⁇ 100> silicon wafers.
  • the temperature of the soldier material during various stages of processes falling within the scope of the present invention will, of course, depend on the specific solder material or materials used.
  • standard eutectic SnPb solder has a melting point of about 183° C.
  • a lead-free alloy such as standard SnCu has a melting point of about 227° C.
  • standard high lead PbSn3 has a melting point of about 323° C.
  • Processing temperatures are typically kept about 20° C. above the melting point for both cavity filling as well as reflow.
  • At least one embodiment falling within the scope of the present invention may overcome at least one deficiency associated with methods used in the prior art.
  • at least one embodiment of the present invention can provide solder balls having volumes that are as uniform as the individual cavities in the mold plate or sheet (where, for example, essentially pure molten material is deposited into precision etched cavities that are then solidified with a flat top as shown in FIGS. 1A-B and 2 A-B).
  • Such size distribution can be expected to be tighter that what would typically be achieved by plating or by the solder ball sieving method used with the ball drop technology.
  • solder balls made according to such embodiments can be expected to have relatively fewer voids and, as a result, may be expected to have better overall mechanical properties.
  • solder balls can be produced in which there is little volume change from molten to solid, which can result in more closely spaced arrays that produce more balls at a given volume.
  • FIG. 1 illustrates a side view ( FIG. 1A ) and a top view ( FIG. 1B ) of hemispherical cavities 12 , which are produced by a precision etching process, such as isotropic etching in a mold plate 10 such as glass or metal. Once filled with solder 14 , these are ready to be reflowed.
  • IMS injection molded solder
  • FIG. 2 illustrates a side view ( FIG. 2A ) and a top view ( FIG. 2B ) of pyramidal shaped cavities 18 , which are produced by a precision etching process in a mold plate 16 such as silicon (for example, 1-0-0 silicon). Once filled with solder 20 , these are ready for reflow.
  • a mold plate 16 such as silicon (for example, 1-0-0 silicon).
  • FIG. 3 illustrates a side view ( FIG. 3A ) and a top view ( FIG. 3B ) of solder reflowed to produce spherical solder balls 22 .
  • FIG. 3B illustrates that when hemispherical cavities 12 are etched in mold plate 10 , the solder balls 22 when reflowed may adhere to any part of the cavity side wall. Although not problematic for extracting solder balls, this potential for slight non-uniform location of reflowed balls can be eliminated by using silicon mold plates as seen in FIG. 4 .
  • FIG. 4 also illustrates a side view ( FIG. 4A ) and a top view ( FIG. 4B ) of solder reflowed to produce spherical solder balls 22 .
  • FIG. 4B the pyramidal shape of each cavity 18 etched in mold plate 16 insures that each reflowed solder ball 22 stays at the center of each cavity.
  • solder balls within individual cavities may or may not impact solder ball retrieval methods. For example, if the balls are simply globally dislodged and amassed, such location will not matter. The balls can simply be cooled and removed from the mold cavity. However, if the balls are individually retrieved, then the centered balls, as shown in FIG. 4B , will be easier to retrieve.
  • FIG. 5 illustrates a side view of a substrate 26 containing wetting pads 28 that are patterned as receiving pads for the solder balls.
  • the substrate can, for example, be selected from silicon wafers as well as organic and ceramic materials and the receiving wetting pads can, for example be selected from Cr, Cu, CrCu, Ti, TiW, N, and Au.
  • the dimensions of the substrate 26 and wetting pads 28 are also not limited and can, for example range from 1′′-12′′ round silicon wafers and 1′′ or larger square or rectangular organic or ceramic and about 25 to about 500 microns for the receiving pads, but are usually preferred in a range such as from about 6′′-12′′ round silicon wafers and about 50 to about 50 microns for the receiving pads.
  • Solder balls as formed with this method may be subsequently attached to these substrates through any of several known solder ball placement methods, such as vacuum assisted arraying fixtures.
  • FIG. 6 illustrates the wafer configuration of FIG. 5 where solder balls 22 have been placed on receiving pad locations 28 of the wafer 26 .
  • flux may or may not be required to achieve wetting of the solder ball 22 to the wetting pad.
  • a fluxing agent may be used to facilitate oxide reduction of both solder ball and wetting pad in non-gold top pad metallurgies. These may be applied by any of several well known methods such as spray, brush, etc and removed after wetting and ball attach by standard solvent means.
  • FIG. 7 illustrates solder balls that have wetted the pads to form solder bumps 24 on wafer 26 .
  • An oxide reducing atmosphere 30 such as formic acid, may be used to enhance the solder wetting of the pads (such as in situations where flux is not desired).
  • a ⁇ 100> silicon wafer was patterned with square openings in a photoresist layer and subsequently etched to produce precise, self-limiting pyramidal shaped cavities of 100 microns on an edge with a spacing between cavities of 200 microns.
  • This silicon mold plate was then scanned by an IMS (Injection Molded Solder) head, which filled the cavities with SnPb eutectic solder.
  • the solder was solidified in the cavities, the contrast of the bright metallic solder and dark silicon enhancing a manual fill inspection. Such process may be readily automated for manufacturing.
  • a thin layer of flux may be used while heating the mold plate about 20° C. above the eutectic melt point (about 183° C. for SnPb). Under such conditions, a surface tension induced change in shape of the solder from the as-molded pyramid to a sphere occurs, resulting in a full array of solder balls sit in the pyramidal cavities.

Abstract

Methods for making solder balls, which can be used to bump semiconductor wafers are disclosed. Methods for bumping semiconductor wafers with the solder balls are also disclosed. The solder balls can be made using an injection molded soldering (IMS) process.

Description

    FIELD OF THE INVENTION
  • The present invention relates to a method for making solder balls that can be used to bump semiconductor wafers. The solder balls can be made using an injection molded soldering process.
    • BACKGROUND OF THE INVENTION
  • Solder bumping of semiconductor wafers is undergoing rapid evolution. Whereas past methods of evaporation, plating and paste screening have been the historical technologies, requirements such as alloy flexibility (especially for lead-free (Pb-free) alloys) and cost reductions are driving the industry towards two emerging new technologies. Included in these technologies are ball placement and injection molded solder, otherwise known as Controlled Collapse Chip Connection New Process (C4NP). This methodology focuses on using injection molded solder for significantly improving ball placement technology.
  • In the past, solder balls have typically been produced by a “ball drop” technique, wherein molten solder is used to produce balls having a wide range of sizes. After the production of these solder balls, a separation step based on ball size is undertaken. Using solder ball sieves of various opening sizes, the balls are separated into groups with tighter size ranges. These may then be used for various bumping applications, depending on sizes required. Elimination of this sieving step is highly desirable.
  • Moreover, even when the sieving step is used, a large size range may still be present in each sieved grouping, depending on the sieving matrix employed. This can lead to unsatisfactory results because in solder bumping applications, the smallest variations in bump sizes are preferred.
  • In view of these challenges, another method that has been disclosed for producing the solder balls is to deposit solder paste into cavities in a silicon mold. This paste is later reflowed to produce solder balls. However, this methodology possesses the same drawback that results from any paste application, namely voiding and volume reduction from paste to solder.
  • Voiding is a well known problem when solder paste is used. As the small solder particles agglomerate, trapping flux voids is a frequent effect. These voids in the solder balls can potentially weaken the mechanical strength of these solder balls in their interconnect applications.
  • Secondly, the volume reduction from paste to solder limits how closely certain sized cavities can be placed in an array, and this limits the upper range of solder bump sizes at a given pitch or spacing.
    • SUMMARY OF THE INVENTION
  • The present invention can, in at least one embodiment, provide a method for making a solder ball, which includes: providing a mold comprising at least one cavity, filling the at least one cavity with a molten solder, cooling the molten solder, and reflowing the solder to form at least one solder ball. The present invention can also provide a solder ball made by the above method.
  • The present invention can, in at least one further embodiment, provide a method for forming a solder bump on a semiconductor, which includes: providing a mold comprising at least one cavity, filling the at least one cavity with a molten solder, cooling the molten solder, reflowing the solder to form at least one solder ball, aligning the at least one cavity with at least one receiving pad, heating to cause the at least one solder ball to flow from the at least one cavity to the at least one receiving pad in order to form at least one solder bump, and removing the mold. The present invention can also provide a semiconductor wafer comprising a solder bump made by the above method.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1A is an illustrative representation of a side view of a filled injection molder solder (IMS) mold plate having round or hemispherical cavities;
  • FIG. 1B is an illustrative representation of a top view of a filled IMS mold plate having round or hemispherical cavities;
  • FIG. 2A is an illustrative representation of a side view of a filled IMS mold plate having pyramidal cavities;
  • FIG. 2B is an illustrative representation of a top view of a filled IMS mold plate having pyramidal cavities;
  • FIG. 3A is an illustrative representation of a side view of reflowed solder balls in an IMS mold plate having round or hemispherical cavities;
  • FIG. 3B is an illustrative representation of a top view of reflowed solder balls in an IMS mold plate having round or hemispherical cavities;
  • FIG. 4A is an illustrative representation of a side view of reflowed solder balls in an IMS mold plate having pyramidal cavities;
  • FIG. 4B is an illustrative representation of a top view of reflowed solder balls in an IMS mold plate having pyramidal cavities;
  • FIG. 5 is an illustrative representation of a side view of a silicon wafer containing wetting pads that are patterned to provide receiving pads for solder balls.
  • FIG. 6 is an illustrative representation of a side view of the wafer configuration of FIG. 5 wherein solder balls have been placed on the receiving pads.
  • FIG. 7 is an illustrative representation of a side view of the wafer configuration of FIG. 5, wherein solder balls have been placed on the receiving pads in an oxide reducing atmosphere to enhance the solder wetting of the pads.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • The present invention, in at least one embodiment, provides a method of making solder balls that can be used in semiconductor applications, particularly solder balls that can be used in bumping semiconductor wafers. The solder balls can be made using an injection molding soldering (IMS) process, wherein molten solder is deposited in a mold cavity followed by reflowing the solder to produce the solder balls.
  • As used herein, the term “solder ball” refers to a ball of solder material made according to processes disclosed herein. The term solder ball includes material in any phase, including material that is in the solid or molten state. The term further includes solder material that is spherical or substantially spherical in shape. The diameter of solder balls made according to processes, while not limited, can range from, for example, about 25 microns to about 500 microns, such as from about 50 microns to about 150 microns.
  • Materials that can be included in solder balls (i.e., “solder material”) may, for example, include Sn, and Pb, as well as alloys containing at least one of Sn and/or Pb such as, for example, SnPb, SnCu, SnAg, SnAgCu, SnCuBi, and SnAgCuBi. Among these, preferred materials include for leaded solders Sn63Pb37, Pb97Sn3 and for lead-free solders SnCu0.7, SnAg3.5, SnAg3.8Cu0.7.
  • In at least one embodiment of the present invention, any of the above-listed materials may be present in its substantially pure form, wherein the material is essentially free of other materials such as solder paste.
  • Solder balls can be produced by using an injection molding soldering (IMS) process, which includes providing a mold plate or sheet containing one or more cavities into which a molten solder material (such one or more of the above-listed materials) is deposited. As a result of the IMS process, the cavities of the mold plate or sheet are filled with the molten solder material as shown, for example, in FIGS. 1A-B and 2A-B. After filling the cavities in the mold plate or sheet, the solder material is allowed to cool and solidify after which it is allowed to reflow to form solder balls, as shown, for example in FIGS. 3A-B and 4A-B.
  • In at least one embodiment falling within the scope of the present invention, reflow may be accomplished in flux or other oxide reducing environment. For example, if the solder balls are a higher temperature Pb97Sn3 alloy, then reflowing in hydrogen is possible, since this environment has oxide reducing properties above about 300° C. On the other hand, if the solder is an Sn63Pb37 alloy, such as standard Sn63Pb37 with a melting temp of about 183° C., or a lead-free alloy such as SnCu0.7, such as a common SnCu0.7 alloy with a melting temp of about 227° C., then liquid flux or a formic acid vapor would be appropriate environments for reflow.
  • In other embodiments, fill and reflow can occur almost simultaneously. This can occur if the solder filling process is done in a very low oxygen environment. As soon as the constraining effect of the IMS solder fill head passes a row of filled cavities, the solder therein immediately “balls up” or becomes spherical. This occurs due to surface tension affecting the unoxidized solder.
  • While the shape of the cavities is not limited, examples of cavity shapes include round or hemispherical (such as is shown in FIGS. 1A-B and 3A-B) and pyramidal (such as is shown in FIGS. 2A-B and 4A-B). The cavities can, for example, be etched into the mold plate or sheet using, for example, a precision etching process, such as an isotropic etching process. While not limited, the diameter of cavities can, for example, range from about 25 microns to about 500 microns, such as from about 50 microns to about 150 microns. Depending on the process used to make the cavities, the depth to diameter aspect ratio of the cavities can, for example, range from about ¼ to about ½.
  • The arrangement of cavities in a mold plate or sheet is not limited. For example, the cavities can be arranged in a manner that mirrors the arrangement of solder receiving pads on a final substrate or wafer. The cavities can also be arranged in an array in which they are evenly spaced in one or more dimensions (such as a two-dimensional array of evenly spaced cavities). Moreover, in at least one embodiment falling within the scope of the present invention, solder balls can be formed, removed, and then rearrayed into the desired configuration. Thus, the present invention can provide a method for making solder balls where they are formed in a different configuration (for example, a more densely packed configuration) than the configuration in which they are finally arrayed.
  • Materials used for the mold plate or sheet, while not limited, can include glass, metal, graphite, and silicon as well as polymer materials such as polyimide sheets. For example, when cavities are round or hemispherical in shape (such as is shown in FIGS. 1A-B and 3A-B), a glass or metal mold plate or sheet may be preferred. When cavities are pyramidal in shape (such as is shown in FIGS. 2A-B and 4A-B), a silicon mold plate or sheet may be preferred, the pyramidal shape being produced by anisotropic etching in <100> silicon wafers.
  • The temperature of the soldier material during various stages of processes falling within the scope of the present invention will, of course, depend on the specific solder material or materials used. For example, standard eutectic SnPb solder has a melting point of about 183° C., a lead-free alloy such as standard SnCu has a melting point of about 227° C., and standard high lead PbSn3 has a melting point of about 323° C. Processing temperatures are typically kept about 20° C. above the melting point for both cavity filling as well as reflow.
  • At least one embodiment falling within the scope of the present invention may overcome at least one deficiency associated with methods used in the prior art. For example, at least one embodiment of the present invention can provide solder balls having volumes that are as uniform as the individual cavities in the mold plate or sheet (where, for example, essentially pure molten material is deposited into precision etched cavities that are then solidified with a flat top as shown in FIGS. 1A-B and 2A-B). Such size distribution can be expected to be tighter that what would typically be achieved by plating or by the solder ball sieving method used with the ball drop technology.
  • In addition, since embodiments of the invention can be practiced without the use of solder paste, solder balls made according to such embodiments can be expected to have relatively fewer voids and, as a result, may be expected to have better overall mechanical properties. In addition, since essentially pure molten solder can be used, solder balls can be produced in which there is little volume change from molten to solid, which can result in more closely spaced arrays that produce more balls at a given volume.
  • Various aspects falling within the scope of the invention will now be further described with reference to the figures.
  • An injection molded solder (IMS) method is used to fill cavities in a mold plate or sheet. FIG. 1 illustrates a side view (FIG. 1A) and a top view (FIG. 1B) of hemispherical cavities 12, which are produced by a precision etching process, such as isotropic etching in a mold plate 10 such as glass or metal. Once filled with solder 14, these are ready to be reflowed.
  • FIG. 2 illustrates a side view (FIG. 2A) and a top view (FIG. 2B) of pyramidal shaped cavities 18, which are produced by a precision etching process in a mold plate 16 such as silicon (for example, 1-0-0 silicon). Once filled with solder 20, these are ready for reflow.
  • FIG. 3 illustrates a side view (FIG. 3A) and a top view (FIG. 3B) of solder reflowed to produce spherical solder balls 22. FIG. 3B illustrates that when hemispherical cavities 12 are etched in mold plate 10, the solder balls 22 when reflowed may adhere to any part of the cavity side wall. Although not problematic for extracting solder balls, this potential for slight non-uniform location of reflowed balls can be eliminated by using silicon mold plates as seen in FIG. 4.
  • FIG. 4 also illustrates a side view (FIG. 4A) and a top view (FIG. 4B) of solder reflowed to produce spherical solder balls 22. Here, as shown in FIG. 4B, the pyramidal shape of each cavity 18 etched in mold plate 16 insures that each reflowed solder ball 22 stays at the center of each cavity.
  • The location of solder balls within individual cavities may or may not impact solder ball retrieval methods. For example, if the balls are simply globally dislodged and amassed, such location will not matter. The balls can simply be cooled and removed from the mold cavity. However, if the balls are individually retrieved, then the centered balls, as shown in FIG. 4B, will be easier to retrieve.
  • FIG. 5 illustrates a side view of a substrate 26 containing wetting pads 28 that are patterned as receiving pads for the solder balls. While not limited to any specific materials, the substrate can, for example, be selected from silicon wafers as well as organic and ceramic materials and the receiving wetting pads can, for example be selected from Cr, Cu, CrCu, Ti, TiW, N, and Au. The dimensions of the substrate 26 and wetting pads 28 are also not limited and can, for example range from 1″-12″ round silicon wafers and 1″ or larger square or rectangular organic or ceramic and about 25 to about 500 microns for the receiving pads, but are usually preferred in a range such as from about 6″-12″ round silicon wafers and about 50 to about 50 microns for the receiving pads. Solder balls as formed with this method may be subsequently attached to these substrates through any of several known solder ball placement methods, such as vacuum assisted arraying fixtures.
  • FIG. 6 illustrates the wafer configuration of FIG. 5 where solder balls 22 have been placed on receiving pad locations 28 of the wafer 26. Depending on the transfer scheme, flux may or may not be required to achieve wetting of the solder ball 22 to the wetting pad. For many applications, a fluxing agent may be used to facilitate oxide reduction of both solder ball and wetting pad in non-gold top pad metallurgies. These may be applied by any of several well known methods such as spray, brush, etc and removed after wetting and ball attach by standard solvent means.
  • FIG. 7 illustrates solder balls that have wetted the pads to form solder bumps 24 on wafer 26. An oxide reducing atmosphere 30, such as formic acid, may be used to enhance the solder wetting of the pads (such as in situations where flux is not desired).
    • EXAMPLES
  • An example of an injection molded solder ball method can be described as follows:
  • A <100> silicon wafer was patterned with square openings in a photoresist layer and subsequently etched to produce precise, self-limiting pyramidal shaped cavities of 100 microns on an edge with a spacing between cavities of 200 microns. This silicon mold plate was then scanned by an IMS (Injection Molded Solder) head, which filled the cavities with SnPb eutectic solder.
  • In the example, the solder was solidified in the cavities, the contrast of the bright metallic solder and dark silicon enhancing a manual fill inspection. Such process may be readily automated for manufacturing.
  • To enable efficient “ball-up” of the solder in the cavities, a thin layer of flux may be used while heating the mold plate about 20° C. above the eutectic melt point (about 183° C. for SnPb). Under such conditions, a surface tension induced change in shape of the solder from the as-molded pyramid to a sphere occurs, resulting in a full array of solder balls sit in the pyramidal cavities.
  • While the present invention has been described in an illustrative manner, it should be understood that the terminology used is intended to be in a nature of words or description rather than of limitation. Furthermore, while the present invention has been described in terms of several illustrative embodiments, it is to be appreciated that those skilled in the art will readily apply these teachings to other possible variations of the inventions.

Claims (20)

1. A method for making a solder ball comprising:
providing a mold comprising at least one cavity;
filling said at least one cavity with a molten solder;
cooling the molten solder; and
reflowing the solder to form at least one solder ball.
2. The method of claim 1, wherein the molten solder comprises at least one material selected from the group consisting of Sn, Pb, SnPb, SnCu, SnAg, SnBi, SnAgCu, and SnAgCuBi.
3. The method of claim 1, wherein the mold comprises at least one material selected from the group consisting of glass, silicon, metal, graphite, and polyimide.
4. The method of claim 1, wherein the shape of the cavities are selected from hemispherical and pyramidal.
5. The method of claim 1, wherein the diameter of the cavity ranges from about 25 microns to about 500 microns.
6. The method of claim 1, wherein the diameter of the solder ball ranges from about 25 microns to about 500 microns.
7. The method of claim 1, further comprising the steps of:
cooling the at least one solder ball; and
removing the at least one solder ball from the at least one cavity.
8. A method for forming a solder bump on a semiconductor wafer comprising:
providing a mold comprising at least one cavity;
filling said at least one cavity with a molten solder;
cooling the molten solder;
reflowing the solder to form at least one solder ball;
aligning the at least one cavity with at least one receiving pad;
heating to cause the at least one solder ball to flow from the at least one cavity to the at least one receiving pad in order to form at least one solder bump; and
removing the mold.
9. The method of claim 8, wherein the molten solder comprises at least one material selected from the group consisting of Sn, Pb, SnPb, SnCu, SnAg, SnBi, SnAgCu, and SnAgCuBi.
10. The method of claim 8, wherein the mold comprises at least one material selected from the group consisting of the group consisting of glass, silicon, metal, graphite, and polyimide.
11. The method of claim 8, wherein the shape of the cavities are selected from hemispherical and pyramidal.
12. The method of claim 8, wherein the diameter of the cavity ranges from about 25 microns to about 500 microns.
13. The method of claim 8, wherein the diameter of the solder ball ranges from about 25 microns to about 500 microns.
14. The method of claim 8, wherein the semiconductor wafer comprises <100> silicon.
15. The method of claim 8, wherein the at least one receiving pad comprises at least one material selected from the group consisting of Cr, Cu, CrCu, Ti, TiW, N, and Au.
16. The method of claim 8, wherein the step of heating to cause the at least one solder ball to flow from the at least one cavity to the at least one receiving pad in order to form at least one solder bump is conducted in an oxide reducing atmosphere.
17. The method of claim 15, wherein the oxide reducing atmosphere comprises formic acid.
18. A solder ball made by a method comprising:
providing a mold comprising at least one cavity;
filling said at least one cavity with a molten solder;
cooling the molten solder; and
reflowing the solder to form at least one solder ball.
19. The solder ball of claim 18, wherein the solder ball comprises at least one material selected from the group consisting of Sn, Pb, SnPb, SnCu, SnAg, SnBi, SnAgCu, and SnAgCuBi.
20. A semiconductor wafer comprising a solder bump made by a method comprising:
providing a mold comprising at least one cavity;
filling said at least one cavity with a molten solder;
cooling the molten solder;
reflowing the solder to form at least one solder ball;
aligning the at least one cavity with at least one receiving pad;
heating to cause the at least one solder ball to flow from the at least one cavity to the at least one receiving pad in order to form at least one solder bump; and
removing the mold.
US11/620,900 2007-01-08 2007-01-08 Injection molded solder ball method Abandoned US20080164609A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US11/620,900 US20080164609A1 (en) 2007-01-08 2007-01-08 Injection molded solder ball method
US12/543,811 US7955966B2 (en) 2007-01-08 2009-08-19 Injection molded solder ball method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/620,900 US20080164609A1 (en) 2007-01-08 2007-01-08 Injection molded solder ball method

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/543,811 Division US7955966B2 (en) 2007-01-08 2009-08-19 Injection molded solder ball method

Publications (1)

Publication Number Publication Date
US20080164609A1 true US20080164609A1 (en) 2008-07-10

Family

ID=39593564

Family Applications (2)

Application Number Title Priority Date Filing Date
US11/620,900 Abandoned US20080164609A1 (en) 2007-01-08 2007-01-08 Injection molded solder ball method
US12/543,811 Expired - Fee Related US7955966B2 (en) 2007-01-08 2009-08-19 Injection molded solder ball method

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/543,811 Expired - Fee Related US7955966B2 (en) 2007-01-08 2009-08-19 Injection molded solder ball method

Country Status (1)

Country Link
US (2) US20080164609A1 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8162203B1 (en) 2011-02-18 2012-04-24 International Business Machines Corporation Spherical solder reflow method
US8408448B1 (en) 2012-02-11 2013-04-02 International Business Machines Corporation Forming constant diameter spherical metal balls
US8523046B1 (en) 2012-10-18 2013-09-03 International Business Machines Corporation Forming an array of metal balls or shapes on a substrate
US8561880B2 (en) 2012-02-11 2013-10-22 International Business Machines Corporation Forming metal preforms and metal balls
US8703274B2 (en) 2008-10-02 2014-04-22 International Business Machines Corporation Microcavity structure and process
US8875978B2 (en) 2012-02-11 2014-11-04 International Business Machines Corporation Forming constant diameter spherical metal balls

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5262045B2 (en) * 2007-09-27 2013-08-14 富士通セミコンダクター株式会社 Electrode forming method and semiconductor device manufacturing method
KR101566921B1 (en) * 2009-01-05 2015-11-09 삼성전자주식회사 Manufacturing method of a charge trap type non-volatile memory device
KR101881063B1 (en) * 2011-12-12 2018-07-25 삼성전자주식회사 Manufacturing method of bump

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6090301A (en) * 1996-12-02 2000-07-18 Fujitsu Limited Method for fabricating bump forming plate member
US20060035454A1 (en) * 2004-08-16 2006-02-16 Ibm Corporation Fluxless solder transfer and reflow process

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6090301A (en) * 1996-12-02 2000-07-18 Fujitsu Limited Method for fabricating bump forming plate member
US20060035454A1 (en) * 2004-08-16 2006-02-16 Ibm Corporation Fluxless solder transfer and reflow process

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8703274B2 (en) 2008-10-02 2014-04-22 International Business Machines Corporation Microcavity structure and process
US8162203B1 (en) 2011-02-18 2012-04-24 International Business Machines Corporation Spherical solder reflow method
US8342387B2 (en) 2011-02-18 2013-01-01 International Business Machines Corporation Spherical solder reflow method
US8408448B1 (en) 2012-02-11 2013-04-02 International Business Machines Corporation Forming constant diameter spherical metal balls
US8561880B2 (en) 2012-02-11 2013-10-22 International Business Machines Corporation Forming metal preforms and metal balls
US8875978B2 (en) 2012-02-11 2014-11-04 International Business Machines Corporation Forming constant diameter spherical metal balls
US8944306B2 (en) 2012-02-11 2015-02-03 International Business Machines Corporation Forming metal preforms and metal balls
US8523046B1 (en) 2012-10-18 2013-09-03 International Business Machines Corporation Forming an array of metal balls or shapes on a substrate
US8833636B2 (en) 2012-10-18 2014-09-16 International Business Machines Corporation Forming an array of metal balls or shapes on a substrate

Also Published As

Publication number Publication date
US7955966B2 (en) 2011-06-07
US20090309219A1 (en) 2009-12-17

Similar Documents

Publication Publication Date Title
US7955966B2 (en) Injection molded solder ball method
Li et al. Characteristics of intermetallics and micromechanical properties during thermal ageing of Sn–Ag–Cu flip-chip solder interconnects
US8342387B2 (en) Spherical solder reflow method
EP1796156B1 (en) Flip chip mounting method
US6683375B2 (en) Semiconductor die including conductive columns
US9343423B2 (en) No flow underfill or wafer level underfill and solder columns
US7473580B2 (en) Temporary chip attach using injection molded solder
EP1796155A1 (en) Bump forming method and solder bump
TWI304006B (en) Tin/indium lead-free solders for low stress chip attachment
US7833897B2 (en) Process for making interconnect solder Pb-free bumps free from organo-tin/tin deposits on the wafer surface
US9978709B2 (en) Solder bump stretching method for forming a solder bump joint in a device
US6319810B1 (en) Method for forming solder bumps
US7703661B2 (en) Method and process for reducing undercooling in a lead-free tin-rich solder alloy
Gruber et al. Injection molded solder technology for Pb-free wafer bumping
US10163835B2 (en) Solder bump stretching method
TW200845251A (en) Bump structure for semiconductor device
Kang et al. Flip-chip interconnections: past, present, and future
Kang et al. An overview of Pb-free, flip-chip wafer-bumping technologies
Zakel et al. High speed laser solder jetting technology for optoelectronics and MEMS packaging
KR100863772B1 (en) Fabrication method of solder ball using a mold with cavity
WO2009130442A1 (en) Method of applying a bump to a substrate
Lim et al. Reliability performance of stretch solder interconnections
Lin et al. Low-cost and fine-pitch micro-ball mounting technology for WLCSP
Vähänen et al. Low-cost bump bonding activities at CERN
Sha et al. 15μm Silver flip-chip technology with solid-state bonding

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GRUBER, PETER A.;HOCHLOWSKI, BARRY A.;NAUGLE, DAVID T.;REEL/FRAME:021343/0717;SIGNING DATES FROM 20061006 TO 20061011

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION