US20080160690A1 - Flash memory device and method for fabricating the same - Google Patents
Flash memory device and method for fabricating the same Download PDFInfo
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- US20080160690A1 US20080160690A1 US12/071,946 US7194608A US2008160690A1 US 20080160690 A1 US20080160690 A1 US 20080160690A1 US 7194608 A US7194608 A US 7194608A US 2008160690 A1 US2008160690 A1 US 2008160690A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
- H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Definitions
- the present invention relates to semiconductor technologies, and more specifically, to a nonvolatile flash memory device and manufacturing method for the same.
- Flash memory which is capable of retaining the stored data without continued supply of electrical power, has a stacked gate structure of a floating gate and a control gate.
- the floating gate which is placed between the control gate and the semiconductor substrate, is isolated by an insulating oxide layer.
- electrons When electrons are on the floating gate, they modify the electric field coming from the control gate, which modifies the threshold voltage of the cell.
- electrical current will either flow or not flow, depending on the threshold voltage of the cell, which is controlled by the electrons on the floating gate. The presence or absence of current is sensed and translated into 1's and 0's, reproducing the stored data.
- the flash memory device is classified, according to its cell structure, into two classifications: NOR flash and NAND flash.
- the NAND flash has higher integration and is suitable for use in electronic devices requiring high storage capacity.
- the NOR flash memory allows higher speed and random access to the memory cells but it requires a space for the each of memory cells being interconnected to bit line and has relatively low integrity.
- the source regions of NOR memory cells are electrically interconnected in parallel to a word line to form a common source line. With the common source line, a plurality of memory cells have one common contact point, and thus the integrity of a NOR memory cell array can be improved by decreasing the intervals between common contact points.
- FIG. 1A is a plan view of the conventional flash memory device and FIGS. 1B to 1D are cross sectional views of FIG. 1A taken along the lines I-I, II-II and III-III, respectively.
- the conventional flash memory device has an isolation layer 12 for defining active regions in a semiconductor substrate 10 , and a plurality of word lines 22 crossing the active regions and the isolation layer 12 .
- a stacked structure 22 a of a tunnel oxide layer 14 , a floating gate 16 , a dielectric layer 18 and a control gate 20 is formed under the word line 22 .
- spacers 24 are formed at the sidewalls of the gate stack 22 a .
- source region 26 and drain region 23 are formed.
- the source region 26 is formed by removing insulating material in the isolation layer 12 and then implanting dopants into the substrate at the isolation layer so that source regions of a plurality of memory cells are interconnected by the source line
- an inclined ion implantation method is used for ensuring the uniform implantation of dopants.
- the dopants may be injected into the gate stack 22 a , which may degrade the device characteristics.
- parts of the active region may be recessed during the removal of insulating material in the isolation layer, which may cause accumulated stress at the substrate and an increase of leakage current due to defects in channel regions that neighbor the source line 26 .
- embodiments of the present invention are directed to a flash memory device comprising: an isolation layer for defining active regions in a semiconductor substrate, the active region being a region in which flash memory cells are to be formed; a gate stack formed to come across the active region and the isolation layer; a sidewall spacer formed at sidewalls of the gate stack; a common source line for electrically interconnecting a plurality of sources of a plurality of the flash memory cells, the common source line being formed in the isolation layer by removing an insulating material in the isolation layer and formed in parallel to a word line formed over the gate stack; and a silicide layer formed in the common source line.
- embodiments of the present invention are directed to a method for manufacturing a flash memory device, comprising the steps of: forming an isolation layer for defining active regions in a semiconductor substrate, the active region being a region in which flash memory cells are to be formed; forming a gate stack that comes across the active region and the isolation layer; forming source and drain regions at both sides of the gate stack; removing insulating material in the isolation layer that is near to the source regions to form a common source line which is parallel to a word line formed over the gate stack; and forming a silicide layer in the common source line.
- the step of forming the common source line comprises the steps of: depositing a conformal spacer insulating material on the entire surface of the semiconductor substrate; recessing the deposited spacer insulating material on the source regions; and selectively etching the spacer insulating material to form sidewall spacers at sidewalls of the gate stack.
- the spacer insulating material formed by silicon nitride, has an etch selectivity to the isolation layer and the step of removing the insulating material in the isolation layer is carried out with reference to the sidewall spacers.
- FIG. 1A is a plan view of the conventional flash memory device and FIGS. 1B to 1D are cross sectional views of FIG. 1A taken along the lines I-I, II-II and III-III, respectively, depicted in FIG. 1A .
- FIG. 2A is a plan view of a flash memory device according to the present invention and FIGS. 2B to 2D are cross sectional views of FIG. 2A taken along the lines I-I, II-II and III-III, respectively, depicted in FIG. 2A .
- FIG. 3A is a plan view for illustrating a first stage of a method of fabricating a flash memory device according to an embodiment of the present invention
- FIGS. 3B to 3 D are cross sectional views of FIG. 3A taken along the lines I-I, II-II and III-III, respectively, depicted in FIG. 3A .
- FIG. 4A is a plan view for illustrating a second stage of method of fabricating a flash memory device according to the embodiment of the present invention and FIGS. 4B to 4D are cross sectional views of FIG. 4A taken along the lines I-I, II-II and III-III, respectively, depicted in FIG. 4A .
- FIG. 5A is a plan view for illustrating a third stage of a method of fabricating a flash memory device according to the embodiment of the present invention and FIGS. 5B to 5D are cross sectional views of FIG. 5A taken along the lines I-I, II-II and III-III, respectively, depicted in FIG. 5A .
- FIG. 6A is a plan view for illustrating a fourth stage of a method of fabricating a flash memory device according to the embodiment of the present invention
- FIGS. 6B to 6D are cross sectional views of FIG. 6A taken along the lines I-I, II-II and III-III, respectively, depicted in FIG. 6A .
- FIG. 7A is a plan view for illustrating a fifth stage of a method of fabricating a flash memory device according to the embodiment of the present invention and FIGS. 7B to 7D are cross sectional views of FIG. 7A taken along the lines I-I, II-II and III-III, respectively, depicted in FIG. 7A .
- FIG. 2A is a plan view of a flash memory device according to the present invention and FIGS. 2B to 2D are cross sectional views of FIG. 2A taken along the lines I-I, II-II and III-III, respectively.
- a flash memory device of the present invention includes active regions separated by isolation layers 52 and a plurality of word lines 62 crossing the active regions and isolation layers 52 .
- a stacked structure 62 a of a tunnel oxide layer 54 , a floating gate 56 , a dielectric layer 58 and a control gate 60 is formed under the word line 62 .
- source region 63 s and drain region 63 d are formed at both sides of the word line 62 .
- the isolation layer 52 is disconnected by the source region 63 s .
- the flash memory cell has a silicide layer 66 disposed in parallel with the word line 62 .
- the silicide layer 62 constitutes a common source line for a plurality of memory cells by interconnecting the source lines of the memory cells.
- a spacer 64 s is formed at the side walls of the stacked structure 62 a .
- the spacer 64 s has a thinner portion that is closer to the source region 63 s , and thus it is possible to reduce the electrical resistance of silicide layer 66 formed in the substrate and aligned with reference to the spacer 64 s .
- the source region 63 s has lower recess than the drain region 63 d , which has sidewall spacers 64 d on both sides thereof.
- the recess region of the source region 63 s is aligned with reference to the sidewall spacer 64 s and apart from the stacked structure 62 a , and therefore even when the recess region has defects, the leakage current from the edge portion of cell transistor can be prevented.
- FIGS. 3A to 7A are plan views for illustrating methods for fabricating a flash memory device according to an embodiment of the present invention
- FIGS. 3B to 7B , 3 C to 7 C and 3 D to 7 D are cross sectional views of FIGS. 3A to 7A taken along the lines I-I, II-II and III-III, respectively.
- isolation layers 52 are formed on a semiconductor substrate 50 to define active regions in which flash memory cells are to be formed, and then gate stack 62 a is formed.
- the gate stack 62 a is comprised of tunnel oxide layer 54 , floating gate 56 , dielectric layer 58 and control gate 60 .
- the floating gate 56 is formed on the active region and the control gate 60 comes across the active region and the isolation layer.
- a source region 63 s and a drain region 63 d are formed at both sides of the word line 62 .
- an insulating material 64 is deposited on the entire surface of the substrate.
- the insulating material 64 has an etch selectivity to the isolation layer 52 and can be formed by, e.g., silicon nitride.
- the insulating material 64 is for forming a spacer and is formed conformal.
- a first photoresist 65 is deposited on the spacer insulating material 64 .
- the first photoresist 65 is patterned to have open regions on the source region 63 s .
- the open regions of the first photoresist 65 are formed in parallel to the word line 62 to make parts of the deposited insulating material 64 to be exposed.
- the boundary of the open region has to overlap the word line in order to assure the alignment margin of the photolithographic process.
- the spacer insulating material 64 is selectively recessed with using the first photoresist layer 65 as an etch mask.
- the depth of the recess can be adjusted in consideration of the thickness of sidewall spacers that is to be formed at sidewalls of the gate stack.
- the first photoresist layer 65 is removed, and the insulating material 64 is anisotropically etched to form the sidewall spacers on the sidewalls of the gate stack.
- the sidewall spacers 64 s which are adjacent to the source region 63 s , are smaller in thickness than the sidewall spacers 64 d , which are adjacent to the drain region 63 d.
- a second photoresist layer 65 (not shown in FIGS. 7A to 7D , but see FIGS. 4A to 4D and 5 A to 5 D) that has the same opening structure as the first photoresist layer is formed, and insulating material of the isolation layer 52 is removed using the second photoresist pattern layer 65 as an etch mask to open the substrate in the isolation layer 52 .
- the removal of the insulating material of the isolation layer 52 is carried out with reference to the sidewall spacers 64 s .
- the active regions having an etching selectivity are not etched during the etching of the isolation layer 52 , while portion of the substrate where the source region 63 s is formed can be recessed.
- the insulating material of the isolation layer is removed after the formation of the sidewall spacers, the recessed portions of the active region are distant from the gate stack 62 a . Therefore, leakage current in the edge portions of the channel does not occur with the present invention.
- the second photoresist is removed and a silicide layer is formed on the source region 63 s , drain region 63 d and control gate by using a conventional silicidation process.
Abstract
A flash memory device including an isolation layer for defining active regions in a semiconductor substrate. The active region is a region in which flash memory cells are to be formed. The device also includes a gate stack is formed to come across the active region and the isolation layer, and a sidewall spacer is formed at sidewalls of the gate stack. The device further includes a common source line that electrically interconnects a plurality of sources of a plurality of the flash memory cells, and is formed in the isolation layer by removing an insulating material in the isolation layer and is formed in parallel to a word line formed over the gate stack. A silicide layer is formed in the common source line.
Description
- This application is a divisional of U.S. Ser. No. 11/320,862, filed on Dec. 30, 2005. This application, in its entirety, is incorporated herein by reference.
- This application claims priority to and the benefit of Korean Patent Application No. 10-2005-0066419 filed in the Korean Intellectual Property Office on Jul. 21, 2005, the entire contents of which are incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates to semiconductor technologies, and more specifically, to a nonvolatile flash memory device and manufacturing method for the same.
- 2. Description of the Related Art
- Flash memory, which is capable of retaining the stored data without continued supply of electrical power, has a stacked gate structure of a floating gate and a control gate. The floating gate, which is placed between the control gate and the semiconductor substrate, is isolated by an insulating oxide layer. When electrons are on the floating gate, they modify the electric field coming from the control gate, which modifies the threshold voltage of the cell. Thus, when the flash memory cell is “read” by applying a specific voltage to the control gate, electrical current will either flow or not flow, depending on the threshold voltage of the cell, which is controlled by the electrons on the floating gate. The presence or absence of current is sensed and translated into 1's and 0's, reproducing the stored data. The flash memory device is classified, according to its cell structure, into two classifications: NOR flash and NAND flash. The NAND flash has higher integration and is suitable for use in electronic devices requiring high storage capacity. The NOR flash memory allows higher speed and random access to the memory cells but it requires a space for the each of memory cells being interconnected to bit line and has relatively low integrity. For increasing the integrity of a cell array, the source regions of NOR memory cells are electrically interconnected in parallel to a word line to form a common source line. With the common source line, a plurality of memory cells have one common contact point, and thus the integrity of a NOR memory cell array can be improved by decreasing the intervals between common contact points.
-
FIG. 1A is a plan view of the conventional flash memory device andFIGS. 1B to 1D are cross sectional views ofFIG. 1A taken along the lines I-I, II-II and III-III, respectively. - Referring to
FIGS. 1A to 1D , the conventional flash memory device has anisolation layer 12 for defining active regions in asemiconductor substrate 10, and a plurality ofword lines 22 crossing the active regions and theisolation layer 12. Under theword line 22, astacked structure 22 a of a tunnel oxide layer 14, afloating gate 16, adielectric layer 18 and acontrol gate 20 is formed. At the sidewalls of the gate stack 22 a,spacers 24 are formed. At both sides of theword line 22,source region 26 and drainregion 23 are formed. Thesource region 26 is formed by removing insulating material in theisolation layer 12 and then implanting dopants into the substrate at the isolation layer so that source regions of a plurality of memory cells are interconnected by the source line - In the formation of the
source line 26, an inclined ion implantation method is used for ensuring the uniform implantation of dopants. In this process, the dopants may be injected into thegate stack 22 a, which may degrade the device characteristics. Furthermore, parts of the active region may be recessed during the removal of insulating material in the isolation layer, which may cause accumulated stress at the substrate and an increase of leakage current due to defects in channel regions that neighbor thesource line 26. - It is an object of the present invention to prevent the problems of conventional flash memory devices that can occur during the formation of a common source line.
- In a first aspect, embodiments of the present invention are directed to a flash memory device comprising: an isolation layer for defining active regions in a semiconductor substrate, the active region being a region in which flash memory cells are to be formed; a gate stack formed to come across the active region and the isolation layer; a sidewall spacer formed at sidewalls of the gate stack; a common source line for electrically interconnecting a plurality of sources of a plurality of the flash memory cells, the common source line being formed in the isolation layer by removing an insulating material in the isolation layer and formed in parallel to a word line formed over the gate stack; and a silicide layer formed in the common source line.
- In a second aspect, embodiments of the present invention are directed to a method for manufacturing a flash memory device, comprising the steps of: forming an isolation layer for defining active regions in a semiconductor substrate, the active region being a region in which flash memory cells are to be formed; forming a gate stack that comes across the active region and the isolation layer; forming source and drain regions at both sides of the gate stack; removing insulating material in the isolation layer that is near to the source regions to form a common source line which is parallel to a word line formed over the gate stack; and forming a silicide layer in the common source line. The step of forming the common source line comprises the steps of: depositing a conformal spacer insulating material on the entire surface of the semiconductor substrate; recessing the deposited spacer insulating material on the source regions; and selectively etching the spacer insulating material to form sidewall spacers at sidewalls of the gate stack. The spacer insulating material, formed by silicon nitride, has an etch selectivity to the isolation layer and the step of removing the insulating material in the isolation layer is carried out with reference to the sidewall spacers.
- These and other aspects of embodiments of the invention will become evident by reference to the following description of embodiments, often referring to the accompanying drawings.
-
FIG. 1A is a plan view of the conventional flash memory device andFIGS. 1B to 1D are cross sectional views ofFIG. 1A taken along the lines I-I, II-II and III-III, respectively, depicted inFIG. 1A . -
FIG. 2A is a plan view of a flash memory device according to the present invention andFIGS. 2B to 2D are cross sectional views ofFIG. 2A taken along the lines I-I, II-II and III-III, respectively, depicted inFIG. 2A . -
FIG. 3A is a plan view for illustrating a first stage of a method of fabricating a flash memory device according to an embodiment of the present invention andFIGS. 3B to 3D are cross sectional views ofFIG. 3A taken along the lines I-I, II-II and III-III, respectively, depicted inFIG. 3A . -
FIG. 4A is a plan view for illustrating a second stage of method of fabricating a flash memory device according to the embodiment of the present invention andFIGS. 4B to 4D are cross sectional views ofFIG. 4A taken along the lines I-I, II-II and III-III, respectively, depicted inFIG. 4A . -
FIG. 5A is a plan view for illustrating a third stage of a method of fabricating a flash memory device according to the embodiment of the present invention andFIGS. 5B to 5D are cross sectional views ofFIG. 5A taken along the lines I-I, II-II and III-III, respectively, depicted inFIG. 5A . -
FIG. 6A is a plan view for illustrating a fourth stage of a method of fabricating a flash memory device according to the embodiment of the present invention andFIGS. 6B to 6D are cross sectional views ofFIG. 6A taken along the lines I-I, II-II and III-III, respectively, depicted inFIG. 6A . -
FIG. 7A is a plan view for illustrating a fifth stage of a method of fabricating a flash memory device according to the embodiment of the present invention andFIGS. 7B to 7D are cross sectional views ofFIG. 7A taken along the lines I-I, II-II and III-III, respectively, depicted inFIG. 7A . - Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
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FIG. 2A is a plan view of a flash memory device according to the present invention andFIGS. 2B to 2D are cross sectional views ofFIG. 2A taken along the lines I-I, II-II and III-III, respectively. - Referring to
FIGS. 2A to 2D , a flash memory device of the present invention includes active regions separated byisolation layers 52 and a plurality ofword lines 62 crossing the active regions and isolation layers 52. Under theword line 62, astacked structure 62 a of atunnel oxide layer 54, a floatinggate 56, adielectric layer 58 and acontrol gate 60 is formed. At both sides of theword line 62,source region 63 s and drainregion 63 d are formed. Theisolation layer 52 is disconnected by thesource region 63 s. The flash memory cell has asilicide layer 66 disposed in parallel with theword line 62. Thesilicide layer 62 constitutes a common source line for a plurality of memory cells by interconnecting the source lines of the memory cells. - At the side walls of the stacked
structure 62 a, aspacer 64 s is formed. Thespacer 64 s has a thinner portion that is closer to thesource region 63 s, and thus it is possible to reduce the electrical resistance ofsilicide layer 66 formed in the substrate and aligned with reference to thespacer 64 s. Thesource region 63 s has lower recess than thedrain region 63 d, which hassidewall spacers 64 d on both sides thereof. The recess region of thesource region 63 s is aligned with reference to thesidewall spacer 64 s and apart from the stackedstructure 62 a, and therefore even when the recess region has defects, the leakage current from the edge portion of cell transistor can be prevented. -
FIGS. 3A to 7A are plan views for illustrating methods for fabricating a flash memory device according to an embodiment of the present invention, andFIGS. 3B to 7B , 3C to 7C and 3D to 7D are cross sectional views ofFIGS. 3A to 7A taken along the lines I-I, II-II and III-III, respectively. - Referring to
FIGS. 3A to 3D , isolation layers 52 are formed on asemiconductor substrate 50 to define active regions in which flash memory cells are to be formed, and then gate stack 62 a is formed. The gate stack 62 a is comprised oftunnel oxide layer 54, floatinggate 56,dielectric layer 58 andcontrol gate 60. The floatinggate 56 is formed on the active region and thecontrol gate 60 comes across the active region and the isolation layer. - A
source region 63 s and adrain region 63 d are formed at both sides of theword line 62. - Referring to
FIGS. 4A to 4D , an insulatingmaterial 64 is deposited on the entire surface of the substrate. The insulatingmaterial 64 has an etch selectivity to theisolation layer 52 and can be formed by, e.g., silicon nitride. The insulatingmaterial 64 is for forming a spacer and is formed conformal. Next, afirst photoresist 65 is deposited on thespacer insulating material 64. Thefirst photoresist 65 is patterned to have open regions on thesource region 63 s. The open regions of thefirst photoresist 65 are formed in parallel to theword line 62 to make parts of the deposited insulatingmaterial 64 to be exposed. The boundary of the open region has to overlap the word line in order to assure the alignment margin of the photolithographic process. - Referring to
FIGS. 5A to 5D , thespacer insulating material 64 is selectively recessed with using thefirst photoresist layer 65 as an etch mask. The depth of the recess can be adjusted in consideration of the thickness of sidewall spacers that is to be formed at sidewalls of the gate stack. - Referring to
FIGS. 6A to 6D , thefirst photoresist layer 65 is removed, and the insulatingmaterial 64 is anisotropically etched to form the sidewall spacers on the sidewalls of the gate stack. The sidewall spacers 64 s, which are adjacent to thesource region 63 s, are smaller in thickness than thesidewall spacers 64 d, which are adjacent to thedrain region 63 d. - Referring to
FIGS. 7A to 7D , a second photoresist layer 65 (not shown inFIGS. 7A to 7D , but seeFIGS. 4A to 4D and 5A to 5D) that has the same opening structure as the first photoresist layer is formed, and insulating material of theisolation layer 52 is removed using the secondphotoresist pattern layer 65 as an etch mask to open the substrate in theisolation layer 52. The removal of the insulating material of theisolation layer 52 is carried out with reference to thesidewall spacers 64 s. The active regions having an etching selectivity are not etched during the etching of theisolation layer 52, while portion of the substrate where thesource region 63 s is formed can be recessed. - However, since the insulating material of the isolation layer is removed after the formation of the sidewall spacers, the recessed portions of the active region are distant from the
gate stack 62 a. Therefore, leakage current in the edge portions of the channel does not occur with the present invention. - Subsequently, the second photoresist is removed and a silicide layer is formed on the
source region 63 s, drainregion 63 d and control gate by using a conventional silicidation process. Thesilicide layer 66 formed on thesource region 63 s and the isolation layer where the insulating material is removed and constitutes the common source line disposed in parallel to the word line. - While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (5)
1-5. (canceled)
6. A method for manufacturing a flash memory device, comprising the steps of: forming an isolation layer for defining active regions in a semiconductor substrate, said active region being a region in which flash memory cells are to be formed; forming a gate stack that comes across the active region and the isolation layer; forming source and drain regions at both sides of the gate stack; removing insulating material in the isolation layer that is near to the source regions to form a common source line which is parallel to a word line formed over the gate stack; and forming a silicide layer in the common source line.
7. The method of claim 6 , wherein the step of forming the common source line comprises the steps of: depositing a conformal spacer insulating material on the entire surface of the semiconductor substrate; recessing the deposited spacer insulating material on the source regions; and selectively etching the spacer insulating material to form sidewall spacers at sidewalls of the gate stack.
8. The method of claim 7 , wherein the spacer insulating material has an etch selectivity to the isolation layer and is formed by silicon nitride.
9. The method of claim 7 , wherein the step of removing the insulating material in the isolation layer is carried out with reference to the sidewall spacers.
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US12/071,946 US20080160690A1 (en) | 2005-07-21 | 2008-02-28 | Flash memory device and method for fabricating the same |
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KR1020050066419A KR100665799B1 (en) | 2005-07-21 | 2005-07-21 | Flash memory device and method of fabricating the same |
US11/320,862 US7355243B2 (en) | 2005-07-21 | 2005-12-30 | Flash memory device and method for fabricating the same |
US12/071,946 US20080160690A1 (en) | 2005-07-21 | 2008-02-28 | Flash memory device and method for fabricating the same |
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US12/071,946 Abandoned US20080160690A1 (en) | 2005-07-21 | 2008-02-28 | Flash memory device and method for fabricating the same |
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KR100864992B1 (en) * | 2006-01-02 | 2008-10-23 | 주식회사 하이닉스반도체 | Method of manufacturing a Nand flash memory device |
KR100732629B1 (en) * | 2006-01-17 | 2007-06-27 | 삼성전자주식회사 | Nonvolatile memory device and method for forming the same |
KR100958632B1 (en) | 2007-05-17 | 2010-05-20 | 주식회사 동부하이텍 | Fabricating Method of Flash Memory Device |
US20100176481A1 (en) * | 2009-01-09 | 2010-07-15 | Macronix International Co., Ltd. | Memory Device and Manufacturing Method Thereof |
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US5736442A (en) * | 1995-09-14 | 1998-04-07 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor memory device |
US5741719A (en) * | 1995-03-13 | 1998-04-21 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method of manufacturing the same |
US6207504B1 (en) * | 1998-07-29 | 2001-03-27 | United Semiconductor Corp. | Method of fabricating flash erasable programmable read only memory |
US6673674B2 (en) * | 1998-02-10 | 2004-01-06 | Nec Electronics Corporation | Method of manufacturing a semiconductor device having a T-shaped floating gate |
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KR19990002554A (en) * | 1997-06-20 | 1999-01-15 | 김영환 | Manufacturing Method of Flash Memory Array Device |
JP3464414B2 (en) | 1999-06-15 | 2003-11-10 | 富士通株式会社 | Nonvolatile semiconductor memory device and method of manufacturing the same |
KR20010055879A (en) * | 1999-12-13 | 2001-07-04 | 윤종용 | Method for fabricating NOR-type flash memory device |
KR100620217B1 (en) * | 2003-12-31 | 2006-09-11 | 동부일렉트로닉스 주식회사 | Method for fabricating of non-volatile memory device |
-
2005
- 2005-07-21 KR KR1020050066419A patent/KR100665799B1/en not_active IP Right Cessation
- 2005-12-30 US US11/320,862 patent/US7355243B2/en not_active Expired - Fee Related
-
2008
- 2008-02-28 US US12/071,946 patent/US20080160690A1/en not_active Abandoned
Patent Citations (5)
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US4852062A (en) * | 1987-09-28 | 1989-07-25 | Motorola, Inc. | EPROM device using asymmetrical transistor characteristics |
US5741719A (en) * | 1995-03-13 | 1998-04-21 | Samsung Electronics Co., Ltd. | Nonvolatile memory device and method of manufacturing the same |
US5736442A (en) * | 1995-09-14 | 1998-04-07 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor memory device |
US6673674B2 (en) * | 1998-02-10 | 2004-01-06 | Nec Electronics Corporation | Method of manufacturing a semiconductor device having a T-shaped floating gate |
US6207504B1 (en) * | 1998-07-29 | 2001-03-27 | United Semiconductor Corp. | Method of fabricating flash erasable programmable read only memory |
Also Published As
Publication number | Publication date |
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US20070020846A1 (en) | 2007-01-25 |
KR100665799B1 (en) | 2007-01-09 |
US7355243B2 (en) | 2008-04-08 |
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