US20080125020A1

US20080125020A1 - Polishing Pad and a Chemical-Mechanical Polishing Method

Info

Publication number: US20080125020A1
Application number: US11/938,540
Authority: US
Inventors: Li Jiang; Wei Zang; Hua Ji; Masahiro Koike
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2006-11-28
Filing date: 2007-11-12
Publication date: 2008-05-29
Also published as: CN101190507A; CN100537148C

Abstract

The present invention provides a polishing pad, which has a flatness area and an emboss area on its polishing surface, wherein the flatness area is a flat surface with a roughness less than 20 um, for polishing a wafer; the emboss area has grooves, holes or a combination thereof, for pulling up a wafer from the polishing surface after polishing. By using the polishing pad according to the invention, a wafer may have a higher surface flatness after Chemical-Mechanical Polishing (CMP); and after polishing, the wafer is moved to the emboss area of the polishing pad, so that the wafer may be easily pulled up from the polishing pad surface.

Description

The present application claims the priority of Chinese Patent Application No. 200610118833.3, titled “A POLISHING PAD AND A CHEMICAL-MECHANICAL POLISHING METHOD”, and filed on Nov. 28, 2006, the whole content of which is incorporated herein by reference

FIELD OF THE INVENTION

The present invention relates to a semiconductor Chemical-Mechanical Polishing (CMP) process, in particular, to a CMP polishing pad and a CMP method for highly flattening a wafer surface.

BACKGROUND OF THE INVENTION

Chemical-Mechanical Polishing (CMP) process was introduced into IC (integrated circuit) manufacturing industry by IBM in 1984, and it was first used in the planarization of inter-metal dielectric (IMD) in Back-End (BE) process, then used in the planarization of tungsten (W) with the improvement of devices and processes, and then used in the planarization of shallow trench isolation (STI) and copper (Cu). CMP has become one of the techniques in IC process that develops most rapidly and attracts most attentions in recent years.
In CMP polishing process, a mechanical force is applied to a wafer surface in the atmospheric environment of a clean room, and a power for breaking and eroding the thin-film layer is generated on the wafer surface. Moreover, the etching efficiency of the polishing process must be improved by the interaction between the chemicals in the grinding fluid and the thin-film layer. In CMP process, a polishing slurry and a polishing pad are two most important elements, wherein the polishing slurry is usually made by diffusing some fine oxide powder in a aqueous solution, and the polishing pad is usually made of foaming-type porous polyurethane. In CMP process, first of all, the polishing slurry is filled in the voids of the grinding pad, and then the polishing pad is rotated at high speed, so that the wafer interacts with the polishing pad and the powder particles in the polishing slurry while rotating at high speed, and at the same time, parameters such as the downward pressure is controlled.
CN 01814133 discloses a structure of a polishing pad having a polishing surface. The polishing surface is in direct contact with a wafer when performing CMP. The polishing surface of the polishing pad has a three-dimensional (3D) structure which comprises a large number of pre-shaped 3D elements in regular arrangement. The shape of individual 3D element may be any one of various geometric solids, and there is emboss between adjacent 3D elements. As shown in FIG. 1, the shape of the 3D element is a pyramid with its top truncated to a predetermined height leaving a flat top surface. CN 03140681 discloses another structure of a polishing pad with emboss of at least one shape selected from lattice, ring and helix formed on the polishing surface side. The polishing pad may also have emboss with one or more shapes of lattice, ring or helix or have a through via extending through the exterior and interior of the polishing pad. A structure of a polishing pad is shown in FIG. 2, wherein the polishing surface has a structure of concentric circle-shaped emboss. Most of the polishing pads used in the current CMP process have the above 3D structure or a polishing surface having emboss with the shape of lattice, ring or helix. Polishing pads with such structures may well diffuse the polishing slurry. However, since these polishing pads all have emboss on their polishing surfaces, there may be emboss with similar structure to that of the polishing surface on the wafer surface when performing CMP, so that the flatness of the wafer surface may be degraded.
In practice, for conventional semiconductor devices, when CMP is performed on a wafer surface using a polishing pad having a polishing surface with a concentric ring shape or a polishing surface with 3D elements of predetermined shapes, the flatness of the wafer surface can meet the application requirements of the device. However, for some wafers used in optical instruments, such as wafers used in image transmitting and image processing elements, and for products laying higher quality requirements on the wafer surface, since especially high requirements are laid on the flatness of the wafer surface, the flatness of the wafer surface obtained by CMP using such polishing pads with emboss often cannot meet the application requirements of the devices, so that the product yield is very low. For example, if wafers obtained by CMP using the existing polishing pads are used for the image transmitting device of an liquid crystal display (LCD), the surface of the LCD may look stripy. This is the result that chromatic aberration caused by accidented wafer surface after CMP is displayed on the LCD surface.
To obtain a wafer surface with better flatness, wafers used for image transmission cannot be processed by CMP method. Thus, chemical etching method is often employed. However, the roughness of wafer surfaces processed by chemical etching method is much greater than that of the wafer surfaces processed by CMP method. Moreover, oxide residuals may be left in some areas; and local flatness is not as good as that of wafer surfaces processed by CMP method.
When CMP is performed using a polishing pad without emboss as described in CN 01814133 and CN 03140681 on its surfaces, i.e. a polishing pad with a flat surface is used directly for CMP, after CMP is performed using a polishing pad with a flat surface, the wafer surface and the polishing surface of the polishing pad are both relatively flat, thus the wafer may be tightly bonded with the polishing pad and difficult to be separated from the polishing pad surface, although the defect can be overcome that the flatness of wafer surfaces cannot meet the requirements.

SUMMARY OF THE INVENTION

The problem to be solved by the present invention is that a wafer surface polished by a polishing pad of the prior art cannot meet the application requirements of optical devices for image transmission and products that lay relatively high quality requirements on wafer surfaces, and that a wafer is difficult to be pulled up from a polishing surface after it is polished by the existing polishing pads having flat surfaces.
To solve the above problem, the invention provides a polishing pad, which has a flatness area and an emboss area on its polishing surface, wherein the emboss area surrounds the flatness area, and the outer contour line of the emboss area coincides with the edge contour of the polishing surface.
Moreover, the flatness area is a flat surface with a roughness less than 20 um, for polishing a wafer, and the emboss area has grooves, holes or a combination thereof, for pulling up a wafer from the polishing surface after polishing.
Furthermore, the minimum distance between any point on the inner contour line of the emboss area and the edge of the polishing surface is 20.5% to 40% of the diameter of the wafer to be polished.
Still further, the distance between any point on the outer contour line of the flatness area and the geometric center of the polishing surface is greater than 120% of the diameter of the wafer to be polished. Preferably, the distance between any point on the outer contour line of the flatness area and the geometric center of the polishing surface is 120% to 150% of the diameter of the wafer to be polished.
As a preferred technical solution, the flatness area and the polishing surface are arranged in the form of concentric circles, and the emboss area is an annular area formed by the polishing surface and the flatness area. Wherein, the diameter of the polishing surface is D₁, and 18 inch≦D1≦28 inch; the diameter of the flatness area is D₂, and 3 inch≦D₁-D₂≦6 inch.
Wherein, the number of the grooves, holes or the combination thereof of the emboss area is greater than two, and the grooves, holes or the combination thereof are arranged on the emboss area uniformly or nonuniformly.
Wherein, the grooves of the emboss area are in the form of individual lattice, ring, XY grid, spoke, helix or a combination of any two or more thereof, and the grooves have a required width, depth and length.
Wherein, the cross-sections of the holes in the emboss area are in the form of individual circle, ellipse, polygon or the combination of any two or more thereof, and the holes have a required depth and sectional size.
Most preferred, the emboss area has several annular grooves arranged in the form of concentric rings, wherein, the spacing between the adjacent concentric rings is 0.1 mm to 2 mm, the width of the grooves is 0.15 mm to 0.5 mm, the depth of the grooves is 0.25 mm to 0.5 mm, and the minimum distance between adjacent grooves is 0.1 mm to 10 mm.
Most preferred, the emboss area has several circular holes arranged in the form of concentric rings, the diameter of the holes is 5 mm to 12 mm, and the spacing between the concentric rings is 0.1 mm to 2 mm.
Most preferred, the emboss area has several annular grooves arranged in the form of concentric rings and several circular holes arranged in the form of concentric rings, and the spacing between the concentric rings is 0.1 mm to 2 mm.
Still further, the polishing pad also has a liner layer set on a non-polishing surface.
In comparison with the prior art, the invention has the following advantages:
1) The polishing surface of the polishing pad provided by the invention has a flatness area and an emboss area, wherein the flatness area is a flat surface with a roughness less than 20 um, for polishing a wafer; the emboss area has grooves, holes or the combination thereof, for separating a wafer from the polishing surface after polishing. The flatness area is used when performing CMP, so the defect is overcome that polishing pads of the prior art with grooves may result in wafer surfaces with low flatness. As a result, a wafer may have a higher surface flatness after CMP, so that the application requirements of optical devices for image transmission and products that lay higher quality requirements on wafer surfaces can be met. After polishing, the wafer is moved to the emboss area of the polishing pad, so that the wafer may be easily pulled up from the polishing pad surface.
2) The distance between any point on the outer edge of the emboss area and the geometric center of the polishing surface of the polishing pad provided by the invention is 1.5 inch to 3 inch. As a result, the size of the flatness area for CMP may be effectively guaranteed and wafers will not enter the emboss area during polishing; moreover, after polishing, it may be ensured that wafers can be pulled up from the polishing pad easily after they are moved to the emboss area.
3) The emboss area, the flatness area and the polishing surface of the polishing pad are set in the form of concentric rings. In addition, the grooves and holes and the combination thereof in the emboss area are also set in the form of concentric rings. Therefore, it may be ensured that wafers will not enter the emboss area during polishing.
4) The diameter of the holes in the emboss area is set to be 5 mm to 12 mm, so that the emboss area will have a sufficient void and wafers may be separated from the polishing pad easily after they are moved to the emboss area.
5) With the polishing pad and the polishing method of the invention, the yield of CMP process of wafers may be raised. The chromatic aberration caused by accidented wafer surfaces after being polished with the existing polishing pad and CMP method will lead to a yield drop of 40% to 80%. After being polished with the polishing pad and the polishing method according to the invention, the yield is increased by 40% to 80%.
6) In comparison with wafer surfaces processed by chemical etching method, the wafer surfaces polished with the polishing pad and the polishing method of the invention have a much lower roughness, i.e., lower than 10 nm. Thus, the wafer surfaces have higher surface reflectivity and better photoelectric characteristics.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a structural representation of an existing pyramid-shaped polishing pad with a polishing surface in the form of a flat top surface;

FIG. 2 shows a structural representation of an existing polishing pad with a polishing surface in the form of a concentric ring-shaped emboss;

FIG. 3 shows a microscopic morphology representation of a soft polishing pad surface of the prior art;

FIG. 4 shows a top view of a morphology representation of a wafer surface after CMP using a polishing pad with emboss;

FIG. 5 shows a stereoscopic representation of a wafer surface after CMP using a polishing pad with emboss;

FIG. 6 shows a cross sectional view of a morphology representation of a wafer surface after CMP using a polishing pad with emboss;

FIG. 7 to FIG. 9 show structural representations of the polishing surfaces according to preferred embodiments of the invention;

FIG. 10 shows a morphology representation of a wafer surface after being polished by the CMP method according to the invention; and

FIG. 11 shows the comparison between the defect incidence rates of a wafer polished by CMP with the polishing pad of prior art and of the invention respectively.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The invention will now be described in detail in conjunction with the drawings and embodiments.
At present, polishing pads used in CMP processes all have grooves on their polishing surfaces. After a wafer is polished using a polishing pad having grooves on its polishing surface, the flatness of the wafer surface cannot meet the requirements of devices for image transmission. To obtain a wafer surface with better flatness, the invention investigates the causes why emboss are generated on the wafer surface after CMP. By inspecting a polishing pad having a polishing surface with emboss through an electron microscope, it is found out that the microscopic structure of emboss of the polishing surface are all as shown in FIG. 3, in which these emboss are apparent.
After CMP is performed on a wafer using a polishing pad having a polishing surface as shown in FIG. 2, it is found out by irradiating with polarized light that the morphology of the wafer surface is as shown in FIG. 4. It is in the form of concentric rings, and the concentric rings on the wafer also have emboss, which conform to the shapes of the emboss on the polishing pad. FIG. 4 shows the morphology of a wafer surface irradiated by polarized light, which is taken by a digital camera.
FIG. 5 shows a stereoscopic morphology representation of the concentric rings of a wafer surface after CMP. The concentric rings and the emboss on the concentric rings on the wafer surface may become more apparent in this figure.
In the invention, the sizes of the grooves of various types of polishing pads usually employed in semiconductor manufacturing and the width of the grooves on the wafer surfaces after polishing are investigated. The result is shown in Table 1. The width of each concentric ring of the wafer surface after polishing is identical to that of the respective concentric ring of the polishing surface of the polishing pad used. Wherein, the width of each ring of the polishing pad is the sum of the widths of a groove part and a non-groove part; the width of each concentric ring of the wafer surface is also the sum of the widths of the groove part and the non-groove part.

TABLE 1

Comparison Between The Width Of Each Ring Of Different Polishing
Pads And The Width Of Each Ring Of The Wafer Surface After Polishing

	The Width Of
	Each Ring Of	The Width Of
	The Polishing	Each Ring Of The
Type Of Polishing Pad	Pad	Wafer Surface

IC1010 polishing pad (LAM	1.4 mm	1.4 mm
polisher)
IC1010 polishing pad (MIRRA	3 mm	3 mm
MESA polisher)
Politex reg polishing pad (MIRRA	2.5 mm	2.5 mm
MESA polisher)

In Table 1, IC1010 polishing pad (LAM polisher) means a polisher manufactured by LAM (USA) equipped with an IC1010 hard polishing pad manufactured by Rohmhass (USA).
In Table 1, IC1010 polishing pad (MIRRA MESA polisher) means an MIRRA MESA polisher manufactured by AMAT (USA) equipped with an IC1010 hard polishing pad manufactured by Rohmhass (USA).
In Table 1, Politex reg polishing pad (MIRRA MESA polisher) means an MIRRA MESA polisher manufactured by AMAT (USA) equipped with a Politex reg soft polishing pad manufactured by Rohmhass (USA).
It is found out by further investigation that emboss generated on the wafer surface after CMP have a shape and width that are totally the same as those of the emboss on the polishing surface of the polishing pad used. Moreover, the height difference between emboss and the peak of the wafer surface is 50 to 200 Å, as shown in FIG. 6.
In view of the above investigation, to obtain a wafer surface with higher flatness, the invention provides a polishing pad, which has a flatness area and an emboss area on its polishing surface, wherein the flatness area is a flat surface with a roughness less than 20 um, for polishing a wafer; the emboss area has grooves, holes or the combination thereof, for pulling up a wafer from the polishing surface after polishing.
Furthermore, the emboss area surrounds the flatness area, and the outer contour line of the emboss area coincides with the edge contour of the polishing surface, and the minimum distance between any point on the inner contour line of the emboss area and the edge contour of the polishing surface is 20.5% to 40% of the diameter of the wafer to be polished. Since the flatness area is used for polishing a wafer, the size of the flatness area should at least guarantee that a wafer will not enter the emboss area when it is polished.
Still further, the geometric centers of the emboss area, the flatness area and polishing surface coincide with each other.
In a preferred technical solution, the distance between any point on the outer contour line of the flatness area and the geometric center of the polishing surface is greater than 120% of the diameter of the wafer to be polished, and more preferably, the distance between any point on the outer contour line of the flatness area and the geometric center of the polishing surface is 120% to 150% of the diameter of the wafer to be polished.
As a more preferred technical solution, assuming that the diameter of the polishing surface is D₁, and the diameter of the emboss area is D₂, then 3 inch≦D₁-D₂≦6 inch (1 inch=25.4 mm), and 18 inch≦D₁≦28 inch.
The flatness area of the polishing pad according to the invention has a flat polishing surface, and the roughness of the polishing surface is less than 20 um. A wafer is mainly polished by the flatness area when performing CMP, and a wafer surface with high flatness may be obtained, which can meet the requirements for the flatness of the wafer surface raised by optical devices.
When CMP is performed using a polishing pad having a flat polishing surface, since the polishing surface and the wafer surface in contact with the polishing surface are both very flat, these contact surfaces are tightly bonded with each other. Thus, after CMP, the wafer cannot be separated from the polishing pad in the flatness area. To separate a wafer from the polishing pad surface more easily, part of the wafer may be rotated to the emboss area of the polishing pad after polishing. Because the emboss area has grooves, holes or the combination thereof, air may be filled between the contact surfaces of the wafer and the polishing pad and the pressure difference between the upper and lower surfaces of the wafer can be reduced, so that the wafer may be separated from the polishing pad surface more easily.
The flat polishing surface according to the invention means a polishing surface that has no grooves, holes or any combination thereof, or any other structures with accidented surfaces.
The emboss area according to the invention has grooves, holes or the combination thereof. The number of the grooves, holes or the combination thereof contained in the emboss area may be set as required. Preferably, there are more than 2 grooves, holes or the combination thereof.
There are no further requirements laid on the arrangement of the grooves, holes or the combination thereof in the emboss area. They may be arranged regularly or irregularly. Preferably, the grooves, holes or the combination thereof are arranged uniformly on the entire emboss area. For example, multiple grooves are arranged in the form of regular circles and ellipses in the emboss area. As another example, multiple holes are distributed at will in the emboss area uniformly, such as in the form of regular tetragons, pentagons, hexagons, etc., or in the form of regular ellipses, circular rings, etc. As another example, multiple grooves and multiple holes are distributed uniformly in the emboss area.
The emboss area according to the invention is used to easily pull up a wafer from the polishing pad surface after polishing, without affecting the flatness of the wafer surface. Therefore, it is only required that an emboss area for air admission exists in the emboss area of the polishing pad according to the invention so as to reduce the pressure difference between the upper and lower surfaces of the wafer, and that the surface roughness of the convex area reaches that of the polishing pad in the prior art.
The grooves in the above mentioned emboss area may be in the form selected from lattice, ring, XY grid, spoke or helix, etc. In addition, the grooves of the emboss area may be in the form of individual lattice, ring, XY grid, spoke or helix, or the combination of any two or three thereof. Preferably, the emboss area is composed of individual annular grooves.
When the grooves in the emboss area are in the form of annular rings, there are no special restrictions on their flat shape; for example, it may be a circle, a polygon (triangle, quadrangle and pentagon), an ellipse, etc. Preferably, the multiple grooves in the emboss area are set in the form of circular rings. More preferably, the multiple grooves are set in the form of concentric rings.
In the invention, no special restrictions are laid on the cross-sectional shape along the width direction of the grooves in the emboss area either. On one hand, the cross-section may have a shape formed by the flat lateral surface and the bottom surface, wherein the width of the opening side of the grooves may be the same as/different from that of the bottom side of the grooves; for example, the width of the opening side is greater than that of the bottom side, or the width of the bottom side is greater than that of the opening side. On the other hand, the cross-section may also be in the form of U or V etc.
According to the invention, the width and depth of the grooves in the emboss area may be set as required. The width and depth of the multiple different grooves in the emboss area may be the same or different.
In the invention, the width of the grooves is preferably greater than 0.1 mm, more preferably 0.1 mm to 5 mm, especially 0.2 mm to 3 mm, and most preferably 0.15 mm to 0.5 mm. The depth of the grooves is preferably greater than 0.1 mm, more preferably 0.1 mm to 2.5 mm, especially 0.2 mm to 2.0 mm, and most preferably 0.25 mm to 0.5 mm. Additionally, the minimum distance between adjacent grooves is preferably greater than 0.05 mm, more preferably 0.05 mm to 100 mm, especially 0.1 mm to 10 mm.
That is to say, according to the invention, in the emboss area of one and the same polishing surface, assuming that there are more than 2 grooves set in the emboss area, then multiple grooves may be arranged at will in the emboss area, or may be uniformly arranged in the form of regular shapes. The spacing between the grooves may be the same or different. The width and depth of the multiple different grooves may be the same or different. The cross-sectional shape along the width direction of each different grooves may be the same or different.
In one preferred technical solution of the invention, there are more than 2 grooves in the emboss area. The grooves are in the form of annular rings. Multiple grooves may be distributed in the form of regular annular rings in the emboss area. Different grooves have the same cross-sectional shape along the width direction. Moreover, the width of the opening side of the grooves is the same as that of the bottom side of the grooves, and the distance between the grooves is the same, and the width and depth of each groove are the same respectively. The specific value of the width and depth of the grooves may be selected from the numerical range given by the invention according to requirements, and no further restrictions are laid here. By using such a preferred technical solution, the manufacturing process of polishing pads may be simplified and the cost may be reduced.
In a most preferred embodiment as shown in FIG. 9, a circular polishing pad is used. The flatness area 31 is a circular area and is arranged concentrically with the polishing surface of the polishing pad. Emboss area 32 is an annular ring formed by the polishing surface and the flatness area. Assuming that the diameter of the polishing surface is D1, D1 may be set according to the polishing device and the size of the wafer to be polished. Usually, D1 is set as 18 inch to 28 inch, usually as 20 inch or 24 inch, etc. Assuming that the diameter of flatness area 31 is D2, then 3 inch≦D₁-D₂≦6 inch. The specific value of D₂is selected from 3 inch, 4 inch, 5 inch, 6 inch etc. in the embodiments. According to requirements, more than two grooves 13 arranged in the form of concentric rings are set in the emboss area (as shown in the Figure, the two grooves arranged in the form of concentric rings are only illustrative, and the actual number is dependent on the various requirements, and no further restrictions will be laid on it in the invention). The cross-sectional shape of the groove 13 is a circular ring, and the diameter difference between adjacent concentric rings is the same. This diameter difference may be set according to the size of the polishing pad, the flatness area and the emboss area, and it is generally between 0.1 mm and 2 mm. The width and depth of the groove 13 are also set according to requirements, and no further restrictions will be laid on it in the invention. However, as one embodiment of the invention, the width is set as 0.15 mm to 0.5 mm, and the depth is set as 0.25 mm to 0.5 mm.
The holes in the above emboss area may have various cross-sectional shapes, which may be various regular shapes, such as circles, ellipses, polygons (triangles, tetragons, pentagons and hexagons), etc., or may be other irregular shapes. The holes of the emboss area may be in the form of individual circles, ellipses, polygons or irregular shapes, or the combination of any two or three thereof.
Multiple holes may be arranged in a regular shape or an irregular shape in the emboss area. Preferably, in the invention, multiple holes are distributed uniformly in the emboss area. More preferably, various holes are arranged in the form of an annular ring, a polygon, a helix, etc. in the emboss area. More preferably, multiple holes are arranged in the form of circular rings in the emboss area, and the spacing between each annular ring is set according to requirements and may be the same or different. Most preferably, in the invention, multiple holes are arranged in the form of concentric circles in the emboss area, and the spacing between respective concentric circles, i.e., the difference between the radiuses of two adjacent concentric circles, is the same. The spacing between the holes that constitute the concentric circles may be adjusted according to requirements.
Along the depth direction of the holes, the cross-section of holes in different depths may be the same or different. For example, the 3D shape of the holes may be a cylinder, or a conoid, or other columns with three or four sides. Preferably, in the invention, the cross-sections in different depths of the holes are the same. More preferably, the holes are circular, and the size of the cross-sections in different depths of the holes is the same.
According to the invention, the width and depth of the holes in the emboss area may be set according to requirements. The width and depth of multiple different holes in the emboss area may be the same or different.
In order to pull up a wafer from the polishing pad after polishing more easily, and prevent the polishing slurry from entering the holes and being wasted and prevent the holes from being blocked, the diameter of individual holes may be set as 5 mm to 12 mm, preferably 6 mm to 10 mm, and more preferably 8 mm to 9 mm.
In the invention, when the emboss area has multiple holes, it is desirable that the holes are distributed relatively uniformly over the emboss area. That is to say, when a majority of a wafer is rotated into any part of the emboss area, there should be multiple holes in this emboss area, which is in contact with the wafer, so that the wafer may be favorably pulled up from the polishing surface. However, there are no further restrictions on the spread geometry of the multiple holes in the emboss area. Preferably, multiple holes are arranged in the form of multiple circular rings in the emboss area, and the spacing between different circular rings may be adjusted according to requirements. The spacing between different circular rings may be the same or different, and the depth and width of each hole that forms the circular rings are also the same respectively.
In one preferred technical solution of the invention, multiple holes of the emboss area are arranged in the form of concentric rings. The difference between the diameters of two adjacent concentric rings is set as the same. In addition, the width and depth of each hole are also set as the same respectively.
In a most preferred embodiment, a circular polishing pad is used. The flatness area is a circular area and is distributed concentrically with the polishing surface of the polishing pad. The emboss area is an annular ring formed by the polishing surface and the flatness area. The emboss area has concentric rings formed by uniformly arranged multiple holes. The concentric rings formed by multiple holes in the emboss area are concentric with the flatness area.
In a most preferred embodiment as shown in FIG. 8, a circular polishing pad is used. Flatness area 21 is a circular area and is concentric with the polishing surface of the polishing pad. Emboss area 22 is an annular ring formed by the polishing surface and the flatness area. Assuming that the diameter of the polishing surface is D₁, then D₁may be set according to the polishing device and the size of the wafer to be polished. Usually, D₁is set as 18 inch to 28 inch, more often as 20 inch, 24 inch, etc. Assuming that the diameter of flatness area 21 is D₂, then 3 inch≦D₁-D₂≦6 inch, and D₂is selected from 3 inch, 4 inch, 5 inch, 6 inch etc. in the embodiments. The emboss area has several holes 23, which are arranged uniformly and form more than 2 circular rings distributed concentrically. The spacing between the circular rings formed may be set according to requirements. The two circular rings shown in the Figure are only illustrative, and the number of the circular rings formed by holes 23 is not limited to 2. The spacing between different circular rings may be set according to the size of the polishing pad, the flatness area and the emboss area, and it is usually between 0.1 mm and 2 mm. The spacing between the holes may be adjusted according to requirements, and it is not intended to be too much restricted in the present embodiment. The cross-section of the individual hole is a circle with a diameter set as 5 mm to 12 mm, and the depth of the holes may be set according to requirements.
Refer to FIG. 9, which shows another embodiment of the invention, wherein a circular polishing pad is used. Flatness area 31 is a circular area and is distributed concentrically with the polishing surface of the polishing pad. Emboss area 32 is an annular ring formed by the polishing surface and the flatness area. Assuming that the diameter of the polishing surface is D1, then D1 may be set according to the polishing device and the size of the wafer to be polished. Usually, D1 is set as 18 inch to 28 inch, and usually it is set as 20 inch, 24 inch, etc. Assuming that the diameter of the flatness area 31 is D2, then 3 inch≦D₁-D₂≦6 inch, and D₁-D₂is selected from 3 inch, 4 inch, 5 inch, 6 inch etc. in the embodiments.
Referring to FIG. 9, emboss area 32 is comprised of grooves 33 with a cross-section in the form of a circular ring and a circle formed by multiple holes 34. The circular ring-shaped grooves 33 are distributed concentrically with the circle formed by multiple holes 34. The number of the circular ring-shaped grooves 33 and the circles formed by multiple holes 34 may be set according to requirements, without being limited to the number shown in the Figure. The spacing between the circular ring-shaped grooves 33 and the circles formed by multiple holes 34 may be set according to requirements and will not be further restricted here. The width and depth of grooves 33 are also set according to requirements, and no further restrictions will be laid on it in the invention. However, in one embodiment of the invention, the width is set as 0.15 mm to 0.5 mm, and the depth is set as 0.25 mm to 0.5 mm. The cross-sectional shapes of the holes 34 are circular rings. The diameter of each individual hole is set as 5 mm to 12 mm, and the depth of the holes is set according to requirements. The spacing between the holes may also be adjusted according to requirements, and it is not intended to be further restricted in the present embodiment.
The polishing pad of the invention may be a hard polishing pad or a soft polishing pad. Since the flatness area is mainly used for CMP, to obtain better dispersibility of the polishing slurry on the polishing pad during CMP, a soft polishing pad is preferably employed in present invention.
There are no special requirements on the material of the polishing pad in the invention. All the materials in the prior art for polishing pads and polishing surfaces may be used. Preferably, polishing surfaces are made of foaming-type porous polyurethane.
The polishing pad may be a multilayer polishing pad, that is, the polishing pad may also have a liner layer set on the non-polishing surface. The material and structural features of the liner layer on the non-polishing surface are totally the same as those of the liner layer of the multilayer polishing pad in the prior art, which will not be described in detail here.
When the emboss area of the polishing surface has holes, in order to prevent the polishing slurry from leaking out of the holes, it must be ensured that the holes will not penetrate through the entire polishing pad. Thus, the polishing pad must be set as a multilayer polishing pad and a liner layer must be set on the non-polishing surface of the polishing pad.
When polishing with the above polishing pad, since the polishing surface has a flat structure, no unevenness on a wafer surface will appear as caused by the unevenness of the emboss in the prior art. As a result, wafer surfaces with high flatness may be obtained. After polishing, part of the wafer may be rotated to the emboss area of the polishing pad, so that the wafer may be easily separated from the polishing surface, and the defect may be avoided that wafers are difficult to be separated from the polishing surface when a polishing pad without grooves on its surface is used.
The invention further provides a novel CMP method, the key point of which is to use a polishing pad according to the invention. The entire polishing process is divided into two steps: first, polish a wafer with a flatness area of a polishing surface; then, move the polishing pad to an emboss area of the polishing surface and separate the wafer from the polishing surface.
In the above CMP method, when the polishing pad is moved to the emboss area of the polishing surface, the minimum distance between any point on the wafer and the edge of the polishing pad should be 0.5 inch to 1 inch, so that the wafer surface will be protected from being scratched by the rough edge contour of the polishing pad.
The microscopic structure of a wafer surface after being polished with the polishing pad and the CMP method according to the invention is as shown in FIG. 10. After polishing, the concentric rings on the wafer surface is eliminated, which may be caused by a polishing pad with emboss, and the wafer surface is uniformly flat, with a roughness less than 10 nm. The flatness of the above wafer surface can meet the application requirements of optical devices for image transmission.
Refer to FIG. 11, which shows the comparison between the defect incidence rates of a wafer polished by CMP using a polishing pad of the invention and a wafer polished by a polishing pad of prior art having grooves on its polishing surface. As shown in FIG. 11, the defect incidence rate of the prior art is 30% to 40%, and after CMP is performed using the polishing pad according to the invention, the defect incidence rate of a wafer may be decreased to 0.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various variations and modifications may be made without departing from the spirit or scope of the invention as defined by the appended claims and their equivalents.

Claims

1. A polishing pad, comprising:

a flatness area, and

an emboss area on its polishing surface, wherein the emboss area surrounds the flatness area and the outer contour line of the emboss area coincides with the edge contour of the polishing surface.

2. The polishing pad according to claim 1, wherein:

the flatness area is a flat surface with a roughness less than 20 um, for polishing a wafer; and the emboss area has grooves, holes or a combination thereof, for pulling up the wafer from the polishing surface after polishing.

3. The polishing pad according to claim 1, wherein:

the minimum distance between any point on the inner contour line of the emboss area and the edge of the polishing surface is 20.5% to 40% of the diameter of the wafer to be polished.

4. The polishing pad according to claim 1, wherein:

the distance between any point on the outer contour line of the flatness area and the geometric center of the polishing surface is greater than 120% of the diameter of the wafer to be polished.

5. The polishing pad according to claim 4, wherein:

the distance between any point on the outer contour line of the flatness area and the geometric center of the polishing surface is 120% to 150% of the diameter of the wafer to be polished.

6. The polishing pad according to claim 1, wherein:

the flatness area and polishing surface are arranged in the form of concentric circles, and the emboss area is an annular area formed by the polishing surface and the flatness area.

7. The polishing pad according to claim 6, wherein:

the diameter of the polishing surface is D1, and 18 inches≦D1≦28 inches; and the diameter of the flatness area is D2, and 3 inches≦D1-D2≦6 inch.

8. The polishing pad according to claim 1, wherein:

the number of the grooves, holes or a combination thereof in the emboss area is greater than two.

9. The polishing pad according to claim 1, wherein:

the grooves in the emboss area are in the form of individual lattice, ring, XY grid, spoke, helix or a combination of any two or more thereof.

10. The polishing pad according to claim 1, wherein:

the cross-sections of the holes in the emboss area are in the form of individual circle, ellipse, polygon or a combination of any two or more thereof.

11. The polishing pad according to claim 1, wherein:

the emboss area has a plurality of annular grooves arranged in the form of concentric rings.

12. The polishing pad according to claim 11, wherein:

the spacing between the adjacent concentric rings is 0.1 mm to 2 mm.

13. The polishing pad according to claim 11, wherein:

the width of the grooves is 0.15 mm to 0.5 mm, the depth of the grooves is 0.25 mm to 0.5 mm, and the minimum distance between adjacent grooves is 0.1 mm to 10 mm.

14. The polishing pad according to claim 1, wherein:

the emboss area has a plurality circular holes arranged in the form of concentric rings.

15. The polishing pad according to claim 14, wherein:

the diameter of the holes is 5 mm to 12 mm.

16. The polishing pad according to claim 14, wherein:

the spacing between the concentric rings is 0.1 mm to 2 mm.

17. The polishing pad according to claim 1, wherein:

the emboss area has a plurality annular grooves arranged in the form of concentric rings and a plurality circular holes arranged in the form of concentric rings.

18. The polishing pad according to claim 17, wherein:

the spacing between the concentric rings is 0.1 mm to 2 mm.

19. The polishing pad according to claim 1, wherein:

the polishing pad also has a liner layer set on a non-polishing surface.

20. A chemical-mechanical polishing method, wherein:

performing chemical-mechanical polishing on a wafer using the flatness area of the polishing pad of claim 1,

moving the polished wafer to the emboss area of the polishing pad of claim 1, and

pulling up the wafer is pulled up from the polishing pad.