US20080100320A1 - Intelligent probe card architecture - Google Patents
Intelligent probe card architecture Download PDFInfo
- Publication number
- US20080100320A1 US20080100320A1 US12/001,281 US128107A US2008100320A1 US 20080100320 A1 US20080100320 A1 US 20080100320A1 US 128107 A US128107 A US 128107A US 2008100320 A1 US2008100320 A1 US 2008100320A1
- Authority
- US
- United States
- Prior art keywords
- test
- circuitry
- probe card
- semiconductor device
- providing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
- G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
- G01R31/31905—Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07364—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch
- G01R1/07385—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch using switching of signals between probe tips and test bed, i.e. the standard contact matrix which in its turn connects to the tester
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/36—Overload-protection arrangements or circuits for electric measuring instruments
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
- G01R31/2889—Interfaces, e.g. between probe and tester
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
Definitions
- the present invention relates to a probe card configuration for a test system used to test integrated circuits (ICs) on a wafer. More particularly, the present invention relates to a probe card configuration with intelligent on board features that can, for example, enable the probe card to distribute a single channel from a test system controller to multiple test probes to connect to the ICs on a wafer.
- test system controllers When testing ICs on a wafer, it is cost effective to test as many devices as possible in parallel, thus reducing the test time per wafer.
- Test system controllers have evolved to increase the number of channels and hence the number of devices that can be tested in parallel.
- a test system controller with increased test channels is a significant cost factor for a test system, as is a probe card with complex routing lines used to accommodate multiple parallel test channels. It is, thus, desirable to provide an overall probe card architecture that allows increased test parallelism without requiring increased test system controller channels and without increased probe card routing complexity.
- test system controller has resources to enable testing a fixed number of Devices Under Test (DUTs) on a wafer. With advancing technology, more DUTs are fabricated on a single wafer. To avoid the cost of a new test system controller, either multiple touchdowns of a test system to the wafer are performed, or the test signals normally provided to a single DUT are fanned out to multiple DUTs in the probe card.
- DUTs Devices Under Test
- the later may be more desirable for burn in testing where during heating of the wafer, multiple touch downs of the probe card to the wafer is sometimes impractical. Further, less touch downs to the wafer decrease the likelihood of damaging the wafer, and less touch downs limit wear on the probes in the test system, which may be expensive to replace.
- Fan out of the test signals in a probe card between a test system controller and DUTs not only increases the complexity of a system, but also can cause inaccurate test results.
- increased circuitry can be provided on the probe card to minimize the effect of a fault on one of the fan out lines.
- a fault short circuit
- probe cards are desirable that can further take on expanded test system functions to increase the lifecycle of an outdated test system.
- Probe cards serving as an interface between a test system controller and a wafer, are typically much less expensive than a test system controller, and typically replaced after a much shorter lifecycle than the test system controller due to wear of probes on the probe card.
- FIG. 1 shows a block diagram of a test system using a probe card for testing DUTs on a semiconductor wafer.
- the test system includes a test system controller 4 , or general purpose computer, connected by a communication cable 6 to a test head 8 .
- the test system further includes a prober 10 made up of a stage 12 for mounting a wafer 14 being tested, the stage 12 being movable to contact the wafer 14 with probes 16 on a probe card 18 .
- the prober 10 includes the probe card 18 supporting probes 16 which contact DUTs formed on the wafer 14 .
- test data is generated by the test system controller 4 and transmitted through the communication cable 6 , test head 8 , probe card 18 , probes 16 and ultimately to DUTs on the wafer 14 .
- Test results are then provided from DUTs on the wafer back through the probe card 18 to the test head 8 for transmission back to the test system controller 4 .
- the wafer is diced up to separate the DUTs.
- Test data provided from the test system controller 4 is divided into the individual test channels provided through the cable 6 and separated in the test head 8 so that each channel is carried to a separate one of the probes 16 .
- the channels from the test head 8 are linked by flexible cable connectors 24 to the probe card 18 .
- the probe card 18 then links each channel to a separate one of the probes 16 .
- FIG. 2 shows a cross sectional view of components of a typical probe card 18 .
- the probe card 18 is configured to provide both electrical pathways and mechanical support for the spring probes 16 that will directly contact the wafer.
- the probe card electrical pathways are provided through a printed circuit board (PCB) 30 , an interposer 32 , and a space transformer 34 .
- Test data from the test head 8 is provided through flexible cable connectors 24 typically connected around the periphery of the PCB 30 .
- Channel transmission lines 40 distribute signals from the connectors 24 horizontally in the PCB 30 to contact pads on the PCB 30 to match the routing pitch of pads on the space transformer 34 .
- the interposer 32 includes a substrate 42 with spring probe electrical contacts 44 disposed on both sides.
- the interposer 32 electrically connects individual pads on the PCB 30 to pads forming a land grid array (LGA) on the space transformer 34 .
- Traces 46 in a substrate 45 of the space transformer 34 distribute or “space transform” connections from the LGA to spring probes 16 configured in an array.
- the space transformer substrate 45 is typically constructed from either multi-layered ceramic or organic based laminates.
- the space transformer substrate 45 with embedded circuitry, probes and LGA is referred to as a probe head.
- Bracket Probe Head Bracket
- frame Probe Head Stiffener Frame
- leaf springs 56 leaf springs
- leveling pins 62 The back plate 50 is provided on one side of the PCB 30 , while the bracket 52 is provided on the other side and attached by screws 59 .
- the leaf springs 56 are attached by screws 58 to the bracket 52 .
- the leaf springs 56 extend to movably hold the frame 54 within the interior walls of the bracket 52 .
- the frame 54 then includes horizontal extensions 60 for supporting the space transformer 34 within its interior walls.
- the frame 54 surrounds the probe head and maintains a close tolerance to the bracket 52 such that lateral motion is limited.
- Leveling pins 62 complete the mechanical support for the electrical elements and provide for leveling of the space transformer 34 .
- the leveling pins 62 are adjusted so that brass spheres 66 provide a point contact with the space transformer 34 .
- the spheres 66 contact outside the periphery of the LGA of the space transformer 34 to maintain isolation from electrical components.
- Leveling of the substrate is accomplished by precise adjustment of these spheres through the use of advancing screws, or leveling pins 62 .
- the leveling pins 62 are screwed through supports 65 in the back plate 50 and PCB 30 . Motion of the leveling pin screws 62 is opposed by leaf springs 56 so that spheres 66 are kept in contact with the space transformer 34 .
- FIG. 3 shows an exploded assembly view of components of the probe card of FIG. 2 .
- FIG. 3 shows attachment of the back plate 50 , PCB 30 , and bracket 52 using two screws 59 .
- Four leveling screws 62 are provided through the back plate 50 and PCB 30 to contact four spheres 66 near the corners of the space transformer substrate 34 .
- the frame 54 is provided directly over the space transformer substrate 34 , the frame 54 fitting inside the bracket 52 .
- the leaf springs 56 are attached by screws 58 to the bracket 52 .
- Two screws 58 are shown for reference, although additional screws 58 (not shown) are provided around the entire periphery to attach the leaf springs.
- FIG. 4 shows a perspective view of the opposing side of PCB 30 illustrating the arrangement of connectors 24 around its periphery.
- the connectors 24 of the PCB 30 are facing down and not shown.
- the connectors 24 typically zero insertion force (ZIF) connectors
- ZIF zero insertion force
- the connectors 24 provide flexible cable connections located around the periphery of the probe card, and are configured to mate with connectors that are typically arranged in a similar fashion on the test head.
- ZIF connectors other connector types may be used, such as pogo pins, non-ZIF flexible cable connectors, conductive elastomer bumps, stamped and formed spring elements, etc.
- a probe card is provided with a number of on board features enabling fan out of a test channel signal to multiple DUTs while limiting undesirable effects of fan out on test results.
- the on board probe card features further enable enhancing test system controller functions, effectively increasing the lifecycle of some test system controllers, providing more advanced functions without the cost of purchasing a more modern test system controller.
- the probe card in accordance with the present invention enables significant fan out with test integrity so that probe cards can be used with a limited channel test system controller to test a wafer with one touch down, a particularly desirable feature during burn in tests.
- On board features of the probe card include one or more of the following: (a) DUT signal isolation provided by placing resistors in series with each DUT input to isolate failed DUTs, as described generally in U.S. Pat. No. 6,603,323 reference previously; (b) DUT power isolation provided by switches, current limiters, or regulators in series with each DUT power pin to isolate the power supply from failed DUTs, allowing a single test system controller power supply to power multiple DUTs; (c) self test provided using an on board micro-controller or FPGA and associated multiplexers and D/A converters, on board self testing being necessary with fanned out test system controller resources since test system controller integrity checks may no longer be valid; (d) stacked or vertically oriented daughter cards provided between test system controller connections which form an outline area on the PCB of the probe card, the stacked daughter cards to accommodate additional circuitry used in accordance with the present invention, and to provide the additional circuitry in close proximity to the PCB, space transformer and other components originally forming the probe card; and (e
- FIG. 1 shows a block diagram of components of a conventional wafer test system
- FIG. 2 is a cross sectional view of a conventional probe card for the wafer test system of FIG. 1 ;
- FIG. 3 is an exploded assembly view of components of the probe card of FIG. 2 ;
- FIG. 4 is a perspective view of the PCB of FIG. 2 showing connectors for connecting to a test head;
- FIG. 5 shows a cross sectional view of a probe card with on board components in accordance with the present invention.
- FIG. 6 shows a circuit diagram for components of the probe card of FIG. 5 ;
- FIG. 7 shows an alternative circuit diagram for components of the probe card of FIG. 5 .
- FIG. 5 shows a cross sectional view of a probe card, modified from the probe card configuration shown in FIG. 2 to include on board components, in accordance with the present invention, including daughter cards 100 and 102 .
- the daughter cards are shown in FIG. 5 as connected by stacked connectors 104 1-4 .
- the stacked connectors are attached to opposing card surfaces, and include male and female mating connectors.
- connector 104 1 is connected to the base PCB 30
- connector 104 2 is connected to daughter card 100 .
- the stacked connectors can be ZIF, pogo pin, or other type connectors suitable for interconnecting printed circuit boards.
- the connectors make the daughter cards removable so that different daughter cards can be easily installed, depending on the test environment.
- the daughter cards can be rigidly connected, such as by soldering.
- two daughter cards are shown, a single card or more than two cards can be used, depending on design requirements.
- the daughter cards 100 and 102 are provided in available spacing between test system controller interface connectors 24 .
- the test system controller could be a conventional Automatic Test Equipment (ATE) tester or a computer system used to control and configure the probe card, which can limit the height above the connectors 24 which the daughter cards can be stacked.
- ATE Automatic Test Equipment
- an opening is provided in the back plate 50 , forming an outline area where the daughter cards 100 and 102 are connected to the base PCB 30 .
- the area of the probe card available for daughter cards is generally dictated by the test system controller connection and prober constraints. With limited horizontal spacing between test system controller interface connectors 24 , board area to accommodate additional circuitry for the architecture in accordance with the present invention is obtained by stacking additional daughter cards within the outline area of the probe card.
- the stacked connectors 104 1-4 provide spacing for discrete components 114 provided on the surface of each of the base PCB 30 and daughter cards 100 and 102 .
- the discrete components 114 can include bypass capacitors for power supply lines.
- similar discrete components 112 are also provided on a surface of the space transformer 34 .
- the discrete components 112 are decoupling capacitors. To accommodate the discrete components 112 , a number of spring contacts 44 are removed from the interposer 32 , and rerouting of lines is provided in the space transformer 34 . With the discrete components 112 being decoupling capacitors they are placed in close proximity to lines carrying power to probes 16 to maximize capacitance on the power lines that affect test results. By being placed in close proximity to where capacitance will improve the decoupling, smaller capacitances can be used for the capacitors 110 .
- the daughter cards such as 100 and 102 shown, may be redundant with the base PCB 30 , in that they carry the same discrete components on their surface. More redundant daughter cards can be simply added if more fan out of test channels is desired. Alternatively, the daughter cards can include differing components depending on test requirements and available space.
- the daughter card 102 is shown to include a micro-controller 110 as a discrete component 114 . Although shown on daughter card 102 , similar micro-controllers can be provided on one or more of the daughter card 102 , daughter card 100 , base PCB 30 , and space transformer 34 .
- the micro-controller 110 may be any of a variety of programmable controllers including a microprocessor, digital signal processor, sequencer, Field Programmable Gate Array (FPGA), Programmable Logic Device (PLD) or other controller or device that can be programmed/configured as a controller for generating and providing test or control signals to electrical circuits.
- the micro-controller 110 is the Microchip PIC18FXX20 with A/D capability.
- the discrete components 114 on a daughter card or base PCB 30 , or 112 on the space transformer can include memory for use by the micro-controller 110 , or by another processor either on the probe card, or external to the probe card.
- the memory can be a random access memory (RAM) providing temporary storage, or a device providing more permanent storage such as a flash memory.
- RAM random access memory
- the memory can be programmed to include test vectors or a test program.
- the memory can include system configuration data.
- the circuitry can also be organized such that, in concert with the DUT, a full system is created for evaluating the DUT.
- the daughter card and probe card circuitry could include support circuits for a personal computer motherboard if the DUT is an Intel or other microprocessor.
- the DUT will experience an electrical environment like the final use environment. In this way, a test of operating correctness can be performed on unpackaged DUT devices.
- a temperature control system can be included along with the discrete components 114 on the probe card daughter cards 100 and 102 , or on the base PCB 30 .
- the temperature control system can include temperature sensors, along with heat sinks, fans, electric coolers, heaters, or other devices needed to maintain component temperatures within a desired range.
- Discrete components 114 in addition to the micro-controller 110 and memory can, for example, include voltage regulators, relays, multiplexers, switches, D/A converters, A/D converters, shift registers, etc. Examples for the configuration of the discrete components are shown in the circuit diagrams of FIG. 6 and FIG. 7 . Further details of these components, as well as other features included on the probe card in accordance with the present invention are described below.
- the space transformer 34 includes thin film resistors placed in series with each probe that provides a DUT input.
- Such thin film resistors 120 1-4 providing signals from a single channel of test system controller 4 to inputs of DUTs 124 1-4 are illustrated in FIG. 6 .
- the architecture in accordance with the present invention uses embedded resistors, such as resistors 120 1-4 , in the space transformer 34 placed in series with each DUT input to isolate failed or shorted DUTs from good DUT inputs.
- the space transformer 34 illustrated in FIG. 5 , is typically a multi-layer ceramic substrate, or may be made up of a multi-layer organic substrate, with the thin film resistors 120 1-4 provided on one or more layers in the path of routing lines to the probes.
- resistors have values ranging between 50 and 5000 ohms each. Values on the order of 1000 ohms allow a single DUT channel to drive 10 to 100 DUTs at frequencies between 5 and 50 MHz. Placement of the embedded resistors close to the DUT is key to enabling maximum performance while at the same time not increasing the size of the probe head. Discrete or surface mounted resistors could also be used for this DUT isolation application.
- buffers are placed in series with each DUT input to isolate failed DUTs, as described in U.S. patent application Ser. No. 10/693,133. Circuitry is then included on a the base PCB or daughter card to assure the delay provided in each line having a buffer is uniform, as described in the application Ser. No. 10/693,133.
- the system might be limited in the number of DUT power supplies it has available. When using a single power supply to drive multiple DUTs, it is desirable to isolate failed or shorted DUTs from affecting the other good devices connected to the same test system controller power supply. It is further desirable to control the power provided since a reduction of power can occur with each channel branch added.
- the present architecture uses voltage regulators, current limiters or switches in series with each DUT power pin to isolate failed DUTs.
- Use of voltage regulators 130 1-4 from a power supply channel 132 of the test system controller 4 is illustrated in FIG. 6 . Although shown provided from the test system controller 4 , power can likewise be provided from separate power supplies.
- the voltage regulators 130 1-4 have power supplied from the test system controller power supply line 132 , and distribute the signal power line to power multiple DUTs 124 1-4 .
- the voltage regulators 130 1-4 function to isolate failed DUTs from the good DUTs operating from the same voltage source by detecting current surges caused by a DUT with a short, or similar fault, and then cutting off or minimizing current to the DUT.
- the voltage regulators 130 1-4 can be replaced by switches or current limiters with similar feedback enabling isolation of a failed DUT.
- the present architecture provides for increasing power from a DUT power supply channel to enable a single power supply to drive more DUTs.
- a DC/DC converter 134 is provided on daughter card 100 between the test system controller 4 and the DUT voltage regulators 130 1-4 to provide additional DUT power.
- the test system controller power supplies generally have a programmable voltage output with a fixed maximum current. Many new silicon devices operate at lower voltages. Hence, the test system controller can be programmed to a higher voltage and the DC/DC converter 134 can regulate down to a lower voltage and higher current enabling the test system controller power supply to drive more DUTs.
- an embodiment of the present invention provides for calibration and monitoring of the voltage regulators 130 1-4 , as well as other probe card components.
- the micro-controller 110 is shown connected to monitor the output of voltage regulators voltage regulators 130 1-4 to determine when current is cut off due to a DUT failure.
- the micro-controller 110 , or other processor or discrete components of the probe card can be configured to calibrate the voltage regulators 130 1-4 to enable accurate control of the voltage provided from the regulators. Control signals can then be provided from the micro-controller 110 , or other component to control the voltage output through the regulators 130 1-4 .
- test system controller can generally monitor each channel for integrity. When test system controller resources are distributed among several DUTs and components are added to isolate DUTs, probe card integrity checks made by the test system controller may no longer be valid checks of the test system.
- the present architecture performs self testing of a combination of the micro-controller 110 , serial-parallel register (controller) 146 , multiplexers 140 and 142 , D/A converter 144 , A/D converter 147 and other circuit components used to assure integrity of the test functions added to the probe card.
- the modes of operation performed with the micro-controller 110 , or processing units on other daughter cards or the base PCB 30 provide for self test allowing the individual daughter card PCB assemblies and base PCB assembly to be tested.
- the probe card can be configured, or include software in memory to provide for self-testing. Test results are reported from the probe card to the test system controller 4 , or other user interface.
- the micro-controller 110 or other processor, can also include a programmable mode allowing the probe card to be reconfigured to allow probe card testing using standard probe card test metrology tools.
- a standard metrology tool which may be used is the probeWoRx system manufactured by Applied Precision Inc. Use of a probe card with such programmable modes allows self test to be performed in the wafer production test environment.
- the micro-controller 110 can include a mode to monitor and report the “health” or performance of the probe card in real time.
- the micro-controller 110 is shown receiving the output of voltage regulators 130 1-4 , illustrating its “health” reporting function if a DUT has failed.
- Circuitry on the probe card to provide for calibration of the regulators 130 1-4 , as well as other components of the probe card, can further assure the accuracy of “health” monitoring.
- the micro-controller 110 , or other circuitry on the probe card can likewise be connected to monitor the “health” of DUTs, or to assure the base PCB and daughter card components are functioning properly and report results to the test system controller 4 , or other user interface.
- the micro-controller 110 can provide for event logging.
- Events logged can, for example, include a test history, wafer statistics, pass/fail statistics, DUT site/pin failures, or other data desired when testing using the probe card.
- Memory included on the probe card can be used to store the event log data.
- a serial bus 145 is provided with the present architecture.
- the micro-controller 110 in FIG. 6 provides a serial bus interface in one embodiment to control the serial bus 145 without additional area overhead.
- the serial bus 145 of the probe card allows for distribution of the probe card built in self test (BIST) features with a minimum number of interface wires.
- the serial bus is a key enabler of the probe card BIST functionality.
- the serial interface bus 145 is provided between the daughter card 100 (and other daughter cards if used) and base PCB 30 .
- the serial bus enables communication between the base PCB 30 and daughter cards with a minimum number of connector and wiring resources.
- the serial to parallel converter, such as serial-parallel shift register 146 is provided on the base PCB 30 for distributing the serial bus signals to individual DUTs internal to the PCB 30 with a minimum amount of routing lines and connector resources.
- the serial-parallel shifting device 146 may be a programmable controller such as a processor, DSP, FPGA, PLD, or micro-controller providing similar functionality to the micro-controller 110 on daughter card 100 , with a basic function of providing parallel to serial conversion.
- the unit 146 can also be configured to perform self test functions, serve to provide programming or data to other processors on the daughter cards, and serve to provide a daisy chained connection of processors through the serial bus 145 .
- the serial/parallel controller unit 146 can further utilize compressed data formats, and can function to compress and decompress data and test vectors.
- the serial/parallel controller unit 146 can be configured to receive BCD data from components not attached to the serial bus and convert the BCD data to serial data for subsequent distribution. Similar data compression and decompression can be provided by other programmable controllers or processors included on one of the daughter cards 100 and 102 or base PCB 30 of the probe card.
- the serial/parallel controller unit 146 configured as a processor can enable the probe card to support scan test features of the DUT.
- Programmable logic and memory chips can have a serial scan port to provide for scan testing.
- the scan port is typically used in manufacturing to provide for a built in self test (BIST) of the chip, with the scan port not later being connected to a package lead after manufacture.
- BIST built in self test
- scan test features of the DUT can be enabled by the daughter card either in conjunction with or separate from the test system controller 4 .
- the serial bus interface 133 to the test system controller 4 is further shown in FIG. 6 , providing for serial communication from the test system controller 4 with a minimal number of wiring and connector resources.
- the test system controller 4 can route control signals to the serial to parallel converter 146 , or to the micro-controller 110 .
- the serial interface 133 can be provided from the JTAG serial port of the test system controller 4 in one embodiment, with a scan register of the test system controller 4 used to provided serial control signals from the test system controller 4 .
- test system controller 4 is shown to have a serial interface 133 connection with the micro-controller 110 , other type communication interfaces can be provided, such as the parallel interface 135 shown.
- the additional interfaces can be used either in combination with the serial interface, or alone.
- Other types of interfaces can include RF, wireless, network, IR, or various connections as the test system controller 4 may have available.
- interface 135 can be connected to other devices on the probe card either directly or over a bus.
- the serial bus 145 can also be used to distribute analog signals to and from the DUTs.
- the present architecture includes a serial digital to analog converter 144 to convert serial signals to analog form and distribute the signals to multiple DUTs.
- the D/A converter 144 receives a test signal input through the serial bus 145 from the serial-parallel shift register 146 , although the signal could be provided from other components connected to the serial bus 145 .
- the D/A converter 144 can contain multiple D/A converters per package (typically 8, 16 or 32 per package) that are connected to the serial interface bus 145 for delivering analog voltages to the DUTs with a minimum wiring and PCB area.
- An A/D converter 147 is further included to receive analog signals from the DUTs and convert to a digital form to provide signals over the serial bus, preferably to the serial-parallel shift register.
- An analog multiplexer 142 is further provided to provide feedback from the outputs of the voltage regulators 130 1-4 to the micro-controller 110 to enable the micro-controller to assure the voltage regulators 130 1-4 are functioning properly for both self test, and test integrity assurance.
- FIG. 7 shows an alternative circuit diagram to FIG. 6 for components that may be used on the probe card of FIG. 5 .
- the circuit of FIG. 7 modifies FIG. 6 by using an FPGA 150 to replace the serial-parallel shift register 146 , as well as serial DAC 144 , and serial ADC 147 on the base PCB 30 .
- the FPGA 150 can include an on-board micro-controller, or be programmed/configured to provide the function of a micro-controller 110 .
- the micro-controller 110 of FIG. 6 is, thus, shown removed in FIG. 7 with its function assumed by FPGA 150 .
- the FPGA 150 of FIG. 7 can be programmed to perform the function of analog multiplexer 142 of FIG. 6 .
- the output of voltage regulators 130 1-4 are, thus, shown in FIG. 7 provided to the FPGA 150 and the analog multiplexer 142 of FIG. 6 is removed in FIG. 7 .
- Other components are carried over from FIG. 6 to FIG. 7 , and are similarly labeled.
- the FPGA 150 can be programmed or configured by a program such as Verilog. Programming or configuration of the FPGA 150 can be provided prior to installation of the FPGA 150 on the probe card. Programming or configuration of the FPGA 150 can further be performed after installation using the test system controller 4 or other user interface connected to the probe card.
- the FPGA 150 can be reconfigured based on responses from one or more DUTs to facilitate specific tests required for the DUTs.
- Programming of the FPGA may be based on the design database or test bench of the DUT.
- the output of a Computer Aided Design (CAD) design system used to develop the DUT may be used to synthesize the test program loaded into the FPGA or micro-controller program memory located on the probe card.
- the CAD design data base can be used directly or post-processed by design or CAD tools used to design the probe card. In this way, a standard or semi-standard daughter card, base PCB, or space transformer mounted controller assembly may be used and customized by software for testing specific DUT designs.
- the FPGA 150 is preferably located on the base PCB 150 to minimize the number of routing lines and connectors between a daughter card 132 and the base PCB 30 , although it is conceivable the FPGA 150 could be included on daughter card 100 .
- the FPGA 150 is shown providing a serial interface to serial bus 145 to provide efficient communications with the test system controller 4 .
- Signal, power and ground traces in a probe card are described previously as being routed with some type of space transformation, either using the space transformer 34 or base PCB 30 . Once these traces are manufactured, there is little flexibility in making changes. Flexibility can be built into probe cards by ICs such as relays, switches, or an FPGA to provide controllable rerouting of the traces. Using a programmable or controllable IC to route signals provides a great degree of flexibility, allowing the same probe card to be used for many designs by simply reprogramming the IC. In one embodiment, the ICs are controlled or programmed from automatic test equipment attached to the probe, allowing test engineers to re-program the probe card in real time as they were debugging a test program.
- the FPGA 150 can be configured to provide programmable line routing.
- the FPGA 150 can function to control routing along with providing a serial-parallel shift function, or function to control trace routing without providing any serial-parallel shifting.
- Other programmable ICs such as a PLD or simple programmable switches, can similarly be used to provide the programmable trace routing.
- connectors 24 distribute signals from the test system controller 4 to connectors 24 of the base PCB 30 .
- Channel transmission lines 40 then distribute signals from the connectors 24 horizontally in the PCB 30 for connection to DUTs.
- the channel transmission lines 40 of the PCB are routed through the FPGA 150 on the base PCB 30 to enable routing resources of the test system controller 4 to be programmably connectable to different DUTs.
- the FPGA 150 simply serves as a programmable switch matrix.
- resources from the test system controller 4 are provided either serially or directly to an FPGA 150 on a daughtercard, or on the space transformer 34 to enable programmable connection of test system controller resources to different DUTs. Connection to the FPGA 150 either through the test system controller 4 , or through a separate connection from a user interface to the FPGA 150 on the probe card allows the FPGA 150 to be reprogrammed to reconfigure trace routing as desired.
- an old generation test system controller might be a 32 DUT test system controller that operates at 33 MHz.
- the test system controller can be expanded to a 256 DUT test system controller operating at the same 33 MHz.
- RA redundancy analysis
- multiplexing of the DUT I/O can enable redundancy analysis testing as well.
- FIGS. 6 and 7 such ability is shown with DUT I/O inputs provided through a multiplexer 140 to the test system controller 4 .
- the multiplexer can be controlled by micro-controller 110 , or the processing unit 146 to route desired DUT I/Os to the test system controller 4 .
- This shared resource or multiplexed test configuration could be very attractive as a wafer level step-burn-in card, where as indicated previously it is desirable to test all DUTs during one touch down during the burn in process.
- the test speed might be reduced by multiplexing of DUT I/Os, but in a burn-in situation, this would generally not be limiting.
- the benefit would be both a wafer level burn-in test system controller solution and possible recovery from burn-in failures with RA either running in the background or provided for in a RA sort after burn in on a separate sort operation.
Abstract
A probe card for a wafer test system is provided with a number of on board features enabling fan out of a test system controller channel to test multiple DUTs on a wafer, while limiting undesirable effects of fan out on test results. On board features of the probe card include one or more of the following: (a) DUT signal isolation provided by placing resistors in series with each DUT input to isolate failed DUTs; (b) DUT power isolation provided by switches, current limiters, or regulators in series with each DUT power pin to isolate the power supply from failed DUTs; (c) self test provided using an on board micro-controller or FPGA; (d) stacked daughter cards provided as part of the probe card to accommodate the additional on board test circuitry; and (e) use of a interface bus between a base PCB and daughter cards of the probe card, or the test system controller to minimize the number of interface wires between the base PCB and daughter cards or between the base PCB and the test system controller.
Description
- 1. Technical Field
- The present invention relates to a probe card configuration for a test system used to test integrated circuits (ICs) on a wafer. More particularly, the present invention relates to a probe card configuration with intelligent on board features that can, for example, enable the probe card to distribute a single channel from a test system controller to multiple test probes to connect to the ICs on a wafer.
- 2. Related Art
- When testing ICs on a wafer, it is cost effective to test as many devices as possible in parallel, thus reducing the test time per wafer. Test system controllers have evolved to increase the number of channels and hence the number of devices that can be tested in parallel. However, a test system controller with increased test channels is a significant cost factor for a test system, as is a probe card with complex routing lines used to accommodate multiple parallel test channels. It is, thus, desirable to provide an overall probe card architecture that allows increased test parallelism without requiring increased test system controller channels and without increased probe card routing complexity.
- With limited test system controller resources, fanning out a signal from a test system controller in the probe card to multiple transmission lines may be desirable, since the increased cost of probe card routing complexity will typically be outweighed by the cost of a new test system controller. A test system controller has resources to enable testing a fixed number of Devices Under Test (DUTs) on a wafer. With advancing technology, more DUTs are fabricated on a single wafer. To avoid the cost of a new test system controller, either multiple touchdowns of a test system to the wafer are performed, or the test signals normally provided to a single DUT are fanned out to multiple DUTs in the probe card. The later may be more desirable for burn in testing where during heating of the wafer, multiple touch downs of the probe card to the wafer is sometimes impractical. Further, less touch downs to the wafer decrease the likelihood of damaging the wafer, and less touch downs limit wear on the probes in the test system, which may be expensive to replace.
- Fan out of the test signals in a probe card between a test system controller and DUTs, however, not only increases the complexity of a system, but also can cause inaccurate test results. To better assure test integrity, increased circuitry can be provided on the probe card to minimize the effect of a fault on one of the fan out lines. With a test system having probe card fan out, a fault (short circuit) in a component connected on a fanned out line will severely attenuate the test signal for all devices on the fanned out test system channels. U.S. Pat. No. 6,603,323 entitled “Closed-Grid Bus Architecture For Wafer Interconnect Structure,” incorporated herein by reference, describes a solution by providing isolation resistors between the channel line branch points and probes to reduce attenuation caused by the faulty component. A further solution is provided in U.S. patent application Ser. No. 10/693,133, incorporated herein by reference, entitled “Isolation Buffers With Controlled Equal Time Delays” describing a system where isolation buffers are used between channel line branch points and probes, with circuitry included to assure the isolation buffers each provide a uniform delay. Other problems, however, may occur with the added circuitry affecting test integrity, as recognized in development of the present invention.
- With the cost of test system controller systems making their long term retention desirable, probe cards are desirable that can further take on expanded test system functions to increase the lifecycle of an outdated test system. Probe cards, serving as an interface between a test system controller and a wafer, are typically much less expensive than a test system controller, and typically replaced after a much shorter lifecycle than the test system controller due to wear of probes on the probe card.
-
FIG. 1 shows a block diagram of a test system using a probe card for testing DUTs on a semiconductor wafer. The test system includes atest system controller 4, or general purpose computer, connected by acommunication cable 6 to a test head 8. The test system further includes aprober 10 made up of astage 12 for mounting awafer 14 being tested, thestage 12 being movable to contact thewafer 14 withprobes 16 on aprobe card 18. Theprober 10 includes theprobe card 18 supportingprobes 16 which contact DUTs formed on thewafer 14. - In the test system, test data is generated by the
test system controller 4 and transmitted through thecommunication cable 6, test head 8,probe card 18,probes 16 and ultimately to DUTs on thewafer 14. Test results are then provided from DUTs on the wafer back through theprobe card 18 to the test head 8 for transmission back to thetest system controller 4. Once testing is complete, the wafer is diced up to separate the DUTs. - Test data provided from the
test system controller 4 is divided into the individual test channels provided through thecable 6 and separated in the test head 8 so that each channel is carried to a separate one of theprobes 16. The channels from the test head 8 are linked byflexible cable connectors 24 to theprobe card 18. Theprobe card 18 then links each channel to a separate one of theprobes 16. -
FIG. 2 shows a cross sectional view of components of atypical probe card 18. Theprobe card 18 is configured to provide both electrical pathways and mechanical support for thespring probes 16 that will directly contact the wafer. The probe card electrical pathways are provided through a printed circuit board (PCB) 30, aninterposer 32, and aspace transformer 34. Test data from the test head 8 is provided throughflexible cable connectors 24 typically connected around the periphery of thePCB 30.Channel transmission lines 40 distribute signals from theconnectors 24 horizontally in thePCB 30 to contact pads on thePCB 30 to match the routing pitch of pads on thespace transformer 34. Theinterposer 32 includes a substrate 42 with spring probeelectrical contacts 44 disposed on both sides. Theinterposer 32 electrically connects individual pads on thePCB 30 to pads forming a land grid array (LGA) on thespace transformer 34. Traces 46 in asubstrate 45 of thespace transformer 34 distribute or “space transform” connections from the LGA tospring probes 16 configured in an array. Thespace transformer substrate 45 is typically constructed from either multi-layered ceramic or organic based laminates. Thespace transformer substrate 45 with embedded circuitry, probes and LGA is referred to as a probe head. - Mechanical support for the electrical components is provided by a
back plate 50, bracket (Probe Head Bracket) 52, frame (Probe Head Stiffener Frame) 54,leaf springs 56, and levelingpins 62. Theback plate 50 is provided on one side of the PCB 30, while thebracket 52 is provided on the other side and attached byscrews 59. Theleaf springs 56 are attached byscrews 58 to thebracket 52. Theleaf springs 56 extend to movably hold theframe 54 within the interior walls of thebracket 52. Theframe 54 then includeshorizontal extensions 60 for supporting thespace transformer 34 within its interior walls. Theframe 54 surrounds the probe head and maintains a close tolerance to thebracket 52 such that lateral motion is limited. -
Leveling pins 62 complete the mechanical support for the electrical elements and provide for leveling of thespace transformer 34. Theleveling pins 62 are adjusted so thatbrass spheres 66 provide a point contact with thespace transformer 34. Thespheres 66 contact outside the periphery of the LGA of the space transformer 34 to maintain isolation from electrical components. Leveling of the substrate is accomplished by precise adjustment of these spheres through the use of advancing screws, or levelingpins 62. Theleveling pins 62 are screwed throughsupports 65 in theback plate 50 and PCB 30. Motion of the levelingpin screws 62 is opposed byleaf springs 56 so thatspheres 66 are kept in contact with thespace transformer 34. -
FIG. 3 shows an exploded assembly view of components of the probe card ofFIG. 2 .FIG. 3 shows attachment of theback plate 50,PCB 30, andbracket 52 using twoscrews 59. Fourleveling screws 62, are provided through theback plate 50 and PCB 30 to contact fourspheres 66 near the corners of thespace transformer substrate 34. Theframe 54 is provided directly over thespace transformer substrate 34, theframe 54 fitting inside thebracket 52. Theleaf springs 56 are attached byscrews 58 to thebracket 52. Twoscrews 58 are shown for reference, although additional screws 58 (not shown) are provided around the entire periphery to attach the leaf springs. -
FIG. 4 shows a perspective view of the opposing side ofPCB 30 illustrating the arrangement ofconnectors 24 around its periphery. InFIG. 3 , theconnectors 24 of thePCB 30 are facing down and not shown. In typical probe cards, the connectors 24 (typically zero insertion force (ZIF) connectors) provide flexible cable connections located around the periphery of the probe card, and are configured to mate with connectors that are typically arranged in a similar fashion on the test head. Although illustrated as ZIF connectors, other connector types may be used, such as pogo pins, non-ZIF flexible cable connectors, conductive elastomer bumps, stamped and formed spring elements, etc. - In accordance with the present invention, a probe card is provided with a number of on board features enabling fan out of a test channel signal to multiple DUTs while limiting undesirable effects of fan out on test results. The on board probe card features further enable enhancing test system controller functions, effectively increasing the lifecycle of some test system controllers, providing more advanced functions without the cost of purchasing a more modern test system controller. The probe card in accordance with the present invention enables significant fan out with test integrity so that probe cards can be used with a limited channel test system controller to test a wafer with one touch down, a particularly desirable feature during burn in tests.
- On board features of the probe card include one or more of the following: (a) DUT signal isolation provided by placing resistors in series with each DUT input to isolate failed DUTs, as described generally in U.S. Pat. No. 6,603,323 reference previously; (b) DUT power isolation provided by switches, current limiters, or regulators in series with each DUT power pin to isolate the power supply from failed DUTs, allowing a single test system controller power supply to power multiple DUTs; (c) self test provided using an on board micro-controller or FPGA and associated multiplexers and D/A converters, on board self testing being necessary with fanned out test system controller resources since test system controller integrity checks may no longer be valid; (d) stacked or vertically oriented daughter cards provided between test system controller connections which form an outline area on the PCB of the probe card, the stacked daughter cards to accommodate additional circuitry used in accordance with the present invention, and to provide the additional circuitry in close proximity to the PCB, space transformer and other components originally forming the probe card; and (e) use of a communications bus between a controller provided on the base PCB and separate daughter cards and the test system controller to minimize the number of interface wires between the base PCB and the daughter cards or between the base PCB and the test system controller. The bus can further be configured to distribute analog signals to the DUTs through the use of serial to parallel D/A or A/D converters on the probe card, providing for minimum wiring and minimum use of PCB area.
- Further details of the present invention are explained with the help of the attached drawings in which:
-
FIG. 1 shows a block diagram of components of a conventional wafer test system; -
FIG. 2 is a cross sectional view of a conventional probe card for the wafer test system ofFIG. 1 ; -
FIG. 3 is an exploded assembly view of components of the probe card ofFIG. 2 ; -
FIG. 4 is a perspective view of the PCB ofFIG. 2 showing connectors for connecting to a test head; -
FIG. 5 shows a cross sectional view of a probe card with on board components in accordance with the present invention; and -
FIG. 6 shows a circuit diagram for components of the probe card ofFIG. 5 ; and -
FIG. 7 shows an alternative circuit diagram for components of the probe card ofFIG. 5 . -
FIG. 5 shows a cross sectional view of a probe card, modified from the probe card configuration shown inFIG. 2 to include on board components, in accordance with the present invention, includingdaughter cards FIG. 2 toFIG. 5 are similarly labeled. The daughter cards are shown inFIG. 5 as connected bystacked connectors 104 1-4. The stacked connectors are attached to opposing card surfaces, and include male and female mating connectors. Forexample connector 104 1 is connected to thebase PCB 30, whileconnector 104 2 is connected todaughter card 100. The stacked connectors can be ZIF, pogo pin, or other type connectors suitable for interconnecting printed circuit boards. The connectors make the daughter cards removable so that different daughter cards can be easily installed, depending on the test environment. Although shown with removable connectors, in one embodiment, the daughter cards can be rigidly connected, such as by soldering. Further, although two daughter cards are shown, a single card or more than two cards can be used, depending on design requirements. - As illustrated, the
daughter cards controller interface connectors 24. The test system controller could be a conventional Automatic Test Equipment (ATE) tester or a computer system used to control and configure the probe card, which can limit the height above theconnectors 24 which the daughter cards can be stacked. In the configuration shown, an opening is provided in theback plate 50, forming an outline area where thedaughter cards base PCB 30. The area of the probe card available for daughter cards is generally dictated by the test system controller connection and prober constraints. With limited horizontal spacing between test systemcontroller interface connectors 24, board area to accommodate additional circuitry for the architecture in accordance with the present invention is obtained by stacking additional daughter cards within the outline area of the probe card. - The
stacked connectors 104 1-4 provide spacing fordiscrete components 114 provided on the surface of each of thebase PCB 30 anddaughter cards discrete components 114 can include bypass capacitors for power supply lines. In one embodiment, similardiscrete components 112 are also provided on a surface of thespace transformer 34. In one embodiment, thediscrete components 112 are decoupling capacitors. To accommodate thediscrete components 112, a number ofspring contacts 44 are removed from theinterposer 32, and rerouting of lines is provided in thespace transformer 34. With thediscrete components 112 being decoupling capacitors they are placed in close proximity to lines carrying power toprobes 16 to maximize capacitance on the power lines that affect test results. By being placed in close proximity to where capacitance will improve the decoupling, smaller capacitances can be used for thecapacitors 110. - The daughter cards, such as 100 and 102 shown, may be redundant with the
base PCB 30, in that they carry the same discrete components on their surface. More redundant daughter cards can be simply added if more fan out of test channels is desired. Alternatively, the daughter cards can include differing components depending on test requirements and available space. - The
daughter card 102 is shown to include amicro-controller 110 as adiscrete component 114. Although shown ondaughter card 102, similar micro-controllers can be provided on one or more of thedaughter card 102,daughter card 100,base PCB 30, andspace transformer 34. Themicro-controller 110 may be any of a variety of programmable controllers including a microprocessor, digital signal processor, sequencer, Field Programmable Gate Array (FPGA), Programmable Logic Device (PLD) or other controller or device that can be programmed/configured as a controller for generating and providing test or control signals to electrical circuits. In one embodiment, themicro-controller 110 is the Microchip PIC18FXX20 with A/D capability. - The
discrete components 114 on a daughter card orbase PCB micro-controller 110, or by another processor either on the probe card, or external to the probe card. The memory can be a random access memory (RAM) providing temporary storage, or a device providing more permanent storage such as a flash memory. To enable themicro-controller 110, or other processor to perform testing, the memory can be programmed to include test vectors or a test program. Similarly, the memory can include system configuration data. - The circuitry can also be organized such that, in concert with the DUT, a full system is created for evaluating the DUT. For example, the daughter card and probe card circuitry could include support circuits for a personal computer motherboard if the DUT is an Intel or other microprocessor. On power up, the DUT will experience an electrical environment like the final use environment. In this way, a test of operating correctness can be performed on unpackaged DUT devices.
- To accommodate the
micro-controller 110 and memory, or other discrete components which can generate a significant amount of heat, a temperature control system can be included along with thediscrete components 114 on the probecard daughter cards base PCB 30. The temperature control system can include temperature sensors, along with heat sinks, fans, electric coolers, heaters, or other devices needed to maintain component temperatures within a desired range. -
Discrete components 114 in addition to themicro-controller 110 and memory can, for example, include voltage regulators, relays, multiplexers, switches, D/A converters, A/D converters, shift registers, etc. Examples for the configuration of the discrete components are shown in the circuit diagrams ofFIG. 6 andFIG. 7 . Further details of these components, as well as other features included on the probe card in accordance with the present invention are described below. - A. DUT Signal Isolation
- In one embodiment the
space transformer 34 includes thin film resistors placed in series with each probe that provides a DUT input. Suchthin film resistors 120 1-4, providing signals from a single channel oftest system controller 4 to inputs ofDUTs 124 1-4 are illustrated inFIG. 6 . As described previously, the architecture in accordance with the present invention uses embedded resistors, such asresistors 120 1-4, in thespace transformer 34 placed in series with each DUT input to isolate failed or shorted DUTs from good DUT inputs. Thespace transformer 34, illustrated inFIG. 5 , is typically a multi-layer ceramic substrate, or may be made up of a multi-layer organic substrate, with thethin film resistors 120 1-4 provided on one or more layers in the path of routing lines to the probes. Use of such DUT isolation resistors is described in U.S. Pat. No. 6,603,323, reference previously. In one embodiment, resistors have values ranging between 50 and 5000 ohms each. Values on the order of 1000 ohms allow a single DUT channel to drive 10 to 100 DUTs at frequencies between 5 and 50 MHz. Placement of the embedded resistors close to the DUT is key to enabling maximum performance while at the same time not increasing the size of the probe head. Discrete or surface mounted resistors could also be used for this DUT isolation application. - In a further embodiment, as an alternative to series resistors, buffers are placed in series with each DUT input to isolate failed DUTs, as described in U.S. patent application Ser. No. 10/693,133. Circuitry is then included on a the base PCB or daughter card to assure the delay provided in each line having a buffer is uniform, as described in the application Ser. No. 10/693,133.
- B. DUT Power Isolation and Power Control
- The system might be limited in the number of DUT power supplies it has available. When using a single power supply to drive multiple DUTs, it is desirable to isolate failed or shorted DUTs from affecting the other good devices connected to the same test system controller power supply. It is further desirable to control the power provided since a reduction of power can occur with each channel branch added.
- The present architecture uses voltage regulators, current limiters or switches in series with each DUT power pin to isolate failed DUTs. Use of
voltage regulators 130 1-4 from apower supply channel 132 of thetest system controller 4 is illustrated inFIG. 6 . Although shown provided from thetest system controller 4, power can likewise be provided from separate power supplies. Thevoltage regulators 130 1-4 have power supplied from the test system controllerpower supply line 132, and distribute the signal power line to powermultiple DUTs 124 1-4. Thevoltage regulators 130 1-4 function to isolate failed DUTs from the good DUTs operating from the same voltage source by detecting current surges caused by a DUT with a short, or similar fault, and then cutting off or minimizing current to the DUT. Although shown as a voltage regulator inFIG. 6 , thevoltage regulators 130 1-4 can be replaced by switches or current limiters with similar feedback enabling isolation of a failed DUT. - In addition to power supply isolation, the present architecture provides for increasing power from a DUT power supply channel to enable a single power supply to drive more DUTs. To increase power, a DC/
DC converter 134 is provided ondaughter card 100 between thetest system controller 4 and theDUT voltage regulators 130 1-4 to provide additional DUT power. The test system controller power supplies generally have a programmable voltage output with a fixed maximum current. Many new silicon devices operate at lower voltages. Hence, the test system controller can be programmed to a higher voltage and the DC/DC converter 134 can regulate down to a lower voltage and higher current enabling the test system controller power supply to drive more DUTs. - To assure a precise voltage is provided to the test system, an embodiment of the present invention provides for calibration and monitoring of the
voltage regulators 130 1-4, as well as other probe card components. Themicro-controller 110 is shown connected to monitor the output of voltageregulators voltage regulators 130 1-4 to determine when current is cut off due to a DUT failure. In addition to receiving a current signal, themicro-controller 110, or other processor or discrete components of the probe card can be configured to calibrate thevoltage regulators 130 1-4 to enable accurate control of the voltage provided from the regulators. Control signals can then be provided from themicro-controller 110, or other component to control the voltage output through theregulators 130 1-4. - C. Probe Card Self Test
- As parallelism for testing is provided by fan out in the probe card and test functionality is moved onto the probe card, it becomes desirable to include features on the probe card to insure probe card test function integrity without requiring additional test system controller functionality. In a conventional probe card, the test system controller can generally monitor each channel for integrity. When test system controller resources are distributed among several DUTs and components are added to isolate DUTs, probe card integrity checks made by the test system controller may no longer be valid checks of the test system.
- Accordingly, in one embodiment shown in
FIG. 6 the present architecture performs self testing of a combination of themicro-controller 110, serial-parallel register (controller) 146,multiplexers 140 and 142, D/Aconverter 144, A/D converter 147 and other circuit components used to assure integrity of the test functions added to the probe card. The modes of operation performed with themicro-controller 110, or processing units on other daughter cards or thebase PCB 30 provide for self test allowing the individual daughter card PCB assemblies and base PCB assembly to be tested. - The probe card can be configured, or include software in memory to provide for self-testing. Test results are reported from the probe card to the
test system controller 4, or other user interface. Themicro-controller 110, or other processor, can also include a programmable mode allowing the probe card to be reconfigured to allow probe card testing using standard probe card test metrology tools. One example of a standard metrology tool which may be used is the probeWoRx system manufactured by Applied Precision Inc. Use of a probe card with such programmable modes allows self test to be performed in the wafer production test environment. - Apart from a self test mode, the
micro-controller 110, or other processor of the probe card can include a mode to monitor and report the “health” or performance of the probe card in real time. As one example, themicro-controller 110 is shown receiving the output ofvoltage regulators 130 1-4, illustrating its “health” reporting function if a DUT has failed. Circuitry on the probe card to provide for calibration of theregulators 130 1-4, as well as other components of the probe card, can further assure the accuracy of “health” monitoring. Themicro-controller 110, or other circuitry on the probe card can likewise be connected to monitor the “health” of DUTs, or to assure the base PCB and daughter card components are functioning properly and report results to thetest system controller 4, or other user interface. - In addition to self-test and real time “health” monitoring, the
micro-controller 110, or other processor of the probe card can provide for event logging. Events logged can, for example, include a test history, wafer statistics, pass/fail statistics, DUT site/pin failures, or other data desired when testing using the probe card. Memory included on the probe card can be used to store the event log data. - D. Serial Bus Interface
- To minimize the amount of routing lines and connector resources needed with use of the daughter cards, a
serial bus 145 is provided with the present architecture. Themicro-controller 110 inFIG. 6 provides a serial bus interface in one embodiment to control theserial bus 145 without additional area overhead. Theserial bus 145 of the probe card allows for distribution of the probe card built in self test (BIST) features with a minimum number of interface wires. The serial bus is a key enabler of the probe card BIST functionality. - The
serial interface bus 145 is provided between the daughter card 100 (and other daughter cards if used) andbase PCB 30. The serial bus enables communication between thebase PCB 30 and daughter cards with a minimum number of connector and wiring resources. The serial to parallel converter, such as serial-parallel shift register 146 is provided on thebase PCB 30 for distributing the serial bus signals to individual DUTs internal to thePCB 30 with a minimum amount of routing lines and connector resources. - Although shown as a simple serial-parallel shift register, the serial-
parallel shifting device 146 may be a programmable controller such as a processor, DSP, FPGA, PLD, or micro-controller providing similar functionality to themicro-controller 110 ondaughter card 100, with a basic function of providing parallel to serial conversion. As a processor, theunit 146 can also be configured to perform self test functions, serve to provide programming or data to other processors on the daughter cards, and serve to provide a daisy chained connection of processors through theserial bus 145. - As a processor, the serial/
parallel controller unit 146 can further utilize compressed data formats, and can function to compress and decompress data and test vectors. For example, the serial/parallel controller unit 146 can be configured to receive BCD data from components not attached to the serial bus and convert the BCD data to serial data for subsequent distribution. Similar data compression and decompression can be provided by other programmable controllers or processors included on one of thedaughter cards base PCB 30 of the probe card. - Similarly, the serial/
parallel controller unit 146 configured as a processor can enable the probe card to support scan test features of the DUT. Programmable logic and memory chips can have a serial scan port to provide for scan testing. The scan port is typically used in manufacturing to provide for a built in self test (BIST) of the chip, with the scan port not later being connected to a package lead after manufacture. With a connection of a DUT scan port to the serial/parallel controller unit, or other scan test circuitry attached to the serial bus, scan test features of the DUT can be enabled by the daughter card either in conjunction with or separate from thetest system controller 4. - The
serial bus interface 133 to thetest system controller 4 is further shown inFIG. 6 , providing for serial communication from thetest system controller 4 with a minimal number of wiring and connector resources. With theserial interface 133, thetest system controller 4 can route control signals to the serial toparallel converter 146, or to themicro-controller 110. Theserial interface 133 can be provided from the JTAG serial port of thetest system controller 4 in one embodiment, with a scan register of thetest system controller 4 used to provided serial control signals from thetest system controller 4. - Although the
test system controller 4 is shown to have aserial interface 133 connection with themicro-controller 110, other type communication interfaces can be provided, such as theparallel interface 135 shown. The additional interfaces can be used either in combination with the serial interface, or alone. Other types of interfaces can include RF, wireless, network, IR, or various connections as thetest system controller 4 may have available. Although shown connected only to themicro-controller 110,interface 135 can be connected to other devices on the probe card either directly or over a bus. - The
serial bus 145 can also be used to distribute analog signals to and from the DUTs. The present architecture includes a serial digital toanalog converter 144 to convert serial signals to analog form and distribute the signals to multiple DUTs. The D/A converter 144 receives a test signal input through theserial bus 145 from the serial-parallel shift register 146, although the signal could be provided from other components connected to theserial bus 145. The D/A converter 144 can contain multiple D/A converters per package (typically 8, 16 or 32 per package) that are connected to theserial interface bus 145 for delivering analog voltages to the DUTs with a minimum wiring and PCB area. An A/D converter 147 is further included to receive analog signals from the DUTs and convert to a digital form to provide signals over the serial bus, preferably to the serial-parallel shift register. An analog multiplexer 142 is further provided to provide feedback from the outputs of thevoltage regulators 130 1-4 to themicro-controller 110 to enable the micro-controller to assure thevoltage regulators 130 1-4 are functioning properly for both self test, and test integrity assurance. -
FIG. 7 shows an alternative circuit diagram toFIG. 6 for components that may be used on the probe card ofFIG. 5 . The circuit ofFIG. 7 modifiesFIG. 6 by using anFPGA 150 to replace the serial-parallel shift register 146, as well asserial DAC 144, andserial ADC 147 on thebase PCB 30. - The
FPGA 150 can include an on-board micro-controller, or be programmed/configured to provide the function of amicro-controller 110. Themicro-controller 110 ofFIG. 6 is, thus, shown removed inFIG. 7 with its function assumed byFPGA 150. Similarly, theFPGA 150 ofFIG. 7 can be programmed to perform the function of analog multiplexer 142 ofFIG. 6 . The output ofvoltage regulators 130 1-4 are, thus, shown inFIG. 7 provided to theFPGA 150 and the analog multiplexer 142 ofFIG. 6 is removed inFIG. 7 . Other components are carried over fromFIG. 6 toFIG. 7 , and are similarly labeled. - The
FPGA 150 can be programmed or configured by a program such as Verilog. Programming or configuration of theFPGA 150 can be provided prior to installation of theFPGA 150 on the probe card. Programming or configuration of theFPGA 150 can further be performed after installation using thetest system controller 4 or other user interface connected to the probe card. TheFPGA 150 can be reconfigured based on responses from one or more DUTs to facilitate specific tests required for the DUTs. - Programming of the FPGA may be based on the design database or test bench of the DUT. In one embodiment, the output of a Computer Aided Design (CAD) design system used to develop the DUT may be used to synthesize the test program loaded into the FPGA or micro-controller program memory located on the probe card. The CAD design data base can be used directly or post-processed by design or CAD tools used to design the probe card. In this way, a standard or semi-standard daughter card, base PCB, or space transformer mounted controller assembly may be used and customized by software for testing specific DUT designs.
- The
FPGA 150 is preferably located on thebase PCB 150 to minimize the number of routing lines and connectors between adaughter card 132 and thebase PCB 30, although it is conceivable theFPGA 150 could be included ondaughter card 100. TheFPGA 150 is shown providing a serial interface toserial bus 145 to provide efficient communications with thetest system controller 4. - F. Programmable Routing
- Signal, power and ground traces in a probe card are described previously as being routed with some type of space transformation, either using the
space transformer 34 orbase PCB 30. Once these traces are manufactured, there is little flexibility in making changes. Flexibility can be built into probe cards by ICs such as relays, switches, or an FPGA to provide controllable rerouting of the traces. Using a programmable or controllable IC to route signals provides a great degree of flexibility, allowing the same probe card to be used for many designs by simply reprogramming the IC. In one embodiment, the ICs are controlled or programmed from automatic test equipment attached to the probe, allowing test engineers to re-program the probe card in real time as they were debugging a test program. - In one embodiment, the
FPGA 150, as shown inFIG. 7 , can be configured to provide programmable line routing. TheFPGA 150 can function to control routing along with providing a serial-parallel shift function, or function to control trace routing without providing any serial-parallel shifting. Other programmable ICs, such as a PLD or simple programmable switches, can similarly be used to provide the programmable trace routing. - As described previously,
connectors 24 distribute signals from thetest system controller 4 toconnectors 24 of thebase PCB 30.Channel transmission lines 40 then distribute signals from theconnectors 24 horizontally in thePCB 30 for connection to DUTs. In one embodiment, thechannel transmission lines 40 of the PCB are routed through theFPGA 150 on thebase PCB 30 to enable routing resources of thetest system controller 4 to be programmably connectable to different DUTs. TheFPGA 150 simply serves as a programmable switch matrix. In other embodiments, resources from thetest system controller 4 are provided either serially or directly to anFPGA 150 on a daughtercard, or on thespace transformer 34 to enable programmable connection of test system controller resources to different DUTs. Connection to theFPGA 150 either through thetest system controller 4, or through a separate connection from a user interface to theFPGA 150 on the probe card allows theFPGA 150 to be reprogrammed to reconfigure trace routing as desired. - F. Combined Features
- The features of an architecture described in sections A-E previously can be used either individually, or combined as test requirements may dictate. A significant increase in the ability to fan out a test signal can be realized with features described according to the present invention. For example, an old generation test system controller might be a 32 DUT test system controller that operates at 33 MHz. Using the intelligent probe card architecture described herein, the test system controller can be expanded to a 256 DUT test system controller operating at the same 33 MHz. If the test system controller has redundancy analysis (RA) capability, multiplexing of the DUT I/O can enable redundancy analysis testing as well. In
FIGS. 6 and 7 , such ability is shown with DUT I/O inputs provided through amultiplexer 140 to thetest system controller 4. The multiplexer can be controlled bymicro-controller 110, or theprocessing unit 146 to route desired DUT I/Os to thetest system controller 4. - This shared resource or multiplexed test configuration could be very attractive as a wafer level step-burn-in card, where as indicated previously it is desirable to test all DUTs during one touch down during the burn in process. The test speed might be reduced by multiplexing of DUT I/Os, but in a burn-in situation, this would generally not be limiting. The benefit would be both a wafer level burn-in test system controller solution and possible recovery from burn-in failures with RA either running in the background or provided for in a RA sort after burn in on a separate sort operation.
- Although the present invention has been described above with particularity, this was merely to teach one of ordinary skill in the art how to make and use the invention. Many additional modifications will fall within the scope of the invention, as that scope is defined by the following claims.
Claims (22)
1-35. (canceled)
36: A test assembly for communicating test data between a test system controller and an unpackaged semiconductor device under test, the unpackaged semiconductor device designed for use in an operational environment, the test assembly comprising:
a probe card for providing connection to the test system controller to communicate test information with the test system controller and having a plurality of resilient probes configured to mechanically and electrically contact the unpackaged semiconductor device to communicate signals to or from the unpackaged semiconductor device; and
circuitry comprising at least a portion of the operational environment.
37: The test assembly of claim 36 , wherein the circuitry includes circuit portions of a personal computer motherboard.
38: The test assembly of claim 36 , wherein an unpackaged semiconductor device is a microprocessor.
37: The test assembly of claim 36 , wherein the circuitry emulates the operational environment power up sequence for the unpackaged semiconductor device.
38: The test assembly of claim 36 , wherein the probe card further comprises a wiring substrate and at least a portion of the circuitry resides on the wiring substrate.
39: The test assembly of claim 36 , wherein the probe card further comprises a probe support substrate and at least a portion of the circuitry resides on the probe support substrate.
40: The test assembly of claim 36 , wherein the probe card further comprises a daughter card mechanically and electrically coupled to the probe card and wherein at least a portion of the circuitry resides on the daughter card.
41: A method of testing an unpackaged semiconductor device with a testing assembly, the unpackaged semiconductor device designed for use in an operational environment, the method comprising:
providing a probe card for making connection to a test system controller to communicate test information and having a plurality of resilient probes configured to mechanically and electrically contact the unpackaged semiconductor device to communicate signals to or from the unpackaged semiconductor device;
providing circuitry including a portion of the operational environment;
bringing into contact the resilient probes and the unpackaged semiconductor device; and
testing the unpackaged semiconductor device with the circuitry to emulate a portion of the operational environment.
42: The method of claim 41 , wherein the providing circuitry comprises providing support circuits from a desired motherboard configuration.
43: The method of claim 41 , wherein the testing includes a power up sequence.
44: The method of claim 41 , wherein the circuitry emulates the operational environment power up sequence for the unpackaged semiconductor device.
45: The method of claim 41 , wherein the providing the circuitry comprises providing at least a portion of the circuitry on a wiring substrate.
46: The method of claim 41 , wherein the providing the circuitry comprises providing at least a portion of the circuitry on a probe support substrate.
47: The method of claim 41 , wherein the providing the circuitry comprises providing at least a portion of the circuitry on a daughter card mechanically and electrically coupled to the probe card.
48: A method of producing a tested semiconductor device, the semiconductor device designed for use in an operational environment, the method comprising:
providing a probe card for making connection to a test system controller to communicate test information and having a plurality of resilient probes configured to mechanically and electrically contact an unpackaged semiconductor device to communicate signals to or from the unpackaged semiconductor device;
providing circuitry including a portion of the operational environment;
bringing into contact the resilient probes and the unpackaged semiconductor device; and
testing the unpackaged semiconductor device with the circuitry to emulate a portion of the operational environment.
49: The method of claim 48 , wherein the providing circuitry comprises providing support circuits from a desired motherboard configuration.
50: The method of claim 48 , wherein the testing includes a power up sequence.
51: The method of claim 48 , wherein the circuitry emulates the operational environment power up sequence for the unpackaged semiconductor device.
52: The method of claim 48 , wherein the providing circuitry comprises providing at least a portion of the circuitry on a wiring substrate.
53: The method of claim 48 , wherein the providing circuitry comprises providing at least a portion of the circuitry on a probe support substrate.
54: The method of claim 48 , wherein the providing circuitry comprises providing at least a portion of the circuitry on a daughter card mechanically and electrically coupled to the probe card.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/001,281 US20080100320A1 (en) | 2004-04-21 | 2007-12-11 | Intelligent probe card architecture |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/828,755 US7307433B2 (en) | 2004-04-21 | 2004-04-21 | Intelligent probe card architecture |
US12/001,281 US20080100320A1 (en) | 2004-04-21 | 2007-12-11 | Intelligent probe card architecture |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/828,755 Division US7307433B2 (en) | 2004-04-21 | 2004-04-21 | Intelligent probe card architecture |
Publications (1)
Publication Number | Publication Date |
---|---|
US20080100320A1 true US20080100320A1 (en) | 2008-05-01 |
Family
ID=35135788
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/828,755 Active 2024-09-24 US7307433B2 (en) | 2004-04-21 | 2004-04-21 | Intelligent probe card architecture |
US12/001,281 Abandoned US20080100320A1 (en) | 2004-04-21 | 2007-12-11 | Intelligent probe card architecture |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/828,755 Active 2024-09-24 US7307433B2 (en) | 2004-04-21 | 2004-04-21 | Intelligent probe card architecture |
Country Status (7)
Country | Link |
---|---|
US (2) | US7307433B2 (en) |
EP (1) | EP1743182A4 (en) |
JP (1) | JP2007534943A (en) |
KR (2) | KR20070006917A (en) |
CN (2) | CN1947022B (en) |
TW (1) | TWI376504B (en) |
WO (1) | WO2005103740A2 (en) |
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060273809A1 (en) * | 2004-04-21 | 2006-12-07 | Formfactor, Inc. | Method of designing an application specific probe card test system |
US20070261009A1 (en) * | 2005-01-31 | 2007-11-08 | Formfactor, Inc. | Programmable devices to route signals on probe cards |
US20080157808A1 (en) * | 1993-11-16 | 2008-07-03 | Formfactor, Inc. | Wafer-level burn-in and test |
US7579269B2 (en) | 1993-11-16 | 2009-08-25 | Formfactor, Inc. | Microelectronic spring contact elements |
US20100169481A1 (en) * | 2008-12-31 | 2010-07-01 | Tsan-Fu Hung | Test system for semiconductor devices based on network monitoring |
US20100219852A1 (en) * | 2007-07-19 | 2010-09-02 | Nhk Spring Co., Ltd | Probe card |
WO2011022301A2 (en) * | 2009-08-18 | 2011-02-24 | Formfactor, Inc. | Wafer level contactor |
US20110128022A1 (en) * | 2009-12-02 | 2011-06-02 | Samsung Electronics Co., Ltd. | Testing apparatus and method |
US20120194212A1 (en) * | 2011-01-27 | 2012-08-02 | January Kister | Fine pitch guided vertical probe array having enclosed probe flexures |
WO2012125606A2 (en) * | 2011-03-16 | 2012-09-20 | Formfactor, Inc. | Wireless probe card verification system and method |
US20130027072A1 (en) * | 2011-07-28 | 2013-01-31 | Star Technologies Inc. | Probing apparatus for semiconductor devices |
US20130141130A1 (en) * | 2011-12-05 | 2013-06-06 | Chia-Huang Wang | Wafer Probe Card |
US8541889B2 (en) * | 2010-12-30 | 2013-09-24 | Samsung Electronics Co., Ltd. | Probe card including frame and cover plate for testing a semiconductor device |
US20140062522A1 (en) * | 2012-08-31 | 2014-03-06 | Erkan Acar | Space Transformation Methods |
US20140062501A1 (en) * | 2012-09-06 | 2014-03-06 | Tpk Touch Solutions (Xiamen) Inc. | Electrical connection assembly and testing method thereof |
US20140103948A1 (en) * | 2010-03-11 | 2014-04-17 | Mpi Corporation | Probe card having configurable structure for exchanging or swapping electronic components for impedance matching |
US20150089289A1 (en) * | 2013-09-26 | 2015-03-26 | Texas Instruments, Incorporated | Programmable interface-based validation and debug |
US9476911B2 (en) | 2004-05-21 | 2016-10-25 | Microprobe, Inc. | Probes with high current carrying capability and laser machining methods |
US20190163344A1 (en) * | 2013-03-29 | 2019-05-30 | Sony Corporation | Information processing apparatus, information processing method, and recording medium |
TWI794925B (en) * | 2020-11-05 | 2023-03-01 | 韓商Sda有限公司 | Probe card |
Families Citing this family (107)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6856150B2 (en) * | 2001-04-10 | 2005-02-15 | Formfactor, Inc. | Probe card with coplanar daughter card |
US8177129B2 (en) * | 2004-02-17 | 2012-05-15 | Timothy D. Larin | Interactive multimedia smart affinity card with flash memory |
US7307433B2 (en) * | 2004-04-21 | 2007-12-11 | Formfactor, Inc. | Intelligent probe card architecture |
US20120212248A9 (en) * | 2004-06-16 | 2012-08-23 | Fu Chiung Chong | Construction Structures and Manufacturing Processes for Integrated Circuit Wafer Probe Card Assemblies |
DE102004035556B3 (en) * | 2004-07-22 | 2005-12-08 | Infineon Technologies Ag | Method and device, in particular probecard, for calibrating a semiconductor device test system, in particular a semiconductor device test device |
US20060038576A1 (en) * | 2004-08-19 | 2006-02-23 | Pooya Tadayon | Sort interface unit having probe capacitors |
US7088118B2 (en) * | 2004-12-15 | 2006-08-08 | Chipmos Technologies (Bermuda) Ltd. | Modularized probe card for high frequency probing |
US7343558B2 (en) * | 2005-03-31 | 2008-03-11 | Teradyne, Inc. | Configurable automatic-test-equipment system |
US20070023879A1 (en) * | 2005-07-29 | 2007-02-01 | Vinayak Pandey | Single unit heat sink, voltage regulator, and package solution for an integrated circuit |
JP4800007B2 (en) * | 2005-11-11 | 2011-10-26 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor integrated circuit device and probe card |
JP4823667B2 (en) * | 2005-12-05 | 2011-11-24 | 日本発條株式会社 | Probe card |
WO2007090465A1 (en) * | 2006-02-08 | 2007-08-16 | Verigy (Singapore) Pte. Ltd. | Testing devices under test by an automatic test apparatus having a multisite probe card |
US7906982B1 (en) * | 2006-02-28 | 2011-03-15 | Cypress Semiconductor Corporation | Interface apparatus and methods of testing integrated circuits using the same |
US7495458B2 (en) * | 2006-05-17 | 2009-02-24 | Texas Instruments Incorporated | Probe card and temperature stabilizer for testing semiconductor devices |
MY147251A (en) * | 2006-05-23 | 2012-11-14 | Integrated Technology Corp | Probe needle protection method for high current probe testing of power devices |
US7521947B2 (en) * | 2006-05-23 | 2009-04-21 | Integrated Technology Corporation | Probe needle protection method for high current probe testing of power devices |
US7557592B2 (en) * | 2006-06-06 | 2009-07-07 | Formfactor, Inc. | Method of expanding tester drive and measurement capability |
US7649366B2 (en) * | 2006-09-01 | 2010-01-19 | Formfactor, Inc. | Method and apparatus for switching tester resources |
US20080100323A1 (en) * | 2006-10-25 | 2008-05-01 | Silicon Test Systems, Inc. | Low cost, high pin count, wafer sort automated test equipment (ate) device under test (dut) interface for testing electronic devices in high parallelism |
US7852094B2 (en) * | 2006-12-06 | 2010-12-14 | Formfactor, Inc. | Sharing resources in a system for testing semiconductor devices |
US8124429B2 (en) * | 2006-12-15 | 2012-02-28 | Richard Norman | Reprogrammable circuit board with alignment-insensitive support for multiple component contact types |
KR100891328B1 (en) * | 2007-01-04 | 2009-03-31 | 삼성전자주식회사 | Parallel type test system for semiconductor device and method of testing semiconductor device in parallel |
US7882405B2 (en) * | 2007-02-16 | 2011-02-01 | Atmel Corporation | Embedded architecture with serial interface for testing flash memories |
KR100867985B1 (en) * | 2007-05-08 | 2008-11-10 | 주식회사 아이티엔티 | Apparatus for testing semiconductor using the fpga |
US7716004B2 (en) * | 2007-07-02 | 2010-05-11 | Advanced Micro Devices, Inc. | Method and apparatus for matching test equipment calibration |
KR100791945B1 (en) * | 2007-08-23 | 2008-01-04 | (주)기가레인 | Probe card |
KR100787829B1 (en) * | 2007-09-07 | 2007-12-27 | (주)큐엠씨 | Apparatus and method for testing probe card |
KR101388674B1 (en) * | 2007-09-07 | 2014-04-25 | 삼성전자주식회사 | Wireless interface probe card for high speed one-shot wafer test and semiconductor testing apparatus having the same |
US7872469B2 (en) * | 2007-09-25 | 2011-01-18 | Qualcomm Incorporated | Apparatus and methods of integrated-circuit device testing |
US7888955B2 (en) * | 2007-09-25 | 2011-02-15 | Formfactor, Inc. | Method and apparatus for testing devices using serially controlled resources |
US7977959B2 (en) * | 2007-09-27 | 2011-07-12 | Formfactor, Inc. | Method and apparatus for testing devices using serially controlled intelligent switches |
US20090224793A1 (en) * | 2008-03-07 | 2009-09-10 | Formfactor, Inc. | Method And Apparatus For Designing A Custom Test System |
US8122309B2 (en) * | 2008-03-11 | 2012-02-21 | Formfactor, Inc. | Method and apparatus for processing failures during semiconductor device testing |
CN101562145B (en) * | 2008-04-16 | 2012-05-30 | 和舰科技(苏州)有限公司 | Method for improving wafer-stage electromigration performance test |
JPWO2009147724A1 (en) | 2008-06-02 | 2011-10-20 | 株式会社アドバンテスト | Test wafer unit and test system |
US8030959B2 (en) * | 2008-06-12 | 2011-10-04 | Texas Instruments Incorporated | Device-under-test power management |
US7924035B2 (en) * | 2008-07-15 | 2011-04-12 | Formfactor, Inc. | Probe card assembly for electronic device testing with DC test resource sharing |
US8095841B2 (en) | 2008-08-19 | 2012-01-10 | Formfactor, Inc. | Method and apparatus for testing semiconductor devices with autonomous expected value generation |
US7944225B2 (en) * | 2008-09-26 | 2011-05-17 | Formfactor, Inc. | Method and apparatus for providing a tester integrated circuit for testing a semiconductor device under test |
KR100907864B1 (en) * | 2008-09-30 | 2009-07-14 | 주식회사 아이엠텍 | Space transformer having isolation resistor for probe card and method of manufacturing space transforber |
JP5475674B2 (en) * | 2008-10-14 | 2014-04-16 | 株式会社アドバンテスト | Test equipment |
CN101750580B (en) * | 2008-12-01 | 2012-05-09 | 豪雅微电子(苏州)有限公司 | Test method of functional module chip in integrated circuit |
US8097979B2 (en) * | 2009-01-29 | 2012-01-17 | Dell Products, Lp | System and method for optimizing regulated voltage output point |
WO2010117565A2 (en) * | 2009-04-09 | 2010-10-14 | Teradyne, Inc. | Automated test equipment employing test signal transmission channel with embedded series isolation resistors |
JP2011089891A (en) * | 2009-10-22 | 2011-05-06 | Micronics Japan Co Ltd | Electrical connection device and testing device using the same |
TWI416117B (en) * | 2009-10-28 | 2013-11-21 | Mpi Corp | Probe card |
CN102062792B (en) * | 2009-11-12 | 2013-07-17 | 旺矽科技股份有限公司 | Probe card |
CN102109569B (en) * | 2009-12-29 | 2013-02-27 | 中芯国际集成电路制造(上海)有限公司 | Method for dielectric breakdown test on gate oxide adopting probe card |
DE102010033991A1 (en) * | 2010-03-11 | 2011-12-01 | Rhode & Schwarz Gmbh & Co. Kg | Measuring tip with integrated transducer |
TWI397697B (en) * | 2010-05-12 | 2013-06-01 | Chipsip Technology Co Ltd | Testing socket |
JP5547579B2 (en) * | 2010-08-02 | 2014-07-16 | 株式会社アドバンテスト | Test apparatus and test method |
CN102402474B (en) * | 2010-09-10 | 2014-08-13 | 中兴通讯股份有限公司 | Prototype verification device for programmable logic devices |
US8540522B2 (en) | 2010-10-05 | 2013-09-24 | Lumetric Lighting, Inc. | Utility control system and method |
JP2013088288A (en) * | 2011-10-18 | 2013-05-13 | Fujitsu Semiconductor Ltd | Inspection device and inspection system |
US10776233B2 (en) | 2011-10-28 | 2020-09-15 | Teradyne, Inc. | Programmable test instrument |
US9759772B2 (en) * | 2011-10-28 | 2017-09-12 | Teradyne, Inc. | Programmable test instrument |
US9470759B2 (en) * | 2011-10-28 | 2016-10-18 | Teradyne, Inc. | Test instrument having a configurable interface |
US9093396B2 (en) * | 2011-10-31 | 2015-07-28 | Masahiro Lee | Silicon interposer systems |
US9391447B2 (en) | 2012-03-06 | 2016-07-12 | Intel Corporation | Interposer to regulate current for wafer test tooling |
KR20130130527A (en) * | 2012-05-22 | 2013-12-02 | (주) 미코에스앤피 | Probe card |
US20140125371A1 (en) * | 2012-11-05 | 2014-05-08 | Hermes Testing Solutions Inc. | Stand alone multi-cell probe card for at-speed functional testing |
KR20140110443A (en) * | 2013-03-08 | 2014-09-17 | 삼성전자주식회사 | Probe card |
JP6306389B2 (en) * | 2013-09-17 | 2018-04-04 | 東京エレクトロン株式会社 | Board inspection equipment |
KR101368000B1 (en) * | 2013-10-30 | 2014-03-26 | 주식회사 아이티엔티 | Apparatus for testing a memory formed by layer structure of control processor and target device using interconnection socket |
CN104614659B (en) * | 2013-11-01 | 2017-08-29 | 普诚科技股份有限公司 | Automatization test system and method |
JP6478562B2 (en) | 2013-11-07 | 2019-03-06 | 株式会社半導体エネルギー研究所 | Semiconductor device |
JP6393590B2 (en) | 2013-11-22 | 2018-09-19 | 株式会社半導体エネルギー研究所 | Semiconductor device |
TWI531803B (en) * | 2013-12-17 | 2016-05-01 | 致伸科技股份有限公司 | Testing system of circuit board |
US9581639B2 (en) * | 2013-12-28 | 2017-02-28 | Intel Corporation | Organic space transformer attachment and assembly |
JP6444723B2 (en) | 2014-01-09 | 2018-12-26 | 株式会社半導体エネルギー研究所 | apparatus |
US9379713B2 (en) | 2014-01-17 | 2016-06-28 | Semiconductor Energy Laboratory Co., Ltd. | Data processing device and driving method thereof |
JP2015165226A (en) | 2014-02-07 | 2015-09-17 | 株式会社半導体エネルギー研究所 | Device |
JP6545970B2 (en) | 2014-02-07 | 2019-07-17 | 株式会社半導体エネルギー研究所 | apparatus |
TWI509259B (en) * | 2014-03-18 | 2015-11-21 | Nat Applied Res Laboratories | Conductive type current probe |
US10935594B1 (en) * | 2014-11-10 | 2021-03-02 | Priority Labs, Inc. | Curve trace analysis testing apparatus controller |
KR102324800B1 (en) | 2014-11-11 | 2021-11-11 | 삼성전자주식회사 | Rechargeable power module and test system including the same |
KR20160110588A (en) * | 2015-03-09 | 2016-09-22 | 삼성전기주식회사 | Semiconductor device and method for manufacturing therefor |
JP6537315B2 (en) * | 2015-03-23 | 2019-07-03 | オルガン針株式会社 | Wire probe jig |
CN104914339A (en) * | 2015-06-10 | 2015-09-16 | 中国航天科技集团公司第九研究院第七七一研究所 | High-speed test system and processing method thereof for ATE machine |
CN105486892A (en) * | 2015-08-28 | 2016-04-13 | 华润赛美科微电子(深圳)有限公司 | Integrated circuit probe card and manufacturing method, and device and method for detecting probe card |
JP2017129544A (en) * | 2016-01-22 | 2017-07-27 | 東京エレクトロン株式会社 | Substrate inspection device and program |
JP2017133848A (en) * | 2016-01-25 | 2017-08-03 | 東京エレクトロン株式会社 | Substrate inspection device and substrate inspection method |
JP6596374B2 (en) * | 2016-03-28 | 2019-10-23 | 東京エレクトロン株式会社 | Board inspection equipment |
TWI610081B (en) * | 2016-05-27 | 2018-01-01 | 蘇州明皜傳感科技有限公司 | Probe card for measuring micro-capacitance |
KR102581480B1 (en) * | 2016-07-27 | 2023-09-21 | 삼성전자주식회사 | Test board and test system for semiconductor package, method of manufacturing semiconductor package |
DE102016114144A1 (en) * | 2016-08-01 | 2018-02-01 | Endress+Hauser Flowtec Ag | Test system for testing electrical connections between components and a printed circuit board |
CN106771959A (en) * | 2016-11-16 | 2017-05-31 | 上海华岭集成电路技术股份有限公司 | A kind of wafer test system |
US10175296B2 (en) * | 2016-12-07 | 2019-01-08 | Intel Corporation | Testing a board assembly using test cards |
WO2018148497A1 (en) | 2017-02-10 | 2018-08-16 | Checksum, Llc | Functional tester for printed circuit boards, and associated systems and methods |
KR102279465B1 (en) * | 2017-07-21 | 2021-07-21 | 주식회사 기가레인 | Thin film resistor for probe card |
US10466299B2 (en) * | 2018-01-04 | 2019-11-05 | Winway Technology Co., Ltd. | Electronic test apparatus |
CN108535521B (en) * | 2018-05-10 | 2021-05-28 | 中国振华集团云科电子有限公司 | Four-wire resistance-adjusting probe card |
US20200116755A1 (en) * | 2018-10-15 | 2020-04-16 | AIS Technology, Inc. | Test interface system and method of manufacture thereof |
CN109581132A (en) * | 2019-01-23 | 2019-04-05 | 张朝霖 | A kind of probe pins test device of integrated circuit test seat |
KR102163321B1 (en) * | 2019-02-08 | 2020-10-21 | 화인인스트루먼트 (주) | Probe Card and Manufacturing Method thereof |
JP7272061B2 (en) * | 2019-03-29 | 2023-05-12 | 新東工業株式会社 | Test system and test head |
DE202019104016U1 (en) * | 2019-07-19 | 2019-08-20 | Feinmetall Gmbh | Test card for electrical testing of electrical / electronic devices, test system |
KR20210016782A (en) | 2019-08-05 | 2021-02-17 | 삼성전자주식회사 | Stiffener Having an Elastic Portion and Stiffener Handling Tools |
US11327095B2 (en) * | 2019-08-19 | 2022-05-10 | Samsung Electronics Co., Ltd. | Probe cards, system for manufacturing semiconductor device, and method of manufacturing semiconductor device |
KR102471771B1 (en) * | 2020-11-20 | 2022-11-29 | 주식회사 에스디에이 | Intelligent probe card for high-speed signal characterization verification |
KR20220155054A (en) | 2021-05-14 | 2022-11-22 | 삼성전자주식회사 | Test board and test apparatus including the same |
CN113419160B (en) * | 2021-06-18 | 2023-09-29 | 珠海美佳音科技有限公司 | Chip detection interface circuit |
US11662366B2 (en) | 2021-09-21 | 2023-05-30 | International Business Machines Corporation | Wafer probe with elastomer support |
US11675010B1 (en) | 2021-11-30 | 2023-06-13 | International Business Machines Corporation | Compliant wafer probe assembly |
DE102022109878B3 (en) | 2022-04-25 | 2023-08-10 | Infineon Technologies Ag | Limiting circuit with controlled parallel DC-DC converters |
CN117074924B (en) * | 2023-10-13 | 2023-12-29 | 天津信天电子科技有限公司 | Hydraulic controller veneer and single machine test fixture |
CN117290189B (en) * | 2023-11-27 | 2024-02-06 | 悦芯科技股份有限公司 | Monitoring control system for memory chip CP testing machine |
Citations (46)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US59971A (en) * | 1866-11-27 | Nathaniel e | ||
US4567432A (en) * | 1983-06-09 | 1986-01-28 | Texas Instruments Incorporated | Apparatus for testing integrated circuits |
US4658209A (en) * | 1984-01-30 | 1987-04-14 | Page Robert E | Universal test board, serial input (for synthesizer testing) |
US5091692A (en) * | 1990-01-11 | 1992-02-25 | Tokyo Electron Limited | Probing test device |
US5323107A (en) * | 1991-04-15 | 1994-06-21 | Hitachi America, Ltd. | Active probe card |
US5329226A (en) * | 1991-06-11 | 1994-07-12 | Sgs-Thomson Microelectronics S.A. | Probe card for testing integrated circuit chips |
US5363038A (en) * | 1992-08-12 | 1994-11-08 | Fujitsu Limited | Method and apparatus for testing an unpopulated chip carrier using a module test card |
US5434513A (en) * | 1992-08-10 | 1995-07-18 | Rohm Co., Ltd. | Semiconductor wafer testing apparatus using intermediate semiconductor wafer |
US5461327A (en) * | 1992-08-31 | 1995-10-24 | Tokyo Electron Limited | Probe apparatus |
US5497079A (en) * | 1992-09-01 | 1996-03-05 | Matsushita Electric Industrial Co., Ltd. | Semiconductor testing apparatus, semiconductor testing circuit chip, and probe card |
US5532610A (en) * | 1993-08-25 | 1996-07-02 | Nec Corporation | Apparatus for testing semicondctor wafer |
US5534784A (en) * | 1994-05-02 | 1996-07-09 | Motorola, Inc. | Method for probing a semiconductor wafer |
US5550480A (en) * | 1994-07-05 | 1996-08-27 | Motorola, Inc. | Method and means for controlling movement of a chuck in a test apparatus |
US5600257A (en) * | 1995-08-09 | 1997-02-04 | International Business Machines Corporation | Semiconductor wafer test and burn-in |
US5608335A (en) * | 1992-12-31 | 1997-03-04 | Sgs-Thomson Microelectronics, S.A. | Method for the testing of integrated circuit chips and corresponding integrated circuit device |
US5642054A (en) * | 1995-08-08 | 1997-06-24 | Hughes Aircraft Company | Active circuit multi-port membrane probe for full wafer testing |
US5862147A (en) * | 1996-04-22 | 1999-01-19 | Nec Corporation | Semiconductor device on semiconductor wafer having simple wirings for test and capable of being tested in a short time |
US5875198A (en) * | 1996-08-08 | 1999-02-23 | Advantest Corporation | Semiconductor device testing apparatus |
US5996102A (en) * | 1996-02-06 | 1999-11-30 | Telefonaktiebolaget L M Ericsson (Publ) | Assembly and method for testing integrated circuit devices |
US6064213A (en) * | 1993-11-16 | 2000-05-16 | Formfactor, Inc. | Wafer-level burn-in and test |
US6133744A (en) * | 1995-04-28 | 2000-10-17 | Nec Corporation | Apparatus for testing semiconductor wafer |
US6137296A (en) * | 1997-09-08 | 2000-10-24 | Samsung Electronics, Co., Ltd. | Probe card for testing semiconductor devices |
US6184053B1 (en) * | 1993-11-16 | 2001-02-06 | Formfactor, Inc. | Method of making microelectronic spring contact elements |
US6275071B1 (en) * | 1999-12-29 | 2001-08-14 | Intel Corporation | Domino logic circuit and method |
US6380753B1 (en) * | 1998-03-14 | 2002-04-30 | Tokyo Electron Limited | Screening method of semiconductor device and apparatus thereof |
US6400173B1 (en) * | 1999-11-19 | 2002-06-04 | Hitachi, Ltd. | Test system and manufacturing of semiconductor device |
US20020105352A1 (en) * | 2001-02-08 | 2002-08-08 | Mitsubishi Denki Kabushiki Kaisha | Apparatus and method for testing semiconductor integrated circuit |
US20020145437A1 (en) * | 2001-04-10 | 2002-10-10 | Formfactor, Inc. | Probe card with coplanar daughter card |
US6525555B1 (en) * | 1993-11-16 | 2003-02-25 | Formfactor, Inc. | Wafer-level burn-in and test |
US20030074611A1 (en) * | 2001-10-10 | 2003-04-17 | Tower Semiconductor Ltd. | Efficient test structure for non-volatile memory and other semiconductor integrated circuits |
US20030115517A1 (en) * | 2001-12-18 | 2003-06-19 | Rutten Ivo Wilhelmus Johaooes Marie | Microprocessor-based probe for integrated circuit testing |
US6603323B1 (en) * | 2000-07-10 | 2003-08-05 | Formfactor, Inc. | Closed-grid bus architecture for wafer interconnect structure |
US20030210031A1 (en) * | 2002-05-08 | 2003-11-13 | Miller Charles A. | Tester channel to multiple IC terminals |
US20030210069A1 (en) * | 2002-04-15 | 2003-11-13 | Shuji Kikuchi | Semiconductor device, and the method of testing or making of the semiconductor device |
US20040008024A1 (en) * | 2002-07-12 | 2004-01-15 | Miller Charles A. | Compensation for test signal degradation due to DUT fault |
US20040075453A1 (en) * | 2002-09-19 | 2004-04-22 | Slupsky Steven Harold | Non-contact tester for electronic circuits |
US6727580B1 (en) * | 1993-11-16 | 2004-04-27 | Formfactor, Inc. | Microelectronic spring contact elements |
US6784674B2 (en) * | 2002-05-08 | 2004-08-31 | Formfactor, Inc. | Test signal distribution system for IC tester |
US20040198081A1 (en) * | 1993-11-16 | 2004-10-07 | Eldridge Benjamin N. | Microelectronic spring contact elements |
US6911835B2 (en) * | 2002-05-08 | 2005-06-28 | Formfactor, Inc. | High performance probe system |
US6970798B1 (en) * | 2004-05-06 | 2005-11-29 | International Business Machines Corporation | Method, apparatus and computer program product for high speed memory testing |
US20060273809A1 (en) * | 2004-04-21 | 2006-12-07 | Formfactor, Inc. | Method of designing an application specific probe card test system |
US7154259B2 (en) * | 2003-10-23 | 2006-12-26 | Formfactor, Inc. | Isolation buffers with controlled equal time delays |
US7245134B2 (en) * | 2005-01-31 | 2007-07-17 | Formfactor, Inc. | Probe card assembly including a programmable device to selectively route signals from channels of a test system controller to probes |
US7307433B2 (en) * | 2004-04-21 | 2007-12-11 | Formfactor, Inc. | Intelligent probe card architecture |
US7342405B2 (en) * | 2000-01-18 | 2008-03-11 | Formfactor, Inc. | Apparatus for reducing power supply noise in an integrated circuit |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100697861B1 (en) * | 1998-03-13 | 2007-03-22 | 캠브리지 디스플레이 테크놀로지 리미티드 | Electroluminescent devices |
KR100305990B1 (en) * | 1998-06-30 | 2001-12-17 | 이수호 | Manufacturing method of ceramic composition for piezoelectric transformer |
JP2001210685A (en) * | 1999-11-19 | 2001-08-03 | Hitachi Ltd | Test system and method of manufacturing semiconductor integrated circuit device |
KR100874450B1 (en) * | 2002-08-21 | 2008-12-17 | 삼성에스디아이 주식회사 | Field emission display device having emitter formed of carbon material |
US6747473B2 (en) * | 2002-09-23 | 2004-06-08 | Lsi Logic Corporation | Device under interface card with on-board testing |
-
2004
- 2004-04-21 US US10/828,755 patent/US7307433B2/en active Active
-
2005
- 2005-04-21 CN CN2005800127374A patent/CN1947022B/en not_active Expired - Fee Related
- 2005-04-21 WO PCT/US2005/013850 patent/WO2005103740A2/en active Application Filing
- 2005-04-21 CN CN2011100332817A patent/CN102116779A/en active Pending
- 2005-04-21 KR KR1020067024380A patent/KR20070006917A/en not_active Application Discontinuation
- 2005-04-21 EP EP05749910A patent/EP1743182A4/en not_active Withdrawn
- 2005-04-21 JP JP2007509677A patent/JP2007534943A/en active Pending
- 2005-04-21 KR KR1020127017228A patent/KR101258385B1/en active IP Right Grant
- 2005-04-21 TW TW094112746A patent/TWI376504B/en not_active IP Right Cessation
-
2007
- 2007-12-11 US US12/001,281 patent/US20080100320A1/en not_active Abandoned
Patent Citations (55)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US59971A (en) * | 1866-11-27 | Nathaniel e | ||
US4567432A (en) * | 1983-06-09 | 1986-01-28 | Texas Instruments Incorporated | Apparatus for testing integrated circuits |
US4658209A (en) * | 1984-01-30 | 1987-04-14 | Page Robert E | Universal test board, serial input (for synthesizer testing) |
US5091692A (en) * | 1990-01-11 | 1992-02-25 | Tokyo Electron Limited | Probing test device |
US5323107A (en) * | 1991-04-15 | 1994-06-21 | Hitachi America, Ltd. | Active probe card |
US5329226A (en) * | 1991-06-11 | 1994-07-12 | Sgs-Thomson Microelectronics S.A. | Probe card for testing integrated circuit chips |
US5434513A (en) * | 1992-08-10 | 1995-07-18 | Rohm Co., Ltd. | Semiconductor wafer testing apparatus using intermediate semiconductor wafer |
US5363038A (en) * | 1992-08-12 | 1994-11-08 | Fujitsu Limited | Method and apparatus for testing an unpopulated chip carrier using a module test card |
US5461327A (en) * | 1992-08-31 | 1995-10-24 | Tokyo Electron Limited | Probe apparatus |
US5497079A (en) * | 1992-09-01 | 1996-03-05 | Matsushita Electric Industrial Co., Ltd. | Semiconductor testing apparatus, semiconductor testing circuit chip, and probe card |
US5608335A (en) * | 1992-12-31 | 1997-03-04 | Sgs-Thomson Microelectronics, S.A. | Method for the testing of integrated circuit chips and corresponding integrated circuit device |
US5532610A (en) * | 1993-08-25 | 1996-07-02 | Nec Corporation | Apparatus for testing semicondctor wafer |
US7078926B2 (en) * | 1993-11-16 | 2006-07-18 | Formfactor, Inc. | Wafer-level burn-in and test |
US6788094B2 (en) * | 1993-11-16 | 2004-09-07 | Formfactor, Inc. | Wafer-level burn-in and test |
US20040198081A1 (en) * | 1993-11-16 | 2004-10-07 | Eldridge Benjamin N. | Microelectronic spring contact elements |
US6525555B1 (en) * | 1993-11-16 | 2003-02-25 | Formfactor, Inc. | Wafer-level burn-in and test |
US6064213A (en) * | 1993-11-16 | 2000-05-16 | Formfactor, Inc. | Wafer-level burn-in and test |
US7345493B2 (en) * | 1993-11-16 | 2008-03-18 | Formfactor, Inc. | Wafer-level burn-in and test |
US6184053B1 (en) * | 1993-11-16 | 2001-02-06 | Formfactor, Inc. | Method of making microelectronic spring contact elements |
US20080157808A1 (en) * | 1993-11-16 | 2008-07-03 | Formfactor, Inc. | Wafer-level burn-in and test |
US6727580B1 (en) * | 1993-11-16 | 2004-04-27 | Formfactor, Inc. | Microelectronic spring contact elements |
US5534784A (en) * | 1994-05-02 | 1996-07-09 | Motorola, Inc. | Method for probing a semiconductor wafer |
US5550480A (en) * | 1994-07-05 | 1996-08-27 | Motorola, Inc. | Method and means for controlling movement of a chuck in a test apparatus |
US6133744A (en) * | 1995-04-28 | 2000-10-17 | Nec Corporation | Apparatus for testing semiconductor wafer |
US5642054A (en) * | 1995-08-08 | 1997-06-24 | Hughes Aircraft Company | Active circuit multi-port membrane probe for full wafer testing |
US6351134B2 (en) * | 1995-08-09 | 2002-02-26 | International Business Machines Corporation | Semiconductor wafer test and burn-in |
US5600257A (en) * | 1995-08-09 | 1997-02-04 | International Business Machines Corporation | Semiconductor wafer test and burn-in |
US5996102A (en) * | 1996-02-06 | 1999-11-30 | Telefonaktiebolaget L M Ericsson (Publ) | Assembly and method for testing integrated circuit devices |
US5862147A (en) * | 1996-04-22 | 1999-01-19 | Nec Corporation | Semiconductor device on semiconductor wafer having simple wirings for test and capable of being tested in a short time |
US5875198A (en) * | 1996-08-08 | 1999-02-23 | Advantest Corporation | Semiconductor device testing apparatus |
US6137296A (en) * | 1997-09-08 | 2000-10-24 | Samsung Electronics, Co., Ltd. | Probe card for testing semiconductor devices |
US6380753B1 (en) * | 1998-03-14 | 2002-04-30 | Tokyo Electron Limited | Screening method of semiconductor device and apparatus thereof |
US6400173B1 (en) * | 1999-11-19 | 2002-06-04 | Hitachi, Ltd. | Test system and manufacturing of semiconductor device |
US6275071B1 (en) * | 1999-12-29 | 2001-08-14 | Intel Corporation | Domino logic circuit and method |
US7342405B2 (en) * | 2000-01-18 | 2008-03-11 | Formfactor, Inc. | Apparatus for reducing power supply noise in an integrated circuit |
US6603323B1 (en) * | 2000-07-10 | 2003-08-05 | Formfactor, Inc. | Closed-grid bus architecture for wafer interconnect structure |
US20020105352A1 (en) * | 2001-02-08 | 2002-08-08 | Mitsubishi Denki Kabushiki Kaisha | Apparatus and method for testing semiconductor integrated circuit |
US20020145437A1 (en) * | 2001-04-10 | 2002-10-10 | Formfactor, Inc. | Probe card with coplanar daughter card |
US7116119B2 (en) * | 2001-04-10 | 2006-10-03 | Formfactor, Inc. | Probe card with coplanar daughter card |
US6856150B2 (en) * | 2001-04-10 | 2005-02-15 | Formfactor, Inc. | Probe card with coplanar daughter card |
US20030074611A1 (en) * | 2001-10-10 | 2003-04-17 | Tower Semiconductor Ltd. | Efficient test structure for non-volatile memory and other semiconductor integrated circuits |
US20030115517A1 (en) * | 2001-12-18 | 2003-06-19 | Rutten Ivo Wilhelmus Johaooes Marie | Microprocessor-based probe for integrated circuit testing |
US20030210069A1 (en) * | 2002-04-15 | 2003-11-13 | Shuji Kikuchi | Semiconductor device, and the method of testing or making of the semiconductor device |
US6911835B2 (en) * | 2002-05-08 | 2005-06-28 | Formfactor, Inc. | High performance probe system |
US20030210031A1 (en) * | 2002-05-08 | 2003-11-13 | Miller Charles A. | Tester channel to multiple IC terminals |
US6798225B2 (en) * | 2002-05-08 | 2004-09-28 | Formfactor, Inc. | Tester channel to multiple IC terminals |
US6784674B2 (en) * | 2002-05-08 | 2004-08-31 | Formfactor, Inc. | Test signal distribution system for IC tester |
US20040008024A1 (en) * | 2002-07-12 | 2004-01-15 | Miller Charles A. | Compensation for test signal degradation due to DUT fault |
US20040075453A1 (en) * | 2002-09-19 | 2004-04-22 | Slupsky Steven Harold | Non-contact tester for electronic circuits |
US7154259B2 (en) * | 2003-10-23 | 2006-12-26 | Formfactor, Inc. | Isolation buffers with controlled equal time delays |
US20060273809A1 (en) * | 2004-04-21 | 2006-12-07 | Formfactor, Inc. | Method of designing an application specific probe card test system |
US7307433B2 (en) * | 2004-04-21 | 2007-12-11 | Formfactor, Inc. | Intelligent probe card architecture |
US6970798B1 (en) * | 2004-05-06 | 2005-11-29 | International Business Machines Corporation | Method, apparatus and computer program product for high speed memory testing |
US7245134B2 (en) * | 2005-01-31 | 2007-07-17 | Formfactor, Inc. | Probe card assembly including a programmable device to selectively route signals from channels of a test system controller to probes |
US20070261009A1 (en) * | 2005-01-31 | 2007-11-08 | Formfactor, Inc. | Programmable devices to route signals on probe cards |
Cited By (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080157808A1 (en) * | 1993-11-16 | 2008-07-03 | Formfactor, Inc. | Wafer-level burn-in and test |
US7579269B2 (en) | 1993-11-16 | 2009-08-25 | Formfactor, Inc. | Microelectronic spring contact elements |
US7688090B2 (en) | 1993-11-16 | 2010-03-30 | Formfactor, Inc. | Wafer-level burn-in and test |
US8581610B2 (en) | 2004-04-21 | 2013-11-12 | Charles A Miller | Method of designing an application specific probe card test system |
US20060273809A1 (en) * | 2004-04-21 | 2006-12-07 | Formfactor, Inc. | Method of designing an application specific probe card test system |
US9476911B2 (en) | 2004-05-21 | 2016-10-25 | Microprobe, Inc. | Probes with high current carrying capability and laser machining methods |
US20070261009A1 (en) * | 2005-01-31 | 2007-11-08 | Formfactor, Inc. | Programmable devices to route signals on probe cards |
US8149008B2 (en) * | 2007-07-19 | 2012-04-03 | Nhk Spring Co., Ltd. | Probe card electrically connectable with a semiconductor wafer |
US20100219852A1 (en) * | 2007-07-19 | 2010-09-02 | Nhk Spring Co., Ltd | Probe card |
US20100169481A1 (en) * | 2008-12-31 | 2010-07-01 | Tsan-Fu Hung | Test system for semiconductor devices based on network monitoring |
KR101822980B1 (en) * | 2009-08-18 | 2018-01-29 | 폼팩터, 인크. | Wafer level contactor |
WO2011022301A3 (en) * | 2009-08-18 | 2011-06-09 | Formfactor, Inc. | Wafer level contactor |
US8400176B2 (en) | 2009-08-18 | 2013-03-19 | Formfactor, Inc. | Wafer level contactor |
WO2011022301A2 (en) * | 2009-08-18 | 2011-02-24 | Formfactor, Inc. | Wafer level contactor |
US20110128022A1 (en) * | 2009-12-02 | 2011-06-02 | Samsung Electronics Co., Ltd. | Testing apparatus and method |
US8378698B2 (en) | 2009-12-02 | 2013-02-19 | Samsung Electronics Co., Ltd. | Integrated circuit testing apparatus and method |
US9927487B2 (en) * | 2010-03-11 | 2018-03-27 | Mpi Corporation | Probe card having configurable structure for exchanging or swapping electronic components for impedance matching |
US20140103948A1 (en) * | 2010-03-11 | 2014-04-17 | Mpi Corporation | Probe card having configurable structure for exchanging or swapping electronic components for impedance matching |
US8541889B2 (en) * | 2010-12-30 | 2013-09-24 | Samsung Electronics Co., Ltd. | Probe card including frame and cover plate for testing a semiconductor device |
US8829937B2 (en) * | 2011-01-27 | 2014-09-09 | Formfactor, Inc. | Fine pitch guided vertical probe array having enclosed probe flexures |
US20120194212A1 (en) * | 2011-01-27 | 2012-08-02 | January Kister | Fine pitch guided vertical probe array having enclosed probe flexures |
US9037432B2 (en) | 2011-03-16 | 2015-05-19 | Formfactor, Inc. | Wireless probe card verification system and method |
WO2012125606A3 (en) * | 2011-03-16 | 2013-03-14 | Formfactor, Inc. | Wireless probe card verification system and method |
WO2012125606A2 (en) * | 2011-03-16 | 2012-09-20 | Formfactor, Inc. | Wireless probe card verification system and method |
US8988092B2 (en) * | 2011-07-28 | 2015-03-24 | Star Technologies Inc. | Probing apparatus for semiconductor devices |
US20130027072A1 (en) * | 2011-07-28 | 2013-01-31 | Star Technologies Inc. | Probing apparatus for semiconductor devices |
US8901948B2 (en) * | 2011-12-05 | 2014-12-02 | Winway Technology Co., Ltd. | Wafer probe card |
US20130141130A1 (en) * | 2011-12-05 | 2013-06-06 | Chia-Huang Wang | Wafer Probe Card |
US10101381B2 (en) * | 2012-08-31 | 2018-10-16 | Intel Corporation | Space transformation methods |
US20140062522A1 (en) * | 2012-08-31 | 2014-03-06 | Erkan Acar | Space Transformation Methods |
US9395401B2 (en) * | 2012-09-06 | 2016-07-19 | Tpk Touch Solutions (Xiamen) Inc. | Electrical connection assembly and testing method thereof |
US20140062501A1 (en) * | 2012-09-06 | 2014-03-06 | Tpk Touch Solutions (Xiamen) Inc. | Electrical connection assembly and testing method thereof |
US20190163344A1 (en) * | 2013-03-29 | 2019-05-30 | Sony Corporation | Information processing apparatus, information processing method, and recording medium |
US11188187B2 (en) * | 2013-03-29 | 2021-11-30 | Sony Corporation | Information processing apparatus, information processing method, and recording medium |
US9152520B2 (en) * | 2013-09-26 | 2015-10-06 | Texas Instruments Incorporated | Programmable interface-based validation and debug |
US20150253387A1 (en) * | 2013-09-26 | 2015-09-10 | Texas Instruments, Incorporated | Programmable interface-based validation and debug |
US20150089289A1 (en) * | 2013-09-26 | 2015-03-26 | Texas Instruments, Incorporated | Programmable interface-based validation and debug |
TWI794925B (en) * | 2020-11-05 | 2023-03-01 | 韓商Sda有限公司 | Probe card |
Also Published As
Publication number | Publication date |
---|---|
KR20070006917A (en) | 2007-01-11 |
CN1947022B (en) | 2011-10-12 |
TWI376504B (en) | 2012-11-11 |
WO2005103740A3 (en) | 2006-06-29 |
US7307433B2 (en) | 2007-12-11 |
JP2007534943A (en) | 2007-11-29 |
EP1743182A4 (en) | 2010-03-10 |
WO2005103740A2 (en) | 2005-11-03 |
CN102116779A (en) | 2011-07-06 |
US20050237073A1 (en) | 2005-10-27 |
KR20120096063A (en) | 2012-08-29 |
CN1947022A (en) | 2007-04-11 |
KR101258385B1 (en) | 2013-04-30 |
TW200604531A (en) | 2006-02-01 |
EP1743182A2 (en) | 2007-01-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7307433B2 (en) | Intelligent probe card architecture | |
US7245134B2 (en) | Probe card assembly including a programmable device to selectively route signals from channels of a test system controller to probes | |
US8581610B2 (en) | Method of designing an application specific probe card test system | |
US20060214679A1 (en) | Active diagnostic interface for wafer probe applications | |
KR101374965B1 (en) | Method and apparatus for testing devices using serially controlled intelligent switches | |
JP2691809B2 (en) | Semiconductor device test equipment | |
US7378862B2 (en) | Method and apparatus for eliminating automated testing equipment index time | |
TWI499782B (en) | Stand alone multi-cell probe card for at-speed functional testing | |
US20150168482A1 (en) | Configurable test equipment | |
US6259263B1 (en) | Compliant contactor for testing semiconductors | |
US7210081B1 (en) | Apparatus and methods for assessing reliability of assemblies using programmable logic devices |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: HSBC BANK USA, NATIONAL ASSOCIATION, CALIFORNIA Free format text: SECURITY INTEREST IN UNITED STATES PATENTS AND TRADEMARKS;ASSIGNORS:FORMFACTOR, INC.;ASTRIA SEMICONDUCTOR HOLDINGS, INC.;CASCADE MICROTECH, INC.;AND OTHERS;REEL/FRAME:039184/0280 Effective date: 20160624 |