US20080067662A1 - Modularized Die Stacking System and Method - Google Patents

Modularized Die Stacking System and Method Download PDF

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Publication number
US20080067662A1
US20080067662A1 US11941718 US94171807A US2008067662A1 US 20080067662 A1 US20080067662 A1 US 20080067662A1 US 11941718 US11941718 US 11941718 US 94171807 A US94171807 A US 94171807A US 2008067662 A1 US2008067662 A1 US 2008067662A1
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flex
contacts
circuit
die
upper
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US11941718
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David Roper
Curtis Hart
James Wilder
Phill Bradley
James Cady
Jeff Buchle
James Wehrly
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Entorian Technologies Inc
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Entorian Technologies Inc
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    • H05K1/147Structural association of two or more printed circuits at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit
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    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/189Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/05Flexible printed circuits [FPCs]
    • H05K2201/056Folded around rigid support or component
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10689Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10734Ball grid array [BGA]; Bump grid array
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits
    • H05K3/361Assembling flexible printed circuits with other printed circuits
    • H05K3/363Assembling flexible printed circuits with other printed circuits by soldering

Abstract

An IC die and a flexible circuit structure are integrated into a lower stack element that can be stacked with either further integrated lower stack element iterations or with pre-packaged ICs in any of a variety of package types. A die is positioned above the surface of portions of a pair of flex circuits. Connection is made between the die and the flex circuitry. A protective layer is formed to protect the flex-connected die and its connection to the flex. Connective elements are placed along the flex circuitry to create an array of module contacts along the second side of the flex circuitry. The flex circuitry is positioned above the body-protected die to create an integrated lower stack element. The integrated lower stack element may be stacked either with iterations of the integrated lower stack element or with a pre-packaged IC to create a multi-element stacked circuit module.

Description

    RELATED APPLICATIONS
  • This application is a continuation of U.S. application Ser. No. 10/435,192, filed May 9, 2003, which is a continuation-in-part of U.S. application Ser. No. 10/005,581, filed Oct. 26, 2001, now U.S. Pat. No. 6,576,992, both of which are hereby incorporated by reference for all purposes.
  • TECHNICAL FIELD
  • The present invention relates to aggregating integrated circuits and, in particular, to stacking integrated circuits.
  • BACKGROUND OF THE INVENTION
  • A variety of techniques are used to stack integrated circuits. Some methods require special packages, while other techniques stack conventional packages and still others stack multiple die within a single package. In some stacks, the leads of the packaged integrated circuits are used to create a stack, while in other systems, added structures such as rails provide all or part of the interconnection between packages. In still other techniques, flexible conductors with certain characteristics are used to selectively interconnect packaged integrated circuits. In yet other methods, one IC is connected to another within a single plastic body from which leads or contacts emerge.
  • The predominant package configuration employed during the past decade has encapsulated an integrated circuit (IC) in a plastic surround typically having a rectangular configuration. The enveloped integrated circuit is connected to the application environment through leads emergent from the edge periphery of the plastic encapsulation. Such “leaded packages” have been the constituent elements most commonly employed by techniques for stacking packaged integrated circuits.
  • Leaded packages play an important role in electronics, but efforts to miniaturize electronic components and assemblies have driven development of technologies that preserve circuit board surface area. Because leaded packages have leads emergent from peripheral sides of the package, leaded packages occupy more than a minimal amount of circuit board surface area. Consequently, alternatives to leaded packages have recently gained market share.
  • One family of alternative packages is identified generally by the term “chip scale packaging” or CSP. CSP refers generally to packages that provide connection to an integrated circuit through a set of contacts (often embodied as “bumps” or “balls”) arrayed across a major surface of the package. Instead of leads emergent from a peripheral side of the package, contacts are placed on a major surface and typically emerge from the planar bottom surface of the package.
  • The goal of CSP is to occupy as little area as possible and, preferably, approximately the area of the encapsulated IC. Therefore, CSP leads or contacts do not typically extend beyond the outline perimeter of the package. The absence of “leads” on package sides renders most stacking techniques devised for leaded packages inapplicable for CSP stacking.
  • CSP has enabled reductions in size and weight parameters for many applications. For example, micro ball grid array for flash and SRAM and wirebond on tape or rigid laminate CSPs for SRAM or EEPROM have been employed in a variety of applications. CSP is a broad category including a variety of packages from near chip scale to die-sized packages such as the die sized ball grid array (DSBGA) recently described in proposed JEDEC standard 95-1 for DSBGA. To meet the continuing demands for cost and form factor reduction with increasing memory capacities, CSP technologies that aggregate integrated circuits in CSP technology have recently been developed. For example, Sharp, Hitachi, Mitsubishi and Intel support what are called the S-CSP specifications for flash and SRAM applications. Those S-CSP specifications describe, however, stacking multiple die within a single chip scale package and do not describe stacking integrated circuits that are individually modularized in plastic, either as BGA's or other common CSP packages. Stacking integrated circuits within a single package requires specialized technology that includes reformulation of package internals and significant expense with possible supply chain vulnerabilities.
  • There are several known techniques for stacking packages articulated in chip scale technology. For example, the assignee of the present invention has developed previous systems for aggregating micro-BGA packages in space saving topologies. The assignee of the present invention has systems for stacking BGA packages on a DIMM in a RAMBUS environment.
  • In U.S. Pat. No. 6,205,654 B1 owned by the assignee of the present invention, a system for stacking ball grid array packages that employs lead carriers to extend connectable points out from the packages is described. Other known techniques add structures to a stack of BGA-packaged ICs. Still others aggregate CSPs on a DIMM with angular placement of the packages. Such techniques provide alternatives, but require topologies of added cost and complexity.
  • U.S. Pat. No. 6,262,895 B1 to Forthun (the “Forthun patent”) purports to disclose a technique for stacking chip scale packaged ICs. The Forthun patent discloses a “package” that exhibits a flex circuit wrapped partially about a CSP. The flex circuit is said to have pad arrays on upper and lower surfaces of the flex.
  • The flex circuit of the Forthun “package” has a pad array on its upper surface and a pad array centrally located upon its lower surface. On the lower surface of the flex there are third and fourth arrays on opposite sides from the central lower surface pad array. To create the package of Forthun, a CSP contacts the pad array located on the upper surface of the flex circuit. As described in the Forthun patent, the contacts on the lower surface of the CSP are pushed through “slits” in the upper surface pads and advanced through the flex to protrude from the pads of the lower surface array and, therefore, the bottom surface of the package. Thus, the contacts of the CSP serve as the contacts for the package. The sides of the flex are partially wrapped about the CSP to adjacently place the third and fourth pad arrays above the upper major surface of the CSP to create from the combination of the third and fourth pad arrays, a fifth pad array for connection to another such package. Thus, as described in the Forthun disclosure, a stacked module of CSPs created with the described packages will exhibit a flex circuit wrapped about each CSP in the module.
  • The previous known methods for stacking CSPs apparently have various deficiencies including complex structural arrangements and thermal or high frequency performance issues. To increase dissipation of heat generated by constituent CSPs, the thermal gradient between the lower CSP and upper CSP in a CSP stack or module should be minimized. Prior art solutions to CSP stacking do not, however, address thermal gradient minimization in disclosed constructions.
  • In other applications, module height concerns impact the utility of known solutions in integrated circuit aggregation. In some stacking solutions, the bad die problem is significant. Indigenous as well as processing-acquired defects can lead to unacceptably high failure rates for stacks created by aggregating IC elements before testing the constituent members of the assembly. For example, where stacking techniques employ one or more unpackaged die, there is typically not an opportunity for adequate preassembly test before the constituent ICs of the assembly are aggregated. Then, testing typically reveals bad stacks, it does not prevent their assembly and consequent waste of resources.
  • What is needed, therefore, is a technique and system for stacking integrated circuits using a technology that provides a thermally efficient, reliable structure that performs well at higher frequencies, but does not add excessive height to the stack yet allows pre-stacking test of constituent stack elements with production at reasonable cost with readily understood and managed materials and methods.
  • SUMMARY OF THE INVENTION
  • The present invention integrates an IC die and a flexible circuit structure into an integrated lower stack element that can be stacked with either further integrated lower stack element iterations or with pre-packaged ICs in any of a variety of package types. The present invention can be used to advantage where size minimization, thermal efficiency and or test before stacking are significant concerns. The present invention may be employed to stack similar or dissimilar integrated circuits and may be used to create modularized systems.
  • In the present invention, an IC die is integrated with flex circuitry to create an integrated lower stack element. In a preferred embodiment, a die is positioned above the surface of portions of a pair of flex circuits. Connection is made between the die and the flex circuitry. A protective layer such as a molded plastic, for example, is formed to create a body that protects the flex-connected die and its connection to the flex. Connective elements are placed along the flex circuits to create an array of module contacts along the second side of the flex circuitry. Portions of the pair of flex circuits are positioned above the body to create an integrated lower stack element. The integrated lower stack element may be stacked either with further iterations of the integrated lower stack element or with pre-packaged ICS to create a multi-element stacked circuit module. The present invention may be employed to advantage in numerous configurations and combinations in modules provided for high-density memories or high capacity computing.
  • SUMMARY OF THE DRAWINGS
  • FIG. 1 is an elevation view of module 10 devised in accordance with a preferred embodiment of the present invention.
  • FIG. 2 depicts an exemplar connection of an integrated circuit die to one of two flex circuits in a preferred embodiment of the present invention.
  • FIG. 3 depicts an elevation view of an integrated lower stack element in accordance with a preferred embodiment of the present invention.
  • FIG. 4 depicts an exemplar integration of a die in a flip-chip configuration with flex circuitry in accordance with a preferred embodiment of the present invention.
  • FIG. 5 depicts an exemplar construction details of an integrated lower stack element in accordance with a preferred embodiment of the present invention.
  • FIG. 6 depicts an exemplar construction details of an integrated lower stack element in accordance with another preferred embodiment of the present invention.
  • FIG. 7 depicts an exemplar conductive layer in a preferred flex circuitry employed in a preferred embodiment of the present invention.
  • DESCRIPTION OF PREFERRED EMBODIMENTS
  • FIG. 1 is an elevation view of module 10 devised in accordance with a preferred embodiment of the present invention. Module 10 is comprised of integrated lower stack element 12 and upper IC element 14.
  • Upper IC element 14 that is depicted in FIG. 1 may be any of a variety of types and configurations of CSP such as, for example, those that are die-sized, as well those that are near chip-scale as well as the variety of ball grid array packages known in the art. Typical CSPs, such as, for example, ball-grid-array (“BGA”), micro-ball-grid array (“μBGA”), and fine-pitch ball grid array (“FBGA”) packages have an array of connective contacts embodied, for example, as leads, bumps, solder balls, or balls that extend from a lower surface of a plastic casing in any of several patterns and pitches. An external portion of the connective contacts is often finished with a ball of solder. Collectively, these will be known herein as chip scale packaged integrated circuits (CSPs) and preferred embodiments will be described in terms of CSPs, but the particular configurations used in the explanatory figures are not, however, to be construed as limiting. For example, in the elevation view of FIG. 1, upper IC element 14 is depicted as a CSP of a particular profile known to those in the art, but it should be understood that the figures are exemplary only. Upper IC element 14 need not be limited to traditional CSP packaging and as those of skill recognize the opportunity, the present invention is adaptable to future package configurations. The present invention is advantageously employed with memory circuits but may be employed to advantage with logic and computing circuits even where the constituent elements of module 10 are dissimilar. Upper IC element 14 is shown with upper IC contacts 19.
  • Integrated lower stack element 12 is shown with die 16 and connections 20 that connect die 16 to flex circuits 18. Protective surround 22 is disposed to protect connections 20 and die 16. In a preferred embodiment, protective surround 22 is a plastic surround. As a protective surround 22 is formed about die 16, a body 23 is formed having lateral sides 21 and an upper surface 25. Protective body 23 will, in a preferred embodiment, surround portions of die 16 that would otherwise be exposed to potential environmental damage.
  • FIG. 2 depicts an exemplar connection of an integrated circuit die 16 to one of two flex circuits 18 in a preferred embodiment of the present invention to create a die-flex combination. As the present description continues, those of skill will recognize that a die-flex combination in accordance with the present invention may be devised in a variety of particular manners including using one or two flex circuits to provide connection to die 16, as well as using flex circuitry having one or more conductive layers. Preferably, the flex circuitry will articulate connective structures such as flex contacts and traces that will later be described.
  • As shown in FIG. 2, die pads 24 on die 16 are connected to flex attachments 26 of flex 18 by connections 20 which, in the illustrated exemplar, are wire bonding connections. Die pads 24 are just one type of die connective site that may be employed in the present invention. Other die connective sites such as flip-chip, tab and connective rings, balls, or pads may be employed. Die connective sites may also be construed to include combinations of such structures to provide a connective site for the die. Wire bonding is well known in the art and those of skill will appreciate that many other methods may be used to provide connections 20 between die 16 and the flex circuitry employed for the invention. For example, tab or flip-chip or other attachment techniques known in the art can be profitably used to implement connections 20. Those of skill will also appreciate that die pads 24 of die 16 can be arranged in a variety of configurations across the IC. As is known in the art, through die pads 24, die 16 expresses data and instructions as well as ground and voltage connections.
  • Flex 18 may be configured to interconnect to die 16 with other connective configurations. For example, as a variant on the flip-chip connectivity scheme, flex attachments 26 may be placed on the side of flex circuits 18 opposite that shown in FIG. 2 to place the flex attachments 26 immediately adjacent to the surface of die 16 to provide direct connection between die 16 and flex circuitry 18. It should also be understood that in the preferred embodiment shown in FIG. 1, two flex circuits 18 are employed but implementations of the invention can be devised using one flex circuit 18.
  • FIG. 3 depicts an elevation view of an integrated lower stack element 12 before its assembly into a module 10. Die 16 is placed adjacent to flex circuits 18 and fixed in place with adhesive 28. A variety of adhesive methods are known in the art and, in a preferred embodiment, an adhesive is used that has thermally conductive properties.
  • With reference to FIG. 4, in a preferred embodiment, portions of flex circuits 18A and 18B are fixed to die 16 by adhesive 28 which may be a liquid or tape adhesive or may be placed in discrete locations across the package. When used, preferably, adhesive 28 is thermally conductive. Adhesives that include a flux are used to advantage in some steps of assembly of module 10. Layer 28 may also be a thermally conductive medium or body to encourage heat flow.
  • As shown in this preferred embodiment, module contacts 30 are fixed along flex circuits 18A and 18B opposite the side of the flex circuits nearest to which die 16 is adjacent. The shown preferred module contacts 30 are familiar to those in the art and may be comprised of eutectic, lead-free, solid copper, or other conductive materials. Other contact implementing structures may be used to create module contacts 30 as long as the conductive layer or layers of the flex circuitry can be connected to module contacts 30 to allow conveyance of the signals conducted in flex circuits 18 to be transmitted to an environment external to integrated lower stack element 12. Balls are well understood, but other techniques and structures such as connective rings, built-up pads, or even leads may be placed along flex circuits 18 to create module contacts 30 to convey signals from module 10 to an external environment. Any of the standard JEDEC patterns may be implemented with module contacts 30 as well as custom arrays of module contacts for specialized applications.
  • FIG. 4 depicts the integration of die 16 devised in a flip-chip configuration with two flex circuits 18A and 18B in accordance with a preferred embodiment of the present invention. Those of skill will understand that the depiction of FIG. 4 is not drawn to scale. Die 16 exhibits die pads 24 along a lower surface of the die. Attached to die pads 24 are die connectors 32 which, in the depicted embodiment, are flip-chip balls or connectors. As shown, flex circuits 18A and 18B have module contacts 30.
  • Any flexible or conformable substrate with a conductive pattern may be used as a flex circuit in the invention. The preferred flex circuitry will employ more than one conductive layer, but the invention may be implemented with flex circuitry that has only a single conductive layer.
  • Even though single conductive layer flex circuitry may readily be used in the invention, flex circuit 18 is preferably a multi-layer flexible circuit structure that has at least two conductive layers. This is particularly appropriate where frequencies to be encountered are higher. Preferably, the conductive layers are metal such as copper alloy 110 although any conductive material may be employed in this role. The use of plural conductive layers provides advantages such as the creation of a distributed capacitance across module 10 intended to reduce noise or bounce effects that can, particularly at higher frequencies, degrade signal integrity, as those of skill in the art will recognize.
  • The entire flex circuit may be flexible or, as those of skill in the art will recognize, a PCB structure made flexible in certain areas to allow conformability around body 23 and rigid in other areas for planarity along surfaces may be employed as an alternative flex circuitry in the present invention. For example, structures known as rigid-flex may be employed.
  • Flex circuits 18A and 18B shown in FIG. 4 are comprised of multiple layers. Depicted flex circuits 18A and 18B have a first outer surface 36 and a second outer surface 38. The depicted preferred flex circuits 18A and 18B have two conductive layers interior to first and second outer surfaces 36 and 38. In the depicted preferred embodiment, first conductive layer 40 and second conductive layer 42 are interior to first and second outer surfaces 36 and 38, respectively. Intermediate support layer 44 lies between first conductive layer 40 and second conductive layer 42. There may be more than one intermediate layer, but an intermediate layer of polyimide is preferred. Preferably, the intermediate layer provides mechanical support for the flex circuitry.
  • It should be understood that in some embodiments of the invention, there will be fewer layers employed in flex circuit 18. For example, a flex circuit 18 may be devised for use in the present invention that lacks first outer surface 36 and/or second outer surface 38. In such a case, first conductive layer 40 will be on the surface of the particular flex circuit 18. Where there is a first outer surface, to make contact with first conductive layer 40 as shown in FIG. 4, die connectors 32 pass through windows 46 to reach first conductive layer 40. Similarly, where there is a second outer surface 38, module contacts 30 pass through windows 48 in second outer surface 38 to reach second conductive layer 42.
  • In a preferred embodiment, first conductive layer 40 is employed as a ground plane, while second conductive layer 42 provides the functions of being a signal conduction layer and a voltage conduction layer. Thus, second conductive layer 42 is employed to implement signal connections between integrated lower stack element 12 and upper IC element 14, while first conductive layer 40 is employed to implement ground connections between integrated lower stack element 12 and upper IC element 14. Those of skill will note that roles of the first and second conductive layers may be reversed. This may be implemented by flex layer design or by attendant use of interconnections. As is understood, thermal management is typically related to conductive layer materials and mass as well as the proximity between the die and the conductive layer.
  • Selective connections between first and second conductive layers 40 and 42 may be implemented with vias such as the via indicated in FIG. 4 by reference 50. There are, however, many other alternative methods to provide any needed connections between the conductive layers. For example, appropriate connections may be implemented by any of several well-known techniques such as plated holes or solid lines or wires. Thus, the connections need not literally be implemented with vias.
  • As will be illustrated in later figures, traces are delineated in conductive layers to convey, where needed, signals between selected module contacts 30 and particular die connectors 32 in the case of flip-chip style die 16 or between module contacts 30 and flex connectors 26 in the case where wire-bond connections 20 are implemented or between upper and lower flex contacts as will be described herein. Those of skill will recognize that traces can be implemented in a variety of configurations and manners and where die connectors are positioned coincident with module contact placement, trace use is minimized. For example, in some cases, if the die connectors 32 (illustrated as flip-chip connectors) are placed appropriately on die 16, a via 50 may be used to directly connect a selected die connector 32 to a selected module contact 30 without intermediate lateral conveyance between the two through a trace. Where a single conductive layer flex circuitry is employed in an embodiment, there will be no need for a via if a die connector 32 is positioned coincident with a module contact 30 to implement connection through a lower flex contact 62 such as is depicted in FIG. 5.
  • FIG. 5 illustrates an exemplar construction of an integrated lower stack element 12 in accordance with an alternative preferred embodiment of the present invention that employs flex circuitry having a single conductive layer. As shown, die 16 is appended to flex circuits 18A and 18B with adhesive 28. The depicted embodiment also exhibits optional inter-flex connective 51 that passes through the part of protective surround 22 that lies between flex circuit 18A and flex circuit 18B. The inter-flex connective may consist of one or more wires or other connective structures such as may be implemented in wire bond, lead frame or other form.
  • As those of skill will recognize, die 16 is connected to flex circuits 18A and 18B through die pads 24 and die connectors 32. Flex circuits 18A and 18B are depicted with first and second outer layers 36 and 38, respectively. Support layer 54 provides structure for flex circuits 18A and 18B and conductive layer 52 provides conductivity between die connectors 32 and module contacts 30. Conductive layer 52 also provides conductivity between integrated lower stack element 12 and added elements such as another integrated lower stack element 12 or upper IC element 14 that may be aggregated to create module 10.
  • Those of skill will recognize that in the depicted embodiment, conductive layer 52 is disposed closer to module contacts 30 than is support layer 54. This relative placement is preferred but not required. Such persons will also recognize that support layer 54 provides a support function similar to that provided by intermediate layer 44 in multi-layer flex circuitry embodiments such as those earlier described herein.
  • Demarcation gap 56 depicted in FIG. 5 provides selective isolation of lower flex contact 62 of conductive layer 52 from areas of conductive layer 52 that may provide other functions or other interconnections between different ones of die connectors 32 and module contacts 30 or other interconnections to other elements of module 10. For example, in the embodiment of FIG. 5, flex circuits 18A and 18B are shown as having one conductive layer (i.e., layer 52). Therefore, in the depicted alternative embodiment, that one conductive layer 52 is intended to provide interconnectivity functions for module 10. Consequently, particular interconnection features should be isolated from each other to allow rational connections to be implemented in module 10 where conductive layer structures are used. This is depicted by demarcation gap 56, but those of skill will understand that demarcation gap 56 is merely exemplary and assorted gaps and traces may be used in conductive layer 52 just as they may (but need not necessarily) be used in conductive layers in multi-conductive layer flex embodiments to provide rational interconnectivity features for module 10. However, as those of skill will recognize, the present invention may be implemented with a flex circuitry that exhibits a dedicated connective network of individual traces and/or interconnections.
  • With continuing reference to FIG. 5, a signal may be conveyed from die 16 through die pad 24 though die connector 32 through lower flex contact 62 at conductive layer 52 to module contact 30. Such connection paths may convey voltage, ground or data or instruction signal connections in and out of die 16.
  • In the depicted embodiment of FIG. 5, lower flex contacts 62 provide connection between die 16 and module contacts 30 as well as participating in selected connections between die 16 and the circuit of upper IC element 14. However, in addition, a set of flex contacts such as those identified in later FIG. 7 as upper flex contacts with respect to a second conductive layer 42 shown in FIG. 7, may, in the single conductive layer embodiment of FIG. 5, participate in the connection between the circuit of upper IC element 14 and the flex circuitry employed in the particular embodiment.
  • FIG. 6 depicts an alternative preferred embodiment of the present invention. In the embodiment as depicted in FIG. 6, die 16 is disposed above first outer surface 36 while die connective sites which, in this instance, are die pads 24 are connected to lower flex contacts 62 at the level of conductive layer 52 with wire bond connections 20 through windows 46. Body 23 is formed about the depicted die-flex combination and, in the preferred embodiment, is formed employing protective surround 22. Module contacts 30 are connected to the lower flex contacts 62 to express the appropriate set of signals emanating from die 16. As those of skill will understand as to the preferred embodiment of FIG. 6, when integrated lower stack element 12 is incorporated into a module 10, a set of upper contacts are articulated in the conductive layer 52 to provide connective facility for an upper IC element 14 or another integrated lower stack element 12. Further, traces 64 may be employed to provide connections between those upper flex contacts and the lower flex contacts and appropriate module contacts 30. Those of skill will recognize that in some instances, there may be module contacts 30 that are connected only to an upper element in a particular module 10.
  • FIG. 7 illustrates an exemplar second conductive layer 42 as may be implemented in flex circuits 18A and 18B of a preferred embodiment. Also shown is a depiction of die 16 and its underside 17. Identified in FIG. 7 are upper flex contacts 60 and lower flex contacts 62 that are at the level of second conductive layer 42 of flex circuits 18A and 18B. Upper flex contacts 60 and lower flex contacts 62 are conductive material and, preferably, are solid metal. Only some of upper flex contacts 60 and lower flex contacts 62 are identified with reference numerals in FIG. 7 to preserve clarity of the view.
  • Each of flex circuits 18A and 18B in the depicted preferred embodiment have both upper flex contacts 60 and lower flex contacts 62. Depending upon the contact pattern of die 16 and upper IC element 14, some embodiments may exhibit only lower or only upper flex contacts in flex circuits 18A or 18B.
  • In the preferred embodiment depicted in FIG. 7, lower flex contacts 62 are employed with module contacts 30 to provide connective facility for integrated lower stack element 12 in module 10. Thus, in a preferred embodiment, module contacts 30 are connected to lower flex contacts 62 as shown in exemplar fashion in FIG. 4 and in FIG. 5 in which figure a trace 64 is shown in the connective path between via 50 and lower flex contact 62. However, as those of skill will recognize, traces between selected upper and lower flex contacts provide a connective path between upper IC element 14 and integrated lower stack element 12 and/or directly to module contacts 30.
  • As those of skill will recognize, interconnection of respective contacts of upper IC element 14 and integrated lower stack element 12 will also preferably provide a thermal path between the two elements 12 and 14 to assist in moderation of thermal gradients through module 10. Those of skill will notice that between first and second conductive layers 40 and 42, there is at least one intermediate layer 44 that, in a preferred embodiment, is a polyimide. Placement of such an intermediate layer between ground-conductive first conductive layer 40 and signal/voltage conductive second conductive layer 42 provides, in the combination, a distributed capacitance that assists in mitigation of ground bounce phenomena to improve high frequency performance of module 10.
  • With continuing reference to FIG. 7, depicted are various types of upper flex contacts 60, various types of lower flex contacts 62, and traces 64. Lower flex contacts 62A are connected to corresponding selected upper flex contacts 60A with signal traces 64. To enhance the clarity of the view, only exemplar individual flex contacts 62A and 60A and traces 64 are literally identified in FIG. 7.
  • To improve high frequency performance, signal traces 64 may be devised to exhibit path routes determined to provide substantially equal signal lengths between corresponding flex contacts 60A and 62A. For example, such relatively equal length traces are illustrated in U.S. patent application Ser. No. 10/005,581 which is incorporated by reference into this application.
  • As shown in the depicted preferred embodiment of FIG. 7, traces 64 are separated from the larger surface area of second conductive layer 42 that is identified as VDD plane 66. VDD plane 66 may be in one or more delineated sections but, preferably is contiguous per flex circuit 18. Further, other embodiments may lack VDD plane 66.
  • Lower flex contacts 62B and upper flex contacts 60B provide connection to VDD plane 66. In a preferred embodiment, upper flex contacts 60B and lower flex contacts 62B selectively connect upper IC element 14 and integrated lower stack element 12, respectively, to VDD plane 66.
  • Lower flex contacts 62 that are connected to first conductive layer 40 by vias 50 are identified as lower flex contacts 62C. To enhance the clarity of the view, only exemplar individual lower flex contacts 62C are literally identified in FIG. 7. Upper flex contacts 60 that are connected to first conductive layer 40 by vias 50 are identified as upper flex contacts 60C.
  • In some embodiments, as shown in incorporated U.S. patent application Ser. No. 10/005,581, module 10 will exhibit an array of module contacts 30 that has a greater number of contacts than the constituent elements of module 10 individually exhibit. In such embodiments, some of the module contacts 30 may contact lower flex contacts 62 that do not make contact with one of the die contacts 24 of integrated lower stack element 12 but are connected to upper IC contacts 19 of upper IC element 14. This allows module 10 to express a wider datapath than that expressed by constituent integrated lower stack element 12 or upper IC element 14.
  • A module contact 30 may also be in contact with a lower flex contact 62 to provide a location through which different levels of constituent elements of the module may be enabled when no unused contacts are available or convenient for that purpose.
  • Those of skill will recognize that as flex circuitry 18 is partially wrapped about lateral side 21 of integrated lower stack element 12, first conductive layer 40 becomes, on the part of flex 18 disposed above upper surface 23 of integrated lower stack element 12, the lower-most conductive layer of flex 18 from the perspective of upper IC element 14. In the depicted embodiment, those upper IC element contacts 19 of upper IC element 14 that provide ground (VSS) connections are connected to the first conductive layer 40. First conductive layer 40 lies beneath, however, second conductive layer 42 in that part of flex 18 that is wrapped above lower stack element 12. Consequently, in the depicted preferred embodiment, those upper flex contacts 60 that are in contact with ground-conveying upper IC element contacts 25 of upper IC element 14 have vias that route through intermediate layer 44 to reach first conductive layer 40. These vias may preferably be “on-pad” or coincident with the flex contact 60 to which they are connected.
  • As those of skill will recognize, there may be embodiments of the present invention that may profitably employ off-pad vias such as are described in previously cited U.S. application Ser. No. 10/005,581, filed Oct. 26, 2001, (the “'581 application) pending, which is incorporated by reference herein.
  • Those of skill who refer to the '581 application will note that the figures in that application will be instructive in teaching details concerning a flex circuitry construction for preferred embodiments of the present invention. Further, as those of skill will recognize, the details on location and relationships between upper and lower flex contacts as described in the '581 application are useful to preferred embodiments of the present invention as modified to fit the particulars of the considered embodiment. Further, alternative embodiments depicted in the '581 application are instructive in understanding alternatives available for embodiments of the present invention. For example, the '581 application provides teachings that are descriptive of features that may be employed to advantage in preferred embodiments in accordance with the present invention where module 10 expresses a datapath that is wider than that of the constituent circuits of either integrated lower stack element 12 or upper IC element 14 or where differential enablement of the respective elements of module 10 is desired as those skilled in the field will understand.
  • Although the present invention has been described in detail, it will be apparent to those skilled in the art that the invention may be embodied in a variety of specific forms and that various changes, substitutions and alterations can be made without departing from the spirit and scope of the invention. The described embodiments are only illustrative and not restrictive and the scope of the invention is, therefore, indicated by the following claims.

Claims (40)

  1. 1. A circuit module comprising:
    an upper IC element;
    an integrated lower stack element comprising:
    an integrated circuit die;
    first and second flex circuits, disposed adjacent to and connected with the integrated circuit die to create a die-flex combination; and
    a protective structure molded to the die-flex combination to create a body having an upper surface above which are placed portions of the first and second flex circuits; and
    the upper IC element and the integrated lower stack element being in stacked conjunction with the upper IC element being disposed above the integrated lower stack element and the upper IC element and integrated lower stack element being connected through the first and second flex circuits.
  2. 2. The circuit module of claim 1 in which the first and second flex circuits each have first and second conductive layers.
  3. 3. The circuit module of claim 2 in which the connection of the upper IC element and integrated lower stack element through the first and second flex circuits is implemented through interconnections articulated at the first and second conductive layers of the first and second flex circuits.
  4. 4. The circuit module of claim 2 in which at least one of the first and second conductive layers of the first and second flex circuits have demarked upper and lower flex contacts.
  5. 5. An integrated lower stack element comprising:
    an integrated circuit die;
    first and second flex circuits, disposed adjacent to and connected with the integrated circuit die to create a die-flex combination; and
    a protective structure molded to the die-flex combination to create a body having an upper surface above which are placed portions of the first and second flex circuits.
  6. 6. The integrated lower stack element of claim 5 in which the first and second flex circuits are connected with the integrated circuit die through wire bonds.
  7. 7. The integrated lower stack element of claim 5 in which the first and second flex circuits are connected with the integrated circuit die through flip-chip connections.
  8. 8. The integrated lower stack element of claim 5 further comprising a set of module contacts disposed along the first and second flex circuits.
  9. 9. The integrated lower stack element of claim 5 in which the first and second flex circuits each have first and second conductive layers.
  10. 10. A circuit module comprising:
    (a) an integrated lower stack element comprising;
    an integrated circuit die having a plurality of die connective sites;
    a flexible circuit having first and second conductive layers, the flexible circuit being disposed in part beneath and affixed to and connected with the integrated circuit die to form a die-flex combination; and
    a protective structure set about the die-flex combination to cover at least a portion of the die and at least a portion of the flexible circuit and create a body having an upper surface above which are placed portions of the flexible circuit; and
    (b) an upper IC element having a plurality of upper IC contacts, the upper IC element being disposed in stacked conjunction with the integrated lower stack element, the upper IC element and integrated lower stack element being connected through the flexible circuit.
  11. 11. The circuit module of claim 10 in which a data signal connection between the upper IC element and the integrated lower stack element is implemented at the second conductive layer of the flex circuit.
  12. 12. The circuit module of claim 10 in which a data signal connection between the upper IC element and the integrated lower stack element is implemented at the first conductive layer of the flex circuit.
  13. 13. The circuit module of claim 10 in which:
    a data set of the plurality of upper IC contacts expresses an n-bit datapath;
    a data set of the plurality of die connective sites expresses an n-bit datapath; and
    a set of module contacts expresses a 2n-bit datapath that combines the n-bit datapath of the data set of the plurality of upper IC contacts and the n-bit datapath of the data set of the plurality of die connective sites.
  14. 14. The circuit module of claim 10 in which the second conductive layer comprises at least one demarked voltage plane and a voltage set of upper flex contacts and a voltage set of lower flex contacts that connect voltage conductive die connective sites and voltage conductive upper IC contacts to one of the at least one voltage planes.
  15. 15. A flex circuit connecting an upper IC element and an integrated circuit die in a circuit module, the flex circuit comprising:
    first and second outer layers; and
    first and second conductive layers, between which there is an intermediate layer, the first and second conductive layers and the intermediate layer being interior to the first and second outer layers, the second conductive layer having demarked first and second flex contacts, the first flex contacts being accessible through first windows through the second outer layer and the second flex contacts being accessible through second windows through the first outer layer, the first conductive layer, and the intermediate layer, the first flex contacts in electrical connection with the upper IC element and the second flex contacts in electrical connection with the integrated circuit die;
    wherein the flex circuit is disposed in part beneath and is combined with the integrated circuit die to form a die-flex combination and wherein a protective structure is set about the die-flex combination to cover at least a portion of the die and at least a portion of the flex circuit, the protective structure having an upper surface above which are placed portions of the flex circuit.
  16. 16. The flex circuit of claim 15 in which the second flex contacts are accessible through module windows through the second outer layer.
  17. 17. The flex circuit of claim 15 in which the first and second conductive layers are metal.
  18. 18. The flex circuit of claim 15 in which selected ones of the first flex contacts are connected to selected ones of the second flex contacts.
  19. 19. The flex circuit of claim 15 in which selected ones of the first flex contacts and selected ones of the second flex contacts are connected to the first conductive layer.
  20. 20. The flex circuit of claim 17 in which the metal of the first and second conductive layers is alloy 110.
  21. 21. The flex circuit of claim 18 in which the connected selected ones of the first and second flex contacts are connected with traces.
  22. 22. The flex circuit of claim 15 in which selected ones of the first flex contacts and selected ones of the second flex contacts are connected to the first conductive layer with vias.
  23. 23. A circuit module that employs the flex circuit of claim 15 to connect selected die contacts of an integrated circuit die to selected contacts of an upper IC element.
  24. 24. A circuit module comprising:
    a first flex circuit devised in accordance with claim 15;
    a second flex circuit devised in accordance with claim 15;
    an integrated circuit die having a plurality of die connective sites, a set of the plurality of die connective sites of the integrated circuit die being in electrical communication with the first flex contacts of each of the first and second flex circuits;
    an upper IC element having a plurality of upper IC contacts, a set of the plurality of upper IC contacts of the upper IC element being in electrical communication with the second flex contacts of each of the first and second flex circuits; and
    a set of module contacts in electrical communication with the second flex contacts.
  25. 25. The circuit module of claim 24 in which the first and second flex circuits are connected through an inter-flex circuit connective.
  26. 26. A circuit module comprising:
    a first flex circuit devised in accordance with claim 15;
    a second flex circuit devised in accordance with claim 15;
    an integrated circuit having a plurality of die connective sites, a set of the plurality of die connective sites, the die contacts of the integrated being in electrical communication with the second flex contacts of each of the first and second flex circuits;
    an upper IC element having a plurality of upper IC contacts, a set of the plurality of upper IC contacts of the upper IC element being in electrical communication with the first flex contacts of each of the first and second flex circuits; and
    a set of module contacts in electrical communication with the first flex contacts.
  27. 27. The circuit module of claims 24 or 26 in which for the first and second flex circuits, the first conductive layer conveys ground, and the second conductive layer conveys voltage in a voltage plane and the intermediate layer is insulative to create a distributed capacitor in the first and second flex circuits.
  28. 28. A circuit module comprising:
    a first CSP having first and second lateral sides and upper and lower major surfaces and a set of CSP contacts along the lower major surface;
    an integrated circuit die having a set of die connective sites connected to a pair of flex circuits;
    each of which pair of flex circuits having a first conductive layer and a second conductive layer, both said conductive layers being interior to first and second outer layers, and demarcated at the second conductive layer of each flex circuit there being upper and lower flex contacts, the upper flex contacts being connected to the set of CSP contacts of the first CSP and the lower flex contacts being connected to the die connective sites of the integrated circuit die and a set of module contacts.
  29. 29. The circuit module of claim 28 in which:
    a chip-enable module contact is connected to an enable lower flex contact that is connected to a chip select CSP contact of the first CSP.
  30. 30. The circuit module of claim 29 in which the connection between the enable lower flex contact and the chip select CSP contact of the first CSP is through an enable connection at the first conductive layer.
  31. 31. The circuit module of claim 28 in which a body having first and second lateral sides and an upper major surface is set about the integrated circuit die and a first one of the flex circuit pair is partially wrapped about the first lateral side of said body and a second one of the flex circuit pair is partially wrapped about the second lateral side of said body to dispose the upper flex contacts above the upper major surface of said body and beneath the lower major surface of the first CSP.
  32. 32. The circuit module of claim 31 in which the first CSP expresses an n-bit datapath and the integrated circuit die expresses an n-bit datapath, each of the flex circuits of the flex circuit pair having supplemental lower flex contacts which, in combination with the lower flex contacts, provide connection for the set of module contacts and a set of supplemental module contacts to express a 2n-bit module datapath that combines the n-bit datapath expressed by the first CSP and the n-bit datapath expressed by the integrated circuit die.
  33. 33. A circuit module comprising:
    a first CSP having first and second major surfaces with a plurality of CSP contacts along the first major surface;
    an integrated lower stack element in accordance with claim 5, the first CSP being disposed above the integrated lower stack element;
    each of the pair of flex circuits of the integrated lower stack element having an outer layer and an inner layer and first and second conductive layers between which conductive layers there is an intermediate layer, the second conductive layer having demarked a plurality of upper and lower flex contacts and a voltage plane, a first set of said plurality of upper and lower flex contacts being connected to the voltage plane, a second set of said plurality of upper and lower flex contacts being connected to the first conductive layer, and a third set of said plurality of upper and lower flex contacts being comprised of selected ones of upper flex contacts that are connected to corresponding selected ones of lower flex contacts, the plurality of CSP contacts of the first CSP being in contact with the upper flex contacts; and
    a set of module contacts in contact with the lower flex contacts.
  34. 34. The circuit module of claim 33 in which the first CSP and the integrated circuit die of the integrated lower stack element are memory circuits.
  35. 35. The circuit module of claim 33 in which the second set of said plurality of upper and lower flex contacts is connected to the first conductive layer with vias that pass through the intermediate layer.
  36. 36. The circuit module of claim 35 in which the second set of said plurality of upper and lower flex contacts is comprised of upper flex contacts connected to the first conductive layer with on-pad vias.
  37. 37. The circuit module of claim 35 in which the second set of said plurality of upper and lower flex contacts is comprised of lower flex contacts connected to the first conductive layer with off-pad vias.
  38. 38. The circuit module of claim 1 mounted on a board.
  39. 39. The circuit module of claims 33 or 34 in which between the first CSP and the integrated lower stack element there is a thermally conductive layer.
  40. 40. A method for assembling a circuit module, the method comprising the steps of:
    acquiring an integrated circuit die;
    acquiring a flex circuit devised in accordance with claim 15;
    disposing an adhesive on a selected area of the first outer surface of the flex circuit;
    adhering the flex circuit to the integrated circuit die;
    forming a connection between the flex circuit and the integrated circuit die;
    protecting the integrated circuit die and the connection formed between the flex circuit and the integrated circuit die with a protective layer to form a body;
    disposing a portion of the flex circuit above the body;
    acquiring a CSP;
    connecting the CSP to the flex circuit.
US11941718 2001-10-26 2007-11-16 Modularized Die Stacking System and Method Abandoned US20080067662A1 (en)

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US10005581 US6576992B1 (en) 2001-10-26 2001-10-26 Chip scale stacking system and method
US10435192 US7485951B2 (en) 2001-10-26 2003-05-09 Modularized die stacking system and method
US11941718 US20080067662A1 (en) 2001-10-26 2007-11-16 Modularized Die Stacking System and Method

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100025835A1 (en) * 2008-08-01 2010-02-04 Oh Jihoon Integrated circuit package stacking system
US20120326304A1 (en) * 2011-06-24 2012-12-27 Warren Robert W Externally Wire Bondable Chip Scale Package in a System-in-Package Module

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001237280A (en) * 2000-02-22 2001-08-31 Nec Corp Tape carrier type semiconductor device and flexible film connection board
KR100699823B1 (en) * 2003-08-05 2007-03-27 삼성전자주식회사 Low cost type flexible film package module and method for fabricating thereof
US8324725B2 (en) * 2004-09-27 2012-12-04 Formfactor, Inc. Stacked die module
US8072058B2 (en) * 2004-10-25 2011-12-06 Amkor Technology, Inc. Semiconductor package having a plurality input/output members
WO2006088270A1 (en) * 2005-02-15 2006-08-24 Unisemicon Co., Ltd. Stacked package and method of fabricating the same
US20070164416A1 (en) * 2006-01-17 2007-07-19 James Douglas Wehrly Managed memory component
JP2006351565A (en) * 2005-06-13 2006-12-28 Shinko Electric Ind Co Ltd Stacked semiconductor package
US7508069B2 (en) * 2006-01-11 2009-03-24 Entorian Technologies, Lp Managed memory component
US7508058B2 (en) * 2006-01-11 2009-03-24 Entorian Technologies, Lp Stacked integrated circuit module
US20070158811A1 (en) * 2006-01-11 2007-07-12 James Douglas Wehrly Low profile managed memory component
US7888185B2 (en) * 2006-08-17 2011-02-15 Micron Technology, Inc. Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device
US7425758B2 (en) * 2006-08-28 2008-09-16 Micron Technology, Inc. Metal core foldover package structures
US8185849B2 (en) * 2006-10-11 2012-05-22 Zuken Inc. Electric information processing method in CAD system, device thereof, program, and computer readable storage medium
US8050047B2 (en) * 2007-07-12 2011-11-01 Stats Chippac Ltd. Integrated circuit package system with flexible substrate and recessed package
JP5642473B2 (en) 2010-09-22 2014-12-17 セイコーインスツル株式会社 Bga semiconductor package and a method of manufacturing the same
KR101796116B1 (en) 2010-10-20 2017-11-10 삼성전자 주식회사 Semiconductor device, memory module and memory system having the same and operating method thereof

Citations (98)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3372310A (en) * 1965-04-30 1968-03-05 Radiation Inc Universal modular packages for integrated circuits
US3718842A (en) * 1972-04-21 1973-02-27 Texas Instruments Inc Liquid crystal display mounting structure
US4079511A (en) * 1976-07-30 1978-03-21 Amp Incorporated Method for packaging hermetically sealed integrated circuit chips on lead frames
US4429349A (en) * 1980-09-30 1984-01-31 Burroughs Corporation Coil connector
US4437235A (en) * 1980-12-29 1984-03-20 Honeywell Information Systems Inc. Integrated circuit package
US4567543A (en) * 1983-02-15 1986-01-28 Motorola, Inc. Double-sided flexible electronic circuit module
US4645944A (en) * 1983-09-05 1987-02-24 Matsushita Electric Industrial Co., Ltd. MOS register for selecting among various data inputs
US4722691A (en) * 1986-02-03 1988-02-02 General Motors Corporation Header assembly for a printed circuit board
US4724611A (en) * 1985-08-23 1988-02-16 Nec Corporation Method for producing semiconductor module
US4727513A (en) * 1983-09-02 1988-02-23 Wang Laboratories, Inc. Signal in-line memory module
US4733461A (en) * 1984-12-28 1988-03-29 Micro Co., Ltd. Method of stacking printed circuit boards
US4891789A (en) * 1988-03-03 1990-01-02 Bull Hn Information Systems, Inc. Surface mounted multilayer memory printed circuit board
US4903169A (en) * 1986-04-03 1990-02-20 Matsushita Electric Industrial Co., Ltd. Shielded high frequency apparatus having partitioned shield case, and method of manufacture thereof
US4911643A (en) * 1988-10-11 1990-03-27 Beta Phase, Inc. High density and high signal integrity connector
US4982265A (en) * 1987-06-24 1991-01-01 Hitachi, Ltd. Semiconductor integrated circuit device and method of manufacturing the same
US4983533A (en) * 1987-10-28 1991-01-08 Irvine Sensors Corporation High-density electronic modules - process and product
US4985703A (en) * 1988-02-03 1991-01-15 Nec Corporation Analog multiplexer
US4992850A (en) * 1989-02-15 1991-02-12 Micron Technology, Inc. Directly bonded simm module
US4992849A (en) * 1989-02-15 1991-02-12 Micron Technology, Inc. Directly bonded board multiple integrated circuit module
US5081067A (en) * 1989-02-10 1992-01-14 Fujitsu Limited Ceramic package type semiconductor device and method of assembling the same
US5099393A (en) * 1991-03-25 1992-03-24 International Business Machines Corporation Electronic package for high density applications
US5191404A (en) * 1989-12-20 1993-03-02 Digital Equipment Corporation High density memory array packaging
US5198965A (en) * 1991-12-18 1993-03-30 International Business Machines Corporation Free form packaging of specific functions within a computer system
US5198888A (en) * 1987-12-28 1993-03-30 Hitachi, Ltd. Semiconductor stacked device
US5276418A (en) * 1988-11-16 1994-01-04 Motorola, Inc. Flexible substrate electronic assembly
US5279029A (en) * 1990-08-01 1994-01-18 Staktek Corporation Ultra high density integrated circuit packages method
US5281852A (en) * 1991-12-10 1994-01-25 Normington Peter J C Semiconductor device including stacked die
US5289062A (en) * 1991-03-18 1994-02-22 Quality Semiconductor, Inc. Fast transmission gate switch
US5289346A (en) * 1991-02-26 1994-02-22 Microelectronics And Computer Technology Corporation Peripheral to area adapter with protective bumper for an integrated circuit chip
US5384690A (en) * 1993-07-27 1995-01-24 International Business Machines Corporation Flex laminate package for a parallel processor
US5386341A (en) * 1993-11-01 1995-01-31 Motorola, Inc. Flexible substrate folded in a U-shape with a rigidizer plate located in the notch of the U-shape
US5394300A (en) * 1992-09-04 1995-02-28 Mitsubishi Denki Kabushiki Kaisha Thin multilayered IC memory card
US5394010A (en) * 1991-03-13 1995-02-28 Kabushiki Kaisha Toshiba Semiconductor assembly having laminated semiconductor devices
US5394303A (en) * 1992-09-11 1995-02-28 Kabushiki Kaisha Toshiba Semiconductor device
US5396573A (en) * 1993-08-03 1995-03-07 International Business Machines Corporation Pluggable connectors for connecting large numbers of electrical and/or optical cables to a module through a seal
US5397916A (en) * 1991-12-10 1995-03-14 Normington; Peter J. C. Semiconductor device including stacked die
US5484959A (en) * 1992-12-11 1996-01-16 Staktek Corporation High density lead-on-package fabrication method and apparatus
US5491612A (en) * 1995-02-21 1996-02-13 Fairchild Space And Defense Corporation Three-dimensional modular assembly of integrated circuits
US5493476A (en) * 1994-03-07 1996-02-20 Staktek Corporation Bus communication system for stacked high density integrated circuit packages with bifurcated distal lead ends
US5592364A (en) * 1995-01-24 1997-01-07 Staktek Corporation High density integrated circuit module with complex electrical interconnect rails
US5594275A (en) * 1993-11-18 1997-01-14 Samsung Electronics Co., Ltd. J-leaded semiconductor package having a plurality of stacked ball grid array packages
US5600178A (en) * 1993-10-08 1997-02-04 Texas Instruments Incorporated Semiconductor package having interdigitated leads
US5708297A (en) * 1992-09-16 1998-01-13 Clayton; James E. Thin multichip module
US5714802A (en) * 1991-06-18 1998-02-03 Micron Technology, Inc. High-density electronic module
US5717556A (en) * 1995-04-26 1998-02-10 Nec Corporation Printed-wiring board having plural parallel-connected interconnections
US5869353A (en) * 1997-11-17 1999-02-09 Dense-Pac Microsystems, Inc. Modular panel stacking process
US5872051A (en) * 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
US6014316A (en) * 1997-06-13 2000-01-11 Irvine Sensors Corporation IC stack utilizing BGA contacts
US6013948A (en) * 1995-11-27 2000-01-11 Micron Technology, Inc. Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US6021048A (en) * 1998-02-17 2000-02-01 Smith; Gary W. High speed memory module
US6025642A (en) * 1995-08-17 2000-02-15 Staktek Corporation Ultra high density integrated circuit packages
US6028365A (en) * 1998-03-30 2000-02-22 Micron Technology, Inc. Integrated circuit package and method of fabrication
US6028352A (en) * 1997-06-13 2000-02-22 Irvine Sensors Corporation IC stack utilizing secondary leadframes
US6172874B1 (en) * 1998-04-06 2001-01-09 Silicon Graphics, Inc. System for stacking of integrated circuit packages
US6178093B1 (en) * 1996-06-28 2001-01-23 International Business Machines Corporation Information handling system with circuit assembly having holes filled with filler material
US6180881B1 (en) * 1998-05-05 2001-01-30 Harlan Ruben Isaak Chip stack and method of making same
US6186106B1 (en) * 1997-12-29 2001-02-13 Visteon Global Technologies, Inc. Apparatus for routing electrical signals in an engine
US6187652B1 (en) * 1998-09-14 2001-02-13 Fujitsu Limited Method of fabrication of multiple-layer high density substrate
US20020001216A1 (en) * 1996-02-26 2002-01-03 Toshio Sugano Semiconductor device and process for manufacturing the same
US6336262B1 (en) * 1996-10-31 2002-01-08 International Business Machines Corporation Process of forming a capacitor with multi-level interconnection technology
US20020006032A1 (en) * 2000-05-23 2002-01-17 Chris Karabatsos Low-profile registered DIMM
US6343020B1 (en) * 1998-12-28 2002-01-29 Foxconn Precision Components Co., Ltd. Memory module
US6347394B1 (en) * 1998-11-04 2002-02-12 Micron Technology, Inc. Buffering circuit embedded in an integrated circuit device module used for buffering clocks and other input signals
US6349050B1 (en) * 2000-10-10 2002-02-19 Rambus, Inc. Methods and systems for reducing heat flux in memory systems
US6351029B1 (en) * 1999-05-05 2002-02-26 Harlan R. Isaak Stackable flex circuit chip package and method of making same
US20030002262A1 (en) * 2001-07-02 2003-01-02 Martin Benisek Electronic printed circuit board having a plurality of identically designed, housing-encapsulated semiconductor memories
US6504104B2 (en) * 1997-12-10 2003-01-07 Siemens Aktiengesellschaft Flexible wiring for the transformation of a substrate with edge contacts into a ball grid array
US6509639B1 (en) * 2001-07-27 2003-01-21 Charles W. C. Lin Three-dimensional stacked semiconductor package
US20030016710A1 (en) * 2001-07-19 2003-01-23 Satoshi Komoto Semiconductor laser device including light receiving element for receiving monitoring laser beam
US20030020153A1 (en) * 2001-07-24 2003-01-30 Ted Bruce Chip stack with differing chip package types
US6514793B2 (en) * 1999-05-05 2003-02-04 Dpac Technologies Corp. Stackable flex circuit IC package and method of making same
US20030026155A1 (en) * 2001-08-01 2003-02-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory module and register buffer device for use in the same
US6522018B1 (en) * 2000-05-16 2003-02-18 Micron Technology, Inc. Ball grid array chip packages having improved testing and stacking characteristics
US6521530B2 (en) * 1998-11-13 2003-02-18 Fujitsu Limited Composite interposer and method for producing a composite interposer
US20030035328A1 (en) * 2001-08-08 2003-02-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device shiftable to test mode in module as well as semiconductor memory module using the same
US6526549B1 (en) * 2000-09-14 2003-02-25 Sun Microsystems, Inc. Hierarchical parasitic capacitance extraction for ultra large scale integrated circuits
US20040000708A1 (en) * 2001-10-26 2004-01-01 Staktek Group, L.P. Memory expansion and chip scale stacking system and method
US6673651B2 (en) * 1999-07-01 2004-01-06 Oki Electric Industry Co., Ltd. Method of manufacturing semiconductor device including semiconductor elements mounted on base plate
US20040004281A1 (en) * 2002-07-03 2004-01-08 Jin-Chuan Bai Semiconductor package with heat sink
US6677670B2 (en) * 2000-04-25 2004-01-13 Seiko Epson Corporation Semiconductor device
US20040012991A1 (en) * 2002-07-18 2004-01-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory module
US6683377B1 (en) * 2000-05-30 2004-01-27 Amkor Technology, Inc. Multi-stacked memory package
US20040021211A1 (en) * 2002-08-05 2004-02-05 Tessera, Inc. Microelectronic adaptors, assemblies and methods
US6690584B2 (en) * 2000-08-14 2004-02-10 Fujitsu Limited Information-processing device having a crossbar-board connected to back panels on different sides
US6689634B1 (en) * 1999-09-22 2004-02-10 Texas Instruments Incorporated Modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or LGA) package to increase device reliability
US20040031972A1 (en) * 2001-10-09 2004-02-19 Tessera, Inc. Stacked packages
US6839266B1 (en) * 1999-09-14 2005-01-04 Rambus Inc. Memory module with offset data lines and bit line swizzle configuration
US6838761B2 (en) * 2002-09-17 2005-01-04 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield
US6841868B2 (en) * 1996-10-08 2005-01-11 Micron Technology, Inc. Memory modules including capacity for additional memory
US6841855B2 (en) * 2003-04-28 2005-01-11 Intel Corporation Electronic package having a flexible substrate with ends connected to one another
US20050018495A1 (en) * 2004-01-29 2005-01-27 Netlist, Inc. Arrangement of integrated circuits in a memory module
US6849949B1 (en) * 1999-09-27 2005-02-01 Samsung Electronics Co., Ltd. Thin stacked package
US20050035440A1 (en) * 2001-08-22 2005-02-17 Tessera, Inc. Stacked chip assembly with stiffening layer
US6858910B2 (en) * 2000-01-26 2005-02-22 Texas Instruments Incorporated Method of fabricating a molded package for micromechanical devices
US20050040508A1 (en) * 2003-08-22 2005-02-24 Jong-Joo Lee Area array type package stack and manufacturing method thereof
US6984885B1 (en) * 2000-02-10 2006-01-10 Renesas Technology Corp. Semiconductor device having densely stacked semiconductor chips
US6998704B2 (en) * 2002-08-30 2006-02-14 Nec Corporation Semiconductor device and method for manufacturing the same, circuit board, electronic apparatus, and semiconductor device manufacturing apparatus
US7180167B2 (en) * 2001-10-26 2007-02-20 Staktek Group L. P. Low profile stacking system and method

Family Cites Families (138)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3411122A (en) 1966-01-13 1968-11-12 Ibm Electrical resistance element and method of fabricating
US3436604A (en) 1966-04-25 1969-04-01 Texas Instruments Inc Complex integrated circuit array and method for fabricating same
US3654394A (en) * 1969-07-08 1972-04-04 Gordon Eng Co Field effect transistor switch, particularly for multiplexing
US3772776A (en) 1969-12-03 1973-11-20 Thomas & Betts Corp Method of interconnecting memory plane boards
US3727064A (en) 1971-03-17 1973-04-10 Monsanto Co Opto-isolator devices and method for the fabrication thereof
US3746934A (en) 1971-05-06 1973-07-17 Siemens Ag Stack arrangement of semiconductor chips
US3766439A (en) 1972-01-12 1973-10-16 Gen Electric Electronic module using flexible printed circuit board with heat sink means
US3806767A (en) * 1973-03-15 1974-04-23 Tek Wave Inc Interboard connector
US3983547A (en) 1974-06-27 1976-09-28 International Business Machines - Ibm Three-dimensional bubble device
US4103318A (en) 1977-05-06 1978-07-25 Ford Motor Company Electronic multichip module
US4288841A (en) 1979-09-20 1981-09-08 Bell Telephone Laboratories, Incorporated Double cavity semiconductor chip carrier
US4381421A (en) * 1980-07-01 1983-04-26 Tektronix, Inc. Electromagnetic shield for electronic equipment
US4398235A (en) 1980-09-11 1983-08-09 General Motors Corporation Vertical integrated circuit package integration
JPH0315340B2 (en) 1981-04-30 1991-02-28 Hitachi Seisakusho Kk
US4513368A (en) * 1981-05-22 1985-04-23 Data General Corporation Digital data processing system having object-based logical memory addressing and self-structuring modular memory
US4406508A (en) 1981-07-02 1983-09-27 Thomas & Betts Corporation Dual-in-line package assembly
US4420794A (en) 1981-09-10 1983-12-13 Research, Incorporated Integrated circuit switch
US4466183A (en) * 1982-05-03 1984-08-21 National Semiconductor Corporation Integrated circuit packaging process
US4712129A (en) 1983-12-12 1987-12-08 Texas Instruments Incorporated Integrated circuit device with textured bar cover
KR890004820B1 (en) 1984-03-28 1989-11-27 제이.에이취.그래디 Stacked double density memory module using industry standard memory chips
US4587596A (en) * 1984-04-09 1986-05-06 Amp Incorporated High density mother/daughter circuit board connector
EP0218796B1 (en) 1985-08-16 1990-10-31 Dai-Ichi Seiko Co. Ltd. Semiconductor device comprising a plug-in-type package
US4696525A (en) 1985-12-13 1987-09-29 Amp Incorporated Socket for stacking integrated circuit packages
US4763188A (en) * 1986-08-08 1988-08-09 Thomas Johnson Packaging system for multiple semiconductor devices
US4839717A (en) 1986-12-19 1989-06-13 Fairchild Semiconductor Corporation Ceramic package for high frequency semiconductor devices
US5016138A (en) 1987-10-27 1991-05-14 Woodman John K Three dimensional integrated circuit package
US4821007A (en) 1987-02-06 1989-04-11 Tektronix, Inc. Strip line circuit component and method of manufacture
US5159535A (en) 1987-03-11 1992-10-27 International Business Machines Corporation Method and apparatus for mounting a flexible film semiconductor chip carrier on a circuitized substrate
US4862249A (en) 1987-04-17 1989-08-29 Xoc Devices, Inc. Packaging system for stacking integrated circuits
US4833568A (en) 1988-01-29 1989-05-23 Berhold G Mark Three-dimensional circuit component assembly and method corresponding thereto
US4956694A (en) 1988-11-04 1990-09-11 Dense-Pac Microsystems, Inc. Integrated circuit chip stacking
DE69006609D1 (en) 1989-03-15 1994-03-24 Ngk Insulators Ltd Ceramic lid for sealing a semiconductor element and method for sealing a semiconductor element in a ceramic package.
JP2647194B2 (en) 1989-04-17 1997-08-27 住友電気工業株式会社 Sealing method of semiconductor package
US4953060A (en) 1989-05-05 1990-08-28 Ncr Corporation Stackable integrated circuit chip package with improved heat removal
US5104820A (en) 1989-07-07 1992-04-14 Irvine Sensors Corporation Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting
US5057903A (en) 1989-07-17 1991-10-15 Microelectronics And Computer Technology Corporation Thermal heat sink encapsulated integrated circuit
US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US5068708A (en) 1989-10-02 1991-11-26 Advanced Micro Devices, Inc. Ground plane for plastic encapsulated integrated circuit die packages
US5012323A (en) 1989-11-20 1991-04-30 Micron Technology, Inc. Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe
US5229641A (en) 1989-11-25 1993-07-20 Hitachi Maxell, Ltd. Semiconductor card and manufacturing method therefor
US5041902A (en) 1989-12-14 1991-08-20 Motorola, Inc. Molded electronic package with compression structures
JPH03227541A (en) 1990-02-01 1991-10-08 Hitachi Ltd Semiconductor device
US5041015A (en) 1990-03-30 1991-08-20 Cal Flex, Inc. Electrical jumper assembly
US5345205A (en) 1990-04-05 1994-09-06 General Electric Company Compact high density interconnected microwave system
US5261068A (en) 1990-05-25 1993-11-09 Dell Usa L.P. Dual path memory retrieval system for an interleaved dynamic RAM memory unit
US5050039A (en) 1990-06-26 1991-09-17 Digital Equipment Corporation Multiple circuit chip mounting and cooling arrangement
US5377077A (en) 1990-08-01 1994-12-27 Staktek Corporation Ultra high density integrated circuit packages method and apparatus
US5148265A (en) * 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
JP3242101B2 (en) 1990-10-05 2001-12-25 三菱電機株式会社 The semiconductor integrated circuit
JPH04162556A (en) 1990-10-25 1992-06-08 Mitsubishi Electric Corp Lead frame and its manufacturing
US5117282A (en) * 1990-10-29 1992-05-26 Harris Corporation Stacked configuration for integrated circuit devices
US5138434A (en) 1991-01-22 1992-08-11 Micron Technology, Inc. Packaging for semiconductor logic devices
US5219794A (en) 1991-03-14 1993-06-15 Hitachi, Ltd. Semiconductor integrated circuit device and method of fabricating same
US5158912A (en) 1991-04-09 1992-10-27 Digital Equipment Corporation Integral heatsink semiconductor package
US5138430A (en) 1991-06-06 1992-08-11 International Business Machines Corporation High performance versatile thermally enhanced IC chip mounting
JPH0513666A (en) 1991-06-29 1993-01-22 Sony Corp Complex semiconductor device
US5214307A (en) * 1991-07-08 1993-05-25 Micron Technology, Inc. Lead frame for semiconductor devices having improved adhesive bond line control
US5311401A (en) 1991-07-09 1994-05-10 Hughes Aircraft Company Stacked chip assembly and manufacturing method therefor
US5252857A (en) 1991-08-05 1993-10-12 International Business Machines Corporation Stacked DCA memory chips
JP2967621B2 (en) 1991-08-27 1999-10-25 日本電気株式会社 Method of manufacturing a package for a semiconductor device
US5168926A (en) 1991-09-25 1992-12-08 Intel Corporation Heat sink design integrating interface material
US5241454A (en) 1992-01-22 1993-08-31 International Business Machines Corporation Mutlilayered flexible circuit package
US5262927A (en) 1992-02-07 1993-11-16 Lsi Logic Corporation Partially-molded, PCB chip carrier package
US5224023A (en) 1992-02-10 1993-06-29 Smith Gary W Foldable electronic assembly module
US5243133A (en) 1992-02-18 1993-09-07 International Business Machines, Inc. Ceramic chip carrier with lead frame or edge clip
US5222014A (en) 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
US5229916A (en) 1992-03-04 1993-07-20 International Business Machines Corporation Chip edge interconnect overlay element
US5259770A (en) 1992-03-19 1993-11-09 Amp Incorporated Impedance controlled elastomeric connector
US5361228A (en) 1992-04-30 1994-11-01 Fuji Photo Film Co., Ltd. IC memory card system having a common data and address bus
US5247423A (en) 1992-05-26 1993-09-21 Motorola, Inc. Stacking three dimensional leadless multi-chip module and method for making the same
DE69325770T2 (en) * 1992-06-02 1999-11-18 Hewlett Packard Co A method of computer-aided design for multi-layer technologies compounds
US5343366A (en) 1992-06-24 1994-08-30 International Business Machines Corporation Packages for stacked integrated circuit chip cubes
US5729894A (en) * 1992-07-21 1998-03-24 Lsi Logic Corporation Method of assembling ball bump grid array semiconductor packages
US5402006A (en) 1992-11-10 1995-03-28 Texas Instruments Incorporated Semiconductor device with enhanced adhesion between heat spreader and leads and plastic mold compound
US5313097A (en) 1992-11-16 1994-05-17 International Business Machines, Corp. High density memory module
US5375041A (en) 1992-12-02 1994-12-20 Intel Corporation Ra-tab array bump tab tape based I.C. package
US5347428A (en) 1992-12-03 1994-09-13 Irvine Sensors Corporation Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip
US5337388A (en) 1993-08-03 1994-08-09 International Business Machines Corporation Matrix of pluggable connectors for connecting large numbers of clustered electrical and/or opticcal cables to a module
US5502333A (en) * 1994-03-30 1996-03-26 International Business Machines Corporation Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit
JPH088389A (en) * 1994-04-20 1996-01-12 Fujitsu Ltd Semiconductor device and semiconductor device unit
JPH07312469A (en) * 1994-05-16 1995-11-28 Nippon Mektron Ltd Structure of bent part of multilayer flexible circuit board
US5509197A (en) * 1994-06-10 1996-04-23 Xetel Corporation Method of making substrate edge connector
US6247228B1 (en) * 1996-08-12 2001-06-19 Tessera, Inc. Electrical connection with inwardly deformable contacts
JPH0846136A (en) * 1994-07-26 1996-02-16 Fujitsu Ltd Semiconductor device
US6002167A (en) * 1995-09-22 1999-12-14 Hitachi Cable, Ltd. Semiconductor device having lead on chip structure
US5922061A (en) * 1995-10-20 1999-07-13 Iq Systems Methods and apparatus for implementing high speed data communications
KR0184076B1 (en) * 1995-11-28 1999-03-20 김광호 Three-dimensional stacked package
US5646446A (en) * 1995-12-22 1997-07-08 Fairchild Space And Defense Corporation Three-dimensional flexible assembly of integrated circuits
JP2810647B2 (en) * 1996-04-30 1998-10-15 山一電機株式会社 Ic package
JP3695893B2 (en) * 1996-12-03 2005-09-14 沖電気工業株式会社 Semiconductor device and a manufacturing method and mounting method thereof
US6225688B1 (en) * 1997-12-11 2001-05-01 Tessera, Inc. Stacked microelectronic assembly and method therefor
US7149095B2 (en) * 1996-12-13 2006-12-12 Tessera, Inc. Stacked microelectronic assemblies
JP3455040B2 (en) * 1996-12-16 2003-10-06 株式会社日立製作所 Source clock synchronous memory system and a memory unit
JP3011233B2 (en) * 1997-05-02 2000-02-21 日本電気株式会社 Semiconductor package and the semiconductor mounting structure
US6208521B1 (en) * 1997-05-19 2001-03-27 Nitto Denko Corporation Film carrier and laminate type mounting structure using same
US5986209A (en) * 1997-07-09 1999-11-16 Micron Technology, Inc. Package stack via bottom leaded plastic (BLP) packaging
JPH1197619A (en) * 1997-07-25 1999-04-09 Oki Electric Ind Co Ltd Semiconductor device, manufacture thereof and mounting thereof
US6040624A (en) * 1997-10-02 2000-03-21 Motorola, Inc. Semiconductor device package and method
US6097087A (en) * 1997-10-31 2000-08-01 Micron Technology, Inc. Semiconductor package including flex circuit, interconnects and dense array external contacts
US6329709B1 (en) * 1998-05-11 2001-12-11 Micron Technology, Inc. Interconnections for a semiconductor device
US6300679B1 (en) * 1998-06-01 2001-10-09 Semiconductor Components Industries, Llc Flexible substrate for packaging a semiconductor component
JP3842444B2 (en) * 1998-07-24 2006-11-08 富士通株式会社 A method of manufacturing a semiconductor device
JP2000068444A (en) * 1998-08-26 2000-03-03 Mitsubishi Electric Corp Semiconductor device
DE69938582T2 (en) * 1998-09-09 2009-06-04 Seiko Epson Corp. Semiconductor device, its manufacturing, circuit board and electronic apparatus
US6360935B1 (en) * 1999-01-26 2002-03-26 Board Of Regents Of The University Of Texas System Apparatus and method for assessing solderability
US6222737B1 (en) * 1999-04-23 2001-04-24 Dense-Pac Microsystems, Inc. Universal package and method of forming the same
JP2000353767A (en) * 1999-05-14 2000-12-19 Universal Instr Corp Board for mounting electronic component, package, mounting method, and method for housing integrated circuit chip in package
US6376769B1 (en) * 1999-05-18 2002-04-23 Amerasia International Technology, Inc. High-density electronic package, and method for making same
DE19933265A1 (en) * 1999-07-15 2001-02-01 Siemens Ag TSOP memory chip housing assembly
US6675469B1 (en) * 1999-08-11 2004-01-13 Tessera, Inc. Vapor phase connection techniques
US6572387B2 (en) * 1999-09-24 2003-06-03 Staktek Group, L.P. Flexible circuit connector for stacked chip module
CN1230046C (en) * 1999-10-01 2005-11-30 精工爱普生株式会社 Wiring board, semiconductor device and method of producing, testing and mounting the same
DE19954888C2 (en) * 1999-11-15 2002-01-10 Infineon Technologies Ag Package for a semiconductor chip
US6262895B1 (en) * 2000-01-13 2001-07-17 John A. Forthun Stackable chip package with flex carrier
JP2001203319A (en) * 2000-01-18 2001-07-27 Sony Corp Laminated semiconductor device
US6528870B2 (en) * 2000-01-28 2003-03-04 Kabushiki Kaisha Toshiba Semiconductor device having a plurality of stacked wiring boards
JP2001217388A (en) * 2000-02-01 2001-08-10 Sony Corp Electronic device and method for manufacturing the same
US6444921B1 (en) * 2000-02-03 2002-09-03 Fujitsu Limited Reduced stress and zero stress interposers for integrated-circuit chips, multichip substrates, and the like
US7115986B2 (en) * 2001-05-02 2006-10-03 Micron Technology, Inc. Flexible ball grid array chip scale packages
US6552910B1 (en) * 2000-06-28 2003-04-22 Micron Technology, Inc. Stacked-die assemblies with a plurality of microelectronic devices and methods of manufacture
US6560117B2 (en) * 2000-06-28 2003-05-06 Micron Technology, Inc. Packaged microelectronic die assemblies and methods of manufacture
JP3390412B2 (en) * 2000-08-07 2003-03-24 株式会社キャットアイ head lamp
US6441476B1 (en) * 2000-10-18 2002-08-27 Seiko Epson Corporation Flexible tape carrier with external terminals formed on interposers
JP3560333B2 (en) * 2001-03-08 2004-09-02 独立行政法人 科学技術振興機構 Metal nanowires and a method of manufacturing the same
US6884653B2 (en) * 2001-03-21 2005-04-26 Micron Technology, Inc. Folded interposer
US6910268B2 (en) * 2001-03-27 2005-06-28 Formfactor, Inc. Method for fabricating an IC interconnect system including an in-street integrated circuit wafer via
US6707684B1 (en) * 2001-04-02 2004-03-16 Advanced Micro Devices, Inc. Method and apparatus for direct connection between two integrated circuits via a connector
US6532162B2 (en) * 2001-05-26 2003-03-11 Intel Corporation Reference plane of integrated circuit packages
US6927471B2 (en) * 2001-09-07 2005-08-09 Peter C. Salmon Electronic system modules and method of fabrication
KR20030029743A (en) * 2001-10-10 2003-04-16 삼성전자주식회사 Stack package using flexible double wiring substrate
US6620651B2 (en) * 2001-10-23 2003-09-16 National Starch And Chemical Investment Holding Corporation Adhesive wafers for die attach application
US6590282B1 (en) * 2002-04-12 2003-07-08 Industrial Technology Research Institute Stacked semiconductor package formed on a substrate and method for fabrication
US6707148B1 (en) * 2002-05-21 2004-03-16 National Semiconductor Corporation Bumped integrated circuits for optical applications
US6600222B1 (en) * 2002-07-17 2003-07-29 Intel Corporation Stacked microelectronic packages
US7246431B2 (en) * 2002-09-06 2007-07-24 Tessera, Inc. Methods of making microelectronic packages including folded substrates
US6869825B2 (en) * 2002-12-31 2005-03-22 Intel Corporation Folded BGA package design with shortened communication paths and more electrical routing flexibility
US6879047B1 (en) * 2003-02-19 2005-04-12 Amkor Technology, Inc. Stacking structure for semiconductor devices using a folded over flexible substrate and method therefor
DE10319984B4 (en) * 2003-05-05 2009-09-03 Qimonda Ag Apparatus for cooling of memory modules

Patent Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3372310A (en) * 1965-04-30 1968-03-05 Radiation Inc Universal modular packages for integrated circuits
US3718842A (en) * 1972-04-21 1973-02-27 Texas Instruments Inc Liquid crystal display mounting structure
US4079511A (en) * 1976-07-30 1978-03-21 Amp Incorporated Method for packaging hermetically sealed integrated circuit chips on lead frames
US4429349A (en) * 1980-09-30 1984-01-31 Burroughs Corporation Coil connector
US4437235A (en) * 1980-12-29 1984-03-20 Honeywell Information Systems Inc. Integrated circuit package
US4567543A (en) * 1983-02-15 1986-01-28 Motorola, Inc. Double-sided flexible electronic circuit module
US4727513A (en) * 1983-09-02 1988-02-23 Wang Laboratories, Inc. Signal in-line memory module
US4645944A (en) * 1983-09-05 1987-02-24 Matsushita Electric Industrial Co., Ltd. MOS register for selecting among various data inputs
US4733461A (en) * 1984-12-28 1988-03-29 Micro Co., Ltd. Method of stacking printed circuit boards
US4724611A (en) * 1985-08-23 1988-02-16 Nec Corporation Method for producing semiconductor module
US4722691A (en) * 1986-02-03 1988-02-02 General Motors Corporation Header assembly for a printed circuit board
US4903169A (en) * 1986-04-03 1990-02-20 Matsushita Electric Industrial Co., Ltd. Shielded high frequency apparatus having partitioned shield case, and method of manufacture thereof
US4982265A (en) * 1987-06-24 1991-01-01 Hitachi, Ltd. Semiconductor integrated circuit device and method of manufacturing the same
US4983533A (en) * 1987-10-28 1991-01-08 Irvine Sensors Corporation High-density electronic modules - process and product
US5198888A (en) * 1987-12-28 1993-03-30 Hitachi, Ltd. Semiconductor stacked device
US4985703A (en) * 1988-02-03 1991-01-15 Nec Corporation Analog multiplexer
US4891789A (en) * 1988-03-03 1990-01-02 Bull Hn Information Systems, Inc. Surface mounted multilayer memory printed circuit board
US4911643A (en) * 1988-10-11 1990-03-27 Beta Phase, Inc. High density and high signal integrity connector
US5276418A (en) * 1988-11-16 1994-01-04 Motorola, Inc. Flexible substrate electronic assembly
US5081067A (en) * 1989-02-10 1992-01-14 Fujitsu Limited Ceramic package type semiconductor device and method of assembling the same
US4992849A (en) * 1989-02-15 1991-02-12 Micron Technology, Inc. Directly bonded board multiple integrated circuit module
US4992850A (en) * 1989-02-15 1991-02-12 Micron Technology, Inc. Directly bonded simm module
US5191404A (en) * 1989-12-20 1993-03-02 Digital Equipment Corporation High density memory array packaging
US5279029A (en) * 1990-08-01 1994-01-18 Staktek Corporation Ultra high density integrated circuit packages method
US5289346A (en) * 1991-02-26 1994-02-22 Microelectronics And Computer Technology Corporation Peripheral to area adapter with protective bumper for an integrated circuit chip
US5394010A (en) * 1991-03-13 1995-02-28 Kabushiki Kaisha Toshiba Semiconductor assembly having laminated semiconductor devices
US5289062A (en) * 1991-03-18 1994-02-22 Quality Semiconductor, Inc. Fast transmission gate switch
US5099393A (en) * 1991-03-25 1992-03-24 International Business Machines Corporation Electronic package for high density applications
US5714802A (en) * 1991-06-18 1998-02-03 Micron Technology, Inc. High-density electronic module
US5397916A (en) * 1991-12-10 1995-03-14 Normington; Peter J. C. Semiconductor device including stacked die
US5281852A (en) * 1991-12-10 1994-01-25 Normington Peter J C Semiconductor device including stacked die
US5198965A (en) * 1991-12-18 1993-03-30 International Business Machines Corporation Free form packaging of specific functions within a computer system
US5394300A (en) * 1992-09-04 1995-02-28 Mitsubishi Denki Kabushiki Kaisha Thin multilayered IC memory card
US5394303A (en) * 1992-09-11 1995-02-28 Kabushiki Kaisha Toshiba Semiconductor device
US5708297A (en) * 1992-09-16 1998-01-13 Clayton; James E. Thin multichip module
US5484959A (en) * 1992-12-11 1996-01-16 Staktek Corporation High density lead-on-package fabrication method and apparatus
US5384690A (en) * 1993-07-27 1995-01-24 International Business Machines Corporation Flex laminate package for a parallel processor
US5396573A (en) * 1993-08-03 1995-03-07 International Business Machines Corporation Pluggable connectors for connecting large numbers of electrical and/or optical cables to a module through a seal
US5600178A (en) * 1993-10-08 1997-02-04 Texas Instruments Incorporated Semiconductor package having interdigitated leads
US5386341A (en) * 1993-11-01 1995-01-31 Motorola, Inc. Flexible substrate folded in a U-shape with a rigidizer plate located in the notch of the U-shape
US5594275A (en) * 1993-11-18 1997-01-14 Samsung Electronics Co., Ltd. J-leaded semiconductor package having a plurality of stacked ball grid array packages
US5493476A (en) * 1994-03-07 1996-02-20 Staktek Corporation Bus communication system for stacked high density integrated circuit packages with bifurcated distal lead ends
US5592364A (en) * 1995-01-24 1997-01-07 Staktek Corporation High density integrated circuit module with complex electrical interconnect rails
US5491612A (en) * 1995-02-21 1996-02-13 Fairchild Space And Defense Corporation Three-dimensional modular assembly of integrated circuits
US5717556A (en) * 1995-04-26 1998-02-10 Nec Corporation Printed-wiring board having plural parallel-connected interconnections
US5872051A (en) * 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
US6025642A (en) * 1995-08-17 2000-02-15 Staktek Corporation Ultra high density integrated circuit packages
US6013948A (en) * 1995-11-27 2000-01-11 Micron Technology, Inc. Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US20020001216A1 (en) * 1996-02-26 2002-01-03 Toshio Sugano Semiconductor device and process for manufacturing the same
US6178093B1 (en) * 1996-06-28 2001-01-23 International Business Machines Corporation Information handling system with circuit assembly having holes filled with filler material
US6841868B2 (en) * 1996-10-08 2005-01-11 Micron Technology, Inc. Memory modules including capacity for additional memory
US6336262B1 (en) * 1996-10-31 2002-01-08 International Business Machines Corporation Process of forming a capacitor with multi-level interconnection technology
US6028352A (en) * 1997-06-13 2000-02-22 Irvine Sensors Corporation IC stack utilizing secondary leadframes
US6014316A (en) * 1997-06-13 2000-01-11 Irvine Sensors Corporation IC stack utilizing BGA contacts
US5869353A (en) * 1997-11-17 1999-02-09 Dense-Pac Microsystems, Inc. Modular panel stacking process
US6504104B2 (en) * 1997-12-10 2003-01-07 Siemens Aktiengesellschaft Flexible wiring for the transformation of a substrate with edge contacts into a ball grid array
US6186106B1 (en) * 1997-12-29 2001-02-13 Visteon Global Technologies, Inc. Apparatus for routing electrical signals in an engine
US6021048A (en) * 1998-02-17 2000-02-01 Smith; Gary W. High speed memory module
US6028365A (en) * 1998-03-30 2000-02-22 Micron Technology, Inc. Integrated circuit package and method of fabrication
US6172874B1 (en) * 1998-04-06 2001-01-09 Silicon Graphics, Inc. System for stacking of integrated circuit packages
US6180881B1 (en) * 1998-05-05 2001-01-30 Harlan Ruben Isaak Chip stack and method of making same
US6187652B1 (en) * 1998-09-14 2001-02-13 Fujitsu Limited Method of fabrication of multiple-layer high density substrate
US6347394B1 (en) * 1998-11-04 2002-02-12 Micron Technology, Inc. Buffering circuit embedded in an integrated circuit device module used for buffering clocks and other input signals
US6521530B2 (en) * 1998-11-13 2003-02-18 Fujitsu Limited Composite interposer and method for producing a composite interposer
US6343020B1 (en) * 1998-12-28 2002-01-29 Foxconn Precision Components Co., Ltd. Memory module
US6514793B2 (en) * 1999-05-05 2003-02-04 Dpac Technologies Corp. Stackable flex circuit IC package and method of making same
US6351029B1 (en) * 1999-05-05 2002-02-26 Harlan R. Isaak Stackable flex circuit chip package and method of making same
US6673651B2 (en) * 1999-07-01 2004-01-06 Oki Electric Industry Co., Ltd. Method of manufacturing semiconductor device including semiconductor elements mounted on base plate
US6839266B1 (en) * 1999-09-14 2005-01-04 Rambus Inc. Memory module with offset data lines and bit line swizzle configuration
US6689634B1 (en) * 1999-09-22 2004-02-10 Texas Instruments Incorporated Modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or LGA) package to increase device reliability
US6849949B1 (en) * 1999-09-27 2005-02-01 Samsung Electronics Co., Ltd. Thin stacked package
US6858910B2 (en) * 2000-01-26 2005-02-22 Texas Instruments Incorporated Method of fabricating a molded package for micromechanical devices
US6984885B1 (en) * 2000-02-10 2006-01-10 Renesas Technology Corp. Semiconductor device having densely stacked semiconductor chips
US6677670B2 (en) * 2000-04-25 2004-01-13 Seiko Epson Corporation Semiconductor device
US6522018B1 (en) * 2000-05-16 2003-02-18 Micron Technology, Inc. Ball grid array chip packages having improved testing and stacking characteristics
US20020006032A1 (en) * 2000-05-23 2002-01-17 Chris Karabatsos Low-profile registered DIMM
US6683377B1 (en) * 2000-05-30 2004-01-27 Amkor Technology, Inc. Multi-stacked memory package
US6690584B2 (en) * 2000-08-14 2004-02-10 Fujitsu Limited Information-processing device having a crossbar-board connected to back panels on different sides
US6526549B1 (en) * 2000-09-14 2003-02-25 Sun Microsystems, Inc. Hierarchical parasitic capacitance extraction for ultra large scale integrated circuits
US6349050B1 (en) * 2000-10-10 2002-02-19 Rambus, Inc. Methods and systems for reducing heat flux in memory systems
US6850414B2 (en) * 2001-07-02 2005-02-01 Infineon Technologies Ag Electronic printed circuit board having a plurality of identically designed, housing-encapsulated semiconductor memories
US20030002262A1 (en) * 2001-07-02 2003-01-02 Martin Benisek Electronic printed circuit board having a plurality of identically designed, housing-encapsulated semiconductor memories
US20030016710A1 (en) * 2001-07-19 2003-01-23 Satoshi Komoto Semiconductor laser device including light receiving element for receiving monitoring laser beam
US20030020153A1 (en) * 2001-07-24 2003-01-30 Ted Bruce Chip stack with differing chip package types
US6509639B1 (en) * 2001-07-27 2003-01-21 Charles W. C. Lin Three-dimensional stacked semiconductor package
US20030026155A1 (en) * 2001-08-01 2003-02-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory module and register buffer device for use in the same
US20030035328A1 (en) * 2001-08-08 2003-02-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device shiftable to test mode in module as well as semiconductor memory module using the same
US20050035440A1 (en) * 2001-08-22 2005-02-17 Tessera, Inc. Stacked chip assembly with stiffening layer
US20040031972A1 (en) * 2001-10-09 2004-02-19 Tessera, Inc. Stacked packages
US20040000708A1 (en) * 2001-10-26 2004-01-01 Staktek Group, L.P. Memory expansion and chip scale stacking system and method
US7180167B2 (en) * 2001-10-26 2007-02-20 Staktek Group L. P. Low profile stacking system and method
US20040004281A1 (en) * 2002-07-03 2004-01-08 Jin-Chuan Bai Semiconductor package with heat sink
US20040012991A1 (en) * 2002-07-18 2004-01-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory module
US20040021211A1 (en) * 2002-08-05 2004-02-05 Tessera, Inc. Microelectronic adaptors, assemblies and methods
US6998704B2 (en) * 2002-08-30 2006-02-14 Nec Corporation Semiconductor device and method for manufacturing the same, circuit board, electronic apparatus, and semiconductor device manufacturing apparatus
US6838761B2 (en) * 2002-09-17 2005-01-04 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield
US6841855B2 (en) * 2003-04-28 2005-01-11 Intel Corporation Electronic package having a flexible substrate with ends connected to one another
US20050040508A1 (en) * 2003-08-22 2005-02-24 Jong-Joo Lee Area array type package stack and manufacturing method thereof
US20050018495A1 (en) * 2004-01-29 2005-01-27 Netlist, Inc. Arrangement of integrated circuits in a memory module

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100025835A1 (en) * 2008-08-01 2010-02-04 Oh Jihoon Integrated circuit package stacking system
US8004093B2 (en) * 2008-08-01 2011-08-23 Stats Chippac Ltd. Integrated circuit package stacking system
US20120326304A1 (en) * 2011-06-24 2012-12-27 Warren Robert W Externally Wire Bondable Chip Scale Package in a System-in-Package Module

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US7485951B2 (en) 2009-02-03 grant

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