US20080067573A1 - Stacked memory and method for forming the same - Google Patents

Stacked memory and method for forming the same Download PDF

Info

Publication number
US20080067573A1
US20080067573A1 US11709234 US70923407A US2008067573A1 US 20080067573 A1 US20080067573 A1 US 20080067573A1 US 11709234 US11709234 US 11709234 US 70923407 A US70923407 A US 70923407A US 2008067573 A1 US2008067573 A1 US 2008067573A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
memory cell
transistor
semiconductor layer
forming
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US11709234
Other versions
US7683404B2 (en )
Inventor
Young-Chul Jang
Won-Seok Cho
Jae-Hoon Jang
Soon-Moon Jung
Hoo-Sung Cho
Jong-Hyuk Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221Three dimensional integrated circuits stacked in different levels
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11517Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate
    • H01L27/11526Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11517Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate
    • H01L27/11526Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region
    • H01L27/11529Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region of memory regions comprising cell select transistors, e.g. NAND
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11517Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate
    • H01L27/11551Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688Integrated circuits having a three-dimensional layout

Abstract

A stacked memory includes at least two semiconductor layers each including a memory cell array. A transistor is formed in a peripheral circuit region of an uppermost semiconductor layer of the at least two semiconductor layers. The transistor is used to operate the memory cell array.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This U.S. application claims benefit of foreign priority to Korean Patent Application No. 2006-89314, filed on Sep. 14, 2006, the disclosure of which is hereby incorporated herein by reference in its entirety.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a semiconductor device and a method for forming the semiconductor device. More particularly, the present invention relates to a stacked memory and a method for forming the stacked memory.
  • 2. Description of the Related Art
  • Memories are used in various products such as mobile products, computers, and portable products. A typical memory device includes memory cells arranged two-dimensionally on a substrate. Customers want high-capacity, high-performance, and inexpensive memory devices, but it may be difficult to satisfy such demands with memory devices that only have two-dimensionally arranged memory cells.
  • For this reason, highly integrated memories having a multi-level or three-dimensional memory cell array structures have been proposed. In a multi-level memory cell array structure, memory cell arrays are vertically stacked on a substrate. A NAND flash memory may include NAND strings in which memory cells are connected in series, which may allow integration at a higher level than other types of memories. For this reason, flash memories having a multi-level array structure (stacked memories) are being actively studied. However, the stacked memories should be further studied for high reliability.
  • SUMMARY OF THE INVENTION
  • The present invention is therefore directed to a stacked memory and method for forming the same, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.
  • At least one of the above and other features and advantages of the present invention may be realized by providing a stacked memory of at least two semiconductor layers. Each of the semiconductor layers may include a memory cell array and a transistor in a peripheral circuit region of an uppermost semiconductor layer of the at least two semiconductor layers.
  • At least one of the above and other features and advantages of the present invention may be realized by providing a method of forming a stacked memory. The method includes forming a first memory cell array at a first semiconductor layer. A second semiconductor layer is formed on the first semiconductor layer having the first memory cell array. A second memory cell array is formed in a cell array region of the second semiconductor layer. A first transistor is formed in a peripheral circuit region of the second semiconductor layer.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:
  • FIG. 1 illustrates a schematic diagram of a stacked memory device according to an embodiment of the present invention;
  • FIG. 2 illustrates an equivalent circuit diagram of the stacked memory device of FIG. 1;
  • FIG. 3 illustrates a schematic diagram of a stacked memory device according to another embodiment of the present invention;
  • FIGS. 4 through 8 illustrate cross-sectional views of stages in a method of forming the stacked memory device shown in FIG. 1 according to an embodiment of the present invention; and
  • FIGS. 9 through 12 illustrate cross-sectional views of stages in a method of forming the stacked memory device shown in FIG. 3 according to an embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE INVENTION
  • The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are illustrated. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
  • It will be understood that although terms such as “first,” “second,” and “third” are used herein to describe various regions, layers, and/or sections, these regions, layers and/or sections are not limited by these terms, which are only used to distinguish one region, layer and/or section from another region, layer and/or section. In the figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout.
  • The terms “semiconductor layer” and “substrate” are used herein to include any semiconductor-based structure. The semiconductor-based structure may include, e.g., a single-crystalline silicon structure, a silicon-on-insulator (SOI) structure, a silicon-on-sapphire (SOS) structure, a silicon-germanium structure, a doped or non-doped silicon structure, an epitaxially grown structure, etc.
  • Exemplary embodiments of the present invention are related to a stacked memory. A stacked memory according to an exemplary embodiment of the present invention may include at least two semiconductor layers, and each semiconductor layer may include a memory cell array. For convenience of explanation, the semiconductor layers may be referred to as “upper” and “lower” layers.
  • A transistor for driving the memory cell array may be provided in a peripheral circuit region of an uppermost semiconductor layer. Hereinafter, such a transistor formed in the peripheral circuit region may be referred to as a “peripheral” transistor. Multiple peripheral transistors may be provided, which may include various transistors that are used to operate the memory cell array. For example, peripheral transistors may include a high-voltage transistor and a low-voltage transistor. The high-voltage transistor may be a transistor that applies a high voltage to the memory cell array, e.g., for programming and/or erasing a memory cell of the memory cell array. The low-voltage transistor may be a transistor that applies a lower voltage, i.e., lower relative to the high voltage transistor. For example, the low-voltage transistor may be a transistor that applies Vdd or Vcc to the memory cell, or various voltages required for reading data from the memory cell. The peripheral transistors may also include a middle-voltage transistor. In the description that follows, unless noted otherwise, the low-voltage transistor, middle-voltage transistor, and high-voltage transistor may each be a peripheral transistor.
  • The memory cell arrays of the semiconductor layers may be individually formed in various ways. For example, a NAND flash memory cell array having NAND strings may be formed on the first semiconductor layer or on the second semiconductor layer, and a NOR flash memory cell array may be formed at the second semiconductor layer or the first semiconductor layer. In another implementation, an SRAM cell array may be formed at the first semiconductor layer or the second semiconductor layer, and a flash memory cell array may be formed at the second semiconductor layer or the first semiconductor layer.
  • The memory cells of the memory cell arrays may be, e.g., floating gate type memory cells. However, the present invention is not limited thereto, and other types of memory cells may be suitably employed. For example, silicon-oxide-nitride-oxide-silicon (SONOS) memory cells, metal-oxide-nitride-oxide-silicon (MONOS) memory cells, phase-changeable random access memory (PRAM) cells, and magneto-resistive random access memory (MRAM) cells may be employed. Moreover, each memory cell may store one or more bits of data.
  • In an embodiment, a peripheral transistor may be provided on an uppermost semiconductor layer of the at least two semiconductor layers of a stacked memory. Here, the uppermost semiconductor layer may be the uppermost of stacked semiconductor layers on which memory cell arrays are respectively formed, or the uppermost one of at least two stacked semiconductor layers. The peripheral transistor may be formed without the thermal budget associated with processes such as high-temperature deposition, oxidation, heat treatment for activating impurities, and rapid heat treatment. Therefore, according to embodiments of the present invention, a stacked memory having a high-performance peripheral transistor may be formed.
  • In addition, the depth of contact holes for interconnection to the peripheral transistors may be reduced, and the size of contact holes may be significantly reduced in a peripheral circuit region. Therefore, embodiments of the present invention may provide a stacked memory that can be more highly integrated. Furthermore, semiconductor layers of the stacked memory, other than the uppermost semiconductor layer, may not include a peripheral transistor, such that areas can be freed up in the lower semiconductor layers. The freed-up areas may thus be used for various other applications, e.g., additional memory cells may be provided therein.
  • In another embodiment, some peripheral transistors may be formed on a lowermost semiconductor layer of the stacked memory, or on a semiconductor layer interposed between the uppermost and lowermost semiconductor layers. For example, a heat-sensitive transistor, such as a low-voltage transistor, may be formed on the uppermost semiconductor layer, which may allow the heat-sensitive transistor to be formed without exposure to high-temperature conditions during processes for cell array regions of the semiconductor layers. A heat-tolerant transistor, such as a high-voltage transistor, may be formed on a semiconductor layer that is disposed in the stack under the uppermost semiconductor layer. In an implementation, a high-voltage peripheral transistor may be formed on the lowermost semiconductor layer, or on a semiconductor layer interposed between the uppermost and lowermost semiconductor layers, and a low-voltage transistor may be formed on the uppermost semiconductor layer of the stack. Each memory cell array of the stacked semiconductor layers may include two-dimensionally arranged memory cells.
  • In the description that follows, particular reference may be made to exemplary embodiments of the present invention wherein NAND flash memory cells are connected in series and a floating gate is used as a memory element. These particular examples are provided simply to present a clear and thorough description of the present invention, but embodiments of the present invention are not limited thereto, and various types and structures of memory cells may be arranged in the memory cell array in various ways, and various programming/erasing operations may be used for the memory cells.
  • FIG. 1 illustrates a schematic diagram of a stacked memory device according to an embodiment of the present invention. In the stacked memory device illustrated in FIG. 1, the stacked memory device may include two or more semiconductor layers. However, for clarity, only a first semiconductor layer 100 and a second semiconductor layer 200 are shown.
  • Referring to FIG. 1, the second semiconductor layer 200 may be stacked on the first semiconductor layer 100. The second semiconductor layer 200 may correspond to the uppermost semiconductor layer and the first semiconductor layer 100 may correspond to the lowermost semiconductor layer.
  • Memory cell arrays may be formed in cell array regions A of the first semiconductor layer 100 and the second semiconductor layer 200. The memory cell array of the first semiconductor layer 100 may include one or more NAND strings 110 and the memory cell array of the second semiconductor layer 200 may include one or more NAND strings 210. One or more peripheral transistors may be formed in a peripheral circuit region B of the second semiconductor layer (uppermost semiconductor layer) 200. The peripheral transistors may drive the memory cell arrays. The peripheral transistors may include a high-voltage transistor 230H and a low-voltage transistor 230L. In an implementation, the first semiconductor layer (lowermost semiconductor layer) 100 may not include a peripheral transistor.
  • The memory cell arrays of the semiconductor layers may each have a same structure. An exemplary memory cell array of the first semiconductor layer 100 will now be described. The NAND string 110 may include a memory cell string (hereinafter, “MCS”), a string selection transistor (hereinafter, “SST”), and a ground selection transistor (hereinafter, “GST”). The MCS may include a plurality of memory cells (hereinafter, individually “MC” and collectively “MCs”) connected in series. The SST may be connected to a first MC of the MCS, and the GST may be connected to a last MC of the MCS.
  • Multiple NAND strings 110 may be disposed on the first semiconductor layer 100, thereby forming a memory cell array. In an implementation, the NAND strings 110 may be repeatedly formed in a mirror-symmetric format, so as to increase the integration density of the stacked memory device. For example, the NAND strings 110 may be repeatedly formed such that GSTs of neighboring NAND strings 110 are disposed close to each other and SSTs of the neighboring NAND strings 110 are also disposed close to each other.
  • Each of the MCs, GST, and SST may include a stacked gate structure having, sequentially stacked on the first semiconductor layer 100, a gate insulation layer 101, a floating gate 103, an inter-gate insulation layer 105, and a control gate 107. The peripheral transistor may include a similar stacked gate structure on the second semiconductor layer 200. The control gates of the peripheral transistor, the SST, and the GST may be electrically connected to the floating gates through the inter-gate insulation layers.
  • The control gates of the MCs that are arranged in a direction perpendicular to cross-section illustrated in FIG. 1, i.e., in and out of the plane of FIG. 1, may be electrically connected to one another to serve as a word line (hereinafter, “WL”). For reference, the direction of MCs of the NAND string 110 illustrated in FIG. 1 will be referred to as the x-axis direction and the direction perpendicular to cross-section illustrated in FIG. 1, i.e., out of plane, will be referred to the y-axis direction. Like the control gates of the MCs forming the WL, the control gates of the SSTs arranged in the y-axis direction may be electrically connected to one another to serve as a string selection line (hereinafter “SSL”), and the control gates of the GSTs arranged in the y-axis direction may be electrically connected to one another to serve as a ground selection line (hereinafter “GSL”).
  • Each MC of the NAND string 110 may include a memory cell gate and impurity diffusion regions formed on opposite sides of the memory cell gate. In a given NAND string 110, neighboring memory cell gates may share impurity diffusion regions. As illustrated in the cell array region A of the first semiconductor layer 100, a common source region CS may be shared by neighboring NAND strings, i.e., an impurity diffusion region 109CS between the GSTs of neighboring NAND strings 110 may be common to the NAND strings 110. That is, in a same semiconductor layer, the impurity diffusion region formed between the neighboring GSTs may be shared as a common source region 109CS.
  • The common source region 109CS may extend in the y-axis direction, i.e., it may be a linear type. Further, common source regions 109CS and 209CS of the stacked semiconductor layers 100 and 200, respectively, may be electrically connected by a linear type source contact 233. The linear type source contact 233 may function as a common source line (hereinafter, “CSL”) that connects a common source region 109CS of the first semiconductor layer 100 to a common source region 209CS of the second semiconductor layer 200. The common source regions 109CS and 209CS may be considered as a CSL in light of the linear configuration of the common source regions 109CS and 209CS, with the source contact 233 connecting the CSL in the lower semiconductor layer to an adjacent CSL in the upper semiconductor layer. Neighboring GSTs of a given semiconductor layer may share a common source region given the mirror-symmetric arrangement of the NAND strings 110. Moreover, neighboring GSTs of another semiconductor layer may share the common source region owing to the source contact 233.
  • An impurity diffusion region (drain region) 109D formed at a side of a given NAND string 110, opposite to the common source region 109CS, may be electrically connected to a bit line 241 through a bit line contact plug 239. Drain regions of SSTs arranged in the y-axis direction may be electrically connected to different bit lines, and drain regions of SSTs arranged in the x-axis direction may be electrically connected to a same bit line. Further, drain regions of SSTs arranged above/below one another may be electrically connected through, for example, a bit line contact plug. In the peripheral circuit region B, impurity diffusion regions 212 of the low-voltage transistor 230L and the high-voltage transistor 230H may be electrically connected to interconnections 243 by interconnection plugs 240.
  • Gate spacers 113 and 213 may be disposed on opposite sides of the gate structures, and etch stop layers 115 and 215 may cover the gate structures and the gate spacers. The memory device may further include interlayer insulation layers 117, 217, and 235, and contact plugs (line plugs) 239 and 240.
  • FIG. 2 illustrates an equivalent circuit diagram of the stacked memory device of FIG. 1. Referring to FIG. 2, WL(1, 1) denotes a first word line of the NAND strings 110 of the first semiconductor layer 100 and WL(2, 1) denotes a first word line of the NAND strings 210 of the second semiconductor layer 200. SSL(1) denotes the SSL of the first semiconductor layer 100 and SSL(2) denotes the SSL of the second semiconductor layer 200. Similarly, GSL(1) denotes the GSL of the first semiconductor layer 100 and GSL(2) denotes the GSL of the second semiconductor layer 200. CSL denotes the common source line, e.g., the source contact 233, connecting the respective common source regions 109CS and 209CS of the first and second semiconductor layers 100 and 200.
  • FIG. 3 illustrates a schematic diagram of a stacked memory device according to another embodiment of the present invention, in which one or more peripheral transistors may be disposed on a semiconductor layer, e.g., the first semiconductor layer 100, under the uppermost semiconductor layer, which may be the second semiconductor layer 200. Referring to FIG. 3, in an implementation, a high-voltage transistor 130H may be disposed on the first semiconductor layer 100, and a low-voltage transistor 230L may be disposed on the second semiconductor layer 200.
  • In another implementation (not shown) the stacked memory device may include L semiconductor layers, where L is a natural number greater than or equal to 3, and the high-voltage transistor 130H may be disposed on the lowermost semiconductor layer, or on a semiconductor layer between the uppermost and lowermost semiconductor layers. The high-voltage transistor 130H may be less affected by high-temperature process conditions than the low-voltage transistor 230L, and, thus, the high-voltage transistor 130H may be disposed on the lowermost semiconductor layer or a semiconductor layer formed between the uppermost and lowermost semiconductor layers.
  • Hereinafter, a method of forming a stacked memory device will be described according to embodiments of the present invention. FIGS. 4 through 8 illustrate cross-sectional views of stages in a method of forming the stacked memory device shown in FIG. 1 according to an embodiment of the present invention. Referring to FIG. 4, first NAND string 110 may be formed in a cell array region A of a first semiconductor layer 100. The first NAND string 110 may include a first memory cell string (hereinafter, “MCS1”) having a plurality of first memory cells (hereinafter, individually “MC1” and collectively “MC1 s”) connected to one another in series, and a first string selection transistor (hereinafter, “SST1”) and a first ground selection transistor (hereinafter, “GST1”) that are respectively connected to MC1 s at ends of the MCS1.
  • Each of the MC1 s, SST1, and GST1 may include a stacked gate structure formed by sequentially stacking a gate insulation layer 101, a floating gate 103, an inter-gate insulation layer 105, and a control gate 107. In the SST1 and the GST1, the control gate may be electrically connected to the floating gate. The control gate 107 of the SST1 and the GST1 may be elongated in the y-axis direction, i.e., in and out of the plane of FIG. 4 and may serve as a SSL and a GSL, respectively. The control gates 107 of the MC1 s may function as word lines.
  • The gate structure may be formed by sequentially stacking the gate insulation layer 101, a first conductive layer for the floating gates 103, the inter-gate insulation layer 105, and a second conductive layer for the control gates 107 on the first semiconductor layer 100 and patterning the stacked layers. After the inter-gate insulation layer 105 is stacked, the inter-gate insulation layer 105 may be patterned to expose the lower first conductive layer, to allow for electrical connections between the floating gate 103 and the control gate 107 of the GST1, and the floating gate 103 and the control gate 107 of the SST1. That is, in the GST1 and SST1, the control gate 107 may be electrically connected to the floating gate 103 through the inter-gate insulating layer 105.
  • In an implementation, the gate insulation layer 101 may be formed of, e.g., a silicon oxide. The first conductive layer for the floating gates 103 may be formed of, e.g., polysilicon. The inter-gate insulation layer 105 may be formed by, e.g., sequentially stacking an oxide layer, a nitride layer, and an oxide layer. The second conductive layer, which may be used for forming the control gates 107, i.e., word lines, of the MC1 s and the control gates 107 (GSL and SSL) of the GST1 and SST1, may be formed of, e.g., polysilicon, metal, metal silicide, conductive metal nitride, a combination thereof, etc. The control gates 107 may be covered with a protective nitride layer.
  • After the gate structure of the first NAND string 110 is formed, impurity diffusion regions 109 may be formed in the first semiconductor layer 100 between the gate structures for source/drain regions using, e.g., ion implantation and heat treatment processes. An impurity diffusion region 109 of neighboring GST1 s may be shared as a common source region 109CS. That is, the common source region 109CS may be formed between gate structures, i.e., between GSLs, of neighboring GST1 s. Similarly, neighboring SST1 s may share a drain region 109D, as illustrated in FIG. 4.
  • Gate spacers 113 may be formed on opposite sides of the gate structures. The gate spacers 113 may be formed by, e.g., depositing a silicon nitride layer and etching the silicon nitride layer. Since the distance between the MC1 s may be very short, gate spacers 113 of neighboring memory cells may contact each other. After the gate spacers 113 are formed, a high-concentration impurity ion implantation process may be performed to improve resistive characteristics of the drain region 109D of the SST1 and the common source region 109CS of the GST1.
  • A first etch stop layer 115 may be formed as shown in FIG. 4. The first etch stop layer 115 may be formed of, e.g., a silicon nitride layer. The first etch stop layer 115 may function as an etch stop layer during a process of forming contacts. In another implementation (not shown), the first etch stop layer may be omitted.
  • Referring to FIG. 5, a first interlayer insulation layer 117 may be formed on the first etch stop layer 115. The first interlayer insulation layer 117 may be formed of, e.g., an insulation material having an etch selectivity with respect to the first etch stop layer 115. The first interlayer insulation layer 117 may be, e.g., a silicon oxide. The first interlayer insulation layer 117 and the first etch stop layer 115 may be patterned to form openings 119 that expose a portion of the first semiconductor layer 100 located beside the gate structure of the GST1 and another portion of the first semiconductor layer 100 located beside the gate structure of the SST1. That is, the common source region 109CS beside the GST1 and the drain region 109D beside the SST1 may be exposed by the openings 119. An epitaxial layer may be grown using the first semiconductor layer 100 exposed by the openings 119 as a seed layer, so as to form a second semiconductor layer 200 filling the openings 119 and covering the first interlayer insulation layer 117.
  • Referring to FIG. 6, second NAND string 210 may be formed in a cell array region A of the second semiconductor layer 200, and a peripheral gate structure 225 may be formed in a peripheral circuit region B of the second semiconductor layer 200 to form a peripheral transistor. Second NAND strings 210 may be formed with the same structure and using the same method as the first NAND strings 110.
  • In detail, a gate structure 220 may be formed in the cell array region A of the second semiconductor layer so as to form second memory cells (hereinafter, “MC2 s”), second string selection transistors (hereinafter, “SST2 s”), and second ground selection transistors (hereinafter, “GST2 s”) of the second NAND strings 210. The peripheral gate structure 225 in the peripheral circuit region B of the second semiconductor layer 200 may be similarly formed. The gate structures in the cell array region A and the peripheral circuit region B of the second semiconductor layer 200 may be formed by sequentially stacking a gate insulation layer 201, a first conductive layer, an inter-gate insulation layer 205, and a second conductive layer on the second semiconductor layer 200 and patterning the stacked layers.
  • After the inter-gate insulation layer 205 is stacked, the inter-gate insulation layer 205 may be patterned to expose the lower first conductive layer to allow for electrical connection between the floating gate 203 and the corresponding control gate 207 in the GST2, the SST2, and the peripheral transistors.
  • Impurity ions may be selectively implanted in the cell array region A of the second semiconductor layer 200 and the cell array region A may be heat treated to form impurity diffusion regions 209 between the gate structures in the cell array region A as source/drain regions. An impurity diffusion region 209 between neighboring GST2 s may be shared as a common source region 209CS. That is, the common source region 209CS may be formed between gate structures of neighboring GST2 s. Similarly, neighboring SST2 s may share a drain region 209D.
  • Referring to FIG. 7, after the impurity diffusion regions 209 are formed in the cell array region A of the second semiconductor layer 200, impurity ions may be selectively implanted in the peripheral circuit region B of the second semiconductor layer 200, and the peripheral circuit region B may be heat treated to form impurity diffusion regions 211 for peripheral transistors 230L and 230H. According to this embodiment of the present invention, the peripheral transistors 230L and 230H need not undergo the ion implantation and heat treatment processes performed for forming the impurity regions 209 in the cell array region A.
  • Gate spacers 213 may be formed on opposite sides of the gate structures of the second semiconductor layer 200. Ions may be implanted to a high concentration level, so as to form high-concentration source/drain regions 212 for the peripheral transistors 230L and 230H. At this time, ions may also be implanted to a high-concentration level into the drain region 209D of the SST2 and the source region (common source region) 209CS of the GST2, so as to improve the resistive characteristics of the drain region 209D and the source region 209CS.
  • A second etch stop layer 215 and a second interlayer insulation layer 217 may be formed, and may include materials having predetermined etch rates. For example, the second etch stop layer 215 may be formed of a silicon nitride and the second interlayer insulation layer 217 may be formed of a silicon oxide.
  • Referring to FIG. 8, the second interlayer insulation layer 217, the second etch stop layer 215, the second semiconductor layer 200, the first interlayer insulation layer 117, and the first etch stop layer 115 may be patterned to form an opening 231 for a source contact in the cell array region A. The opening 231 may expose the common source regions 109CS and 209CS formed between gate structures of the GST1 s and GST2 s of the first and second semiconductor layers 100 and 200.
  • The opening 231 may be filled with a conductive material to form a source contact 233 that electrically connects the common source regions 109CS and 209CS of the first and second semiconductor layers 100 and 200. The source contact 233 may be used as a CSL for the first and second semiconductor layers 100 and 200. In an implementation, impurity ions may be implanted into the common source regions 109CS and 209CS through the opening 231 to improve the resistive characteristics of the common source regions 109CS and 209CS.
  • A third interlayer insulation layer 235 may be formed on the second interlayer insulation layer 217 and on the source contact 233. The third interlayer insulation layer 235, the second interlayer insulation layer 217, the second etch stop layer 215, the second semiconductor layer 200, the first interlayer insulation layer 117, and the first etch stop layer 115 may be patterned to form a bit line contact hole 237 in the cell array region A that exposes the drain regions 109D and 209D between gate structures of the SST1 s and SST2 s of the first and second semiconductor layers 100 and 200. At the same time, in the peripheral circuit region B of the second semiconductor layer 200, an interconnection contact hole 238 may be formed through the third interlayer insulation layer 235, the second interlayer insulation layer 217, and the second etch stop layer 215 to expose the drain region 212. In an implementation, impurity ions may be implanted into the drain regions 109D and 209D through the bit line contact hole 237 to improve the resistive characteristics of the drain regions 109D and 209D.
  • A conductive material may be formed on the third interlayer insulation layer 235 to fill the bit line contact hole 237 and the contact hole 238 for interconnections (not shown). Then, referring again to FIG. 1, the conductive material may be patterned to form a bit line 241 in the cell array region A and a metal line 243 in the peripheral circuit region B.
  • The plurality of semiconductor layers may be stacked using various methods including, e.g., forming an upper semiconductor layer by epitaxial growth using a lower semiconductor as a seed layer, as described above. In another implementation, a plurality of semiconductor layers may be stacked by depositing amorphous silicon and heat-treating the deposited amorphous silicon. In this case, referring to FIGS. 4 and 5, after forming the NAND strings 110 in the cell array region A of the first semiconductor layer 100, and forming the first etch stop layer 115 and the first interlayer insulation layer 117 on the first semiconductor layer 100, amorphous silicon may be deposited on the first interlayer insulation layer 117 and heat treated so as to form a second semiconductor layer. The remaining processes illustrated in FIGS. 6 through 8 may then be performed as described above.
  • In another implementation, a plurality of semiconductor layers may be stacked by bonding separately-prepared semiconductor layers. In this case, referring again to FIGS. 4 and 5, after forming the NAND strings 110 in the cell array region A of the first semiconductor layer 100, and after forming the first etch stop layer 115 and the first interlayer insulation layer 117 on the first semiconductor layer 100, a separately prepared second semiconductor layer may be bonded to the first interlayer insulation layer 117. The remaining processes illustrated in FIGS. 6 through 8 may then be performed as described above.
  • FIGS. 9 through 12 illustrate cross-sectional views of stages in a method of forming the stacked memory device illustrated in FIG. 3 according to an embodiment of the present invention. A peripheral transistor, e.g., a high-voltage transistor, may be formed on the lowermost semiconductor layer or a semiconductor layer between the uppermost and lowermost semiconductor layers, instead of forming the high-voltage transistor on the uppermost semiconductor layer.
  • Referring to FIG. 9, when a NAND string 110 is formed in the cell array region A of the first semiconductor layer 100, a high-voltage transistor 130H may be formed in the peripheral circuit region B of the first semiconductor layer 100. Gate structures may be formed for MC1 s, GST1, SST1, and the high-voltage transistor 130H. Ion implantation and heat-treatment processes may be performed to form impurity diffusion regions between the gate structures as source/drain regions. Gate spacers 113 may be formed on opposite sides of the gate structures, and the first etch stop layer 115 and the first interlayer insulation layer 117 (see FIG. 10) may be formed on the gate structures and the gate spacers 113. As in the previous embodiment, after the gate spacers 113 are formed, ions may be implanted into the impurity diffusion regions of the SST1, the GST1, and the high-voltage transistor 130H to a high concentration level, so as to improve the resistive characteristics of the impurity diffusion regions.
  • Referring to FIG. 10, similar to the process described above in connection with FIG. 5, the opening 119 may be formed to expose predetermined portions of the first semiconductor layer 100, and then a second semiconductor layer 200 may disposed on the first interlayer insulation layer 117, e.g., using formation by epitaxial growth. In an implementation (not shown) another opening to enable the epitaxial growth of the second semiconductor layer 200 may be formed in the peripheral circuit region B, the opening exposing an impurity region 112 of the high-voltage transistor 130H in the peripheral circuit region B of the second semiconductor layer 100.
  • Similar to the process described above in connection with FIG. 6, a second NAND string 210 may be formed in the cell array region A of the second semiconductor layer 200, and a low-voltage gate structure 225L may be formed in the peripheral circuit region B of the second semiconductor layer 200.
  • Referring to FIG. 11, impurity diffusion regions 209, 209CS, and 209D may be formed in the cell array region A of the second semiconductor layer 200. Impurity ions may be selectively implanted in the peripheral circuit region B of the second semiconductor layer 200, and the peripheral circuit region B may be heat treated to form impurity diffusion regions 211 for a low-voltage transistor 230L. According to the current embodiment of the present invention, the low-voltage transistor 230L need not undergo the impurity ion implantation and heat treatment processes performed for the impurity diffusion regions of the cell array regions A of the first and second semiconductor layers 100 and 200.
  • Gate spacers 213 may be formed on opposite sides of the gate structures, and ions may be implanted into the second semiconductor layer 200 to a high-concentration level to form high-concentration impurity regions 212 for the low-voltage transistor 230L. At the same time, ions may be implanted into the impurity diffusion regions (the common source region 209CS and the drain region 209D) of the second semiconductor layer 200 to a high-concentration level. Subsequently, the second etch stop layer 215 and the second interlayer insulation layer 217 may be formed.
  • Referring to FIG. 12, the second interlayer insulation layer 217, the second etch stop layer 215, the second semiconductor layer 200, the first interlayer insulation layer 117, and the first etch stop layer 115 may be patterned to form the opening 231 for a source contact that exposes the common source regions 109CS and 209CS between the respective gate structures of the GST1 s and GST2 s of the first and second semiconductor layers 100 and 200. The opening 231 may be filled with a conductive material to form the source contact 233 that electrically connects the common source regions 109CS and 209CS of the first and second semiconductor layers 100 and 200.
  • The third interlayer insulation layer 235 may be formed on the second interlayer insulation layer 217 and the source contact 233. The third interlayer insulation layer 235, the second interlayer insulation layer 217, the second etch stop layer 215, the second semiconductor layer 200, the first interlayer insulation layer 117, and the first etch stop layer 115 may be patterned to form the bit line contact hole 237 that exposes drain regions 109D and 209D formed between gate structures of the SST1 s and SST2 s of the first and second semiconductor layers 100 and 200. At the same time, in the peripheral circuit region B of the second semiconductor layer 200, a first contact hole 238L may be formed through the third interlayer insulation layer 235, the second interlayer insulation layer 217, and the second etch stop layer 215 to expose the impurity region 212 of the low-voltage transistor 230L. Further, in the peripheral circuit regions B of the first and second semiconductor layers 100 and 200, a second contact hole 238H may be formed through the third interlayer insulation layer 235, the second interlayer insulation layer 217, the second etch stop layer 215, the second semiconductor layer 200, the first interlayer insulation layer 117, and the etch stop layer 115 to expose the impurity diffusion region 212 of the high-voltage transistor 230H.
  • A conductive material may be formed on the third interlayer insulation layer 235 to fill the bit line contact hole 237 and the contact holes 238L and 238H. The contact material may be patterned to form the bit line 241 in the cell array region A and metal lines 243 in the peripheral circuit region B, as illustrated in FIG. 3.
  • According to an embodiment of the invention, a highly integrated stacked memory device having a reliable peripheral transistor in a peripheral circuit region can be provided.
  • According to an embodiment of the invention, a stacked memory device can be provided in which the size, e.g., the depth, of contact holes formed in the peripheral circuit region may be reduced.
  • Exemplary embodiments of the present invention have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.

Claims (20)

  1. 1. A stacked memory comprising:
    at least two semiconductor layers, each of the at least two semiconductor layers including a memory cell array; and
    a transistor in a peripheral circuit region of an uppermost semiconductor layer of the at least two semiconductor layers
  2. 2. The stacked memory of claim 1, wherein the transistor is configured to drive the memory cell array of each of the at least two semiconductor layers.
  3. 3. The stacked memory of claim 1, wherein the transistor comprises a low-voltage transistor.
  4. 4. The stacked memory of claim 1, wherein the transistor is configured to read data from a memory cell of the memory cell array of the at least two semiconductor layers.
  5. 5. The stacked memory of claim 1, wherein the transistor comprises a low-voltage, and wherein the stacked memory further comprises a high-voltage transistor in a peripheral circuit region of a lowermost semiconductor layer or a semiconductor layer interposed between the uppermost and lowermost semiconductor layers.
  6. 6. The stacked memory of claim 5, wherein the high-voltage transistor is configured to program and/or erase a memory cell of the memory cell array of the at least two semiconductor layers.
  7. 7. The stacked memory of claim 1, wherein the memory cell array of each of the at least two semiconductor layers comprises:
    a memory cell string of memory cells connected in series;
    a string selection transistor connected to a first end memory cell of the memory cell string; and
    a ground selection transistor connected to a second end memory cell of the memory cell string.
  8. 8. The stacked memory of claim 7, further comprising:
    a bit line on the uppermost semiconductor layer and connected to the string selection transistors of the at least two semiconductor layers;
    common source regions alongside the ground selection transistors of the at least two semiconductor layers, respectively; and
    a source contact electrically connecting the common source regions.
  9. 9. The stacked memory of claim 7, wherein the transistor comprises a low-voltage transistor, and wherein the stacked memory further comprises a high-voltage transistor in a peripheral circuit region of a lowermost semiconductor layer of the at least semiconductor layers or a semiconductor layer interposed between the uppermost and lowermost semiconductor layers.
  10. 10. The stacked memory of claim 9, further comprising:
    a bit line formed on the uppermost semiconductor layer and connected to the string selection transistors of the at least two semiconductor layers;
    common source regions alongside the ground selection transistors of the at least two semiconductor layers, respectively; and
    a source contact electrically connecting the common source regions.
  11. 11. A method of forming a stacked memory, comprising:
    forming a first memory cell array at a first semiconductor layer;
    forming a second semiconductor layer on the first semiconductor layer having the first memory cell array;
    forming a second memory cell array in a cell array region of the second semiconductor layer; and
    forming a first transistor in a peripheral circuit region of the second semiconductor layer.
  12. 12. The method of claim 11, wherein forming a second memory cell array comprises forming a first impurity diffusion region, and forming a first transistor comprises forming a second impurity diffusion region, and wherein the second impurity diffusion region is formed after the first impurity diffusion region.
  13. 13. The method of claim 12, wherein the first transistor is configured to drive the first and second memory cell arrays.
  14. 14. The method of claim 12, wherein the first transistor is configured to read a data from a memory cell of first and second memory cell arrays.
  15. 15. The method of claim 11, wherein the first transistor is configured to drive the first and second memory cell arrays.
  16. 16. The method of claim 11, further comprising forming a second transistor in a peripheral circuit region of the first semiconductor layer or in a peripheral circuit region of the second semiconductor layer, the second transistor configured to operate at a higher voltage than the first transistor.
  17. 17. The method of claim 11, wherein the forming of the first memory cell array and the forming of the second memory cell array comprise:
    forming a memory cell string of memory cells connected in series; and
    forming a string selection transistor and a ground selection transistor, the string selection transistor connected to a first end memory cell of the memory cell string, and the ground selection transistor connected to a second end memory cell of the memory cell string.
  18. 18. The method of claim 17, further comprising forming a source contact electrically connected to ground selection transistors of the first and second semiconductor layers.
  19. 19. The method of claim 17, further comprising forming a bit line electrically connected to the string selection transistors of the first and second semiconductor layers.
  20. 20. The method of claim 19, further comprising forming a local interconnection electrically connected to the first transistor when the bit line is formed.
US11709234 2006-09-14 2007-02-22 Stacked memory and method for forming the same Active 2027-06-10 US7683404B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR10-2006-0089314 2006-09-14
KR2006-89314 2006-09-14
KR20060089314A KR100895853B1 (en) 2006-09-14 2006-09-14 Stacked memory and method for forming the same

Publications (2)

Publication Number Publication Date
US20080067573A1 true true US20080067573A1 (en) 2008-03-20
US7683404B2 US7683404B2 (en) 2010-03-23

Family

ID=39187676

Family Applications (1)

Application Number Title Priority Date Filing Date
US11709234 Active 2027-06-10 US7683404B2 (en) 2006-09-14 2007-02-22 Stacked memory and method for forming the same

Country Status (2)

Country Link
US (1) US7683404B2 (en)
KR (1) KR100895853B1 (en)

Cited By (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070096197A1 (en) * 2005-03-22 2007-05-03 Jae-Hoon Jang Non-volatile memory devices including etching protection layers and methods of forming the same
US20080096328A1 (en) * 2006-10-20 2008-04-24 Jung-Dal Chol Nonvolatile memory devices and methods of forming the same
US20090250745A1 (en) * 2008-04-07 2009-10-08 Kim Jae-Ho Memory devices and methods of forming and operating the same
US20090250761A1 (en) * 2008-04-07 2009-10-08 Nec Electronics Corporation Semiconductor device with transistors and its manufacturing method
US20100213458A1 (en) * 2009-02-23 2010-08-26 Micron Technology, Inc. Rigid semiconductor memory having amorphous metal oxide semiconductor channels
US20110031997A1 (en) * 2009-04-14 2011-02-10 NuPGA Corporation Method for fabrication of a semiconductor device and structure
US20110051512A1 (en) * 2009-08-25 2011-03-03 Micron Technology, Inc. 3d memory devices decoding and routing systems and methods
US20110062507A1 (en) * 2009-09-15 2011-03-17 Macronix International Co., Ltd. Semiconductor device and a method of fabricating the same
US20110199116A1 (en) * 2010-02-16 2011-08-18 NuPGA Corporation Method for fabrication of a semiconductor device and structure
US20110221006A1 (en) * 2010-03-11 2011-09-15 Spansion Llc Nand array source/drain doping scheme
JP2011228709A (en) * 2010-04-20 2011-11-10 Micron Technology Inc Flash memory having multi-level architecture
US20120306082A1 (en) * 2011-03-06 2012-12-06 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US8476145B2 (en) 2010-10-13 2013-07-02 Monolithic 3D Inc. Method of fabricating a semiconductor device and structure
US8492886B2 (en) 2010-02-16 2013-07-23 Monolithic 3D Inc 3D integrated circuit with logic
US8537613B2 (en) 2011-03-31 2013-09-17 Sandisk Technologies Inc. Multi-layer memory system
US8541819B1 (en) 2010-12-09 2013-09-24 Monolithic 3D Inc. Semiconductor device and structure
US8546250B2 (en) * 2011-08-18 2013-10-01 Wafertech Llc Method of fabricating vertical integrated semiconductor device with multiple continuous single crystal silicon layers vertically separated from one another
US8557632B1 (en) 2012-04-09 2013-10-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8574929B1 (en) 2012-11-16 2013-11-05 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US8642416B2 (en) 2010-07-30 2014-02-04 Monolithic 3D Inc. Method of forming three dimensional integrated circuit devices using layer transfer technique
US8664042B2 (en) 2009-10-12 2014-03-04 Monolithic 3D Inc. Method for fabrication of configurable systems
US8669778B1 (en) 2009-04-14 2014-03-11 Monolithic 3D Inc. Method for design and manufacturing of a 3D semiconductor device
US8674470B1 (en) 2012-12-22 2014-03-18 Monolithic 3D Inc. Semiconductor device and structure
US8686428B1 (en) 2012-11-16 2014-04-01 Monolithic 3D Inc. Semiconductor device and structure
US8687399B2 (en) 2011-10-02 2014-04-01 Monolithic 3D Inc. Semiconductor device and structure
US8703597B1 (en) 2010-09-30 2014-04-22 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8709880B2 (en) 2010-07-30 2014-04-29 Monolithic 3D Inc Method for fabrication of a semiconductor device and structure
US8742476B1 (en) 2012-11-27 2014-06-03 Monolithic 3D Inc. Semiconductor device and structure
US8754533B2 (en) 2009-04-14 2014-06-17 Monolithic 3D Inc. Monolithic three-dimensional semiconductor device and structure
US8753913B2 (en) 2010-10-13 2014-06-17 Monolithic 3D Inc. Method for fabricating novel semiconductor and optoelectronic devices
US8803206B1 (en) 2012-12-29 2014-08-12 Monolithic 3D Inc. 3D semiconductor device and structure
US8873284B2 (en) 2012-12-31 2014-10-28 Sandisk Technologies Inc. Method and system for program scheduling in a multi-layer memory
US8901613B2 (en) 2011-03-06 2014-12-02 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US8902663B1 (en) 2013-03-11 2014-12-02 Monolithic 3D Inc. Method of maintaining a memory state
US8907442B2 (en) 2009-10-12 2014-12-09 Monolthic 3D Inc. System comprising a semiconductor device and structure
US8956959B2 (en) 2010-10-11 2015-02-17 Monolithic 3D Inc. Method of manufacturing a semiconductor device with two monocrystalline layers
US8975670B2 (en) 2011-03-06 2015-03-10 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US8987079B2 (en) 2009-04-14 2015-03-24 Monolithic 3D Inc. Method for developing a custom device
US20150084204A1 (en) * 2013-09-25 2015-03-26 Jang-Gn Yun Semiconductor device and method of fabricating the same
US8994404B1 (en) 2013-03-12 2015-03-31 Monolithic 3D Inc. Semiconductor device and structure
US9000557B2 (en) 2012-03-17 2015-04-07 Zvi Or-Bach Semiconductor device and structure
US9029173B2 (en) 2011-10-18 2015-05-12 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9099424B1 (en) 2012-08-10 2015-08-04 Monolithic 3D Inc. Semiconductor system, device and structure with heat removal
US9099526B2 (en) 2010-02-16 2015-08-04 Monolithic 3D Inc. Integrated circuit device and structure
US9117749B1 (en) 2013-03-15 2015-08-25 Monolithic 3D Inc. Semiconductor device and structure
US9136153B2 (en) 2010-11-18 2015-09-15 Monolithic 3D Inc. 3D semiconductor device and structure with back-bias
US20150294695A1 (en) * 2014-04-14 2015-10-15 Jaekyu Lee Semiconductor resistive memory devices including separately controllable source lines
US9197804B1 (en) 2011-10-14 2015-11-24 Monolithic 3D Inc. Semiconductor and optoelectronic devices
US9219005B2 (en) 2011-06-28 2015-12-22 Monolithic 3D Inc. Semiconductor system and device
US9223693B2 (en) 2012-12-31 2015-12-29 Sandisk Technologies Inc. Memory system having an unequal number of memory die on different control channels
US9336133B2 (en) 2012-12-31 2016-05-10 Sandisk Technologies Inc. Method and system for managing program cycles including maintenance programming operations in a multi-layer memory
US9348746B2 (en) 2012-12-31 2016-05-24 Sandisk Technologies Method and system for managing block reclaim operations in a multi-layer memory
US9465731B2 (en) 2012-12-31 2016-10-11 Sandisk Technologies Llc Multi-layer non-volatile memory system having multiple partitions in a layer
US9509313B2 (en) 2009-04-14 2016-11-29 Monolithic 3D Inc. 3D semiconductor device
US9577642B2 (en) 2009-04-14 2017-02-21 Monolithic 3D Inc. Method to form a 3D semiconductor device
US9734050B2 (en) 2012-12-31 2017-08-15 Sandisk Technologies Llc Method and system for managing background operations in a multi-layer memory
US9734911B2 (en) 2012-12-31 2017-08-15 Sandisk Technologies Llc Method and system for asynchronous die operations in a non-volatile memory
US9778855B2 (en) 2015-10-30 2017-10-03 Sandisk Technologies Llc System and method for precision interleaving of data writes in a non-volatile memory
US9871034B1 (en) 2012-12-29 2018-01-16 Monolithic 3D Inc. Semiconductor device and structure
US9953925B2 (en) 2011-06-28 2018-04-24 Monolithic 3D Inc. Semiconductor system and device
US10043781B2 (en) 2009-10-12 2018-08-07 Monolithic 3D Inc. 3D semiconductor device and structure
US10042553B2 (en) 2015-10-30 2018-08-07 Sandisk Technologies Llc Method and system for programming a multi-layer non-volatile memory having a single fold data path
US10115663B2 (en) 2018-03-06 2018-10-30 Monolithic 3D Inc. 3D semiconductor device and structure

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100813618B1 (en) * 2006-07-25 2008-03-17 삼성전자주식회사 Semiconductor memory device with three-dimentional array structure
KR100978911B1 (en) 2008-02-28 2010-08-31 삼성전자주식회사 Semiconductor Device And Method Of Forming The Same
KR100971532B1 (en) 2008-05-27 2010-07-21 삼성전자주식회사 A semiconductor device haivng a driving transistor
KR101471492B1 (en) * 2008-12-15 2014-12-10 삼성전자주식회사 Stack array structure of the semiconductor memory device
US8624300B2 (en) * 2010-12-16 2014-01-07 Intel Corporation Contact integration for three-dimensional stacking semiconductor devices
JP5981711B2 (en) 2011-12-16 2016-08-31 ルネサスエレクトロニクス株式会社 The method of manufacturing a semiconductor device and a semiconductor device
KR20130123904A (en) 2012-05-04 2013-11-13 에스케이하이닉스 주식회사 Semiconductor memory device
KR20140089792A (en) 2013-01-07 2014-07-16 에스케이하이닉스 주식회사 Semiconductor device
JP6139370B2 (en) * 2013-10-17 2017-05-31 株式会社東芝 Nonvolatile semiconductor memory device
KR20150057696A (en) * 2013-11-20 2015-05-28 에스케이하이닉스 주식회사 Electronic device
US9355725B2 (en) 2013-12-12 2016-05-31 Cypress Semiconductor Corporation Non-volatile memory and method of operating the same
US9245898B2 (en) * 2014-06-30 2016-01-26 Sandisk Technologies Inc. NAND flash memory integrated circuits and processes with controlled gate height

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030119212A1 (en) * 2000-05-26 2003-06-26 Toshiyuki Nishihara Ferroelectric-type nonvolatile semiconductor memory and operation method thereof
US20030223292A1 (en) * 2002-05-16 2003-12-04 Hasan Nejad Stacked 1T-nmemory cell structure
US20050122771A1 (en) * 2003-12-05 2005-06-09 Bomy Chen Memory device and method of operating same
US20060071074A1 (en) * 2004-09-29 2006-04-06 Matrix Semiconductor, Inc. Doped polysilicon via connecting polysilicon layers
US20060108627A1 (en) * 2004-11-24 2006-05-25 Samsung Electronics Co., Ltd. NAND flash memory devices including multi-layer memory cell transistor structures and methods of fabricating the same
US20060125017A1 (en) * 2001-12-21 2006-06-15 Synopsys, Inc. Stacked memory cell utilizing negative differential resistance devices
US20060171224A1 (en) * 2002-08-08 2006-08-03 Hasan Nejad 1T-nmemory cell structure and its method of formation and operation
US20070132049A1 (en) * 2005-12-12 2007-06-14 Stipe Barry C Unipolar resistance random access memory (RRAM) device and vertically stacked architecture
US7327590B2 (en) * 2003-04-21 2008-02-05 Elpida Memory, Inc. Memory module and memory system
US20090046501A1 (en) * 2006-04-27 2009-02-19 Yadav Technology, Inc. Low-cost non-volatile flash-ram memory
US7521353B2 (en) * 2005-03-25 2009-04-21 Sandisk 3D Llc Method for reducing dielectric overetch when making contact to conductive features
US7553611B2 (en) * 2005-03-31 2009-06-30 Sandisk 3D Llc Masking of repeated overlay and alignment marks to allow reuse of photomasks in a vertical structure
US7589375B2 (en) * 2005-03-22 2009-09-15 Samsung Electronics Co., Ltd. Non-volatile memory devices including etching protection layers and methods of forming the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11145431A (en) 1997-11-12 1999-05-28 Hitachi Ltd Semiconductor device and manufacture thereof
JP2002026283A (en) * 2000-06-30 2002-01-25 Seiko Epson Corp Multilayered memory device and its manufacturing method
JP2002368141A (en) 2001-06-06 2002-12-20 Sony Corp Non-volatile semiconductor memory device
JP4670187B2 (en) 2001-06-06 2011-04-13 ソニー株式会社 Non-volatile semiconductor memory device

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030119212A1 (en) * 2000-05-26 2003-06-26 Toshiyuki Nishihara Ferroelectric-type nonvolatile semiconductor memory and operation method thereof
US20060125017A1 (en) * 2001-12-21 2006-06-15 Synopsys, Inc. Stacked memory cell utilizing negative differential resistance devices
US20030223292A1 (en) * 2002-05-16 2003-12-04 Hasan Nejad Stacked 1T-nmemory cell structure
US20060171224A1 (en) * 2002-08-08 2006-08-03 Hasan Nejad 1T-nmemory cell structure and its method of formation and operation
US7327590B2 (en) * 2003-04-21 2008-02-05 Elpida Memory, Inc. Memory module and memory system
US20050122771A1 (en) * 2003-12-05 2005-06-09 Bomy Chen Memory device and method of operating same
US20060071074A1 (en) * 2004-09-29 2006-04-06 Matrix Semiconductor, Inc. Doped polysilicon via connecting polysilicon layers
US20060108627A1 (en) * 2004-11-24 2006-05-25 Samsung Electronics Co., Ltd. NAND flash memory devices including multi-layer memory cell transistor structures and methods of fabricating the same
US7589375B2 (en) * 2005-03-22 2009-09-15 Samsung Electronics Co., Ltd. Non-volatile memory devices including etching protection layers and methods of forming the same
US7521353B2 (en) * 2005-03-25 2009-04-21 Sandisk 3D Llc Method for reducing dielectric overetch when making contact to conductive features
US7553611B2 (en) * 2005-03-31 2009-06-30 Sandisk 3D Llc Masking of repeated overlay and alignment marks to allow reuse of photomasks in a vertical structure
US20070132049A1 (en) * 2005-12-12 2007-06-14 Stipe Barry C Unipolar resistance random access memory (RRAM) device and vertically stacked architecture
US20090046501A1 (en) * 2006-04-27 2009-02-19 Yadav Technology, Inc. Low-cost non-volatile flash-ram memory

Cited By (96)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7671389B2 (en) 2005-03-22 2010-03-02 Samsung Electronics Co., Ltd. SRAM devices having buried layer patterns
US20070096197A1 (en) * 2005-03-22 2007-05-03 Jae-Hoon Jang Non-volatile memory devices including etching protection layers and methods of forming the same
US20100120217A1 (en) * 2005-03-22 2010-05-13 Jae-Hoon Jang Methods of Forming SRAM Devices having Buried Layer Patterns
US7589375B2 (en) * 2005-03-22 2009-09-15 Samsung Electronics Co., Ltd. Non-volatile memory devices including etching protection layers and methods of forming the same
US8048727B2 (en) 2005-03-22 2011-11-01 Samsung Electronics Co., Ltd. Methods of forming SRAM devices having buried layer patterns
US7572684B2 (en) * 2006-10-20 2009-08-11 Samsung Electronics Co., Ltd. Nonvolatile memory devices and methods of forming the same
US20080096328A1 (en) * 2006-10-20 2008-04-24 Jung-Dal Chol Nonvolatile memory devices and methods of forming the same
US20090250761A1 (en) * 2008-04-07 2009-10-08 Nec Electronics Corporation Semiconductor device with transistors and its manufacturing method
US20090250745A1 (en) * 2008-04-07 2009-10-08 Kim Jae-Ho Memory devices and methods of forming and operating the same
US7888731B2 (en) * 2008-04-07 2011-02-15 Samsung Electronics Co., Ltd. Memory devices and methods of forming and operating the same
US8138551B2 (en) * 2008-04-07 2012-03-20 Renesas Electronics Corporation Semiconductor device with transistors and its manufacturing method
KR101420352B1 (en) 2008-04-07 2014-07-16 삼성전자주식회사 Memory device and method of operating the same
USRE46949E1 (en) 2008-11-14 2018-07-10 Toshiba Memory Corporation Non-volatile semiconductor storage device
US20100213458A1 (en) * 2009-02-23 2010-08-26 Micron Technology, Inc. Rigid semiconductor memory having amorphous metal oxide semiconductor channels
US8669778B1 (en) 2009-04-14 2014-03-11 Monolithic 3D Inc. Method for design and manufacturing of a 3D semiconductor device
US8987079B2 (en) 2009-04-14 2015-03-24 Monolithic 3D Inc. Method for developing a custom device
US9577642B2 (en) 2009-04-14 2017-02-21 Monolithic 3D Inc. Method to form a 3D semiconductor device
US9412645B1 (en) 2009-04-14 2016-08-09 Monolithic 3D Inc. Semiconductor devices and structures
US20110031997A1 (en) * 2009-04-14 2011-02-10 NuPGA Corporation Method for fabrication of a semiconductor device and structure
US8754533B2 (en) 2009-04-14 2014-06-17 Monolithic 3D Inc. Monolithic three-dimensional semiconductor device and structure
US9509313B2 (en) 2009-04-14 2016-11-29 Monolithic 3D Inc. 3D semiconductor device
US8320181B2 (en) * 2009-08-25 2012-11-27 Micron Technology, Inc. 3D memory devices decoding and routing systems and methods
US20110051512A1 (en) * 2009-08-25 2011-03-03 Micron Technology, Inc. 3d memory devices decoding and routing systems and methods
CN102625948A (en) * 2009-08-25 2012-08-01 美光科技公司 3D memory devices decoding and routing systems and methods
US20110062507A1 (en) * 2009-09-15 2011-03-17 Macronix International Co., Ltd. Semiconductor device and a method of fabricating the same
US8471324B2 (en) * 2009-09-15 2013-06-25 Macronix International Co., Ltd. Semiconductor device
US10043781B2 (en) 2009-10-12 2018-08-07 Monolithic 3D Inc. 3D semiconductor device and structure
US8907442B2 (en) 2009-10-12 2014-12-09 Monolthic 3D Inc. System comprising a semiconductor device and structure
US9406670B1 (en) 2009-10-12 2016-08-02 Monolithic 3D Inc. System comprising a semiconductor device and structure
US8664042B2 (en) 2009-10-12 2014-03-04 Monolithic 3D Inc. Method for fabrication of configurable systems
US8846463B1 (en) 2010-02-16 2014-09-30 Monolithic 3D Inc. Method to construct a 3D semiconductor device
US20110199116A1 (en) * 2010-02-16 2011-08-18 NuPGA Corporation Method for fabrication of a semiconductor device and structure
US8492886B2 (en) 2010-02-16 2013-07-23 Monolithic 3D Inc 3D integrated circuit with logic
US9564432B2 (en) 2010-02-16 2017-02-07 Monolithic 3D Inc. 3D semiconductor device and structure
US9099526B2 (en) 2010-02-16 2015-08-04 Monolithic 3D Inc. Integrated circuit device and structure
US20110221006A1 (en) * 2010-03-11 2011-09-15 Spansion Llc Nand array source/drain doping scheme
JP2011228709A (en) * 2010-04-20 2011-11-10 Micron Technology Inc Flash memory having multi-level architecture
US8642416B2 (en) 2010-07-30 2014-02-04 Monolithic 3D Inc. Method of forming three dimensional integrated circuit devices using layer transfer technique
US8709880B2 (en) 2010-07-30 2014-04-29 Monolithic 3D Inc Method for fabrication of a semiconductor device and structure
US8703597B1 (en) 2010-09-30 2014-04-22 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9419031B1 (en) 2010-10-07 2016-08-16 Monolithic 3D Inc. Semiconductor and optoelectronic devices
US20150123072A1 (en) * 2010-10-11 2015-05-07 Monolithic 3D Inc. Semiconductor device and structure
US9818800B2 (en) * 2010-10-11 2017-11-14 Monolithic 3D Inc. Self aligned semiconductor device and structure
US8956959B2 (en) 2010-10-11 2015-02-17 Monolithic 3D Inc. Method of manufacturing a semiconductor device with two monocrystalline layers
US8753913B2 (en) 2010-10-13 2014-06-17 Monolithic 3D Inc. Method for fabricating novel semiconductor and optoelectronic devices
US8476145B2 (en) 2010-10-13 2013-07-02 Monolithic 3D Inc. Method of fabricating a semiconductor device and structure
US8823122B2 (en) 2010-10-13 2014-09-02 Monolithic 3D Inc. Semiconductor and optoelectronic devices
US9136153B2 (en) 2010-11-18 2015-09-15 Monolithic 3D Inc. 3D semiconductor device and structure with back-bias
US8541819B1 (en) 2010-12-09 2013-09-24 Monolithic 3D Inc. Semiconductor device and structure
US8450804B2 (en) * 2011-03-06 2013-05-28 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US8975670B2 (en) 2011-03-06 2015-03-10 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US20120306082A1 (en) * 2011-03-06 2012-12-06 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US8901613B2 (en) 2011-03-06 2014-12-02 Monolithic 3D Inc. Semiconductor device and structure for heat removal
US8537613B2 (en) 2011-03-31 2013-09-17 Sandisk Technologies Inc. Multi-layer memory system
US9219005B2 (en) 2011-06-28 2015-12-22 Monolithic 3D Inc. Semiconductor system and device
US9953925B2 (en) 2011-06-28 2018-04-24 Monolithic 3D Inc. Semiconductor system and device
US8546250B2 (en) * 2011-08-18 2013-10-01 Wafertech Llc Method of fabricating vertical integrated semiconductor device with multiple continuous single crystal silicon layers vertically separated from one another
US8841676B2 (en) 2011-08-18 2014-09-23 Wafertech, Llc Vertical integrated semiconductor device with multiple continuous single crystal silicon layers vertically separated from one another
US8687399B2 (en) 2011-10-02 2014-04-01 Monolithic 3D Inc. Semiconductor device and structure
US9030858B2 (en) 2011-10-02 2015-05-12 Monolithic 3D Inc. Semiconductor device and structure
US9197804B1 (en) 2011-10-14 2015-11-24 Monolithic 3D Inc. Semiconductor and optoelectronic devices
US9029173B2 (en) 2011-10-18 2015-05-12 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9000557B2 (en) 2012-03-17 2015-04-07 Zvi Or-Bach Semiconductor device and structure
US8557632B1 (en) 2012-04-09 2013-10-15 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US8836073B1 (en) 2012-04-09 2014-09-16 Monolithic 3D Inc. Semiconductor device and structure
US9305867B1 (en) 2012-04-09 2016-04-05 Monolithic 3D Inc. Semiconductor devices and structures
US9099424B1 (en) 2012-08-10 2015-08-04 Monolithic 3D Inc. Semiconductor system, device and structure with heat removal
US8574929B1 (en) 2012-11-16 2013-11-05 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US8686428B1 (en) 2012-11-16 2014-04-01 Monolithic 3D Inc. Semiconductor device and structure
US8742476B1 (en) 2012-11-27 2014-06-03 Monolithic 3D Inc. Semiconductor device and structure
US8921970B1 (en) 2012-12-22 2014-12-30 Monolithic 3D Inc Semiconductor device and structure
US8674470B1 (en) 2012-12-22 2014-03-18 Monolithic 3D Inc. Semiconductor device and structure
US9252134B2 (en) 2012-12-22 2016-02-02 Monolithic 3D Inc. Semiconductor device and structure
US9911627B1 (en) 2012-12-29 2018-03-06 Monolithic 3D Inc. Method of processing a semiconductor device
US9385058B1 (en) 2012-12-29 2016-07-05 Monolithic 3D Inc. Semiconductor device and structure
US8803206B1 (en) 2012-12-29 2014-08-12 Monolithic 3D Inc. 3D semiconductor device and structure
US9871034B1 (en) 2012-12-29 2018-01-16 Monolithic 3D Inc. Semiconductor device and structure
US9460978B1 (en) 2012-12-29 2016-10-04 Monolithic 3D Inc. Semiconductor device and structure
US9460991B1 (en) 2012-12-29 2016-10-04 Monolithic 3D Inc. Semiconductor device and structure
US9223693B2 (en) 2012-12-31 2015-12-29 Sandisk Technologies Inc. Memory system having an unequal number of memory die on different control channels
US9734911B2 (en) 2012-12-31 2017-08-15 Sandisk Technologies Llc Method and system for asynchronous die operations in a non-volatile memory
US9465731B2 (en) 2012-12-31 2016-10-11 Sandisk Technologies Llc Multi-layer non-volatile memory system having multiple partitions in a layer
US9348746B2 (en) 2012-12-31 2016-05-24 Sandisk Technologies Method and system for managing block reclaim operations in a multi-layer memory
US9734050B2 (en) 2012-12-31 2017-08-15 Sandisk Technologies Llc Method and system for managing background operations in a multi-layer memory
US8873284B2 (en) 2012-12-31 2014-10-28 Sandisk Technologies Inc. Method and system for program scheduling in a multi-layer memory
US9336133B2 (en) 2012-12-31 2016-05-10 Sandisk Technologies Inc. Method and system for managing program cycles including maintenance programming operations in a multi-layer memory
US9496271B2 (en) 2013-03-11 2016-11-15 Monolithic 3D Inc. 3DIC system with a two stable state memory and back-bias region
US8902663B1 (en) 2013-03-11 2014-12-02 Monolithic 3D Inc. Method of maintaining a memory state
US8994404B1 (en) 2013-03-12 2015-03-31 Monolithic 3D Inc. Semiconductor device and structure
US9117749B1 (en) 2013-03-15 2015-08-25 Monolithic 3D Inc. Semiconductor device and structure
US20150084204A1 (en) * 2013-09-25 2015-03-26 Jang-Gn Yun Semiconductor device and method of fabricating the same
US9620190B2 (en) * 2014-04-14 2017-04-11 Samsung Electronics Co., Ltd. Semiconductor resistive memory devices including separately controllable source lines
US20150294695A1 (en) * 2014-04-14 2015-10-15 Jaekyu Lee Semiconductor resistive memory devices including separately controllable source lines
US10042553B2 (en) 2015-10-30 2018-08-07 Sandisk Technologies Llc Method and system for programming a multi-layer non-volatile memory having a single fold data path
US9778855B2 (en) 2015-10-30 2017-10-03 Sandisk Technologies Llc System and method for precision interleaving of data writes in a non-volatile memory
US10115663B2 (en) 2018-03-06 2018-10-30 Monolithic 3D Inc. 3D semiconductor device and structure

Also Published As

Publication number Publication date Type
KR100895853B1 (en) 2009-05-06 grant
KR20080024764A (en) 2008-03-19 application
US7683404B2 (en) 2010-03-23 grant

Similar Documents

Publication Publication Date Title
US7696559B2 (en) Semiconductor memory device including pillar-shaped semiconductor layers and a method of fabricating the same
US7847342B2 (en) Non-volatile semiconductor storage device and method of manufacturing the same
US8208279B2 (en) Integrated circuit self aligned 3D memory array and manufacturing method
US7821058B2 (en) Nonvolatile semiconductor memory and method for manufacturing the same
US6376876B1 (en) NAND-type flash memory devices and methods of fabricating the same
US8503213B2 (en) Memory architecture of 3D array with alternating memory string orientation and string select structures
US8383512B2 (en) Method for making multilayer connection structure
US8372720B2 (en) Non-volatile semiconductor storage device and method of manufacturing the same
US20120248399A1 (en) Semiconductor storage device and method for manufacturing same
US20080173933A1 (en) Semiconductor memory device
US20090173981A1 (en) Nonvolatile semiconductor storage device and method of manufacturing the same
US20050269626A1 (en) Vertical NAND flash memory device
US20090242968A1 (en) Nonvolatile semiconductor memory device and method for manufacturing same
US20080173928A1 (en) Nonvolatile semiconductor memory and process of producing the same
US20130009235A1 (en) Non-volatile memory device and method of manufacturing the same
US20080087932A1 (en) NAND flash memory devices having 3-dimensionally arranged memory cells and methods of fabricating the same
US20110084397A1 (en) 3d integrated circuit layer interconnect
US20060108627A1 (en) NAND flash memory devices including multi-layer memory cell transistor structures and methods of fabricating the same
US20110018051A1 (en) Integrated Circuit Memory Devices Having Vertical Transistor Arrays Therein and Methods of Forming Same
US7910432B2 (en) Non-volatile semiconductor storage device and method of manufacturing the same
US20090027955A1 (en) Non-volatile memory devices including stacked nand-type resistive memory cell strings and methods of fabricating the same
US20120007167A1 (en) 3D Memory Array With Improved SSL and BL Contact Layout
US20100327323A1 (en) Three-dimensional nonvolatile memory device and method for fabricating the same
US20100006922A1 (en) Nonvolatile semiconductor memory device
US20080157092A1 (en) Nonvolatile semiconductor memory

Legal Events

Date Code Title Description
AS Assignment

Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JANG, YOUNG-CHUL;CHO, WON-SEOK;JANG, JAE-HOON;AND OTHERS;REEL/FRAME:019017/0330

Effective date: 20070109

Owner name: SAMSUNG ELECTRONICS CO., LTD.,KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JANG, YOUNG-CHUL;CHO, WON-SEOK;JANG, JAE-HOON;AND OTHERS;REEL/FRAME:019017/0330

Effective date: 20070109

FPAY Fee payment

Year of fee payment: 4

MAFP

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552)

Year of fee payment: 8