US20080017407A1 - Interposer and electronic device using the same - Google Patents

Interposer and electronic device using the same Download PDF

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Publication number
US20080017407A1
US20080017407A1 US11491288 US49128806A US2008017407A1 US 20080017407 A1 US20080017407 A1 US 20080017407A1 US 11491288 US11491288 US 11491288 US 49128806 A US49128806 A US 49128806A US 2008017407 A1 US2008017407 A1 US 2008017407A1
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Prior art keywords
interposer
formed
substrate
hole
conductors
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Abandoned
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US11491288
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Shuichi Kawano
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Ibiden Co Ltd
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Ibiden Co Ltd
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
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    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
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    • H01L23/50Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/05005Structure
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4602Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H05K3/4608Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated comprising an electrically conductive core

Abstract

A novel interposer(10) includes a silicon substrate(12), a plurality of through-hole conductors (20) formed on the silicon substrate, and capacitors (15) having of upper and lower electrodes (14,18) formed with land portions, respectively, of the through-hole conductors, and a dielectric layer (16) formed between both the electrodes. When desired, wiring pattern layers can be formed on a layer separate from the capacitors.

Description

    BACKGROUND OF THE INVENTION
  • [0001]
    1. Field of the Invention
  • [0002]
    The present invention relates to an interposer and an electronic device using it, and, more particularly, to an interposer interposed between a semiconductor chip and a package substrate as well as to an electronic device composed of a combination of the semiconductor chip, the interposer, and the package substrate.
  • [0003]
    2. Description of the Related Art
  • [0004]
    There is conventionally known an interposer utilizing a printed wiring board for carrying out wiring between a semiconductor chip and a package substrate. The interposer is a wiring device used to mutually connect a conductor circuit of a semiconductor chip which has an ultra dense pitch (for example, 50 μm) and a conductor circuit of a package substrate (also referred to as “mounting substrate”) which has a pitch more coarse than the above pitch (for example, 150 μm).
  • [0005]
    Recently, an example of an interposer including a capacitor is disclosed in Japanese Patent Laid-open Publication No. 2001-326305 entitled “Interposer for Semiconductor Device, Method of Manufacturing the Same, and Semiconductor Device (published on Nov. 22, 2001).
  • [0006]
    Claim 1 of the Laid-open publication states “An interposer for a semiconductor device having first electrodes, dielectric layers formed on the first electrodes, and second electrodes formed on the dielectric layer, characterized in that a necessary number of capacitors composed of the first electrodes, the dielectric layers, and the second electrodes are formed on the interposer”.
  • [0007]
    The Japanese Patent laid-open Publication describes “Further, since a wiring is carried out by a wiring pattern on the interposer, a fine pattern can be achieved. Accordingly, since the wiring is carried out on the interposer, it is possible to reduce one layer from the layers on a mounting substrate made by a multilayer board” (see paragraph 0006).
  • SUMMARY OF THE INVENTION
  • [0008]
    However, the inventor has found by his study carried out thereafter that various problems may arise when a capacitor and a wiring layer are formed together on the interposer as disclosed in the Japanese Patent laid-open Publication.
  • [0009]
    Accordingly, an object of the present invention is to provide a novel interposer and electronic device using it.
  • [0010]
    An interposer of the present invention comprises a capacitor formed on a generally entire surface of a substrate.
  • [0011]
    The interposer may comprise the substrate including a plurality of through-hole conductors; some of the through hole conductors that have land portions formed with an upper electrode of the capacitors; some of the remaining of the through-hole conductors that have land portions formed with a lower electrode of the capacitor; and a dielectric layer interposed between the upper electrodes and the lower electrodes.
  • [0012]
    In the interposer, some of the through-hole conductors may be formed as through-hole conductors for signal on a central portion of the surface of the substrate, and through-hole conductors for power supply for forming one of the upper and lower electrodes and through-hole conductors for ground for forming the other of the upper and lower electrodes may be formed surrounding the through-hole conductors for signal.
  • [0013]
    In the interposer, some of the through-hole conductors may be formed as through-hole conductors for signal on a peripheral region of the surface of the substrate, and through-hole conductors for power supply for forming one of the upper and lower electrodes and through-hole conductors for ground for forming the other of the upper and lower electrodes may be formed inside of the peripheral region.
  • [0014]
    The interposer may further comprise a wiring layer that is formed on at least one insulating layer disposed above the capacitors.
  • [0015]
    In the interposer, the substrate may be a silicon substrate.
  • [0016]
    In the interposer, the through-hole conductors may be made of copper.
  • [0017]
    In the interposer, the upper and lower electrodes may be made of nickel or platinum.
  • [0018]
    In the interposer, the dielectric layer may be made of a ferroelectric substance.
  • [0019]
    In the interposer, the dielectric layer may be made of barium titanate.
  • [0020]
    In the interposer, at least one surface of the interposer may be covered with a solder resist layer or an insulating resin layer.
  • [0021]
    An electronic device of the present invention comprises an IC chip; a package substrate; and an interposer, according to claim 1 or 2, interposed between the IC chip and the package substrate and electrically connected to the both, wherein the interposer provides capacitors.
  • [0022]
    According to the present invention, there are provided the novel interposer and the electronic device using it.
  • BRIEF DESCRIPTION OF DRAWINGS
  • [0023]
    FIG. 1 is a sectional view showing a main portion of an embodiment of an interposer according to this invention;
  • [0024]
    FIG. 2 is a sectional view showing a main portion of another interposer according to this invention;
  • [0025]
    FIG. 3 is a sectional view showing an actual arrangement of the interposer; and
  • [0026]
    FIG. 4 is a sectional view showing an actual arrangement of the another interposer.
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • [0027]
    Embodiments of novel interposers and electronic devices using the interposers according to the present invention will be explained below in detail with reference to the accompanying drawings. It should be understood that the embodiments are only exemplified and the present invention is not limited thereto. Also, note that, in the drawings, the same components are denoted by the same reference numerals to omit duplicate explanation.
  • [Interposer]
  • [0028]
    FIG. 1 is a sectional view showing an embodiment of a main portion of an interposer 10 according to this invention. The main portion of the interposer 10 includes through-hole conductors 20-1, 20-2, 20-3 formed on a silicon substrate 12, lower electrodes 18 formed on a surface of the silicon substrate 12, a dielectric layer 16 formed on the lower electrodes 18, and upper electrodes 14 formed on the dielectric layer 16.
  • [0029]
    When the surface of the silicon substrate 12 is properly polished, it has such a property that the surface is very flat and smooth. Alternatively a glass substrate and a polyimide substrate may be used in place of the silicon substrate when they satisfy the level of a surface flatness required in this embodiment.
  • [0030]
    The through-hole conductors 20-1 of the through-hole conductors 20 formed on the silicon substrate 12 are conductors for signal supply and transmit a signal between a semiconductor chip (not shown) and a package substrate (not shown) as described later. The through-hole conductors 20-2 are conductors for power supply, and the land portions of the through-hole conductors 20-2 extend to form, for example, the lower broad electrodes 18. The through-hole conductors 20-3 are conductors for ground (GND), and the land portions of the through-hole conductors 20-3 extend to form, for example, the upper broad electrodes 14.
  • [0031]
    Alternatively, the upper electrodes 14 may be formed as the land portions of the through-hole conductors 20-2 for power supply, while the lower electrodes 18 may be formed as the land portions of the through-hole conductors 20-3 for GND.
  • [0032]
    The upper and lower electrodes 14, 18 each are formed of an appropriate metal. In this embodiment the upper electrodes 14 are formed of, for example, nickel (Ni), and the lower electrodes 18 are formed of, for examples, platinum (Pt), for convenience of production. However, they may be formed of other metals.
  • [0033]
    The dielectric layer 16 is preferably composed of a high dielectric substance, for example, barium titanate (BaTiO3) having ferroelectricity.
  • [0034]
    Here, the upper electrodes 14 (the land portions of the through-hole conductors 20-3 for GND), the dielectric layer 16, and the lower electrodes 18 (or the land portions of the through-hole conductors 20-2 for power supply) form capacitors 15.
  • [0035]
    As described later, the interposer 10 shown in FIG. 1 is interposed between a semiconductor chip (not shown) and a package substrate (also referred to as a “mounting substrate”) (not shown). The interposer 10 is located very near to the semiconductor chip and functions as a decoupling capacitor between a power supply and the ground to absorb noise.
  • [0036]
    A features of the interposer 10 shown in FIG. 1 are that only the through-hole conductors 20 and the dielectric layer 16 are formed on the silicon substrate 12 and that the land portions of the through-hole conductors 20 form the upper or lower electrodes 14, 18. In other words, a wiring pattern that occupies the surface area of the silicon substrate 12 does not exist in the interposer 10 shown in FIG. 1. Accordingly, the electrodes 14, 18 of the capacitors can be spread out on the surface of the silicon substrate 12 to have a large area.
  • [0037]
    Further, since the silicon substrate 12 used for the interposer 10 shown in FIG. 1 has a very flat and smooth surface, the dielectric layer 16 can be formed very thin since the gap between the upper electrode 14 and the lower electrode 18 can be formed very narrow.
  • [0038]
    Further, a barium titanate (BaTIO3) layer being of ferroelectricity can be employed as the dielectric layer 16 used for the interposer 10 shown in FIG. 1.
  • [0039]
    The interposer 10 shown in FIG. 1 can form a capacitor (condenser) having a very large capacity by employing at least one of above described factors.
  • [0040]
    FIG. 2 is a sectional view showing another embodiment of main portion of an interposer according to this invention. On the main portion of the interposer shown in FIG. 1, the capacitors 15 are formed in that the through-hole conductors 20-2 for power supply and the through-hole conductors 20-3 for ground are disposed on a central portion of the surface of the silicon substrate 12 and that these through-hole conductors 20-2, 20-3 are surrounded by the through-hole conductors 20-1 for signal supply disposed on a peripheral region of the surface of the silicon substrate 12. In contrast, the main portion of the interposer shown in FIG. 2 is different from that shown in FIG. 1 in that the through-hole conductors 20-2 for power supply and the through-hole conductors 20-3 for ground are disposed on the peripheral region of the surface of the silicon substrate 12 and the through-hole conductors 20-1 for signal are disposed to a central portion surrounded by these through-hole conductors 20-2, 20-3.
  • [0041]
    As shown in FIG. 2, the land portions of the through-hole conductors 20-2 for power supply extend to form the broad upper electrodes 14 and are insulated from the lower electrodes 18 by gap 16. The through-hole conductors 20-1 for signal are insulated from the upper electrodes 14 by clearances 24 and are insulated from the lower electrodes 18 by the clearances 26. The land portions of the through-hole conductors 20-3 extend to form the lower electrodes 18.
  • [0042]
    Alternatively, the through-hole conductors 20-1, the through-hole conductors 20-2, and the through-hole conductors 20-3 may be disposed in mixture.
  • [0043]
    FIG. 3 is a sectional view showing an actual arrangement of the interposer 10. The interposer 10 is interposed between an IC chip (IC) 40 and a package substrate (PK) 42 and is connected to the IC chip 40 through solder bumps 26 and to the package substrate 42 through solder bumps 30, respectively, by soldering.
  • [0044]
    In addition to the upper electrodes 14, the dielectric layer 16, the lower electrodes 18, the silicon substrate 12, and the through-hole conductors 20 explained in relation to FIGS. 1 and 2, the interposer 10 shown in FIG. 3 includes an insulating resin layer 21 formed on the upper electrodes 14, nickel (Ni) lands 24-1 connected to the through-hole conductor through openings of the insulating resin layer 21, gold (Au) plated layers 24-2 overlaying the nickel lands 24-1, the solder bumps 26 formed on the gold plated layers 24-2, a solder resist layer 28 formed on the lower surface of the silicon substrate 12, and the solder bumps 30 formed on land portions of the through-hole conductors 20 through openings of the solder resist layer 28.
  • [0045]
    The interposer 10 shown in FIG. 3 possesses the same function and features as those of the interposer explained in relation to FIGS. 1 and 2. That is, the interposer 10 is located very near to the semiconductor chip 40 so that it absorbs noise by functioning as a decoupling capacitor between a power supply and the ground. The feature of the interposer 10 resides in the facts that: (1) since these exists no a wiring pattern that occupies the surface of the silicon substrate 12, the electrodes 14, 18 for capacitor (condenser) having large areas can be formed; (2) since the surface of the silicon substrate 12 is very flat and smooth, the gap between the upper electrodes 14 and the lower electrodes 18 can be narrowed; and (3) since ferroelectric dielectric substance can be employed for the dielectric layer 16, the capacitor (condenser) having the greatly large capacity can be formed.
  • [0046]
    FIG. 4 is a sectional view showing an actual arrangement of another interposer 10. The arrangement of the interposer 10 shown in FIG. 4 is different from that of FIG. 3 in that wiring layers 23-1, 23-2 are added.
  • [0047]
    In addition to the upper electrodes 14, the dielectric layer 16, the lower electrodes 18, the silicon substrate 12, the through-hole conductors 20, the solder bumps 26, the solder resist layer 28, and the solder bumps 30 explained in relation to FIG. 3, the interposer 10 shown in FIG. 4 includes a lower interlayer insulating resin layer 21-1 on which the land portions of the through-hole conductor or the wiring patterns 23-1 are formed, and an upper interlayer insulating resin layer 21-2 on which the land portion of the through hole conductor portions or the wiring patterns 23-2 are formed.
  • [0048]
    However, the wiring patterns 23-1, 23-2 are formed on the layers different from those of the capacitors 15 (i.e. on the interlayer insulating resin layers 21-1, 21-2). That is, since no wiring pattern exists in the capacitors 15 formed by the upper electrodes 14, the dielectric layer 16, and the lower electrodes 18, capacitor electrodes having a large area can be still formed.
  • [0049]
    Accordingly, the interposer 10 shown in FIG. 4 possesses the same function and features as those of the interposer explained in relation to FIGS. 1 and 3. That is, the function of the interposer 10 shown in FIG. 4 is such that it is located very near to the semiconductor chip 40 to function as a decoupling capacitor between a power supply and the ground to absorb noise. The features of the interposer 10 are as follows: Since no wiring pattern exists in the portions of the capacitors 15, the electrodes for capacitors having a large area can be formed. Since the surface of the silicon substrate 12 is very flat and smooth, the space between the upper electrodes 14 and the lower electrodes 18 can be made very narrow. Since a ferroelectric substance can be utilized for the dielectric layer 16, the capacitor (condenser) having the greatly large capacity can be formed.
  • (Manufacturing Method)
  • [0050]
    Although a method of manufacturing the interposers 10 shown in FIGS. 2 and 3 is not shown, they can be manufactured as described, for example, below. First, the silicon substrate 12 is prepared, the lower electrodes 18 are then formed by patterning on the silicon substrate 12, the dielectric layer 16 is then formed on the lower electrode by sputtering and the like while controlling its thickness, and further the upper electrodes 14 are formed on the dielectric layer by patterning. When desired, the lower and upper interlayer insulating resin layers 21-1, 21-2 may be formed to form wiring layers. They are formed by a known buildup method. Further, openings are formed from the back surface of the silicon substrate 12, and the through-hole conductors 20 are formed. When desired, solder resists 28, 38 may be formed by, for example, a screen printing.
  • [Electronic Device Using Interposer]
  • [0051]
    The interposer 10 shown in FIG. 2 is interposed between the IC chip 40 and the package substrate 42, and is connected to the both to form electronic device 70 that is composed of a combination of the semiconductor chip, the interposer, and the package substrate.
  • [0052]
    After the interposer 10 is manufactured, the electronic device 70 is formed by subjecting the solder bumps 26, 30 to reflow and connecting the interposer 10 to the semiconductor chip 40 and the package substrate 42, respectively, by soldering. The interposer 10 is located in the vicinity of the semiconductor chip 40 and functions as the decoupling capacitor having a large capacity.
  • [0053]
    The interposer 10 shown in FIG. 3 is interposed between the IC chip 40 and the package substrate 42 to be connected to each other, and forms electronic device 70 that is composed of a combination of the semiconductor chip, the interposer, and the package substrate. After the interposer 10 is manufactured, the electronic device 70 is formed by reflowing the solder bumps 26, 30 to connect the interposer 10 to the IC chip 40 and the package substrate 42, respectively, by soldering. The interposer 10 is located in the vicinity of the semiconductor chip 40 and functions as a decoupling capacitor having a large capacity. Further, the interposer 10 shown in FIG. 4 also provides the wiring layers 23-1, 23-2 between the IC chip 40 and the package substrate 42.
  • Features, Advantages, and the Like of the Embodiments
  • [0054]
    The interposers 10 according to the embodiments possess the following features and advantages.
  • [0055]
    (1) Because of no wiring pattern that occupies the surface of the silicon substrate 12, the electrodes for capacitor having a large area can be formed.
  • [0056]
    (2) Since the silicon substrate 12 has very flat and smooth surface, the dielectric layer 16 can be formed very thin, whereby the space between the upper electrodes 14 and the lower electrodes 18 can be formed very narrow.
  • [0057]
    (3) A ferroelectric material, for example, barium titanate (BaTiO3), can be used for the dielectric layer 16 of the interposer 10.
  • [0058]
    (4) The interposer 10 can provide capacitors (condenser) having a very large capacity by employing at least one of the above factors.
  • [0059]
    The electronic devices according to the embodiments has the following features and advantages.
  • [0060]
    (1) Noise can be absorbed by providing a decoupling capacitor having large capacity that is connected between the power supply and the ground at a position very near the semiconductor chip 40 in the devices composing the combination of the semiconductor chip 40, the interposer 10, and the package substrate 42.
  • [0061]
    (2) The wiring layers 23-1, 23-2 can be also provided by using the interposer 10 explained in relation to FIG. 4 while providing the decoupling capacitor having the large capacity at the position very near the semiconductor chip 40.
  • [Others]
  • [0062]
    The embodiments of the interposers and the electronic devices making use of the interposers according to the present invention have been explained above. It should be noted that they are only examples, and the present invention is not limited thereto.
  • [0063]
    The technical scope of the present invention should be determined according to the description of the accompanying claims.

Claims (12)

  1. 1. An interposer comprising a capacitor formed on a generally entire surface of a substrate.
  2. 2. The interposer according to claim 1, comprising:
    the substrate including a plurality of through-hole conductors;
    some of the through hole conductors that have land portions formed with an upper electrode of the capacitors;
    some of the remaining of the through-hole conductors that have land portions formed with a lower electrode of the capacitor; and
    a dielectric layer interposed between the upper electrodes and the lower electrodes.
  3. 3. The interposer according to claim 2, wherein
    some of the through-hole conductors are formed as through-hole conductors for signal on a central portion of the surface of the substrate, and
    through-hole conductors for power supply for forming one of the upper and lower electrodes and through-hole conductors for ground for forming the other of the upper and lower electrodes are formed surrounding the through-hole conductors for signal.
  4. 4. The interposer according to claim 2, wherein
    some of the through-hole conductors are formed as through-hole conductors for signal on a peripheral region of the surface of the substrate, and
    through-hole conductors for power supply for forming one of the upper and lower electrodes and through-hole conductors for ground for forming the other of the upper and lower electrodes are formed inside of the peripheral region of the surface of the substrate.
  5. 5. The interposer according to claim 1 or 2, further comprising a wiring layer that is formed on at least one insulating layer disposed above the capacitors.
  6. 6. The interposer according to claim 1 or 2, wherein the substrate is a silicon substrate.
  7. 7. The interposer according to claim 1 or 2, wherein the through-hole conductors are made of copper.
  8. 8. The interposer according to claim 1 or 2, wherein the upper and lower electrodes are made of nickel or platinum.
  9. 9. The interposer according to claim 1 or 2, wherein the dielectric layer is made of a ferroelectric substance.
  10. 10. The interposer according to claim 1 or 2, wherein the dielectric layer is made of barium titanate.
  11. 11. The interposer according to claim 1 or 2, wherein at least one surface of the interposer is covered with a solder resist layer or an insulating resin layer.
  12. 12. An electronic device comprising
    an IC chip;
    a package substrate; and
    an interposer, according to claim 1 or 2, interposed between the IC chip and the package substrate and electrically connected to the both,
    wherein the interposer provides capacitors.
US11491288 2006-07-24 2006-07-24 Interposer and electronic device using the same Abandoned US20080017407A1 (en)

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US11491288 US20080017407A1 (en) 2006-07-24 2006-07-24 Interposer and electronic device using the same
KR20087009227A KR100977436B1 (en) 2006-07-24 2007-07-10 Interposer and electronic device using the same
CN 200780002425 CN101371355B (en) 2006-07-24 2007-07-10 Interposer and electronic device using the same and their production method
PCT/JP2007/063757 WO2008013054A1 (en) 2006-07-24 2007-07-10 Interposer and electronic device using the same
JP2008509262A JPWO2008013054A1 (en) 2006-07-24 2007-07-10 Interposer and an electronic device using the same
EP20070790575 EP1928022A1 (en) 2006-07-24 2007-07-10 Interposer and electronic device using the same
US11860132 US8149585B2 (en) 2006-07-24 2007-09-24 Interposer and electronic device using the same

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KR100977436B1 (en) 2010-08-24 grant
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US8149585B2 (en) 2012-04-03 grant
WO2008013054A1 (en) 2008-01-31 application

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