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US20070271440A1 - Computer processor architecture selectively using finite-state-machine for control code execution - Google Patents

Computer processor architecture selectively using finite-state-machine for control code execution Download PDF

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US20070271440A1
US20070271440A1 US11803997 US80399707A US2007271440A1 US 20070271440 A1 US20070271440 A1 US 20070271440A1 US 11803997 US11803997 US 11803997 US 80399707 A US80399707 A US 80399707A US 2007271440 A1 US2007271440 A1 US 2007271440A1
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Prior art keywords
fsm
microinstruction
control
finite
state
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US11803997
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Paul Master
W. Scheuermann
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QuickSilver Tech Inc
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QuickSilver Tech Inc
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/30181Instruction operation extension or modification
    • G06F9/30189Instruction operation extension or modification according to execution mode, e.g. mode flag
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/22Microcontrol or microprogramme arrangements
    • G06F9/223Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/30145Instruction analysis, e.g. decoding, instruction word fields
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/32Address formation of the next instruction, e.g. incrementing the instruction counter, jump
    • G06F9/322Address formation of the next instruction, e.g. incrementing the instruction counter, jump for non-sequential address
    • G06F9/325Address formation of the next instruction, e.g. incrementing the instruction counter, jump for non-sequential address for loops, e.g. loop detection, loop counter

Abstract

A microprocessor architecture including a finite state machine in combination with a microcode instruction cache for executing microinstructions. Microinstructions which would normally result in small sequences of high-repetition looped operations are implemented in a finite state machine (FSM). The use of the FSM is more energy-efficient than looping instructions in a cache or register set. In addition, the flexibility of a cache, or other memory oriented approach, in executing microcode instructions is still available. A microinstruction is identified as an FSM operation (as opposed to a cache operation) by an ID tag. Other fields of the microinstruction can be used to identify the type of FSM circuitry to use, direct configuration of a FSM to implement the microinstruction, indicate that certain fields are to be implemented in one or more FSMs and/or in memory-oriented operations such as in a cache or register.

Description

    BACKGROUND OF THE INVENTION
  • [0001]
    This application relates in general to digital processing and more specifically to a digital processor microarchitecture for reducing power consumption in processors.
  • [0002]
    Reducing power consumption in microprocessor design is becoming more important as increasing numbers of portable digital processing applications, such as cellular telephones, personal digital assistants (PDAs), pocketbook computers, etc., become more popular. Also, as digital processors become faster, and as process technologies allow for increasingly dense designs, the effective capacitance, Ceff, encountered in new processor designs increases. The increased Ceff can require prohibitive amounts of power to achieve desired speeds. Recent projections indicate that traditional processor architectures that include significant random-access memory (RAM) and read-only memory (ROM) in the processor's microstore, cache, buffers, registers and other areas; requires much more power due to fast signal switching requirements encumbered by high Ceff.
  • [0003]
    Traditionally, the liberal use of memory at the processor level has been desirable. The program store allows the processor to be re-configured with updated instruction set functionality. The design of microprocessor instructions, or the “instruction set,” can be changed to a degree without greatly affecting hardware design. The use of a microinstruction cache allows instructions that need to be repeated many times to be more quickly accessed by placing instructions within the loop to be executed in the fast cache. However, the use of large memories and memory caches also require cell arrays, control lines, decode logic, etc., whose operations are highly affected by Ceff. In general, storage accessing has a significant overhead at speeds desired for central processing unit (CPU) instruction execution.
  • [0004]
    The prior art has tried to minimize the use of memory devices in modern processor architecture designs by making the microinstruction or instruction cache extremely small, and by using large, complex instructions, e.g., very long instruction word (VLIW) or complex instruction set computer (CISC) approaches. These approaches use large instruction words, that can perform one or more functions that would otherwise require multiple, simpler, instructions. At an extreme, a single complex microinstruction might be the entirety of a loop so that frequently-executed loops and functions can be performed by keeping the single microinstruction in a small, single-word cache and executing the same microinstruction many times. However, the mere operation of looping a register, memory or cache, requires high switching speeds of signals in many transistors in the register memory, control memory and associated support circuitry. Such an approach is prohibitive where Ceff is large. The trend of denser numbers of transistors to control more and more circuitry and chip designs is causing a rapid increase in Ceff. Other aspects of microprocessor design can further thwart register and memory oriented approaches.
  • [0005]
    Thus, it is desirable to provide a system that alleviates one or more shortcomings in the prior art.
  • SUMMARY OF THE INVENTION
  • [0006]
    One embodiment of the invention uses a finite state machine in combination with a microcode instruction (“microinstruction”) cache. Selected instructions which would normally result in small sequences of high-repetition looped operations are implemented in a finite state machine (FSM). The use of the FSM is more energy-efficient than looping instructions in a cache or register set. In addition, the flexibility of a cache, or other memory oriented approach, in executing microcode instructions is still available.
  • [0007]
    In a preferred embodiment a microinstruction, or many microinstructions, are identified as an FSM operation (as opposed to a cache operation) by an ID tag. Other fields of the microinstruction can be used to identify the type of FSM circuitry to use, direct configuration of a FSM to implement the microinstruction, indicate that certain fields are to be implemented in one or more FSMs and/or in memory-oriented operations such as in a cache or register.
  • [0008]
    In one embodiment, the invention provides a digital processor responsive to a microinstruction to perform an operation, the digital processor comprising, a memory for storing data associated with the operation to be performed; a finite state machine (FSM) for performing a function in association with the operation; and control circuitry for providing data to the register and for starting execution of the FSM in response to the microinstruction.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0009]
    FIG. 1 shows basic components of the present invention;
  • [0010]
    FIG. 2A is a first diagram of an FSM control designation in a microinstruction;
  • [0011]
    FIG. 2B is a second diagram of an FSM control designation in a microinstruction;
  • [0012]
    FIG. 2C is a third diagram of an FSM control designation in a microinstruction; and
  • [0013]
    FIG. 3 is a flowchart of basic steps in a routine to determine whether FSM circuitry is invoked.
  • DESCRIPTION OF A PREFERRED EMBODIMENT
  • [0014]
    FIG. 1 illustrates a preferred embodiment of the invention.
  • [0015]
    In FIG. 1, microprocessor architecture 100 includes microstore 102 for storing microinstructions for execution by the components of the microprocessor architecture. As is known in the art, such instructions direct memory and register accessing, logical and arithmetic data operations, sequencing operations, and other operations to direct hardware in a digital processing system to perform functionality according to instructions stored in system memory (not shown).
  • [0016]
    Microstore 102 is indexed by program counter 104 to access a location of a current microinstruction whose data is output as current instruction 106. Note that a separate register or latch can be used to hold the current microinstruction, or the data can simply be output directly from the microstore. Many approaches to accessing and manipulating microinstructions are possible and are within the scope of the present invention.
  • [0017]
    The current microinstruction is used by control circuitry 108 to direct finite state machine (FSM) 112, FSM configuration 110 and memory oriented circuitry such as register 114 and loop control 116 to perform functions in accordance with the current microinstruction. Control circuitry 108 can also be used to direct, or control, other components in the system such as program counter 104, arithmetic/logic hardware and sequencing hardware 118, system memory accesses, etc.
  • [0018]
    Register 114 and loop control 116 can be microinstruction looping components as are known in the art. Other standard architecture components can be used. In a preferred embodiment, control circuitry 108 determines whether the current instruction, or a portion of the current instruction, is suitable, or has been designated, for using FSM processing. If so, control circuitry 108 directs the use of FSM 112 to execute according to data in the current instruction. In applications where the FSM is configurable, FSM configuration circuit 110 is used to pre-configure FSM 112, as desired. Note that any number of configurable, or fixed, FSMs can be used. For ease of illustration, only one is shown in FIG. 1.
  • [0019]
    Control circuitry 108 can be implemented in various ways, as desired. For example, in a simple implementation the control circuitry need be no more than hardwired routing of control signals and data in the current instruction, or from the microstore, to the appropriate components (such as FSM 112 or register 114). Other implementations can use multiplexers, gates or other devices to more flexibly control, generate, process, monitor, etc., the information from a microinstruction and use the information to control components.
  • [0020]
    Note that memory oriented circuitry can be other than a simple register and loop control. For example, multiple registers can be used. A memory bank can be employed, fast memory can be used as a cache, etc. In general, an FSM can be used in combination with any type of computer architecture, including additional FSMs.
  • [0021]
    FSM configuration circuitry 110 can be invoked by earlier instructions to prepare an FSM for later use by a different microinstruction. Alternatively, portions of an instruction can be used to direct configuration of the FSM via the configuration circuitry, while other parts of the same instruction serve to control FSM execution. In some applications, control of an FSM need not be more involved than merely invoking the FSM to begin execution.
  • [0022]
    FIGS. 2A-C illustrate different types of FSM control microinstructions.
  • [0023]
    In FIG. 2A, microinstruction 200 includes typical fields 204 for directing the operation of CPU circuitry. Typical fields can be, e.g., a next address field, arithmetic logic unit (ALU) control field, register access field, memory access, access mode, etc. Additionally, an FSM control bit FSMCTL at 202 is reserved. FSMCTL is set to 0 the FSM feature of the present invention is not invoked. In this case, the CPU can behave as a traditional processor. However, when FSMCTL is set to 1 then fields 204, and subsequent fields in subsequent instructions, can invoke FSM processing.
  • [0024]
    FIG. 2B illustrates the microinstruction format where FSM control is enabled.
  • [0025]
    In FIG. 2B, microinstruction 200 now has FSM control bit 202 set to 1. This enables FSMCTL control field 206 which would otherwise be used for other purposes. Depending on the microinstruction set design, additional fields such as 208, etc., can be used for FSM control. In different embodiments, many different arrangements for determining when, and how, a microinstruction (or instructions) will be interpreted to control an FSM. For example, other approaches can use fixed, predetermined fields for FSM control so that an FSM control bit is not needed. The configuration information for the FSM can be stored in these fields.
  • [0026]
    FIG. 2C illustrates an FSM control mode where multiple instructions are used.
  • [0027]
    In FIG. 2C, the FSM control bit is set to 1. FSMCTL field 212 then indicates how many microinstruction words following word 200 are to be used for FSM control. In this example, the remaining fields of microinstruction 200 along with the next two microinstructions, 214 and 216, can be used in their entirety for FSM-related purposes.
  • [0028]
    In other embodiments, the FSM control bit can be derived from a signal generated by hardware within the digital processing system, or obtained or derived from an external source. One refinement is to provide control circuit 108 of FIG. 1 with a “power saving mode” signal. When on, control circuit 108 will attempt to utilize FSM execution unit hardware as much as possible. When off, the emphasis will be on speed of execution which. One approach is to provide parallel instructions for different functions to be executed. One set of microinstructions is FSM oriented while the other is non-FSM. The control circuitry can selectively retrieve the desired (FSM, or non-FSM) instructions from a microstore as dictated by the power saving mode. Both the FSM and normal microstore operations could be executing in parallel.
  • [0029]
    FIG. 3 illustrates a flowchart showing basic steps in a routine to determine whether FSM circuitry, such as FSM 110 of FIG. 1, is invoked.
  • [0030]
    In FIG. 3, the routine of flowchart 300 is entered at step 302. At step 304, a next microinstruction to be executed is obtained. At step 306, a determination is made as to whether FSM mode execution is desired, or directed. As discussed above, this determination can be made from information in the obtained microinstruction, itself, or from a different microinstruction or from a control signal. If not desired, then step 308 is performed to execute the microinstruction's functions or operations in a non-FSM manner.
  • [0031]
    If, however, it is desired at step 306 to use FSM mode execution then step 310 is next executed to check whether FSM mode is available. Even though desired, FSM mode may not be available for a variety of reasons including lack of availability of the FSM execution unit (112 of FIG. 1), or lack of other resources. In an embodiment where dual sets of microinstructions are used to allow FSM or non-FSM modes for same operations, not all operations may be provided with dual FSM microinstructions so that FSM mode execution will not be possible. If FSM mode is not possible then step 308 is executed to execute the microinstruction's operations in a non-FSM mode.
  • [0032]
    If FSM mode is possible then step 312 is performed to check whether configuration data is needed. If so, step 314 obtains the configuration data. Configuration data can be provided by microinstructions, data elsewhere in the system, or hardwired circuitry for frequently used tasks. After configuration, or if it determined that configuration is not necessary, execution proceeds to step 316 where microinstruction operations are executed in an FSM mode and the routine exits at step 318.
  • [0033]
    Note that the functionality described by the steps of FIG. 3 may be achieved in many different ways. Steps can be added to or removed from those shown in FIG. 3. The steps can be modified and the sequencing can vary without departing from the scope of the invention. The functionality can be achieved by hardware, software or a combination of both.
  • [0034]
    Although the invention has been described with respect to specific embodiments above, the embodiments are merely illustrative, and not restrictive, of the invention. For example, even though aspects of the invention have been described advantageously reducing power consumption, the invention can be applied to designs where use of an FSM along with other execution units is desirable for other reasons. In some applications, power consumption may actually increase. For example, reducing the area of a design can be achieved, faster implementation of certain microinstructions can be realized (resulting in faster performance), advantages in microinstruction length, complexity, organization, execution, etc., can be obtained.
  • [0035]
    Although a distinction has been made between FSM and non-FSM execution, these terms are intended to mean either use of specialized FSM execution unit circuitry or non-use of such circuitry for a specific instruction, set of instructions, or portion of instruction. The term “non-FSM” or similar does not mean that no FSM is used. Nor does “FSM” mean that only FSM circuitry is used. For example, a non-FSM execution may still use FSM circuitry, but not the specialized FSM circuitry that is illustrated as FSM 112 of FIG. 1. In the art, FSM is a design approach that can be used to implement many different functions. For example, it is popular to use an FSM to generate control signals so that an FSM may be used in control circuitry 108 and ALU hardware/sequencer 118. The discussion herein, relating to use or non-use of FSM execution hardware includes specialized FSM circuitry that is selectable according to a microinstruction's fields, a control signal, or other component or approach discussed or implied herein. The type of specialized circuitry can vary widely. The same specialized circuitry need not be used for different instructions, or even for a same instruction executed at a later time.
  • [0036]
    Thus, the scope of the invention is to be determined solely by the appended claims.

Claims (26)

  1. 1-8. (canceled)
  2. 9. A computer processor for executing a microinstruction, the computer processor comprising:
    a configurable finite state machine (FSM);
    processing circuitry; and
    control circuitry for controlling the configurable finite state machine (FSM) to implement at least a portion of the microinstruction in parallel with the processing circuitry.
  3. 10. The computer processor of claim 9, wherein the configurable finite state machine (FSM) and processing circuitry are operated concurrently.
  4. 11. (canceled)
  5. 12. A method of performing an operation according to a microinstruction having a finite state machine control field, comprising:
    storing data associated with the operation to be performed;
    configuring a configurable finite state machine via a finite state machine configuration circuit to perform a function in association with the operation;
    detecting a predefined value in the finite state machine control field in the microinstruction; and
    providing data to enable execution of the function by the finite state machine in response to the predefined value.
  6. 13. The method of claim 12, further comprising configuring a second configurable finite state machine via the finite state configuration circuit to perform a second function in association with the operation.
  7. 14. The method of claim 12, further comprising configuring the configurable finite state machine in advance to perform the function associated with the microinstruction.
  8. 15. The method of claim 12, wherein a second microinstruction having the same function as the first microinstruction is executed by the finite state machine.
  9. 16. A method of processing a microinstruction using a plurality of finite state machines in a processing system, the microinstruction including a finite state machine data field and directing at least one operation, the method comprising:
    reading the microinstruction;
    determining the at least one operation directed by the microinstruction to be performed;
    selecting one of the plurality of finite state machines to perform the at least one operation of the microinstruction; and
    configuring the selected finite state machine to perform the at least one operation of the microinstruction.
  10. 17. The method of claim 16, wherein the finite state machine is selected by hardware within the processing system.
  11. 18. The method of claim 16, wherein the finite state machine is selected by a source external to the processing system.
  12. 19. The method of claim 16, wherein the configuration of the selected finite state machine occurs prior to reading the microinstruction.
  13. 20. The method of claim 16, wherein the microinstruction includes configuration data used to select the finite state machine and control data to control the performance of the operation via the finite state machine.
  14. 21. The method of claim 16, wherein the finite state machine is selected from the plurality of finite state machines based on the use of the plurality of finite state machines in the processing system.
  15. 22. The method of claim 16, wherein the finite state machine is selected based on power requirements.
  16. 23. The method of claim 16, wherein configuring the finite state machine is performed via a hardwired configuration circuit.
  17. 24. The method of claim 16, wherein configuring the finite state machine is performed via the microinstruction.
  18. 25. A method for executing software with a computer processor having a configurable finite state machine, control circuitry for configuring the configurable finite state machine to perform different operations, and processing circuitry, the method comprising:
    reading the software;
    deriving at least one microinstruction from the software, the microinstruction including directing an operation;
    determining whether the operation should be executed using the configurable finite state machine;
    providing an instruction that the operation is to be executed by the configurable finite state machine based on the determination; and
    executing the operation with the configurable finite state machine.
  19. 26. A processor system for processing a microinstruction including a finite state machine data field and directing at least one operation, the processor comprising:
    a plurality of finite state machines;
    an input device to read the microinstruction;
    a controller to determine the at least one operation directed by the microinstruction to be performed and to select one of the plurality of finite state machines to perform the at least one operation of the microinstruction; and
    a configuration circuit to configure the selected finite state machine to perform the at least one operation of the microinstruction.
  20. 27. The processor system of claim 26, wherein controller is hardware within the processing system.
  21. 28. The processor system of claim 26, wherein the controller configures the selected finite state machine prior to the input device reading the microinstruction.
  22. 29. The processor system of claim 26, wherein the microinstruction includes configuration data used to select the finite state machine and control data to control the performance of the operation via the finite state machine.
  23. 30. The processor system of claim 26, wherein the controller selects the finite state machine from the plurality of finite state machines based on the use of the plurality of finite state machines in the processor system.
  24. 31. The processor system of claim 26, wherein the controller selects the finite state machine based on power requirements of the processor system.
  25. 32. The processor system of claim 26, wherein the configuration circuit is hardwired.
  26. 33. The processor system of claim 26, wherein the configuration circuit performs the configuration via reading the microinstruction.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004043788A1 (en) * 2003-09-11 2005-04-14 Ingo Franz Personal computing device executes program based on individual programming code to provide predefined code and to define direct relation between input and output of data by user and attribute of classes in input model
US20080109645A1 (en) * 2006-11-08 2008-05-08 Ite Tech. Inc. Data processing apparatus for loop structure and method thereof
EP2009544B1 (en) * 2007-06-26 2010-04-07 Telefonaktiebolaget LM Ericsson (publ) Data-processing unit for nested-loop instructions

Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US555417A (en) * 1896-02-25 baron
US3938639A (en) * 1973-11-28 1976-02-17 The Cornelius Company Portable dispenser for mixed beverages
US4076145A (en) * 1976-08-09 1978-02-28 The Cornelius Company Method and apparatus for dispensing a beverage
US4143793A (en) * 1977-06-13 1979-03-13 The Cornelius Company Apparatus and method for dispensing a carbonated beverage
US4181242A (en) * 1978-05-30 1980-01-01 The Cornelius Company Method and apparatus for dispensing a beverage
US4252253A (en) * 1978-02-21 1981-02-24 Mcneil Corporation Drink dispenser having central control of plural dispensing stations
US4377246A (en) * 1977-06-13 1983-03-22 The Cornelius Company Apparatus for dispensing a carbonated beverage
US4578799A (en) * 1983-10-05 1986-03-25 Codenoll Technology Corporation Method and apparatus for recovering data and clock information from a self-clocking data stream
US4577782A (en) * 1983-05-02 1986-03-25 The Cornelius Company Beverage dispensing station
US4719056A (en) * 1984-06-25 1988-01-12 Isoworth Limited Fluid treatment
US4726494A (en) * 1986-02-10 1988-02-23 Isoworth Limited Beverage dipensing apparatus
US4800492A (en) * 1987-05-13 1989-01-24 The Coca-Cola Company Data logger for a post-mix beverage dispensing system
US4811214A (en) * 1986-11-14 1989-03-07 Princeton University Multinode reconfigurable pipeline computer
US4901887A (en) * 1988-08-08 1990-02-20 Burton John W Beverage dispensing system
US4905231A (en) * 1988-05-03 1990-02-27 American Telephone And Telegraph Company, At&T Bell Laboratories Multi-media virtual circuit
US4982876A (en) * 1986-02-10 1991-01-08 Isoworth Limited Carbonation apparatus
US4993604A (en) * 1985-09-13 1991-02-19 The Coca-Cola Company Low-cost post-mix beverage dispenser and syrup supply system therefor
US5090015A (en) * 1989-02-06 1992-02-18 Motorola, Inc. Programmable array logic self-checking system
US5099418A (en) * 1990-06-14 1992-03-24 Hughes Aircraft Company Distributed data driven process
US5190083A (en) * 1990-02-27 1993-03-02 The Coca-Cola Company Multiple fluid space dispenser and monitor
US5190189A (en) * 1990-10-30 1993-03-02 Imi Cornelius Inc. Low height beverage dispensing apparatus
US5193151A (en) * 1989-08-30 1993-03-09 Digital Equipment Corporation Delay-based congestion avoidance in computer networks
US5193718A (en) * 1991-06-25 1993-03-16 Imi Cornelius Inc. Quick electronic disconnect for a beverage dispensing valve
US5297400A (en) * 1993-02-17 1994-03-29 Maytag Corporation Liquid dispensing assembly for a refrigerator
US5379343A (en) * 1993-02-26 1995-01-03 Motorola, Inc. Detection of unauthorized use of software applications in communication units
US5381546A (en) * 1987-04-13 1995-01-10 Gte Laboratories Incorporated Control process for allocating services in communications systems
US5381550A (en) * 1991-12-13 1995-01-10 Thinking Machines Corporation System and method for compiling a source code supporting data parallel variables
US5388062A (en) * 1993-05-06 1995-02-07 Thomson Consumer Electronics, Inc. Reconfigurable programmable digital filter architecture useful in communication receiver
US5388212A (en) * 1993-02-26 1995-02-07 Motorola Inc. Detecting unauthorized modification of communication unit based on comparison between stored hardware identification code and hardware identification code generated from operational platform identification code
US5491823A (en) * 1994-01-25 1996-02-13 Silicon Graphics, Inc. Loop scheduler
US5594657A (en) * 1993-09-27 1997-01-14 Lucent Technologies Inc. System for synthesizing field programmable gate array implementations from high level circuit descriptions
US5600810A (en) * 1994-12-09 1997-02-04 Mitsubishi Electric Information Technology Center America, Inc. Scaleable very long instruction word processor with parallelism matching
US5600844A (en) * 1991-09-20 1997-02-04 Shaw; Venson M. Single chip integrated circuit system architecture for document installation set computing
US5603043A (en) * 1992-11-05 1997-02-11 Giga Operations Corporation System for compiling algorithmic language source code for implementation in programmable hardware
US5608643A (en) * 1994-09-01 1997-03-04 General Programming Holdings, Inc. System for managing multiple dispensing units and method of operation
US5607083A (en) * 1992-05-22 1997-03-04 Imi Cornelius Inc. Beverage dispensing valve
US5611867A (en) * 1995-04-12 1997-03-18 Maytag Corporation Method of selecting a wash cycle for an appliance
US5706191A (en) * 1995-01-19 1998-01-06 Gas Research Institute Appliance interface apparatus and automated residence management system
US5706976A (en) * 1995-12-21 1998-01-13 Purkey; Jay Floyd Vending machine inventory control device
US5712996A (en) * 1993-03-15 1998-01-27 Siemens Aktiengesellschaft Process for dividing instructions of a computer program into instruction groups for parallel processing
US5720002A (en) * 1993-06-14 1998-02-17 Motorola Inc. Neural network and method of using same
US5721854A (en) * 1993-11-02 1998-02-24 International Business Machines Corporation Method and apparatus for dynamic conversion of computer instructions
US5721693A (en) * 1995-01-07 1998-02-24 Lg Electronics Inc. Electric home appliance real use state information collection and analysis apparatus
US5729754A (en) * 1994-03-28 1998-03-17 Estes; Mark D. Associative network method and apparatus
US5734808A (en) * 1993-09-28 1998-03-31 Namco Ltd. Pipeline processing device, clipping processing device, three-dimensional simulator device and pipeline processing method
US5732563A (en) * 1993-09-22 1998-03-31 Imi Cornelius Inc. Electronically controlled beverage dispenser
US5860021A (en) * 1997-04-24 1999-01-12 Klingman; Edwin E. Single chip microcontroller having down-loadable memory organization supporting "shadow" personality, optimized for bi-directional data transfers over a communication channel
US5862961A (en) * 1993-10-26 1999-01-26 Imi Cornelius Inc. Connection device for dispensing fluid from a bottle
US5870427A (en) * 1993-04-14 1999-02-09 Qualcomm Incorporated Method for multi-mode handoff using preliminary time alignment of a mobile station operating in analog mode
US5873045A (en) * 1997-10-29 1999-02-16 International Business Machines Corporation Mobile client computer with radio frequency transceiver
US5881106A (en) * 1994-09-05 1999-03-09 Sgs-Thomson Microelectronics S.A. Signal processing circuit to implement a Viterbi algorithm
US5884284A (en) * 1995-03-09 1999-03-16 Continental Cablevision, Inc. Telecommunication user account management system and method
US5887174A (en) * 1996-06-18 1999-03-23 International Business Machines Corporation System, method, and program product for instruction scheduling in the presence of hardware lookahead accomplished by the rescheduling of idle slots
US5886537A (en) * 1997-05-05 1999-03-23 Macias; Nicholas J. Self-reconfigurable parallel processor made from regularly-connected self-dual code/data processing cells
US5889816A (en) * 1996-02-02 1999-03-30 Lucent Technologies, Inc. Wireless adapter architecture for mobile computing
US5890014A (en) * 1996-08-05 1999-03-30 Micronet Technology, Inc. System for transparently identifying and matching an input/output profile to optimal input/output device parameters
US5889989A (en) * 1996-09-16 1999-03-30 The Research Foundation Of State University Of New York Load sharing controller for optimizing monetary cost
US6016395A (en) * 1996-10-18 2000-01-18 Samsung Electronics Co., Ltd. Programming a vector processor and parallel programming of an asymmetric dual multiprocessor comprised of a vector processor and a risc processor
US6021186A (en) * 1995-04-17 2000-02-01 Ricoh Company Ltd. Automatic capture and processing of facsimile transmissions
US6021492A (en) * 1996-10-09 2000-02-01 Hewlett-Packard Company Software metering management of remote computing devices
US6023742A (en) * 1996-07-18 2000-02-08 University Of Washington Reconfigurable computing architecture for providing pipelined data paths
US6028610A (en) * 1995-08-04 2000-02-22 Sun Microsystems, Inc. Geometry instructions for decompression of three-dimensional graphics data
US6039219A (en) * 1998-01-20 2000-03-21 Bach; Lanae E. Liquid dispensing system for a refrigerator
US6041322A (en) * 1997-04-18 2000-03-21 Industrial Technology Research Institute Method and apparatus for processing data in a neural network
US6173389B1 (en) * 1997-12-04 2001-01-09 Billions Of Operations Per Second, Inc. Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor
US6195788B1 (en) * 1997-10-17 2001-02-27 Altera Corporation Mapping heterogeneous logic elements in a programmable logic device
US6199181B1 (en) * 1997-09-09 2001-03-06 Perfecto Technologies Ltd. Method and system for maintaining restricted operating environments for application programs or operating systems
US6202130B1 (en) * 1998-04-17 2001-03-13 Motorola, Inc. Data processing system for processing vector data and method therefor
US20020010848A1 (en) * 2000-05-29 2002-01-24 Shoichi Kamano Data processing system
US20020013937A1 (en) * 1999-02-17 2002-01-31 Ostanevich Alexander Y. Register economy heuristic for a cycle driven multiple issue instruction scheduler
US20020013799A1 (en) * 2000-05-11 2002-01-31 Blaker David M. Accelerated montgomery multiplication using plural multipliers
US20020015439A1 (en) * 1996-04-25 2002-02-07 Sanjai Kohli GPS system for navigating a vehicle
US6347346B1 (en) * 1999-06-30 2002-02-12 Chameleon Systems, Inc. Local memory unit system with global access for use on reconfigurable chips
US6346824B1 (en) * 1996-04-09 2002-02-12 Xilinx, Inc. Dedicated function fabric for use in field programmable gate arrays
US20020023210A1 (en) * 2000-04-12 2002-02-21 Mark Tuomenoksa Method and system for managing and configuring virtual private networks
US20020024993A1 (en) * 1999-12-30 2002-02-28 Ravi Subramanian Method and apparatus to support multi standard, multi service base-stations for wireless voice and data networks
US20020024942A1 (en) * 2000-08-30 2002-02-28 Nec Corporation Cell search method and circuit in W-CDMA system
US20030007606A1 (en) * 2001-02-01 2003-01-09 Estech Systems, Inc. Service observing in a voice over IP telephone system
US20030012270A1 (en) * 2000-10-06 2003-01-16 Changming Zhou Receiver
US6510138B1 (en) * 1999-02-25 2003-01-21 Fairchild Semiconductor Corporation Network switch with head of line input buffer queue clearing
US6510510B1 (en) * 1996-01-25 2003-01-21 Analog Devices, Inc. Digital signal processor having distributed register file
US20030018446A1 (en) * 2001-06-29 2003-01-23 National Instruments Corporation Graphical program node for generating a measurement program
US20030018700A1 (en) * 2001-03-26 2003-01-23 Giroti Sudhir K. Unified XML voice and data media converging switch and application delivery system
US20030023830A1 (en) * 2001-07-25 2003-01-30 Hogenauer Eugene B. Method and system for encoding instructions for a VLIW that reduces instruction memory requirements
US20030026242A1 (en) * 1997-06-18 2003-02-06 Harri Jokinen Method for identifying base stations of a time division cellular network in a mobile station and mobile station
US20030030004A1 (en) * 2001-01-31 2003-02-13 General Electric Company Shared memory control between detector framing node and processor
US6526570B1 (en) * 1999-04-23 2003-02-25 Sun Microsystems, Inc. File portability techniques
US6675284B1 (en) * 1998-08-21 2004-01-06 Stmicroelectronics Limited Integrated circuit with multiple processing cores
US20040006584A1 (en) * 2000-08-08 2004-01-08 Ivo Vandeweerd Array of parallel programmable processing engines and deterministic method of operating the same
US20040010645A1 (en) * 2002-06-25 2004-01-15 Quicksilver Technology, Inc. Uniform interface for a functional node in an adaptive computing engine
US20040015970A1 (en) * 2002-03-06 2004-01-22 Scheuermann W. James Method and system for data flow control of execution nodes of an adaptive computing engine (ACE)
US20040015973A1 (en) * 2002-05-31 2004-01-22 International Business Machines Corporation Resource reservation for large-scale job scheduling
US20040025159A1 (en) * 2002-06-25 2004-02-05 Quicksilver Technology, Inc. Hardware task manager
US6691148B1 (en) * 1998-03-13 2004-02-10 Verizon Corporate Services Group Inc. Framework for providing quality of service requirements in a distributed object-oriented computer system
US6694380B1 (en) * 1999-12-27 2004-02-17 Intel Corporation Mapping requests from a processing unit that uses memory-mapped input-output space
US6859434B2 (en) * 2002-10-01 2005-02-22 Comsys Communication & Signal Processing Ltd. Data transfer scheme in a communications system incorporating multiple processing elements
US20050044344A1 (en) * 2003-08-21 2005-02-24 Quicksilver Technology, Inc. System, method and software for static and dynamic programming and configuration of an adaptive computing architecture
US6986142B1 (en) * 1989-05-04 2006-01-10 Texas Instruments Incorporated Microphone/speaker system with context switching in processor
US20060031660A1 (en) * 2001-11-30 2006-02-09 Master Paul L Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5301100A (en) * 1991-04-29 1994-04-05 Wagner Ferdinand H Method of and apparatus for constructing a control system and control system created thereby
US5751295A (en) * 1995-04-27 1998-05-12 Control Systems, Inc. Graphics accelerator chip and method
US5822308A (en) * 1995-07-17 1998-10-13 National Semiconductor Corporation Multi-tasking sequencer for a TDMA burst mode controller
US5822313A (en) * 1996-05-24 1998-10-13 National Semiconductor Corporation Seamless handover in a cordless TDMA system
FR2770659A1 (en) * 1997-10-31 1999-05-07 Sgs Thomson Microelectronics perfects processor
US6442672B1 (en) * 1998-09-30 2002-08-27 Conexant Systems, Inc. Method for dynamic allocation and efficient sharing of functional unit datapaths
US6570877B1 (en) * 1999-04-07 2003-05-27 Cisco Technology, Inc. Search engine for forwarding table content addressable memory
EP1061437A1 (en) * 1999-06-16 2000-12-20 SGS-THOMSON MICROELECTRONICS S.r.l. Improved control unit for electronic microcontrollers or microprocessors
US6349346B1 (en) * 1999-09-23 2002-02-19 Chameleon Systems, Inc. Control fabric unit including associated configuration memory and PSOP state machine adapted to provide configuration address to reconfigurable functional unit
EP1117031B1 (en) * 2000-01-14 2007-07-11 Texas Instruments France Microprocessor with reduced power-consumption.
JP4558879B2 (en) * 2000-02-15 2010-10-06 富士通株式会社 Data processing apparatus and processing system using a table
US6675265B2 (en) * 2000-06-10 2004-01-06 Hewlett-Packard Development Company, L.P. Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants
US6842895B2 (en) * 2000-12-21 2005-01-11 Freescale Semiconductor, Inc. Single instruction for multiple loops

Patent Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US555417A (en) * 1896-02-25 baron
US3938639A (en) * 1973-11-28 1976-02-17 The Cornelius Company Portable dispenser for mixed beverages
US4076145A (en) * 1976-08-09 1978-02-28 The Cornelius Company Method and apparatus for dispensing a beverage
US4143793A (en) * 1977-06-13 1979-03-13 The Cornelius Company Apparatus and method for dispensing a carbonated beverage
US4377246A (en) * 1977-06-13 1983-03-22 The Cornelius Company Apparatus for dispensing a carbonated beverage
US4252253A (en) * 1978-02-21 1981-02-24 Mcneil Corporation Drink dispenser having central control of plural dispensing stations
US4181242A (en) * 1978-05-30 1980-01-01 The Cornelius Company Method and apparatus for dispensing a beverage
US4577782A (en) * 1983-05-02 1986-03-25 The Cornelius Company Beverage dispensing station
US4578799A (en) * 1983-10-05 1986-03-25 Codenoll Technology Corporation Method and apparatus for recovering data and clock information from a self-clocking data stream
US4719056A (en) * 1984-06-25 1988-01-12 Isoworth Limited Fluid treatment
US4993604A (en) * 1985-09-13 1991-02-19 The Coca-Cola Company Low-cost post-mix beverage dispenser and syrup supply system therefor
US4982876A (en) * 1986-02-10 1991-01-08 Isoworth Limited Carbonation apparatus
US4726494A (en) * 1986-02-10 1988-02-23 Isoworth Limited Beverage dipensing apparatus
US4811214A (en) * 1986-11-14 1989-03-07 Princeton University Multinode reconfigurable pipeline computer
US5381546A (en) * 1987-04-13 1995-01-10 Gte Laboratories Incorporated Control process for allocating services in communications systems
US4800492A (en) * 1987-05-13 1989-01-24 The Coca-Cola Company Data logger for a post-mix beverage dispensing system
US4905231A (en) * 1988-05-03 1990-02-27 American Telephone And Telegraph Company, At&T Bell Laboratories Multi-media virtual circuit
US4901887A (en) * 1988-08-08 1990-02-20 Burton John W Beverage dispensing system
US5090015A (en) * 1989-02-06 1992-02-18 Motorola, Inc. Programmable array logic self-checking system
US6986142B1 (en) * 1989-05-04 2006-01-10 Texas Instruments Incorporated Microphone/speaker system with context switching in processor
US5193151A (en) * 1989-08-30 1993-03-09 Digital Equipment Corporation Delay-based congestion avoidance in computer networks
US5190083A (en) * 1990-02-27 1993-03-02 The Coca-Cola Company Multiple fluid space dispenser and monitor
US5099418A (en) * 1990-06-14 1992-03-24 Hughes Aircraft Company Distributed data driven process
US5190189A (en) * 1990-10-30 1993-03-02 Imi Cornelius Inc. Low height beverage dispensing apparatus
US5193718A (en) * 1991-06-25 1993-03-16 Imi Cornelius Inc. Quick electronic disconnect for a beverage dispensing valve
US5600844A (en) * 1991-09-20 1997-02-04 Shaw; Venson M. Single chip integrated circuit system architecture for document installation set computing
US5381550A (en) * 1991-12-13 1995-01-10 Thinking Machines Corporation System and method for compiling a source code supporting data parallel variables
US5607083A (en) * 1992-05-22 1997-03-04 Imi Cornelius Inc. Beverage dispensing valve
US5603043A (en) * 1992-11-05 1997-02-11 Giga Operations Corporation System for compiling algorithmic language source code for implementation in programmable hardware
US5297400A (en) * 1993-02-17 1994-03-29 Maytag Corporation Liquid dispensing assembly for a refrigerator
US5388212A (en) * 1993-02-26 1995-02-07 Motorola Inc. Detecting unauthorized modification of communication unit based on comparison between stored hardware identification code and hardware identification code generated from operational platform identification code
US5379343A (en) * 1993-02-26 1995-01-03 Motorola, Inc. Detection of unauthorized use of software applications in communication units
US5712996A (en) * 1993-03-15 1998-01-27 Siemens Aktiengesellschaft Process for dividing instructions of a computer program into instruction groups for parallel processing
US5870427A (en) * 1993-04-14 1999-02-09 Qualcomm Incorporated Method for multi-mode handoff using preliminary time alignment of a mobile station operating in analog mode
US5388062A (en) * 1993-05-06 1995-02-07 Thomson Consumer Electronics, Inc. Reconfigurable programmable digital filter architecture useful in communication receiver
US5720002A (en) * 1993-06-14 1998-02-17 Motorola Inc. Neural network and method of using same
US5732563A (en) * 1993-09-22 1998-03-31 Imi Cornelius Inc. Electronically controlled beverage dispenser
US5594657A (en) * 1993-09-27 1997-01-14 Lucent Technologies Inc. System for synthesizing field programmable gate array implementations from high level circuit descriptions
US5734808A (en) * 1993-09-28 1998-03-31 Namco Ltd. Pipeline processing device, clipping processing device, three-dimensional simulator device and pipeline processing method
US5862961A (en) * 1993-10-26 1999-01-26 Imi Cornelius Inc. Connection device for dispensing fluid from a bottle
US5721854A (en) * 1993-11-02 1998-02-24 International Business Machines Corporation Method and apparatus for dynamic conversion of computer instructions
US5491823A (en) * 1994-01-25 1996-02-13 Silicon Graphics, Inc. Loop scheduler
US5729754A (en) * 1994-03-28 1998-03-17 Estes; Mark D. Associative network method and apparatus
US5608643A (en) * 1994-09-01 1997-03-04 General Programming Holdings, Inc. System for managing multiple dispensing units and method of operation
US5881106A (en) * 1994-09-05 1999-03-09 Sgs-Thomson Microelectronics S.A. Signal processing circuit to implement a Viterbi algorithm
US5600810A (en) * 1994-12-09 1997-02-04 Mitsubishi Electric Information Technology Center America, Inc. Scaleable very long instruction word processor with parallelism matching
US5721693A (en) * 1995-01-07 1998-02-24 Lg Electronics Inc. Electric home appliance real use state information collection and analysis apparatus
US5706191A (en) * 1995-01-19 1998-01-06 Gas Research Institute Appliance interface apparatus and automated residence management system
US5884284A (en) * 1995-03-09 1999-03-16 Continental Cablevision, Inc. Telecommunication user account management system and method
US5611867A (en) * 1995-04-12 1997-03-18 Maytag Corporation Method of selecting a wash cycle for an appliance
US6021186A (en) * 1995-04-17 2000-02-01 Ricoh Company Ltd. Automatic capture and processing of facsimile transmissions
US6028610A (en) * 1995-08-04 2000-02-22 Sun Microsystems, Inc. Geometry instructions for decompression of three-dimensional graphics data
US5706976A (en) * 1995-12-21 1998-01-13 Purkey; Jay Floyd Vending machine inventory control device
US6510510B1 (en) * 1996-01-25 2003-01-21 Analog Devices, Inc. Digital signal processor having distributed register file
US5889816A (en) * 1996-02-02 1999-03-30 Lucent Technologies, Inc. Wireless adapter architecture for mobile computing
US6346824B1 (en) * 1996-04-09 2002-02-12 Xilinx, Inc. Dedicated function fabric for use in field programmable gate arrays
US20020015439A1 (en) * 1996-04-25 2002-02-07 Sanjai Kohli GPS system for navigating a vehicle
US5887174A (en) * 1996-06-18 1999-03-23 International Business Machines Corporation System, method, and program product for instruction scheduling in the presence of hardware lookahead accomplished by the rescheduling of idle slots
US6023742A (en) * 1996-07-18 2000-02-08 University Of Washington Reconfigurable computing architecture for providing pipelined data paths
US5890014A (en) * 1996-08-05 1999-03-30 Micronet Technology, Inc. System for transparently identifying and matching an input/output profile to optimal input/output device parameters
US5889989A (en) * 1996-09-16 1999-03-30 The Research Foundation Of State University Of New York Load sharing controller for optimizing monetary cost
US6021492A (en) * 1996-10-09 2000-02-01 Hewlett-Packard Company Software metering management of remote computing devices
US6016395A (en) * 1996-10-18 2000-01-18 Samsung Electronics Co., Ltd. Programming a vector processor and parallel programming of an asymmetric dual multiprocessor comprised of a vector processor and a risc processor
US6041322A (en) * 1997-04-18 2000-03-21 Industrial Technology Research Institute Method and apparatus for processing data in a neural network
US5860021A (en) * 1997-04-24 1999-01-12 Klingman; Edwin E. Single chip microcontroller having down-loadable memory organization supporting "shadow" personality, optimized for bi-directional data transfers over a communication channel
US5886537A (en) * 1997-05-05 1999-03-23 Macias; Nicholas J. Self-reconfigurable parallel processor made from regularly-connected self-dual code/data processing cells
US20030026242A1 (en) * 1997-06-18 2003-02-06 Harri Jokinen Method for identifying base stations of a time division cellular network in a mobile station and mobile station
US6199181B1 (en) * 1997-09-09 2001-03-06 Perfecto Technologies Ltd. Method and system for maintaining restricted operating environments for application programs or operating systems
US6195788B1 (en) * 1997-10-17 2001-02-27 Altera Corporation Mapping heterogeneous logic elements in a programmable logic device
US5873045A (en) * 1997-10-29 1999-02-16 International Business Machines Corporation Mobile client computer with radio frequency transceiver
US6173389B1 (en) * 1997-12-04 2001-01-09 Billions Of Operations Per Second, Inc. Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor
US6039219A (en) * 1998-01-20 2000-03-21 Bach; Lanae E. Liquid dispensing system for a refrigerator
US6691148B1 (en) * 1998-03-13 2004-02-10 Verizon Corporate Services Group Inc. Framework for providing quality of service requirements in a distributed object-oriented computer system
US6202130B1 (en) * 1998-04-17 2001-03-13 Motorola, Inc. Data processing system for processing vector data and method therefor
US6675284B1 (en) * 1998-08-21 2004-01-06 Stmicroelectronics Limited Integrated circuit with multiple processing cores
US20020013937A1 (en) * 1999-02-17 2002-01-31 Ostanevich Alexander Y. Register economy heuristic for a cycle driven multiple issue instruction scheduler
US6510138B1 (en) * 1999-02-25 2003-01-21 Fairchild Semiconductor Corporation Network switch with head of line input buffer queue clearing
US6526570B1 (en) * 1999-04-23 2003-02-25 Sun Microsystems, Inc. File portability techniques
US6347346B1 (en) * 1999-06-30 2002-02-12 Chameleon Systems, Inc. Local memory unit system with global access for use on reconfigurable chips
US6694380B1 (en) * 1999-12-27 2004-02-17 Intel Corporation Mapping requests from a processing unit that uses memory-mapped input-output space
US20020024993A1 (en) * 1999-12-30 2002-02-28 Ravi Subramanian Method and apparatus to support multi standard, multi service base-stations for wireless voice and data networks
US20020023210A1 (en) * 2000-04-12 2002-02-21 Mark Tuomenoksa Method and system for managing and configuring virtual private networks
US20020013799A1 (en) * 2000-05-11 2002-01-31 Blaker David M. Accelerated montgomery multiplication using plural multipliers
US20020010848A1 (en) * 2000-05-29 2002-01-24 Shoichi Kamano Data processing system
US20040006584A1 (en) * 2000-08-08 2004-01-08 Ivo Vandeweerd Array of parallel programmable processing engines and deterministic method of operating the same
US20020024942A1 (en) * 2000-08-30 2002-02-28 Nec Corporation Cell search method and circuit in W-CDMA system
US20030012270A1 (en) * 2000-10-06 2003-01-16 Changming Zhou Receiver
US20030030004A1 (en) * 2001-01-31 2003-02-13 General Electric Company Shared memory control between detector framing node and processor
US20030007606A1 (en) * 2001-02-01 2003-01-09 Estech Systems, Inc. Service observing in a voice over IP telephone system
US20030018700A1 (en) * 2001-03-26 2003-01-23 Giroti Sudhir K. Unified XML voice and data media converging switch and application delivery system
US20030018446A1 (en) * 2001-06-29 2003-01-23 National Instruments Corporation Graphical program node for generating a measurement program
US20030023830A1 (en) * 2001-07-25 2003-01-30 Hogenauer Eugene B. Method and system for encoding instructions for a VLIW that reduces instruction memory requirements
US20060031660A1 (en) * 2001-11-30 2006-02-09 Master Paul L Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements
US20040015970A1 (en) * 2002-03-06 2004-01-22 Scheuermann W. James Method and system for data flow control of execution nodes of an adaptive computing engine (ACE)
US20040015973A1 (en) * 2002-05-31 2004-01-22 International Business Machines Corporation Resource reservation for large-scale job scheduling
US20040010645A1 (en) * 2002-06-25 2004-01-15 Quicksilver Technology, Inc. Uniform interface for a functional node in an adaptive computing engine
US20040025159A1 (en) * 2002-06-25 2004-02-05 Quicksilver Technology, Inc. Hardware task manager
US6859434B2 (en) * 2002-10-01 2005-02-22 Comsys Communication & Signal Processing Ltd. Data transfer scheme in a communications system incorporating multiple processing elements
US20050044344A1 (en) * 2003-08-21 2005-02-24 Quicksilver Technology, Inc. System, method and software for static and dynamic programming and configuration of an adaptive computing architecture

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