New! View global litigation for patent families

US20070194236A1 - Semiconductor inspection system - Google Patents

Semiconductor inspection system Download PDF

Info

Publication number
US20070194236A1
US20070194236A1 US11790224 US79022407A US2007194236A1 US 20070194236 A1 US20070194236 A1 US 20070194236A1 US 11790224 US11790224 US 11790224 US 79022407 A US79022407 A US 79022407A US 2007194236 A1 US2007194236 A1 US 2007194236A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
system
data
image
inspection
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11790224
Inventor
Atsushi Takane
Haruo Yoda
Shoji Yoshida
Mitsuji Ikeda
Yasuhiko Ozawa
Original Assignee
Atsushi Takane
Haruo Yoda
Shoji Yoshida
Mitsuji Ikeda
Yasuhiko Ozawa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/26Electron or ion microscopes; Electron or ion diffraction tubes
    • H01J37/28Electron or ion microscopes; Electron or ion diffraction tubes with scanning beams

Abstract

An operator-free and fully automated semiconductor inspection system with high throughput is realized. All conditions required for capturing and inspection are generated from design information such as CAD data. In order to perform actual inspection under the conditions, a semiconductor inspection system is composed of a navigation system for generating all the conditions required for capturing and inspection from the design information and a scanning electron microscope system for actually performing capturing and inspection. Moreover, in the case of performing a matching process between designed data and a SEM image, deformed parts are corrected by use of edge information in accordance with multiple directions and smoothing thereof. Furthermore, a SEM image corresponding to a detected position is re-registered as a template, and the matching process is thereby performed.

Description

    BACKGROUND OF THE INVENTION
  • [0001]
    1. Field of the Invention
  • [0002]
    The present invention relates to a semiconductor inspection system for analyzing patterns on a semiconductor wafer by use of design data. More specifically, the present invention relates to a semiconductor inspection system provided with a system configuration for automatically generating conditions for capturing and inspection of patterns out of the design data, as well as a method of stably performing a matching process between the design data and scanning electron microscope (SEM) images.
  • [0003]
    2. Background Art
  • [0004]
    In recent years, there is a production shift in the semiconductor industry from production of memory chips to production of system large scale integrated circuits (LSIs). From a viewpoint of patterns on a semiconductor wafer, unlike patterns of a memory chip, patterns of a system LSI are not designed as simply repeated patterns. Accordingly, in the case of performing pattern measurement of the system LSI with a length-measuring SEM, which is one of the semiconductor evaluation systems, templates for measuring positions, in other words, templates for matching need to be frequently changed. In actual measurement, frequent capturing operations for registration of the templates may incur a considerable decline in entire throughput. Accordingly, generation of the templates directly from existing design data such as computer aided design (CAD) data has been requested. In the meantime, a wafer size is increased up to 300 mm, whereby the wafer cannot be conveyed by manpower. In addition, inspection in a high-purity clean room is becoming essential. Therefore, complete robotization has been desired in a semiconductor facility. Accordingly, an operator-free and fully-automated semiconductor inspection system is requested, which is not arranged to generate only the templates for measuring positions but is also arranged to generate all conditions required for inspection including capturing conditions, points for length measurement and length-measuring algorithms out of the design data, whereby actual inspection is performed under the foregoing conditions.
  • [0005]
    In a conventional length-measuring SEM, an image of an actual wafer is captured first and the image is used for registration of the points for image recognition, the positions for length measurement and the length-measuring algorithms. In other words, the actual wafer is required in the first place, and it is also necessary to occupy the length-measuring SEM temporarily to perform capturing of SEM images and registration of various conditions. Moreover, since technologies for matching design data with SEM images have not been developed adequately, accurate matching has been difficult to do. For example, in the case of specifying a pattern position on a SEM image of a semiconductor wafer by applying the design data to a template with the conventional technology, the SEM image is filtered with a Sobel filter or the like to detect edge components for generating an edge image, and then matching such as a normalized correlation process between the edge image and the design data is performed.
  • [0006]
    FIG. 1 shows a schematic flowchart of conventional processes and FIG. 7 shows some image examples used in the conventional processes. First in Step 101, registration of a template of a desired pattern is performed by use of the design data. The pattern registered from the design data is shown as an image 701. Next, a SEM image is obtained in Step 102. The obtained SEM image is shown as an image 702. In Step 103, the obtained SEM image is subjected to edge emphasis filtering with a Sobel filter or the like. In Step 104, the edge-emphasized image is converted into binary codes for generating a line image in which the edge is only extracted. An image 703 shows the line image extracted out of the SEM image 702. In Step 105, a matching process such as normalized correlation is performed between the line image and the design image registered in Step 101. Then, position detection is performed in Step 106. When detection is performed a plurality of times, Step 102 to 107 will be iterated.
  • [0007]
    In a conventional semiconductor inspection system, registration of points for image recognition, positions for length measurement and length-measuring algorithms have been performed once after capturing an image of an actual wafer and by use of the image. For this reason, there has been a problem that throughput is not improved because registration is time-consuming and the system is occupied at the time of registration. Moreover, there has been a problem that it is impossible to construct an operator-free and fully automated semiconductor inspection system because the conventional system always requires an operator for judgment and registration by observation of actual SEM images. Furthermore, concerning the technology for matching design information with the SEM images, the conventional technology cannot respond to deformation between the CAD data and the SEM images. The conventional technology also has a problem in the event of extracting edge information out of the SEM image that the edge information cannot be adequately extracted due to a signal/noise ratio (an S/N ratio) of the image. In the event of generating a line image by conversion into binary codes, the conventional technology would be incapable of obtaining an optimum value for a threshold, because determination thereof has been difficult. Accordingly, there has been a problem that a correlation coefficient becomes considerably small in the subsequent matching process by normalized correlation.
  • SUMMARY OF THE INVENTION
  • [0008]
    An object of the present invention is to realize an operator-free and fully-automated semiconductor inspection system which generates all necessary conditions, including, conditions for capturing, points for length measurement and length-measuring algorithms, out of design information such as CAD data for performing actual inspection under those conditions. Another object of the present invention is to realize the semiconductor inspection system capable of executing a stable matching process with a high correlation value in the case of performing the matching process between the design data using as a template and SEM images in that system.
  • [0009]
    In order to achieve the foregoing objects, a first aspect of the present invention is a semiconductor inspection system, which includes: a navigation system for storing design information such as CAD data of a semiconductor chip and for setting capturing and inspecting conditions including a region on a semiconductor wafer subject to inspection based on the design information; and a scanning electron microscope system for performing actual capturing of the semiconductor wafer and for executing inspection in accordance with the capturing and inspecting conditions being set up.
  • [0010]
    A second aspect of the present invention is the semiconductor inspection system according to the first aspect, in which the navigation system includes a function to design semiconductor patterns by itself or a function to retrieve the design information from another navigation system connected via a network, foregoing another navigation system possessing a designing function.
  • [0011]
    A third aspect of the present invention is the semiconductor inspection system according to the first aspect, in which the navigation system specifies and retrieves desired design data out of the stored design information to display the design data on a display screen.
  • [0012]
    A fourth aspect of the present invention is the semiconductor inspection system according to the first aspect, in which the navigation system includes a function to specify and retrieve an arbitrary portion out of the CAD data being the stored design information and to generate bitmap data therefrom.
  • [0013]
    A fifth aspect of the present invention is the semiconductor inspection system according to the first aspect, in which the navigation system has a function to effectuate automatic editing of all the capturing and inspecting conditions to be used in the scanning electron microscope system out of the design information including the CAD data and to transmit the edited capturing and inspecting conditions to the scanning electron microscope system.
  • [0014]
    A sixth aspect of the present invention is the semiconductor inspection system according to the first aspect, in which the navigation system has a function to effectuate transmission and receipt of data with another navigation system connected to a network of a facility installed and further to transmit the capturing and inspecting conditions to a plurality of the scanning electron microscope systems connected to the network.
  • [0015]
    A seventh aspect of the present invention is the semiconductor inspection system according to the first aspect, in which the navigation system includes: a bitmap data generator having a function to generate bitmap data by retrieving desired design data out of the stored design information; and a capturing and inspecting condition editor having a function to edit and transmit the capturing and inspecting conditions to be used in the scanning electron microscope system out of the design data.
  • [0016]
    An eighth aspect of the present invention is the semiconductor inspection system according to the first aspect, in which the navigation system has a function to automatically detect a characteristic pattern portion and to register the pattern portion as a template, in the case of selecting a template for matching out of bitmap data as one of the inspecting conditions to be used in the scanning electron microscope system.
  • [0017]
    A ninth aspect of the present invention is the semiconductor inspection system according to the first aspect, in which the scanning electron microscope system uses the capturing and inspecting conditions received from the navigation system, obtains a scanning electron microscope image automatically and performs inspection.
  • [0018]
    A tenth aspect of the present invention is the semiconductor inspection system according to the first aspect, in which the scanning electron microscope system uses the capturing and inspecting conditions received from another navigation system connected via a network, obtains a scanning electron microscope image automatically and performs inspection.
  • [0019]
    An eleventh aspect of the present invention is the semiconductor inspection system according to the first aspect, in which the scanning electron microscope system has a function for matching between bitmap data generated from the design information and a scanning electron microscope image.
  • [0020]
    A twelfth aspect of the present invention is the semiconductor inspection system according to the eleventh aspect, in which the scanning electron microscope system includes: means for generating edge images by retrieving edge information severally from the scanning electron microscope image obtained by capturing and from a template being bitmap data in the case performing a matching process with the scanning electron microscope image obtained by capturing using the bitmap data from the design data as a template; and means for performing the matching process with respect to the edge images severally generated from the scanning electron microscope image and the template while providing the both images with a smoothing process severally so as to make up deformed parts of the both images.
  • [0021]
    A thirteenth aspect of the present invention is the semiconductor inspection system according to the eleventh aspect, in which the scanning electron microscope system retrieves edge information in accordance with multiple directions and generates edge images depending on the multiple directions in the case of generating edge images by retrieving edge information from a scanning electron microscope image and from a template being bitmap data, and the scanning electron microscope system performs a matching process with respect to each of the images.
  • [0022]
    A fourteenth aspect of the present invention is the semiconductor inspection system according to the eleventh aspect, in which the scanning electron microscope system performs a matching process by composing edge images generated in accordance with multiple directions and by integrating the edge images into one image, in the case of generating edge images by retrieving edge information from a scanning electron microscope image and from a template being bitmap data.
  • [0023]
    A fifteenth aspect of the present invention is the semiconductor inspection system according to the first aspect, in which the scanning electron microscope system includes: means for generating an edge image by retrieving edge information from a scanning electron microscope image obtained by capturing in the case of performing a matching process between the scanning electron microscope image and bitmap data from the design information as a template; means for re-registering a portion of the scanning electron microscope image as a template, foregoing portion corresponding to a position of the edge image detected by the matching process between the edge image and design data; and means for using the re-registered template of the scanning electron microscope image in the subsequent matching process.
  • [0024]
    A sixteenth aspect of the present invention is the semiconductor inspection system according to the fifteenth aspect, in which the scanning electron microscope system carries out re-registration of the template during repeated capturing processes at an interval of an arbitrary period of time or an arbitrary frequency of the processes in the case that the scanning electron microscope system uses the re-registered template of the scanning electron microscope image and performs the matching processes with respect to scanning electron microscope images repeatedly captured.
  • [0025]
    A seventeenth aspect of the present invention is the semiconductor inspection system according to the fifteenth aspect, in which the scanning electron microscope system compares a correlation value between the design data and the scanning electron microscope image every time and re-registers a new template only when the compared correlation value is higher than the correlation value of the template used at that time.
  • [0026]
    An eighteenth aspect of the present invention is the semiconductor inspection system according to the fifteenth aspect, in which the scanning electron microscope system performs an arbitrary frequency of the matching processes initially, compares correlation values between the design data and the scanning electron microscope images obtained in the arbitrary frequency of the matching processes, and re-registers the scanning electron microscope image having the highest correlation value as a new template.
  • [0027]
    A nineteenth aspect of the present invention is the semiconductor inspection system according to the first aspect, in which the capturing and inspecting conditions are selected from a capturing and inspecting condition file registered in advance with any one of the navigation system and the scanning electron microscope system.
  • [0028]
    A twentieth aspect of the present invention is the semiconductor inspection system according to the nineteenth aspect, in which the capturing and inspecting conditions are selected from the capturing and inspecting condition file weighted in accordance with a frequency of use in the past.
  • [0029]
    A twenty-first aspect of the present invention is the semiconductor inspection system according to the nineteenth aspect, in which a capturing and inspecting condition inside the capturing and inspecting condition file is automatically deleted from the capturing and deleting condition file when a frequency of use of the capturing and inspecting condition is lower than a predetermined frequency.
  • [0030]
    A twenty-second aspect of the present invention is the semiconductor inspection system according to the nineteenth aspect, which further includes a function to modify and to edit a part of the capturing and inspecting conditions inside the capturing and inspecting condition file, the capturing and inspecting condition file being registered in advance.
  • [0031]
    A twenty-third aspect of the present invention is the semiconductor inspection system according to the nineteenth aspect, which further includes a function to register a condition with the capturing and inspecting condition file as another condition, when a part of the capturing and inspecting conditions inside the capturing and inspecting condition file being registered in advance is modified.
  • [0032]
    The semiconductor inspection system according to the first aspect is composed of the navigation system for storing the design data of a semiconductor chip and the scanning electron microscope system for executing actual capturing and inspection of a semiconductor wafer by use of the information. Therefore, it is possible to construct a system which generates the capturing and inspecting conditions using the design data of a semiconductor chip and actually executes capturing and inspection.
  • [0033]
    In the semiconductor inspection system according to the second aspect, the navigation system includes the function to design semiconductor patterns by itself or the function to retrieve and store the design information from another navigation system connected via a network which possesses a designing function. Therefore, the capturing and inspecting conditions can be readily set up based on the design information.
  • [0034]
    In the semiconductor inspection system according to the third aspect, the navigation system is provided with a function to specify and retrieve desired design data out of the design information storing various information such as layers and cells required for pattern designing and to display the design data on a display screen. Therefore, an operator can readily set up the capturing and inspecting conditions based on the design data on the display screen.
  • [0035]
    In the semiconductor inspection system according to the fourth aspect, the navigation system is provided with the function to retrieve an arbitrarily specified portion out of the CAD data being the design information in order to generate bitmap data. Therefore, the bitmap data can be used for matching by the scanning electron microscope system.
  • [0036]
    In the semiconductor inspection system according to the fifth aspect, the navigation system is provided with the function to effectuate automatic editing of all the capturing and inspecting conditions to be used in the scanning electron microscope system out of the design information including the CAD data and to transmit the edited capturing and inspecting conditions to the scanning electron microscope system. Therefore, the scanning electron microscope system can execute capturing and inspection by use of the automatically extracted conditions, whereby full-automation of the system becomes feasible.
  • [0037]
    In the semiconductor inspection system according to the sixth aspect, the navigation system is provided with the function to effectuate transmission and receipt of data with another navigation system connected to a network of a facility installed and further to transmit the capturing and inspecting conditions to a plurality of the scanning electron microscope systems connected to the network. Therefore, a plurality of navigation systems and a plurality of the scanning electron microscope systems can collaborate to execute efficient capturing and inspection.
  • [0038]
    In the semiconductor inspection system according to the seventh aspect, the navigation system includes a portion having the function to generate bitmap data by retrieving desired design data out of the stored design information, and a portion having the function to edit and transmit the capturing and inspecting conditions to be used in the scanning electron microscope system out of the design data. Therefore, the capturing and inspecting conditions can be edited by use of the bitmap data. Moreover, the navigation system can be also composed of a plurality of systems by use of the network.
  • [0039]
    In the semiconductor inspection system according to the eighth aspect, the navigation system is provided with the function to automatically detect a characteristic pattern portion and to register the pattern portion as a template, in the case of selecting a template for matching out of bitmap data as one inspecting condition to be used in the scanning electron microscope system. Therefore, the template registration does not require manpower.
  • [0040]
    In the semiconductor inspection system according to the ninth aspect, the scanning electron microscope system is provided with the function to use the capturing and inspecting conditions received from the navigation system, to obtain a scanning electron microscope image automatically and to perform inspection. Therefore, the system does not require control by an operator and capturing and inspection can be thereby automated.
  • [0041]
    In the semiconductor inspection system according to the tenth aspect, the scanning electron microscope system is provided with the function to use the capturing and inspecting conditions received from another navigation system connected via a network, to obtain a scanning electron microscope image automatically and to perform inspection. Therefore, a plurality of scanning electron microscope systems can be automatically operated without controlling by an operator.
  • [0042]
    In the semiconductor inspection system according to the eleventh aspect, the scanning electron microscope system is provided with the function for matching between bitmap data generated from the design information and a scanning electron microscope image. Therefore, the scanning electron microscope system can perform highly accurate and efficient inspection by use of the design information.
  • [0043]
    In the semiconductor inspection system according to the twelfth aspect, the scanning electron microscope system is provided with a function to generate edge images by retrieving edge information severally from the scanning electron microscope image obtained by capturing and from a template being bitmap data in the case of performing a matching process between the scanning electron microscope image and the bitmap data out of the design data while providing a smoothing process severally so as to make up deformed parts thereof. Therefore, matching can be performed with a high detection ratio.
  • [0044]
    In the semiconductor inspection system according to the thirteenth aspect, the scanning electron microscope system is provided with a function to retrieve edge information in accordance with multiple directions and to generate edge images depending on the multiple directions in the case of generating edge images by retrieving edge information from a scanning electron microscope image and from the bitmap data, a function to perform a matching process with respect to each of the images. Therefore, matching can be performed with good positional accuracy.
  • [0045]
    In the semiconductor inspection system according to the fourteenth aspect, the scanning electron microscope system is provided with a function to perform a matching process by composing edge images generated in accordance with multiple directions and by integrating the edge images into one image in the case of generating edge images by retrieving edge information from a scanning electron microscope image and from bitmap data. Therefore, matching can be performed with fine positional accuracy and in a high speed.
  • [0046]
    The semiconductor inspection system according to the fifteenth aspect uses the re-registered template of the SEM image and effectuates a matching process between graded SEM images. Therefore, matching can be performed with a high correlation value and with a stable detection ratio.
  • [0047]
    In the semiconductor inspection system according to the sixteenth aspect, re-registration of the template as described in the fifteenth aspect is carried out during repeated capturing at an interval of either an arbitrary period of time or an arbitrary frequency of the processes. Therefore, the matching process with a high correlation value and with a stable detection ratio can be performed in response to changes of SEM images with passage of time in the course of capturing.
  • [0048]
    In the semiconductor inspection system according to the seventeenth aspect, a correlation value between the design data and a SEM image is compared in the case of registering a new template, and the template is re-registered only when the correlation value is higher than before. Therefore, the template can be optimized along with a higher correlation value.
  • [0049]
    In the semiconductor inspection system according to the eighteenth aspect, the matching processes between the design data and the edge images as described in the fifteenth aspect are performed initially in an arbitrary frequency. Thereafter, correlation values then are compared and the edge image having the highest correlation value of all the edge images is re-registered as the template. Accordingly, it is possible to select a template of a SEM image having a higher correlation value.
  • [0050]
    In the semiconductor inspection system according to the nineteenth aspect, either the navigation system or the scanning electron microscope system is provided with a function to select the capturing and inspecting conditions from a previously registered file. Therefore, the conditions can be efficiently decided.
  • [0051]
    In the semiconductor inspection system according to the twentieth aspect, in the case of selecting from the capturing and inspecting condition file, the capturing and inspecting conditions are weighted depending on a frequency of use in the past and the conditions are selected therefrom. Therefore, the conditions can be efficiently decided.
  • [0052]
    In the semiconductor inspection system according to the twenty-first aspect, a capturing and inspecting condition inside the capturing and inspecting condition file is deleted automatically from the capturing and inspecting condition file in the case that a frequency of use thereof is lower than a predetermined frequency. Therefore, the conditions can be efficiently decided.
  • [0053]
    In the semiconductor inspection system according to the twenty-second aspect, the semiconductor inspection system of the nineteenth aspect is provided with a function to modify and edit a part of the capturing and inspecting conditions inside the capturing and inspecting condition file registered in advance. Therefore, the conditions can be efficiently decided with reference to the precedent conditions.
  • [0054]
    In the semiconductor inspection system according to the twenty-third aspect, in the case that a part of the capturing and inspecting conditions inside the capturing and inspecting condition file being registered in advance is modified and edited, the semiconductor inspection system of the nineteenth aspect is provided with a function to register the relevant condition with the capturing and inspecting condition file as another condition. Therefore the conditions can be efficiently decided thereafter.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0055]
    FIG. 1 is a flowchart of a conventional matching process between design data and a SEM image.
  • [0056]
    FIG. 2 is a flowchart of a matching process by use of design data and a SEM image according to one embodiment of the present invention.
  • [0057]
    FIG. 3 is a schematic diagram of a configuration of a semiconductor inspection system according to the embodiment of the present invention.
  • [0058]
    FIG. 4 is a flowchart for a case of time-lapse re-registration of a SEM image as a template according to the embodiment of the present invention.
  • [0059]
    FIG. 5 is a flowchart of a re-registration process of a SEM image as a template according to the embodiment of the present invention, in the case that a correlation value is higher than the previous value.
  • [0060]
    FIG. 6 is a flowchart of a re-registration process of a SEM image as a template according to the embodiment of the present invention, in which the SEM image having the highest correlation value during an arbitrary frequency of the matching processes between the design data and the SEM images is re-registered.
  • [0061]
    FIG. 7 shows image examples used in a conventional process.
  • [0062]
    FIG. 8 is a flowchart of a matching process by use of a template of bitmap data and a SEM image according to the embodiment of the present invention.
  • [0063]
    FIG. 9 is a flowchart of a matching process by use of a template of bitmap data and a SEM image according to another embodiment of the present invention.
  • [0064]
    FIG. 10 shows a method of composition and integration of an image decomposed into directions.
  • [0065]
    FIG. 11 is a view of a configuration of a semiconductor inspection system according to the embodiment of the present invention.
  • [0066]
    FIG. 12 is a view of a configuration of a navigation system according to the embodiment of the present invention.
  • [0067]
    FIG. 13 is a view of a configuration of the semiconductor inspection system according to another embodiment of the present invention.
  • [0068]
    FIG. 14 is a view of a network configuration of the semiconductor inspection system according to the embodiment of the present invention.
  • [0069]
    FIG. 15 is a display example in the navigation system according to the embodiment of the present invention.
  • [0070]
    FIG. 16 is an example of bitmap data generated by the navigation system according to the embodiment of the present invention.
  • [0071]
    FIG. 17 is a flowchart of a process performed by the navigation system according to the embodiment of the present invention.
  • [0072]
    FIG. 18 shows examples of specifying a length-measuring point and a template in the navigation system according to the embodiment of the present invention.
  • [0073]
    FIG. 19 is a flowchart of a process performed by a scanning electron microscope system according to the embodiment of the present invention.
  • [0074]
    FIG. 20 shows an automatic condition file according to the embodiment of the present invention, in which capturing and inspecting conditions are registered.
  • [0075]
    FIG. 21 is a flowchart of a process in the case of using the automatic condition film according to the embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • [0076]
    FIG. 3 is a block diagram of a schematic configuration of a scanning electron microscope system of the present invention. Reference numeral 301 denotes a body of an electron microscope. An electron beam 303 emitted out of an electron gun 302 is converged by an unillustrated electron lens and irradiated on a sample 305. Either intensity of secondary electrons generated from a surface of the sample or intensity of reflected electrons by electron beam irradiation is detected by an electron detector 306 and amplified by an amplifier 307. Reference numeral 304 denotes a deflector 304 which deflects the electron beam, thus subjecting the electron beam 303 to raster scanning on the sample surface according to a control signal 308 of a controlling computer 310. A signal outputted from the amplifier 307 is converted from analog to digital inside an imaging processor 309, whereby digital image data are generated. Reference numeral 311 denotes a display device for displaying the image data. Moreover, the imaging processor 309 includes an image memory for storing the digital image data, an imaging circuit for performing various imaging processes and a display control circuit for performing display control. Input means 312 such as a keyboard and a mouse is connected with the controlling computer 310.
  • [0077]
    During fabrication of a semiconductor device, the electron microscope system is used upon measurement of line widths of fine patterns drawn on a wafer. In this event, the normalized correlation method is currently used as a method to find out a portion on the wafer to measure the line width. In such a case, selection of an optimum template is deemed essential. The imaging processor 309 of the present invention has a constitution which effectuates optimum template selection upon template matching, whereby the imaging processor 309 is adoptable to the electron microscope system.
  • [0078]
    FIG. 2 is a flowchart of a matching process according to one embodiment of the present invention using design data and a SEM image. First in Step 201, a pattern portion requested for detection is registered out of the design data as a template. The SEM image is obtained in Step 202, and the matching process is performed in Step 203. Although there are various ways concerning this matching process, a way similar to Steps 103 to 105 of FIG. 1 (the edge emphasis filtering process, the binary conversion process and the normalized correlation process) may be used, for example. As a result, a position on the SEM image corresponding to the pattern of the designed data is detected in Step 204. Next in Step 205, the portion of the SEM image detected in Step 204 as corresponding to the pattern of the design data is re-registered as a template. Thereafter, another SEM image is obtained in Step 206. Then in Step 207, a matching process is performed while using the SEM image re-registered in Step 205 as the template, and position detection is performed in Step 208. In the foregoing steps, since the re-registered template is a SEM image, the matching process takes place between two graded SEM images. Accordingly, it is possible to perform the matching process with a high correlation value and a stable detection ratio as well. When detection is performed a plurality of times, Steps 206 to 209 will be iterated. If the template for initial registration is preset, then the subsequent processes can be conducted automatically by a computer program.
  • [0079]
    FIG. 4 is a flowchart of a case of time-lapse re-registration of the SEM image as the template according to the embodiment of the present invention. Steps 401 to 408 correspond to Steps 201 to 208 of FIG. 2, respectively. In Step 409, judgment is made as to whether or not re-registration of the template is carried out in every certain time interval or in every certain process frequency. When re-registration is carried out, Steps 402 to 405 are executed for performing the matching process again by use of the design data and the SEM image. In this way, it is possible to perform the matching process with a high correlation value and a high detection ratio even if the SEM image is changed with passage of time in the course of image capturing.
  • [0080]
    FIG. 5 is a flowchart of a re-registration process of the SEM image as the template according to the embodiment of the present invention, in the case that the correlation value higher than the previous value is obtained. Steps 501 to 504 and Steps 506 to 510 correspond to Steps 401 to 404 and Steps 405 to 409 of FIG. 4, respectively. In Step 510, judgment is made as to whether or not re-registration of the template is carried out in every certain time interval or in every certain process frequency. When re-registration is carried out, Steps 502 to 504 are executed for performing the matching process again by use of the design data and the SEM image. Next in Step 505, if the correlation value detected in the position at this time is higher than the correlation value of the currently effective template, re-registration of the template is performed in Step 506. However, if the detected correlation value is smaller than the correlation value of the currently effective template, re-registration does not take place and the process proceeds to subsequent Steps starting from Step 507. Accordingly, it is possible to optimize the template for use as the template having the highest correlation value.
  • [0081]
    FIG. 6 is a flowchart of a re-registration process of the SEM image as the template according to the embodiment of the present invention, in the case which the matching processes between the design data and the SEM image are performed in an arbitrary frequency, whereby the SEM image in the position highest in the correlation value among all the correlation values of the SEM images is re-registered as the template. Steps 601 to 604 and Steps 606 to 610 correspond to Steps 201 to 204 and Steps 205 to 209 in FIG. 2, respectively. The matching processes using the design data and the SEM image are iterated by an arbitrary frequency from Step 602 to Step 605, and then in Step 606, the SEM image in the position highest in the correlation value among all the detected positions is re-registered as the template. Accordingly, it is possible to select the SEM image high in the correlation value. When detection is performed a plurality of times, Steps 607 to 609 will be iterated by use of the template. Note that the both processes shown in FIG. 4 and in FIG. 6 can be automated by computer programs.
  • [0082]
    FIG. 8 is a flowchart of the matching process according to the embodiment of the present invention by use of a template of bitmap data and the SEM image. In Step 801, edge information is severally extracted out of the bitmap data and out of the SEM image. In this part of the process, an edge emphasis filter such as a Sobel filter is generally used. In this part, both images lose contrast information and matching is thereby facilitated. However, since the SEM image has quite a different shape from the actual CAD data, the detection ratio upon matching will be reduced if nothing is done. Therefore, in Step 802, each of both images converted into edge images is severally subjected to a smoothing process to make up deformation thereof. A slightly stronger smoothing filter is applied this part of the process. In addition, smoothing strength should be varied according to the CAD data or the SEM image; specifically, smoothing of the CAD data should be carried out more strongly. Since the pair of edge images, of which deformed parts are corrected, are subjected to the matching process in Step 803, it is possible to perform the matching process with a high detection ratio. Note that the matching process can be automated by a computer program if the edge information is preset severally by the bitmap data and the SEM image to be initially extracted.
  • [0083]
    FIG. 9 is a flowchart of the matching process according to another embodiment of the present invention by use of the template of bitmap data and the SEM image. A difference from the process flow of FIG. 8 is that edge extraction is performed in multiple directions in Step 901. As for edge extraction process in multiple directions, generally used is a Sobel filter which is capable of extracting edges in multiple directions. As for the directions, either 2 directions of X and Y, or 4 directions of X, Y, XY and YX is used. In Step 902, a smoothing process is performed on each edge image decomposed in each direction in order to make up a deformed part thereof. In Step 903, images decomposed in the respective directions are composed and integrated as illustrated in FIG. 10. In Step 904, the matching process can be performed between a pair of plain images owing to the above composition process. Needless to say, the matching process may be also performed severally with respect to each pair in the corresponding direction without performing the integration in Step 903. By extracting the edges and subjecting to the matching process with respect to each direction, matching accuracy in each direction can be enhanced. Note that an original image in FIG. 10 corresponds to a template and to an inputted SEM image in FIG. 9. Accordingly, upon finding differentials of these images in the X direction, such differentiation is carried out by dividing the original images into a plurality of lines along the Y direction. On the contrary, upon finding differentials in the Y direction, such differentiation is carried out by dividing the original images into a plurality of lines along the X direction. This matching process can be also automated by a computer program.
  • [0084]
    FIG. 11 is a view of a configuration of a semiconductor inspection system according to the embodiment of the present invention. Reference numeral 1101 denotes a navigation system, which is capable of storing design information of a semiconductor chip such as CAD data, and arbitrarily retrieving regions for inspection out of the design information. Reference numeral 1102 denotes the scanning electron microscope system for actually performing image capturing of a semiconductor wafer by using the information, and for executing given inspection. These systems 1101 and 1102 are linked together with a network, thus having a configuration to effectuate exchanges of information and data.
  • [0085]
    FIG. 12 is a view of a configuration of the navigation system according to the embodiment of the present invention. The navigation system 1101 is composed of a bitmap data generator 1201 having functions to retrieve desired design data out of the stored design information and to generate bitmap data therefrom, and a capturing and inspecting condition editor 1202 having a function to edit and transmit capturing and inspecting conditions out of the design data for use in the scanning electron microscope system 1102. In the meantime, the navigation system 1101 may be composed in a manner that functional parts of the bitmap data generator 1201 and the capturing/editing condition editor 1202 are separately configured within one workstation (a WS) or one personal computer (a PC), or in a manner that the functional parts thereof are separately configured in two or a plurality of WSs or PCs.
  • [0086]
    FIG. 13 is a view of a configuration of the semiconductor inspection system according to another embodiment of the present invention. A navigation system 1302 possesses a designing function of semiconductor patterns by itself. If the navigation system 1302 does not possess the designing function, the navigation system 1302 retrieves the design information from another system 1301 having the designing function, which is connected via the network, and uses the information.
  • [0087]
    FIG. 14 is a view of a network configuration of the semiconductor inspection system according to the embodiment of the present invention. In the semiconductor inspection system of the present invention, a navigation system 1401 can transmit and receive data with other navigation systems 1402 to 1404 connected to a network of a facility installed. The navigation system 1401 can further transmit the capturing and inspecting conditions to a plurality of scanning electron microscope systems 1405 and 1406 connected to the network. In this way, it is possible to share the capturing and inspecting conditions within the network, and it is also possible to drive a plurality of systems automatically and simultaneously.
  • [0088]
    FIG. 15 is a display example in the navigation system according to the embodiment of the present invention. Design data 1501 of a semiconductor is stored in the navigation system, and the navigation system has a function to allow an operator to retrieve a specified portion 1502 out of the design data 1501 by specifically inputting the design information such as layers and cells with respect to the specified portion 1502 in order to display the specified portion 1502 on a display screen as shown in reference numeral 1503. In this case, the design data 1501 may be stored in another design system connected via the network as shown in FIG. 13.
  • [0089]
    FIG. 16 is an example of the bitmap data generated by the navigation system 1302 according to the embodiment of the present invention. Reference numeral 1601 denotes a region retrieved from the design data in FIG. 15. Within this region, a portion 1602 subject to inspection and length measurement is specified. In this case, such an inspection/length-measurement specified region 1602 is converted into bitmap data 1603 and then transmitted to the scanning electron microscope system 1303. Here, the bitmap data 1603 consists of two values of black and white. However, such colors may be set up arbitrarily.
  • [0090]
    FIG. 17 is a flowchart of a process performed by the navigation system according to the embodiment of the present invention. In Step 1701, layer and cell information of the design or the like is specified as shown in FIG. 15, whereby the data specified out of the stored design data are displayed on the screen. A region for capturing is specified in Step 1702. In Step 1703, pattern data and positional information within a scope (the region specified as the region for capturing) are retrieved and then converted into the bitmap data 1603. This part is the same as the content as shown in FIG. 16. Next in Step 1704, a place subject to inspection and length measurement is specified and coordinate data thereof are read in. In Step 1705, specification of a template for matching is performed and registration of pattern data and positional information of the template are performed. As for specification of the template, the operator normally selects and specifies the most distinctive and characteristic portion. It is also possible to specify such a characteristic portion automatically by use of an image processing technology to detect high frequency components and distinction of an image. Lastly in Step 1706, all the information necessary for performing capturing and inspection with the scanning electron microscope system is edited based on the information gathered in Steps 1701 to 1705, and the edited information is transmitted to the scanning electron microscope system.
  • [0091]
    FIG. 18 shows examples of specifying a length-measuring point and the template in the navigation system according to the embodiment of the present invention. Reference numeral 1801 denotes specification of the length-measuring point and reference numeral 1802 denotes specification of the template. Although the image subject to specification herein is set as bitmap data, it is by all means possible to specify the template on the design data prior to conversion into the bitmap data.
  • [0092]
    FIG. 19 is a flowchart of a process performed by the scanning electron microscope system according to the embodiment of the present invention. In Steps 1901 to 1904, information concerning wafer alignment, information concerning the template for matching and information concerning the length-measuring point, conditions for capturing and a method of length measurement are registered based on the information transmitted in Step 1706 of FIG. 17. Actual capturing takes place in Step 1905. Then in Step 1906, a search process (detection of positions) is executed by use of the template registered in Step 1902. In Step 1907, the length-measuring point is computed from matching coordinates detected in Step 1906 and length measurement is executed. In Step 1908, judgment is made as to whether or not length measurement is completed with respect to all the length-measuring points. Step 1908 is provided for effectuating length measurement with respect to all the length-measuring points.
  • [0093]
    FIG. 20 shows an automatic condition file according to the embodiment of the present invention, in which capturing and inspecting conditions are registered. The automatic condition file may reside either in the navigation system or in the scanning electron microscope system. Actual capturing and inspection are performed by the scanning electron microscope system in accordance with the conditions registered in the automatic condition file 2001. In the case of deciding the capturing and inspecting conditions out of the information obtained by the navigation system, if the most suitable condition is selected from recipes registered in advance as in the present invention, a process for generating the conditions can be simplified and management and maintenance thereof become convenient. Moreover, each recipe registered in the automatic condition file can be partially modified or deleted as illustrated in a table 2002. Furthermore, each recipe can be also registered in another name. In addition, it is also possible to take statistics as to how often each recipe is used in order to delete less frequently used recipes automatically.
  • [0094]
    FIG. 21 is a flowchart of a process in the case of using the automatic condition film according to the embodiment of the present invention. In Step 2101, judgment is made as to whether a new recipe should be generated or not. If an identical or partially modifiable recipe does not exist yet in the automatic condition file 2001, the new recipe is generated in Step 2102. After generated, the new recipe is registered with the automatic condition file 2001 in Step 2106. After registration, it is possible to execute the recipe in Step 2108 with reference thereto. There may be also a case where execution only takes place without registration. In the case that the identical or partially modifiable recipe already exists in the automatic condition file 2001, the existing recipe inside the automatic condition file is referred in Step 2103, and then judgment is made as to whether the recipe should be partially modified or not in Step 2104. It is unnecessary to modify the recipe partially if the recipe is identical; therefore, the existing recipe is executed directly in Step 2108. The same is applicable to a case in which the existing recipe is not identical but substitutable. When the recipe is to be partially modified, after partial modification in Step 2105, judgment is made as to whether or not the modified recipe should be registered with the automatic condition file 2001 in Step 2106. Thereafter, the modified recipe is either registered in Step 2107 then executed in Step 2108, or just executed in Step 2108 without registration. By registering the recipe once used with the automatic condition file, it is possible to refer to the condition next time. Moreover, if the capturing and inspecting condition is modified partially, it is possible to register the modified condition as another condition in Step 2106. In this case, it is possible to refer to both files before and after such modification.
  • [0095]
    As the present invention has the configuration as described above, the following effects are achieved.
  • [0096]
    In a conventional semiconductor inspection system, registration of points for image recognition, positions for length measurement and length measuring algorithms has been performed once after capturing an image of an actual wafer and by use of the image. For this reason, there has been a problem that throughput is not improved because the registrations are time-consuming and the apparatus is occupied at the time of the registrations. Moreover, there has been a problem that it is impossible to construct an operator-free and fully-automated semiconductor inspection system because the conventional system always requires an operator for judgment and registration who observes actual SEM images.
  • [0097]
    In response to these problems, the present invention is arranged to generate all conditions necessary for inspection, including, the conditions for capturing, the points for length measurement and the length-measuring algorithms, out of the design information such as the CAD data. As the present invention is designed to perform actual inspection under these conditions, an operator-free and fully automated semiconductor inspection system with high throughput can be realized.
  • [0098]
    Moreover, in the conventional case of performing the matching process between the design data and the SEM images, it has been impossible to perform a stable matching process because the correlation efficient becomes considerably small due to inadaptability to deformed parts between the design data and the SEM images. In response to the foregoing problem, the present invention performs the matching process to make up the deformed parts by use of the edge information in multiple directions and smoothing thereof in the case that the matching process between the design data and the SEM images takes place. In addition, the present invention performs the matching process between the edge images and the templates of the design data, and performs the matching process after re-registering the part of the SEM image corresponding to the detected position as the template. Therefore, a stable matching process with a high correlation value and a high detection ratio can be achieved.

Claims (2)

  1. 1. A semiconductor inspection system, comprising:
    a navigation system for storing design information such as CAD data of a semiconductor chip and for setting capturing and inspecting conditions including a region on a semiconductor wafer subject to inspection based on the design information; and
    a scanning electron microscope system for performing actual capturing of the semiconductor wafer and for executing inspection in accordance with the capturing and inspecting conditions being set up.
  2. 2-23. (canceled)
US11790224 2001-04-27 2007-04-24 Semiconductor inspection system Abandoned US20070194236A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2001132668A JP4199939B2 (en) 2001-04-27 2001-04-27 Semiconductor inspection system
JP2001-132668 2001-04-27
US10082286 US7235782B2 (en) 2001-04-27 2002-02-26 Semiconductor inspection system
US11790224 US20070194236A1 (en) 2001-04-27 2007-04-24 Semiconductor inspection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11790224 US20070194236A1 (en) 2001-04-27 2007-04-24 Semiconductor inspection system

Publications (1)

Publication Number Publication Date
US20070194236A1 true true US20070194236A1 (en) 2007-08-23

Family

ID=18980646

Family Applications (3)

Application Number Title Priority Date Filing Date
US10082286 Active US7235782B2 (en) 2001-04-27 2002-02-26 Semiconductor inspection system
US10365383 Active US7026615B2 (en) 2001-04-27 2003-02-13 Semiconductor inspection system
US11790224 Abandoned US20070194236A1 (en) 2001-04-27 2007-04-24 Semiconductor inspection system

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US10082286 Active US7235782B2 (en) 2001-04-27 2002-02-26 Semiconductor inspection system
US10365383 Active US7026615B2 (en) 2001-04-27 2003-02-13 Semiconductor inspection system

Country Status (2)

Country Link
US (3) US7235782B2 (en)
JP (1) JP4199939B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8767038B2 (en) 2008-09-11 2014-07-01 Hitachi High-Technologies Corporation Method and device for synthesizing panorama image using scanning charged-particle microscope

Families Citing this family (91)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6711283B1 (en) 2000-05-03 2004-03-23 Aperio Technologies, Inc. Fully automatic rapid microscope slide scanner
WO2005036464A3 (en) 2003-10-08 2006-06-15 Applied Materials Israel Ltd A measurement system and a method
US7129484B2 (en) * 2004-01-21 2006-10-31 Hitachi Global Storage Technologies Netherlands B.V. Method for pattern recognition in energized charge particle beam wafer/slider inspection/measurement systems in presence of electrical charge
KR101056142B1 (en) 2004-01-29 2011-08-10 케이엘에이-텐코 코포레이션 A method implemented by a computer for detecting a defect in the reticle design data
JP4847685B2 (en) * 2004-04-16 2011-12-28 株式会社日立ハイテクノロジーズ Pattern search method
US7522763B2 (en) * 2004-07-30 2009-04-21 Mitutoyo Corporation Method of measuring occluded features for high precision machine vision metrology
JP4904034B2 (en) * 2004-09-14 2012-03-28 ケーエルエー−テンカー コーポレイション The method for evaluating reticle layout data, system and carrier medium
JP4230980B2 (en) 2004-10-21 2009-02-25 株式会社東芝 Pattern matching method and program
DE102005032601A1 (en) * 2005-01-07 2006-07-20 Heidelberger Druckmaschinen Ag press
JP2006214816A (en) * 2005-02-02 2006-08-17 Nikon Corp Semiconductor inspection device
JP2006234588A (en) 2005-02-25 2006-09-07 Hitachi High-Technologies Corp Pattern measuring method and pattern measuring device
JP4769025B2 (en) 2005-06-15 2011-09-07 株式会社日立ハイテクノロジーズ Creating a scanning electron microscope imaging recipe apparatus and a shape evaluation apparatus of the method, and a semiconductor pattern
JP4585926B2 (en) 2005-06-17 2010-11-24 株式会社日立ハイテクノロジーズ Pattern layer data generating apparatus, a pattern layer data generation system using the same, a semiconductor pattern display apparatus, a pattern layer data generation method, and a computer program
JP5180428B2 (en) * 2005-06-21 2013-04-10 株式会社日立ハイテクノロジーズ Creating a scanning electron microscope imaging recipe apparatus and a shape evaluation apparatus of the method, and a semiconductor pattern
US7769225B2 (en) 2005-08-02 2010-08-03 Kla-Tencor Technologies Corp. Methods and systems for detecting defects in a reticle design pattern
JP4644065B2 (en) * 2005-08-11 2011-03-02 株式会社日立ハイテクノロジーズ Scanning electron microscope and an image display method thereof
JP4658756B2 (en) 2005-09-14 2011-03-23 株式会社日立ハイテクノロジーズ Image processing apparatus, image processing method and a scanning electron microscope
JP4641924B2 (en) * 2005-10-21 2011-03-02 株式会社日立ハイテクノロジーズ Semiconductor inspection apparatus and semiconductor inspection method
US7676077B2 (en) * 2005-11-18 2010-03-09 Kla-Tencor Technologies Corp. Methods and systems for utilizing design data in combination with inspection data
US7570796B2 (en) * 2005-11-18 2009-08-04 Kla-Tencor Technologies Corp. Methods and systems for utilizing design data in combination with inspection data
US8041103B2 (en) 2005-11-18 2011-10-18 Kla-Tencor Technologies Corp. Methods and systems for determining a position of inspection data in design data space
JP5156619B2 (en) * 2006-02-17 2013-03-06 株式会社日立ハイテクノロジーズ Samples dimensional inspection and measurement method, and sample size Inspection Equipment
CN102759540B (en) 2006-02-17 2015-04-15 株式会社日立高新技术 Scanning electron microscope and imaging method using the same
WO2007102421A1 (en) * 2006-03-06 2007-09-13 Advantest Corporation Pattern inspecting system and pattern inspecting method
JP4901254B2 (en) 2006-03-22 2012-03-21 株式会社日立ハイテクノロジーズ Pattern matching method, and a computer program for performing pattern matching
JP5094033B2 (en) * 2006-03-27 2012-12-12 株式会社日立ハイテクノロジーズ Pattern matching method, and a computer program for performing pattern matching
JP5401005B2 (en) * 2006-06-16 2014-01-29 株式会社日立ハイテクノロジーズ Template matching method, and scanning electron microscopy
KR100819094B1 (en) * 2006-10-26 2008-04-02 삼성전자주식회사 Global matching method for semiconductor memory device manufacturing
JP5077992B2 (en) * 2006-11-06 2012-11-21 東京エレクトロン株式会社 Server device, information processing method, and program
JP4365854B2 (en) 2006-12-13 2009-11-18 株式会社日立ハイテクノロジーズ Sem device or sem system and imaging recipe and measuring recipe creation method
WO2008077100A3 (en) 2006-12-19 2009-09-24 Kla-Tencor Corporation Systems and methods for creating inspection recipes
US7898653B2 (en) 2006-12-20 2011-03-01 Hitachi High-Technologies Corporation Foreign matter inspection apparatus
WO2008086282A3 (en) 2007-01-05 2008-09-12 Kla Tencor Corp Methods and systems for using electrical information for a device being fabricated on a wafer to perform one or more defect-related functions
US8019164B2 (en) * 2007-01-29 2011-09-13 Hitachi High-Technologies Corporation Apparatus, method and program product for matching with a template
JP2008211087A (en) * 2007-02-27 2008-09-11 Fujitsu Ltd Wafer flatness measuring device
US7925072B2 (en) * 2007-03-08 2011-04-12 Kla-Tencor Technologies Corp. Methods for identifying array areas in dies formed on a wafer and methods for setting up such methods
US7962863B2 (en) * 2007-05-07 2011-06-14 Kla-Tencor Corp. Computer-implemented methods, systems, and computer-readable media for determining a model for predicting printability of reticle features on a wafer
US7738093B2 (en) 2007-05-07 2010-06-15 Kla-Tencor Corp. Methods for detecting and classifying defects on a reticle
US8213704B2 (en) 2007-05-09 2012-07-03 Kla-Tencor Corp. Methods and systems for detecting defects in a reticle design pattern
US7796804B2 (en) 2007-07-20 2010-09-14 Kla-Tencor Corp. Methods for generating a standard reference die for use in a die to standard reference die inspection and methods for inspecting a wafer
US7711514B2 (en) 2007-08-10 2010-05-04 Kla-Tencor Technologies Corp. Computer-implemented methods, carrier media, and systems for generating a metrology sampling plan
US7975245B2 (en) 2007-08-20 2011-07-05 Kla-Tencor Corp. Computer-implemented methods for determining if actual defects are potentially systematic defects or potentially random defects
JP2009071136A (en) * 2007-09-14 2009-04-02 Hitachi High-Technologies Corp Data management device, inspection system and defect reviewing apparatus
US8010315B2 (en) * 2007-11-27 2011-08-30 General Electric Company Multi-modality inspection method with data validation and data fusion
US7840367B2 (en) * 2007-11-28 2010-11-23 General Electric Company Multi-modality inspection system
JP4627782B2 (en) 2008-03-05 2011-02-09 株式会社日立ハイテクノロジーズ Edge detection method, and a charged particle beam device
JP5647761B2 (en) 2008-03-07 2015-01-07 株式会社日立ハイテクノロジーズ Template creation method and image processing apparatus
JP5559957B2 (en) 2008-03-18 2014-07-23 株式会社日立ハイテクノロジーズ Pattern measurement method and pattern measuring apparatus
JP5530601B2 (en) 2008-03-31 2014-06-25 株式会社日立ハイテクノロジーズ Dimension measurement apparatus and method of a circuit pattern using a scanning electron microscope
JP5202071B2 (en) 2008-03-31 2013-06-05 株式会社日立ハイテクノロジーズ Charged particle microscope apparatus and an image processing method using the same
US8139844B2 (en) 2008-04-14 2012-03-20 Kla-Tencor Corp. Methods and systems for determining a defect criticality index for defects on wafers
US9659670B2 (en) 2008-07-28 2017-05-23 Kla-Tencor Corp. Computer-implemented methods, computer-readable media, and systems for classifying defects detected in a memory device area on a wafer
DE102008040803A1 (en) * 2008-07-28 2010-02-04 Carl Zeiss Surgical Gmbh A method for the quantitative representation of the blood flow
JP5063551B2 (en) * 2008-10-03 2012-10-31 株式会社日立ハイテクノロジーズ Pattern matching method, and an image processing apparatus
JP5066056B2 (en) * 2008-10-31 2012-11-07 株式会社日立ハイテクノロジーズ Sample observation method, and an electron microscope
JP2010177500A (en) * 2009-01-30 2010-08-12 Hitachi High-Technologies Corp Overlap evaluation method of pattern
US8775101B2 (en) 2009-02-13 2014-07-08 Kla-Tencor Corp. Detecting defects on a wafer
US8204297B1 (en) 2009-02-27 2012-06-19 Kla-Tencor Corp. Methods and systems for classifying defects detected on a reticle
US8112241B2 (en) 2009-03-13 2012-02-07 Kla-Tencor Corp. Methods and systems for generating an inspection process for a wafer
JP4926208B2 (en) * 2009-05-26 2012-05-09 株式会社日立ハイテクノロジーズ Scanning electron microscope, and the evaluation point generation method, and program
JP5500871B2 (en) 2009-05-29 2014-05-21 株式会社日立ハイテクノロジーズ Templating method for template matching, and the template creation apparatus
WO2011001635A1 (en) * 2009-06-30 2011-01-06 株式会社日立ハイテクノロジーズ Semiconductor inspection device and semiconductor inspection method using the same
JP5313069B2 (en) 2009-07-17 2013-10-09 株式会社日立ハイテクノロジーズ Measurement method of scanning charged particle microscope and a pattern dimension using the same
JP5604067B2 (en) * 2009-07-31 2014-10-08 株式会社日立ハイテクノロジーズ How to create a matching template, and the template creation apparatus
JP5154527B2 (en) * 2009-09-16 2013-02-27 株式会社日立ハイテクノロジーズ Foreign matter inspection apparatus
JP5568277B2 (en) 2009-10-22 2014-08-06 株式会社日立ハイテクノロジーズ Pattern matching method, and pattern matching device
JP5357725B2 (en) * 2009-12-03 2013-12-04 株式会社日立ハイテクノロジーズ Defect inspection method and a defect inspection apparatus
JP5241697B2 (en) * 2009-12-25 2013-07-17 株式会社日立ハイテクノロジーズ Alignment data creation system and method
JP5564276B2 (en) 2010-01-28 2014-07-30 株式会社日立ハイテクノロジーズ Pattern matching image creation device
JP5313939B2 (en) * 2010-02-09 2013-10-09 株式会社日立ハイテクノロジーズ Pattern inspection method, pattern inspection program, an electronic device testing system
JP5174863B2 (en) 2010-07-28 2013-04-03 株式会社日立ハイテクノロジーズ Image acquisition condition setting apparatus, and computer program
US8781781B2 (en) 2010-07-30 2014-07-15 Kla-Tencor Corp. Dynamic care areas
JP5657349B2 (en) * 2010-11-05 2015-01-21 株式会社日立ハイテクノロジーズ Design template generating apparatus, a recipe generator and microscopic image matching device
JP5683907B2 (en) * 2010-11-08 2015-03-11 株式会社日立ハイテクノロジーズ The method of scanning electron microscope and the apparatus
JP5466142B2 (en) * 2010-12-15 2014-04-09 アペリオ・テクノロジーズ・インコーポレイテッドAperio Technologies, Inc. Data management system and method in microscope slide scanner using a linear array
JP5417358B2 (en) * 2011-02-28 2014-02-12 株式会社日立ハイテクノロジーズ Computer programs for performing the image processing apparatus, and image processing
US9170211B2 (en) 2011-03-25 2015-10-27 Kla-Tencor Corp. Design-based inspection using repeating structures
US8483489B2 (en) 2011-09-02 2013-07-09 Sharp Laboratories Of America, Inc. Edge based template matching
US9087367B2 (en) 2011-09-13 2015-07-21 Kla-Tencor Corp. Determining design coordinates for wafer defects
US8831334B2 (en) 2012-01-20 2014-09-09 Kla-Tencor Corp. Segmentation for wafer inspection
US8826200B2 (en) 2012-05-25 2014-09-02 Kla-Tencor Corp. Alteration for wafer inspection
JP5783953B2 (en) * 2012-05-30 2015-09-24 株式会社日立ハイテクノロジーズ Pattern evaluation apparatus and the pattern evaluation method
US9189844B2 (en) 2012-10-15 2015-11-17 Kla-Tencor Corp. Detecting defects on a wafer using defect-specific information
US9053527B2 (en) 2013-01-02 2015-06-09 Kla-Tencor Corp. Detecting defects on a wafer
US9134254B2 (en) 2013-01-07 2015-09-15 Kla-Tencor Corp. Determining a position of inspection system output in design data space
US9311698B2 (en) 2013-01-09 2016-04-12 Kla-Tencor Corp. Detecting defects on a wafer using template image matching
WO2014149197A1 (en) 2013-02-01 2014-09-25 Kla-Tencor Corporation Detecting defects on a wafer using defect-specific and multi-channel information
JP2014203109A (en) * 2013-04-01 2014-10-27 株式会社ディスコ The target pattern setting method
US9865512B2 (en) 2013-04-08 2018-01-09 Kla-Tencor Corp. Dynamic design attributes for wafer inspection
US9310320B2 (en) 2013-04-15 2016-04-12 Kla-Tencor Corp. Based sampling and binning for yield critical defects
CN105097585A (en) * 2014-05-21 2015-11-25 中芯国际集成电路制造(上海)有限公司 CDSEM measuring method of wafer layout

Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4683496A (en) * 1985-08-23 1987-07-28 The Analytic Sciences Corporation System for and method of enhancing images using multiband information
US5600734A (en) * 1991-10-04 1997-02-04 Fujitsu Limited Electron beam tester
US6094501A (en) * 1997-05-05 2000-07-25 Shell Oil Company Determining article location and orientation using three-dimensional X and Y template edge matrices
US6107637A (en) * 1997-08-11 2000-08-22 Hitachi, Ltd. Electron beam exposure or system inspection or measurement apparatus and its method and height detection apparatus
US6108033A (en) * 1996-05-31 2000-08-22 Hitachi Denshi Kabushiki Kaisha Method and system monitoring video image by updating template image
US6114681A (en) * 1997-06-04 2000-09-05 Kabushiki Kaisha Toshiba Automatic focus control method and automatic focus control system having in focus and out of focus states detection
US6154714A (en) * 1997-11-17 2000-11-28 Heuristic Physics Laboratories Method for using wafer navigation to reduce testing times of integrated circuit wafers
US6292582B1 (en) * 1996-05-31 2001-09-18 Lin Youling Method and system for identifying defects in a semiconductor
US6330353B1 (en) * 1997-12-18 2001-12-11 Siemens Corporate Research, Inc. Method of localization refinement of pattern images using optical flow constraints
US6363167B1 (en) * 1998-03-03 2002-03-26 Kabushiki Kaisha Toshiba Method for measuring size of fine pattern
US6453274B2 (en) * 1994-09-16 2002-09-17 Mitsubishi Denki Kabushiki Kaisha Method of forming a pattern using proximity-effect-correction
US6479819B1 (en) * 1997-08-19 2002-11-12 Nikon Corporation Object observation apparatus and object observation
US20020166964A1 (en) * 1999-01-08 2002-11-14 Talbot Christopher G. Detection of defects in patterned substrates
US6539106B1 (en) * 1999-01-08 2003-03-25 Applied Materials, Inc. Feature-based defect detection
US6563114B1 (en) * 1999-03-05 2003-05-13 Kabushiki Kaisha Toshiba Substrate inspecting system using electron beam and substrate inspecting method using electron beam
US6570157B1 (en) * 2000-06-09 2003-05-27 Advanced Micro Devices, Inc. Multi-pitch and line calibration for mask and wafer CD-SEM system
US6763129B1 (en) * 1999-10-05 2004-07-13 Kabushiki Kaisha Toshiba Image processing apparatus

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6454305U (en) 1987-09-29 1989-04-04
US4905151A (en) * 1988-03-07 1990-02-27 Transitions Research Corporation One dimensional image visual system for a moving vehicle
JP3258601B2 (en) 1997-07-17 2002-02-18 エーザイ株式会社 Automatic analyzer
JP4067677B2 (en) 1999-02-17 2008-03-26 富士通株式会社 Automatic measurement sequence The method of automatic detection sequence file creating method of a scanning electron microscope and a scanning electron microscope
JP2000266706A (en) 1999-03-18 2000-09-29 Toshiba Corp Detecting device and its method
US6671405B1 (en) * 1999-12-14 2003-12-30 Eastman Kodak Company Method for automatic assessment of emphasis and appeal in consumer images

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4683496A (en) * 1985-08-23 1987-07-28 The Analytic Sciences Corporation System for and method of enhancing images using multiband information
US5600734A (en) * 1991-10-04 1997-02-04 Fujitsu Limited Electron beam tester
US5872862A (en) * 1991-10-04 1999-02-16 Fujitsu Limited Electron beam tester
US6453274B2 (en) * 1994-09-16 2002-09-17 Mitsubishi Denki Kabushiki Kaisha Method of forming a pattern using proximity-effect-correction
US6108033A (en) * 1996-05-31 2000-08-22 Hitachi Denshi Kabushiki Kaisha Method and system monitoring video image by updating template image
US6292582B1 (en) * 1996-05-31 2001-09-18 Lin Youling Method and system for identifying defects in a semiconductor
US6094501A (en) * 1997-05-05 2000-07-25 Shell Oil Company Determining article location and orientation using three-dimensional X and Y template edge matrices
US6114681A (en) * 1997-06-04 2000-09-05 Kabushiki Kaisha Toshiba Automatic focus control method and automatic focus control system having in focus and out of focus states detection
US6107637A (en) * 1997-08-11 2000-08-22 Hitachi, Ltd. Electron beam exposure or system inspection or measurement apparatus and its method and height detection apparatus
US6479819B1 (en) * 1997-08-19 2002-11-12 Nikon Corporation Object observation apparatus and object observation
US6154714A (en) * 1997-11-17 2000-11-28 Heuristic Physics Laboratories Method for using wafer navigation to reduce testing times of integrated circuit wafers
US6330353B1 (en) * 1997-12-18 2001-12-11 Siemens Corporate Research, Inc. Method of localization refinement of pattern images using optical flow constraints
US6363167B1 (en) * 1998-03-03 2002-03-26 Kabushiki Kaisha Toshiba Method for measuring size of fine pattern
US20020166964A1 (en) * 1999-01-08 2002-11-14 Talbot Christopher G. Detection of defects in patterned substrates
US6539106B1 (en) * 1999-01-08 2003-03-25 Applied Materials, Inc. Feature-based defect detection
US6563114B1 (en) * 1999-03-05 2003-05-13 Kabushiki Kaisha Toshiba Substrate inspecting system using electron beam and substrate inspecting method using electron beam
US6763129B1 (en) * 1999-10-05 2004-07-13 Kabushiki Kaisha Toshiba Image processing apparatus
US6570157B1 (en) * 2000-06-09 2003-05-27 Advanced Micro Devices, Inc. Multi-pitch and line calibration for mask and wafer CD-SEM system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8767038B2 (en) 2008-09-11 2014-07-01 Hitachi High-Technologies Corporation Method and device for synthesizing panorama image using scanning charged-particle microscope

Also Published As

Publication number Publication date Type
US7235782B2 (en) 2007-06-26 grant
US7026615B2 (en) 2006-04-11 grant
JP2002328015A (en) 2002-11-15 application
US20030173516A1 (en) 2003-09-18 application
JP4199939B2 (en) 2008-12-24 grant
US20020158199A1 (en) 2002-10-31 application

Similar Documents

Publication Publication Date Title
US6799130B2 (en) Inspection method and its apparatus, inspection system
US20080058977A1 (en) Reviewing apparatus using a sem and method for reviewing defects or detecting defects using the reviewing apparatus
US6763130B1 (en) Real time defect source identification
US6839470B2 (en) Pattern evaluation method, pattern evaluation system and computer readable recorded medium
US6865288B1 (en) Pattern inspection method and apparatus
US20070177787A1 (en) Fault inspection method
US6028664A (en) Method and system for establishing a common reference point on a semiconductor wafer inspected by two or more scanning mechanisms
US5694481A (en) Automated design analysis system for generating circuit schematics from high magnification images of an integrated circuit
US5777327A (en) Pattern shape inspection apparatus for forming specimen image on display apparatus
US6236746B1 (en) Method to extract circuit information
US20040081350A1 (en) Pattern inspection apparatus and method
US6775817B2 (en) Inspection system and semiconductor device manufacturing method
US6987873B1 (en) Automatic defect classification with invariant core classes
US20010002697A1 (en) Electron beam inspection method and apparatus and semiconductor manufacturing method and its manufacturing line utilizing the same
US20030021463A1 (en) Method and apparatus for circuit pattern inspection
US6334097B1 (en) Method of determining lethality of defects in circuit pattern inspection method of selecting defects to be reviewed and inspection system of circuit patterns involved with the methods
US20060045326A1 (en) Pattern matching apparatus and scanning electron microscope using the same
US20070031026A1 (en) Method and apparatus for reviewing defects of semiconductor device
US20020051565A1 (en) Circuit pattern inspection method and apparatus
US6388747B2 (en) Inspection method, apparatus and system for circuit pattern
US6898305B2 (en) Circuit pattern inspection method and apparatus
US7231079B2 (en) Method and system for inspecting electronic circuit pattern
US20020051567A1 (en) Method of adjusting a lithographic tool
US20060215901A1 (en) Method and apparatus for reviewing defects
US20060038986A1 (en) Method of reviewing detected defects