US20070190692A1 - Low resistance and inductance backside through vias and methods of fabricating same - Google Patents

Low resistance and inductance backside through vias and methods of fabricating same Download PDF

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Publication number
US20070190692A1
US20070190692A1 US11275542 US27554206A US2007190692A1 US 20070190692 A1 US20070190692 A1 US 20070190692A1 US 11275542 US11275542 US 11275542 US 27554206 A US27554206 A US 27554206A US 2007190692 A1 US2007190692 A1 US 2007190692A1
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Prior art keywords
layer
substrate
dielectric
contact
forming
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US7563714B2 (en )
Inventor
Mete Erturk
Robert Groves
Jeffrey Johnson
Alvin Joseph
Qizhi Liu
Edmund Sprogis
Anthony Stamper
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International Business Machines Corp
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International Business Machines Corp
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.

Description

    FIELD OF THE INVENTION
  • [0001]
    The present invention relates to the field of integrated circuits; more specifically, it relates to backside through vias and methods of fabricating backside through vias for electrical connection to elements of integrated circuits.
  • BACKGROUND OF THE INVENTION
  • [0002]
    There are many integrated circuit applications where it is desirable to reduce the resistance and inductance of signal lines in circuits normally associated with frontside wire bond pad connections. For example, because of the inductance associated with wire bond pad connections to the emitter of NPN hetero-junction bipolar transistors (HBT), the maximum practical operating frequency of circuits using NPN HBTs in wire bond packages is about 3 GHz even though the transistors are capable of running at higher frequencies. Therefore, there is a need for interconnect structures and methods of fabricating interconnect structures with reduced inductance and resistance for connecting signals to circuit elements of integrated circuits.
  • SUMMARY OF THE INVENTION
  • [0003]
    A first aspect of the present invention is a method for forming a contact, comprising: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from the backside of the substrate to expose the through via.
  • [0004]
    A second aspect of the present invention is the first aspect, further including: forming a device contact opening in the first dielectric layer and simultaneously with the filling the trench and co-planarizing, filling the device contact opening and co-planarizing a top surface of the filled device contact opening with a top surface of the first dielectric layer to form an electrically conductive device contact.
  • [0005]
    A third aspect of the present invention is the first aspect, further including: before forming the through via, forming a device contact opening in the first dielectric layer, filling the device contact opening and co-planarizing a top surface of the filled device contact opening with a top surface of the first dielectric layer to form an electrically conductive device contact.
  • [0006]
    A fourth aspect of the present invention is the first aspect, further including: after forming the through via, forming a device contact opening in the first dielectric layer, filling the device contact opening and co-planarizing a top surface of the filled contact opening with a top surface of the first dielectric layer to form an electrically conductive device contact.
  • [0007]
    A fifth aspect of the present invention is the first aspect, wherein said filling said trench includes: either forming a insulating layer on sidewalls and a bottom of said trench and forming a tungsten layer over said insulating layer, said tungsten layer of sufficient thickness to fill said trench; or forming said tungsten layer on said sidewalls and said bottom of said trench, said tungsten layer of sufficient thickness to fill said trench.
  • [0008]
    A sixth aspect of the present invention is the first aspect, wherein said filling said trench includes: either forming a insulating layer on sidewalls and a bottom of said trench, forming a conformal polysilicon layer over said insulating layer, and forming a tungsten layer over said polysilicon layer, said tungsten layer of sufficient thickness to fill said trench; or forming said polysilicon layer on said sidewalls and said bottom of said trench; and forming a tungsten layer over said polysilicon layer, said tungsten layer of sufficient thickness to fill said trench.
  • [0009]
    A seventh aspect of the present invention is the first aspect, wherein said filling said trench includes: either forming a insulating layer on sidewalls and a bottom of said trench; forming a conformal tungsten layer over said insulating layer, and forming an oxide layer over said tungsten layer, said oxide layer of sufficient thickness to fill said trench; or forming a conformal tungsten layer on said sidewalls and said bottom of said trench, and forming an oxide layer over said tungsten layer, said oxide layer of sufficient thickness to fill said trench.
  • [0010]
    An eighth aspect of the present invention is the first aspect, wherein said filling said trench includes: either forming a insulating layer on sidewalls and a bottom of said trench, forming a conformal polysilicon layer over said insulating layer, forming a conformal tungsten layer over said polysilicon layer, and forming an oxide layer over said tungsten layer, said oxide layer of sufficient thickness to fill said trench; or forming a conformal polysilicon layer on said sidewalls and said bottom of said trench, forming a conformal tungsten layer over said polysilicon layer, and forming an oxide layer over said tungsten layer, said oxide layer of sufficient thickness to fill said trench.
  • [0011]
    A ninth aspect of the present invention is the first aspect, further including: forming a hetero-junction bipolar transistor in and on said substrate; forming a device contact in the first dielectric layer, the device contact in physical and electrical contact to an emitter of the hetero-junction bipolar transistor; and forming a wire in a second dielectric layer, the second dielectric layer formed over the first dielectric layer and the wire in direct physical and electrical contact with the device contact and the through via.
  • [0012]
    A tenth aspect of the present invention is the first aspect, wherein the trench extends to and contacts a buried oxide layer in the substrate and the thinning the substrate removes the buried oxide layer.
  • BRIEF DESCRIPTION OF DRAWINGS
  • [0013]
    The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
  • [0014]
    FIGS. 1A through 1E are cross-sectional drawings illustrating fabrication of a backside interconnect structure according to a first embodiment of the present invention;
  • [0015]
    FIGS. 1F through 1H are cross-sectional drawings illustrating variations of backside interconnect structures according to the first embodiment of the present invention;
  • [0016]
    FIGS. 2A through 2E are cross-sectional drawings illustrating fabrication of a backside interconnect structure according to a second embodiment of the present invention;
  • [0017]
    FIGS. 3A1 through 3A5 are cross-sectional drawings illustrating fabrication of a backside interconnect structure according to a first variation of a third embodiment of the present invention;
  • [0018]
    FIGS. 3B1 through 3B3 are cross-sectional drawings illustrating fabrication of a backside interconnect structure according to a second variation of the third embodiment of the present invention;
  • [0019]
    FIGS. 3C1 through 3C3 are cross-sectional drawings illustrating fabrication of a backside interconnect structure according to a third variation of the third embodiment of the present invention;
  • [0020]
    FIGS. 4A1 through 4A3 are cross-sectional drawings illustrating a first method of filling a through via or stud contact of the third embodiment of the present invention;
  • [0021]
    FIGS. 4B1 through 4B4 are cross-sectional drawings illustrating a second method of filling a through via or stud contact of the third embodiment of the present invention;
  • [0022]
    FIGS. 4C1 through 4C4 are cross-sectional drawings illustrating a third method of filling a through via or stud contact of the third embodiment of the present invention;
  • [0023]
    FIGS. 4D1 through 4D5 are cross-sectional drawings illustrating a fourth method of filling a through via or stud contact of the third embodiment of the present invention;
  • [0024]
    FIGS. 5A and 5B are cross-sectional drawings illustrating fabrication of a backside interconnect structure using alternative substrate according to any of the variations of the third embodiment of the present invention;
  • [0025]
    FIGS. 6A and 6B are cross-sectional drawings illustrating fabrication of a backside interconnect structure according to a fourth embodiment of the present invention; and
  • [0026]
    FIG. 7 is a cross-sectional view of an exemplary hetero-junction bipolar transistor having a backside connection to a substrate.
  • DETAILED DESCRIPTION OF THE INVENTION
  • [0027]
    A damascene process is one in which wire trenches or via openings (via openings may also be called via trenches) are formed in a dielectric layer, an electrical conductor of sufficient thickness to fill the trenches is deposited on a top surface of the dielectric, and a planarization process, such as a one or more of a chemical-mechanical-polish (CMP) process or reactive ion etch (RIE) process, is performed to remove excess conductor and make the surface of the conductor co-planer or substantially co-planer with the surface of the dielectric layer to form damascene wires (or damascene vias). When only a trench and a wire (or a via opening and a via) are formed the process is called single-damascene. Stud contacts (which are equivalent to single damascene wires and vias and which are formed in the first dielectric layer over the semiconductor substrate) are also formed using single-damascene processes.
  • [0028]
    A dual-damascene process is one in which wire and via openings are formed in a dielectric prior to metallization. For example, via openings are formed through the entire thickness of a dielectric layer followed by formation of trenches part of the way through the dielectric layer in any given cross-sectional view. (Alternatively, the wire trenches may be formed first, followed by formation of the via openings.) All via openings intended to conduct electric current are intersected by integral wire trenches above and by a wire trench below, but not all trenches need intersect a via opening. An electrical conductor of sufficient thickness to fill the trenches and via opening is deposited on a top surface of the dielectric and a CMP process is performed to make the surface of the conductor in the trench co-planer with the surface the dielectric layer to form dual-damascene wires and dual-damascene wires having integral dual-damascene vias.
  • [0029]
    FIGS. 1A through 1H are cross-sectional drawings illustrating fabrication of a backside interconnect structure according to a first embodiment of the present invention. In FIG. 1A, a portion of an integrated circuit chip before dicing is illustrated. Formed on a substrate 100 is a first dielectric layer 105. Substrate 100 is also commonly called a “wafer.” First dielectric layer 105 may be a multilayer dielectric layer comprising, for example, a layer of silicon dioxide (SiO2) contacting substrate 100, a layer of silicon nitride on top of the silicon dioxide layer and a layer of phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG) on top of the SiO2. In a first example, substrate 100 is a bulk silicon substrate. In a second example, substrate 100 is a silicon on insulator (SOI) substrate.
  • [0030]
    Formed on top of first dielectric layer 105 is a second dielectric layer 110. Formed on top of second dielectric layer 110 is a third dielectric layer 115. Formed on top of third dielectric layer 115 is a fourth dielectric layer 120. In one example, second, third and fourth dielectric layers 110, 115 and 120 each comprising one or more layers of a low K (dielectric constant) material, hydrogen silsesquioxane polymer (HSQ), methyl silsesquioxane polymer (MSQ), SiLK™ (polyphenylene oligomer) manufactured by Dow Chemical, Midland, Tex., Black Diamond™ (methyl doped silica or SiOx(CH3)y or SiCxOyHy or SiOCH) manufactured by Applied Materials, Santa Clara, Calif., organosilicate glass (SiCOH), porous SiCOH, a high, silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), silicon oxy nitride (SiON), silicon oxy carbide (SiOC), plasma-enhanced silicon nitride (PSiNx) or NBLok (SiC(N,H)). A low K dielectric material has a relative permittivity of about 3 or less. Formed on top of fourth dielectric layer 120 is a insulating layer 125. In one example, insulating layer 125 comprises a layer of SiO2, Si3N4, polyimide or combinations of layers thereof. The use of four dielectric layers is exemplary and more or less dielectric layer and corresponding wires and vias may be used.
  • [0031]
    Formed partially in substrate 100 and partially in first dielectric layer 105 is an exemplary HBT 130. HBT 130, may be replaced by other devices known in the art, such as metal-oxide-silicon field effect transistor (MOSFET)s, standard bipolar transistors, diodes, thin film or diffused silicon substrate resistors and thin film capacitors. (See also FIG. 8A). Formed partially in substrate 100 and partially in first dielectric layer 105 is an exemplary MOSFET 135. MOSFET 135, may be replaced by other devices known in the art, such as standard bipolar transistors, diodes, resistors and capacitors. Formed in first dielectric layer 105 are stud contacts 140A, 140B and 140C. Since stud contacts 140A and 140C contact devices (i.e. HBT 130 and MOSFET 135), stud contacts 140A and 140C may be called device contacts to distinguish them from contacts 140B which will be used to contact a through via as described infra. Formed in second dielectric layer 110 are damascene wires 145 and 150. Damascene wire 145 is in direct physical and electrical contact with stud contacts 140A and 140B and wire 150 is in direct physical and electrical contact with stud contact 140C. Stud contact 140A is in direct physical and electrical contact with HBT 130 (for example the emitter of HBT 130). Stud contacts 140B are in direct physical contact with substrate 100 at this point in the fabrication. Stud contact 140C is in direct physical and electrical contact with MOSFET 135 (for example, the gate of MOSFET 135). In one example, stud contacts 140A, 140B and 140C comprise a core conductor of tungsten (W) surrounded by a liner on the sidewalls and bottom of the core conductor, the liner comprising titanium (Ti), titanium nitride (TiN) or combinations of layers thereof.
  • [0032]
    Formed in third dielectric layer 115 is a dual-damascene wire/via 155. Formed in fourth dielectric layer is a dual-damascene wirebond pad/vias 160A and 160B. In one example, dual-damascene wire/via 155 and dual-damascene wirebond pad/vias 160A and 160B comprise a core conductor of copper (Cu) surrounded by a liner on the sidewalls and bottom of the core conductor, the liner comprising Ta, TaN, tantalum silicon nitride (TaSiN), tungsten (W), tungsten nitride (WN), titanium nitride (TiN) or combinations of layers thereof. Dual-damascene wirebond pad/vias 160A and 160B may also include a layer of aluminum (Al) on the exposed top surface of the core conductor.
  • [0033]
    In FIG. 1B, substrate 100 is thinned to a thickness T1. In one example T1 is between about 100 microns and about 400 microns, (in one example about 150 microns). In one example, thinning of substrate 100 may accomplished by backside grinding, wet etching or combinations thereof. Examples of suitable wet etchants include, but are not limited to aqueous tetrametylammonium hydroxide (TMAH), alcoholic potassium hydroxide (KOH) and other aqueous/alcoholic base solutions.
  • [0034]
    In FIG. 1C, a through via opening 165 is etched from the backside of substrate 100, through the substrate, to expose first dielectric layer 105 and at least bottom surfaces of stud contacts 140B in the bottom of the through via. Through via opening 165 may be formed by applying a photoresist layer on the backside of substrate, exposing the photoresist to actinic radiation and developing the exposed (positive resist) or unexposed (negative resist) and then reactive ion etching (RIE) the substrate. Combinations of RIE and wet etches may be used. Examples of suitable wet etchants include, but are not limited to aqueous tetrametylammonium hydroxide (TMAH), alcoholic potassium hydroxide (KOH) and other aqueous/alcoholic base solutions. In one example the area of backside opening is between about 2,500 square microns and about 10,000 square microns with a depth of at least T1 (see FIG. 1B). In one example, alignment of the photoresist layer to stud contacts 140B utilizes an expose tool equipped with an infrared (IR) alignment system, which allows for alignment to structures, such as studs or wires, on the wafer front side. Although FIG. 1D shows no overetch into dielectric layer 105, some overetch might occur, e.g. 10-500 nm, during the silicon through via etch.
  • [0035]
    Although FIGS. 1C and 1D do not show how the thinned wafer would be handled as it is processed upside down during the via processing, it is understood that either the substrate frontside would be attached to a temporary or permanent wafer carrier, such as a second quartz or polyimide substrate; or layers 125, 160A, and 160B would be durable enough to withstand the processing shown in FIGS. 1C and 1D. One method of making layers 125, 160A, and 160B durable enough would be to increase the thickness of layer 125 to a few 10's of microns, to raise layers 160A and 160B above the plane of the chuck holding the wafer during the processing shown in FIGS. 1C and 1D; an alternative method would be to limit wafer handling and chucking to the extreme edge of the wafer, (in one example about 2 mm to about 3 mm) from the edge, to prevent mechanical damage of the wafer surface.
  • [0036]
    In FIG. 1D, a first conformal and electrically conductive layer 170 of refractory material, such as W, Ti, TiN, Ta, TaN or combinations of layers thereof is formed on all exposed surfaces of substrate 100 including sidewalls of through via opening 165 surfaces of first dielectric layer 105 and stud contacts 140B exposed in the bottom of through via opening 165. Then a second conformal and electrically conductive layer 175 is formed in direct physical and electrical contact with exposed surfaces of first conductive layer 170 to form a through via 165A. In one example second conductive layer 175 comprises copper. In one example, first conductive layer 170 is between about 10 nm and about 200 nm thick. In one example, second conductive layer 175 is between about 500 nm and about 10000 nm thick. In one example, the resistance through via 165A is about 0.002 ohm per 10,000 square microns. Thus, a short, low resistance and low inductance path has been created from second conductive layer 175, through first conductive layer 170, stud contacts 140B, damascene wire 145 and stud contact 140A to HBT 130; and all structures wired with through vias are shorted together. In one example, the method terminates at this point so all stud contacts are electrically shorted together. In one example, the methods continues with FIG. 1E.
  • [0037]
    In FIG. 1E, an optional backside chemical-mechanical-polish (CMP) is performed to remove any of first and second conductive layers 170 and 175 from the backside of substrate 100, leaving first and second conductive layers 170 and 175 only within via opening 165.
  • [0038]
    FIGS. 1F through 1E are cross-sectional drawings illustrating variations of backside interconnect structures according to the first embodiment of the present invention. FIG. 1F is similar to FIG. 1E, except an optional dielectric spacer 180 has been formed on sidewalls 185 of through via 165 so a through via 165B is electrically isolated from substrate 100. (Through via 165A of FIGS. 1D and 1E is shorted to substrate 100). Dielectric spacers 180 may be formed, for example, by deposition of a conformal dielectric material followed by a RIE as is well known in the art. In one example, dielectric spacer 180 is SiO2 and is between about 100 nm and about 2500 nm thick and it is deposited using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process, such as liquid phase CVD (LPCVD) SiO2, plasma enhanced CVD (PECVD) SiO2, or ALD SiO2.
  • [0039]
    FIG. 1G is similar to FIG. 1F, except substrate 100 is an SOI substrate having a buried oxide layer (BOX) 190 between the bulk of the substrate and a thin silicon layer 195. In one example, silicon layer 195 is about 30 nm thick. Again, dielectric spacers 180 are optional, as is the CMP step used to remove the first and second conductive layers 170 and 175 from the backside surface of substrate 100.
  • [0040]
    FIG. 1H is similar to FIG. 1F, except substrate 100 includes an embedded alignment mark 200 which is exposed during the processing illustrated in FIG. 1A and described supra. For example, a narrow trench (e.g. 3 um wide) could be lithographically patterned and etched from the substrate front side to a depth equal to or deeper than the thickness of layer 100 in FIG. 1B prior to the deposition of dielectric layer 105 and filled with SiO2. The SiO2 could be deposited using any known method, such as LPCVD, and would be planarized as described supra. Since alignment mark 200 is exposed prior to photoresist application during substrate 100 back side removal, an IR alignment system is not required. In one example alignment mark 200 comprises SiO2. This variation of the first embodiment of the present invention may also use SOI substrates.
  • [0041]
    FIGS. 2A through 2E are cross-sectional drawings illustrating fabrication of a backside interconnect structure according to a second embodiment of the present invention. In FIG. 2A, formed on a lightly doped P-type (P−) substrate 205 is a patterned photoresist layer 210. In one example, substrate 205 is a bulk 100 silicon substrate. A first boron ion implant is performed forming highly P-type doped (P+) regions 215 and 220 in substrate 205. In one example, substrate 205 has a resistivity between about 10 ohm-cm and about 500 ohm-cm. In one example, the first boron ion implant dose is between about 1E15 atoms/cm2 and about 1E16 atoms/cm2 at an energy of between about 3 KeV and about 30 KeV.
  • [0042]
    In FIG. 2B, photoresist layer 210 (see FIG. 2A) is removed and an optional anneal is performed to activate and diffuse the dopants (e.g. about 800 to about 1100° C. for about 1 to about 60 minutes) and a wet (or dry) oxidation performed to grow an oxide layer 225 over exposed top surface of substrate 205. Because of the higher doping level of regions 215 and 220, oxide layer 225 is thicker over regions 215 and 220 than over the rest of substrate 205 and are recessed into the surface of substrate 205.
  • [0043]
    In FIG. 2C, oxide layer 225 is removed (see FIG. 2B) and a doped P-type epitaxial layer 230 is grown. Steps 221 and 222 are defined in epitaxial layer 230 after removal of oxide layer 225 and step 221 can serve as an alignment mark for the processes illustrated in FIG. 2D and described infra. During epitaxial growth, regions 215 and 220 diffuse into substrate 205 and epitaxial layer 230 to form diffused regions 215A and 220A. In one example epitaxial layer 230 is at least about 20 microns thick and has a resistivity between about 10 ohm-cm and about 500 ohm-cm. In one example, epitaxial layer 230 has boron concentration of between about 1E19 atoms/cm3 and about 1E20 atoms/cm3.
  • [0044]
    In FIG. 2D, a patterned photoresist layer 235 is formed on epitaxial layer 230. A second boron ion implant is performed using conditions similar to the one described supra in reference to FIG. 2A, forming a highly P-type doped region 240 extending into epitaxial later 230. No ion implant is performed into epitaxial layer 230 over diffused region 220A.
  • [0045]
    In FIG. 2E, an anneal in an inert atmosphere is first performed which drive implant regions 240 and 215A (see FIG. 2D) together to form a diffused through via 245. In one example, the anneal is performed for about 6 hours at a temperature of about 1200° C. In one example, the boron doping level of through via 245 is between about 1E18 atoms/cm3 and about 5E18 atoms/cm3. In one example, through via 245 has a resistivity between about 0.005 ohm-cm and about 0.05 ohm-cm. In one example, the resistance of through via 245 is about 0.8 ohm per 10,000 square microns. Thus, a short, low resistance and low inductance path has been created from substrate 205, through the through via 245, stud contacts 140B, damascene wire 145 and stud contact 140A to HBT 130. Substrate 205 may be thinned as described supra in reference to the first embodiment of the present invention, however, through vias 245 should not be exposed on the new backside of a thinned substrate 205.
  • [0046]
    Afterwards, of additional levels of an integrated circuit are performed fabricated and the exemplary HBT, MOSFET 135, stud contacts 140A, 140B and 140C and other structures illustrated in FIG. 2E and described supra are formed. At least one of the photomasks used to fabricate the additional levels may be aligned to step 221 (see FIG. 2C).
  • [0047]
    FIGS. 3A1 through 3A5 are cross-sectional drawings illustrating fabrication of a backside interconnect structure according to a first variation of a third embodiment of the present invention. In FIG. 3A 1 , a shallow trench isolation (STI) 250 dielectric is formed between HBT 130 and MOSFET 135. Alternatively, STI 250 may be replaced with a thick field oxide such as a recessed oxidation (ROX) layer. STI 250 extends from the top surface of substrate 100 a fixed depth into the substrate. If substrate 100 is an SOI substrate, then STI 250 may contact the BOX layer which is, for example, about 0.03 microns below the top surface of the substrate. In one example, STI comprises SiO2. Alternatively, any known method in the art to form isolation oxide, such as ROX, could be employed.
  • [0048]
    In FIG. 3A 1, openings 265A and 265B have been formed through first dielectric layer 105 using a photolithographic process. Dielectric layer 105 can be composed of multiple layers, such as one of the group comprising a thin layer of Si3N4, SiC and SiCN in contact with substrate and one of the group comprising a thick layer of SiO2, PSG, BPSG and SiCOH for the balance of the layer.
  • [0049]
    Opening 265A is aligned over the emitter of HBT 130, openings 265B are aligned over STI 250 and opening 265C over the gate of MOSFET 135. An optional silicide layer (not shown) has been previously formed (prior to formation of dielectric layer 105) on the emitter of HBT 130 the gate of FET 265C exposed in opening 265C. An optional silicide layer (not shown) was also formed over the base and collector of HBT 130, the source and drain of MOSFET 135, contacts to substrate 100, and other structures that requiring ohmic contact. Examples of metal suicides include but is not limited to titanium, cobalt, and nickel silicide. Silicides are usually formed using a self-aligned selective process by deposition of a metal on a silicon surface, heating to between about 400° C. and about 900° C. (in one example, heating to about 600° C.) and etching away the unreacted metal; or other processes, such as polycide with lithographic patterning and RIE or wet etching, can be used.
  • [0050]
    In FIG. 3A 2, openings 265C have been formed through first dielectric layer 105, STI 250 and into substrate 100 using a photolithographic process. Openings 265C have a width W1 and extend depth D1 into substrate 100. In one example, W1 is about 3 microns and D1 is a least about 140 microns. In one example, the total bottom surface area of all openings 265C is about 100 square microns. In one example, openings 265C are etched into substrate 100 using a Bosch RIE process. In a Bosch RIE process, the chemistry is switched between a silicon etch chemistry and a polymer depositing chemistry every few seconds allowing for the formation of high aspect ratio (Depth/Width) openings. Because the openings 265B are relatively small and have very high post etch aspect ratio (about 50:1 as defined as height:width), the silicon etch process should have low undercut of STI 250, substantially vertical sidewalls (e.g. minimal scalloping of the via sidewalls, minimal barreling out of the via sidewalls, and about 90 degree etch angle). To enable the vias to be exposed during subsequent wafer backside removal, the via etch deep needs to have good uniformity. To enable the via to be metallized without excessive wafer bending, the via size needs to be minimized. The data in Table I show acceptable and exemplary values for these parameters.
    TABLE I
    Parameter Acceptable Exemplary
    Via nominal width  5 um  2 um
    Via average depth 100 um 200 um
    Via depth variation +/−10% +/−1%
    Via etch undercut of dielectric <0.5 um <0.05 um
    Via scalloping minimum to maximum <0.5 um <0.05 um
    Via barreling minimum to maximum <0.5 um <0.05 um
    Via angle 90 +/− 0.5 90 +/− 0.05
  • [0051]
    In FIG. 3A 3, upper dielectric layer 107 is removed by a blanket etch and an optional clean performed, for example, a 500:1 BHF flowed by Huang A and B cleans. Then openings 265A, 265B and 265C (see FIG. 3A 2) are filled simultaneously using either a fill process illustrated in FIGS. 4A1, through 4A3 or a fill process illustrated in FIGS. 4C1 through 4C4 and described infra to form stud contacts 270A and 270B and through vias 270C. Since stud contacts 270A and 270B contact devices (i.e. HBT 130 and MOSFET 135), stud contacts 270A and 270B may be called device contacts to distinguish them from through vias 270C.
  • [0052]
    In FIG. 3A 4, normal integrated circuit fabrication is performed and the exemplary dielectric layers 110, 115, 120 and 125, damascene wires 145 and 150, dual damascene wire/via 155 and dual-damascene wirebond pad/vias 160A and 160B are formed.
  • [0053]
    In FIG. 3A 5, substrate 100 is thinned to a thickness T2. in order to expose through vias 270C. In one example T1 is between about 100 microns and about 150 microns. Thinning may be accomplished by backside grinding, wet etching or combinations thereof. Examples of suitable wet etchants include, but are not limited to aqueous tetrametylammonium hydroxide (TMAH), alcoholic potassium hydroxide (KOH) and other aqueous/alcoholic base solutions.
  • [0054]
    In one example, the resistance through vias 265C is about 0.003 ohm per 10,000 square microns. Thus, a short, low resistance and low inductance path has been created from the backside of substrate 100, through the through vias 270C, damascene wire 145 and stud contact 140A to HBT 130.
  • [0055]
    FIGS. 3B1 through 3B3 are cross-sectional drawings illustrating fabrication of a backside interconnect structure according to a second variation of the third embodiment of the present invention. Except for the fact, that in the second variation of the third embodiment of the present invention, stud contacts are completely formed first and then through vias, the second variation of the third embodiment of the present invention is similar to the first variation.
  • [0056]
    In FIG. 3B 1, openings 265A and 265B are formed in first dielectric layer 105. In FIG. 3B 2 openings 265A and 265B (see FIG. 3B 1) are filled to form stud contacts 270A and 270B, In one example stud contacts 270A and 270B comprise a core conductor of W surrounded by a liner on the sidewalls and bottom of the core conductor, the liner comprising Ti, TiN or combinations of layers thereof. In FIG. 3B 3, through vias 270C are formed by forming openings through first dielectric layer 105, through STI 250, and into substrate 100. Then upper dielectric layer 107 (see FIG. 3B 2) is removed by a blanket etch and an optional clean performed, for example, a 500:1 BHF flowed by Huang A and B cleans. Then the openings are filled using either a fill process illustrated in FIGS. 4A1, through 4A3, a fill process illustrated in FIGS. 4B1 through 4B4, a fill process illustrated in FIGS. 4C1 through 4C4 or a fill process illustrated in FIGS. 4D1 through 4D5 and described infra to form stud contacts 270A and 270B and through vias 270C. The processes illustrated in FIGS. 3A4 and 3A5 and described supra are next performed.
  • [0057]
    FIGS. 3C1 through 3C3 are cross-sectional drawings illustrating fabrication of a backside interconnect structure according to a third variation of the third embodiment of the present invention. Except for the fact that in the third variation of the third embodiment of the present invention stud contacts are not formed until after the through vias, the third variation of the third embodiment of the present invention is similar to the first variation.
  • [0058]
    In FIG. 3C 1, through vias 270C are formed by etching openings through dielectric layer 105, through STI 250 and into substrate 100 as described supra in reference to the first variation of the third embodiment of the present invention. Then the openings are filled using either a fill process illustrated in FIGS. 4A1, through 4A3, a fill process illustrated in FIGS. 4B1 through 4B4, a fill process illustrated in FIGS. 4C1 through 4C4 or a fill process illustrated in FIGS. 4D1 through 4D5 and described infra to form through vias 270C. In FIG. 3C 2, openings 265A and 265C are formed in first dielectric layer 105. In FIG. 3C 3, upper dielectric layer 107 (see FIG. 3C 2) is removed by a blanket etch and an optional clean performed, for example, a 500:1 BHF flowed by Huang A and B cleans. Then openings 265A and 265C (see FIG. 3C 2) are filled to form stud contacts 270A and 270B. In one example stud contacts 270A and 270B comprise a core conductor of W surrounded by a liner on the sidewalls and bottom of the core conductor, the liner comprising Ti, TiN or combinations of layers thereof. The processes illustrated in FIGS. 3A4 and 3A5 and described supra are next performed.
  • [0059]
    Again, substrate 100 may be an SOI substrate for any of the three variations of the third embodiment of the present invention.
  • [0060]
    In the following four methods of filling a through via/and or a stud contact depending upon the variation of the third embodiment of the present invention that is being practiced, only an exemplary through via will be illustrated.
  • [0061]
    FIGS. 4A1 through 4A3 are cross-sectional drawings illustrating a first method of filling a through via or stud contact of the third embodiment of the present invention. In FIG. 4A 1, opening 265C is cleaned using, for example, buffered hydrofluoric acid (BHF) and Huang A and B wet cleans. Then an optional conformal insulating layer 275 is formed on the sidewalls and bottom of openings 265C. Insulating layer 275 may be formed by thermally oxidizing the exposed silicon surface or by depositing a dielectric film using LPCVD or deposited using an ALD SiO2 process. An important property of optional insulating layer 275 is that it have close to 100% conformality (e.g. it covers the via sidewalls and bottoms with enough film to electrically insulate the via from the substrate). Insulating layer 275 is used only when is desirable to electrically isolate the through via from substrate 100. Then a conformal conductive liner 280 comprising one or more layers of TiN formed by chemical vapor deposition (CVD), separated by hydrogen plasma densification steps as known in the art, is formed over insulating layer 275, if present or on sidewalls and bottom of opening 265C if there is no insulating layer.
  • [0062]
    In FIG. 4A 2, a metal organic CVD (MOCVD) W deposition from tungsten hexa-fluoride (WF6) is performed to form a tungsten layer 285 over liner 280 and to fill opening 265B. Tungsten layer 285 overfills opening 265C. Tungsten layer 285 needs to have good sidewall coverage and minimal bread loafing (the notch in the top of tungsten layer 285) during the portion of the deposition when the through via is being filled and low stress during the overburden portion of the deposition. Optimal W sidewall coverage is achieved by depositing the film at relatively low temperature (e.g. about 350° C. to about −400° C.) and in a WF6 saturated (e.g. high WF6 flow) regime, which results in a high tensile stress. To reduce stress and wafer (substrate) bending, it is advantageous to perform the overburden portion of the W deposition using a minimal WF6 flow, in a WF6 starved regime, or performing the deposition at a maximum possible temperature (e.g. about 418° C. to about 450° C.) or both. In order to reduce attack of silicon by WF6 it is advantageous to mix silane (SiH4) or diborane (B2H6) with the WF6 as known in the art (e.g. silane or diborane CVD W nucleation).
  • [0063]
    In FIG. 4A 3 a CMP is performed, coplanizing the top surfaces of first dielectric layer 105 and through vias 270C. Alternatively, excess W may be removed by a wet etch using, for example, aqueous hydrogen peroxide (H2O2) followed by a CMP.
  • [0064]
    FIGS. 4B1 through 4B4 are cross-sectional drawings illustrating a second method of filling a through via or stud contact of the third embodiment of the present invention. In FIG. 4B 1, opening 265C is cleaned using, for example, buffered hydrofluoric acid (BHF) and Huang A and B wet cleans. Then optional insulating layer 275 is formed on the sidewalls and bottom of openings 265C, as discussed supra.
  • [0065]
    In FIG. 4B 2, a conformal polysilicon layer 290 is formed over insulating layer 275, if present or on sidewalls and bottom of opening 265C if there is no insulating layer. If silicide is present under the stud contacts, then the LPCVD poly-silicon temperature should be held to no higher than about 620° C. for CoSi and about 800° C. for TiSi in order to avoid degradation of the silicide.
  • [0066]
    In FIG. 4B 3, liner 280 comprising TiN (described supra) is formed over polysilicon layer 290 and tungsten layer 285 formed over liner 280 to overfill opening 265C. In order to reduce stress and wafer (substrate) bending, it is advantageous to perform the W overburden deposition using a minimal WF6 flow or performing the deposition at a maximum possible temperature or both, as described supra.
  • [0067]
    In FIG. 4B 4 a CMP is performed, coplanizing the top surfaces of first dielectric layer 105 and through vias 270C.
  • [0068]
    FIGS. 4C1 through 4C4 are cross-sectional drawings illustrating a third method of filling a through via or stud contact of the third embodiment of the present invention. In FIG. 4C 1, opening 265C is cleaned using, for example, buffered hydrofluoric acid (BHF) and Huang A and B wet cleans. Then optional insulating layer 275 is formed on the sidewalls and bottom of opening 265C, as discussed supra.
  • [0069]
    In FIG. 4C 2, liner 280 comprising TiN (described supra) is formed over insulating layer 275, if present or on sidewalls and bottom of opening 265C if there is no insulating layer. Then a conformal tungsten layer 300 is formed over liner 280.
  • [0070]
    In FIG. 4C 3, a dielectric layer 300, such as SiO2, which overfills openings 265B tungsten layer 285. In one example, oxide layer 300 is tetraethoxysilane oxide (TEOS) deposited at 400° C. using PECVD.
  • [0071]
    In FIG. 4C 4, a CMP is performed, coplanizing the top surfaces of first dielectric layer 105 and through vias 270C.
  • [0072]
    FIGS. 4D1 through 4D5 are cross-sectional drawings illustrating a fourth method of filling a through via or stud contact of the third embodiment of the present invention. In FIG. 4D 1, opening 265C is cleaned using, for example, buffered hydrofluoric acid (BHF) and Huang A and B wet cleans. Then optional insulating layer 275 is formed on the sidewalls and bottom of openings 265C, as discussed supra.
  • [0073]
    In FIG. 4D 2, conformal polysilicon layer 290 is formed over insulating layer 275, if present or on sidewalls and bottom of opening 265C if there is no insulating layer. If silicide is present under the stud contacts, then the LPCVD poly-silicon temperature should be held to no higher than about 620° C. for CoSi and about 800° C. for TiSi in order to avoid degradation of the silicide.
  • [0074]
    In FIG. 4D 3, liner 280 comprising TiN (described supra) is formed over polysilicon layer 285 and a conformal tungsten layer 295 is formed over liner 280. In order to reduce stress and wafer (substrate) bending, it is advantageous to perform the W deposition using a minimal WF6 flow or performing the deposition at a maximum possible temperature (see supra) or both. In order to reduce attack of silicon by WF6 it is advantageous to mix diborane (B2H6) with the WF6 as known in the art. In FIG. 4D 4, oxide layer 300 (as described supra) is deposited over tungsten layer 295 which overfills openings 265B. In one example, oxide layer 300 is TEOS.
  • [0075]
    In FIG. 4D 5 a CMP is performed, coplanizing the top surfaces of first dielectric layer 105 and through vias 270C.
  • [0076]
    The first (FIGS. 4A1 through 4A3) and third (FIGS. 4C1 through 4C4) fill processes described supra may be used with the first (FIGS. 3A1-3A5) variation of the third embodiment of the present invention. The first (FIGS. 4A1 through 4A3), second (FIGS. 4B1 through 4B4), third (FIGS. 4C1 through 4C4) and fourth (FIGS. 4D1 through 4D5) fill processes described supra may be used with the second (FIGS. 3B1 through 3B3) and third variations (FIGS. 3B1 through 3B3) of the third embodiment of the present invention.
  • [0077]
    FIGS. 5A and 5B are cross-sectional drawings illustrating fabrication of a backside interconnect structure using alternative substrate according to any of the variations of the third embodiments of the present invention. All three variations of the third embodiment of the present invention can use the alternate substrate described infra. FIGS. 5A and B would replace FIGS. 3A4 and 3A5 respectively.
  • [0078]
    FIG. 5A is similar to FIG. 3A 4 except substrate 100 is replaced with a substrate 310 having a buried oxide layer (BOX) 315 between a lower portion 320 and upper portion 325. Upper portion 325 may be mono-crystalline silicon or standard SOI. Lower portion 320 may also be mono-crystalline silicon. In one example, substrate 310 is a bulk silicon substrate in which BOX 315 is formed. In a second example, substrate 310 is a bonded substrate and lower portion 320 and silicon layer 325 are bonded together via buried oxide layer 315. Silicon layer 325 has a thickness T3. In one example T3 is between about 140 micron and about 160 microns and buried oxide layer 315 is between about 0.2 microns and about 5 microns thick. Silicon layer 325 may be an SOI layer, e.g. contain an additional BOX layer about 300 nm below the top surface of silicon layer 325. BOX layer 315 acts as a silicon etch stop as openings 265C (see for example, FIG. 3A 2) are etched so all openings 265C are of uniform depth and relatively uniform width. Through vias 270C are metallized as discussed supra, prior to forming the first wire level 110.
  • [0079]
    In FIG. 5B, substrate 310 is thinned to a thickness T4, removing all of BOX layer 315 (see FIG. 5A) in order to expose through vias 270C. In one example T4 is between about 100 microns and about 150 microns. Thinning may be accomplished by backside grinding, wet etching or combinations thereof. Examples of suitable wet etchants include, but are not limited to aqueous tetrametylammonium hydroxide (TMAH), alcoholic potassium hydroxide (KOH) and other aqueous/alcoholic base solutions.
  • [0080]
    FIGS. 6A and 6B are cross-sectional drawings illustrating fabrication of a backside interconnect structure according to a fourth embodiment of the present invention. The fourth embodiment of the present invention is similar to the third embodiments except for the use of a different substrate and the fact that the through vias 270C (see FIG. 6B) are not exposed on the backside of the substrate. All three variations of the third embodiment of the present invention to form stud contacts and through vias as well as any of the four fill methods may be practiced in conjunction with the fourth embodiment of the present invention. FIGS. 6A and 6B would replace FIGS. 3A4 and 3A5 respectively.
  • [0081]
    FIG. 6A is similar to FIG. 3A 4 except substrate 100 is replaced with a substrate 600 comprising a upper substrate 605 having a thickness T5. Upper substrate 605 is either bonded to lower substrate 610, or is formed using the process illustrated in FIGS. 2B and 2C and supra. Upper substrate is lightly P-type doped relative to more highly P-type doped lower substrate 610. In a first example, both upper and lower substrates 605 and 610 are bulk silicon substrates. In a second example, upper substrate 605 is an SOI substrate and lower substrate 610 is a bulk silicon substrate. Upper 605 may be formed from a thinned SOI substrate or a BOX layer may be formed in the upper substrate after bonding. Through vias physically and electrically contact lower substrate 610 and may be slightly embedded into lower substrate 610. In one example lower 610 has a resistivity between about 0.005 ohm-cm and about 0.05 ohm cm. In one example upper substrate 605 has a resistivity between about 10 ohm-cm and about 500 ohm cm. In one example T5 is between about 40 microns and about 100 microns.
  • [0082]
    In FIG. 6B, lower substrate 610 (see FIG. 6A) is thinned by backside grinding, wet etching or combinations thereof, to form thinned lower substrate 610 having a thickness T6. In one example T6 is between about 50 microns and about 100 microns. In one example the combined resistance of thinned lower substrate 610A and through vias 270C is less than about 0.4 ohms per 10,000 square microns.
  • [0083]
    FIG. 7 is a cross-sectional view of an exemplary hetero-junction bipolar transistor having a backside connection to a substrate. In FIG. 7, a HBT 700 includes, formed in a substrate 705, a subcollector 710 formed in an N-well 715 surrounded by deep trench isolation 720 and contacted by reach throughs 725, and STI 730. HBT 700 also includes, formed on top of substrate 705, a P type low-temperature epitaxial (LTE) base 735, a P type polysilicon base 740, an N type mono-crystalline emitter 745 and a polysilicon emitter 750. LTE base 735 may comprise SiGe or SiGeC. SiGe (and SiGeC) bipolar transistors are examples of hetero-junction bipolar transistors. Mono-crystalline emitter 745 is formed from a portion of polysilicon emitter 750 that is in direct physical contact with LTE base 735. Likewise LTE base 735 is formed from that portion of polysilicon base 740 in direct physical contact with N-well 720.
  • [0084]
    Formed in a first dielectric layer 755 is a stud contact 760 in physical and electrical contact with polysilicon emitter 750. There may be a layer of metal silicide between stud contact 760 and polysilicon emitter 750. Also formed in first dielectric layer 755 is a though via 765 extending into/through substrate 705 according to any of the various embodiments of the present invention. Formed in a second dielectric layer 770 is a damascene wire 775. Damascene wire 770 is in direct physical and electrical contact with stud contact 755 and through via 765, thus providing an electrical path from the emitter of HBT 700 to the backside of substrate 705. The connection to the emitter of HBT 700 should be considered exemplary and connections may be made to the base or collector reach throughs. A third dielectric layer 780 is formed on top of second dielectric layer 770 and wire 775. Additional dielectric layers and wiring layers may be formed as required.
  • [0085]
    Thus, the various embodiments of the present invention provide interconnect structures and methods of fabricating interconnect structures with reduced inductance and resistance for connecting signals to circuit elements of integrated circuits.
  • [0086]
    The description of the embodiments of the present invention is given above for the understanding of the present invention. It will be understood that the invention is not limited to the particular embodiments described herein, but is capable of various modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, it is intended that the following claims cover all such modifications and changes as fall within the true spirit and scope of the invention.

Claims (55)

  1. 1. A method for forming a contact, comprising:
    forming a dielectric isolation in a substrate, said substrate having a frontside and an opposing backside;
    forming a first dielectric layer on said frontside of said substrate;
    forming a shallow trench in said first dielectric layer, said trench aligned over and within a perimeter of said trench isolation and extending to said dielectric isolation;
    extending said trench formed in said first dielectric layer through said dielectric isolation and into said substrate to a depth less than a thickness of said substrate;
    filling said trench and co-planarizing a top surface of said trench with a top surface of said first dielectric layer to form an electrically conductive through via; and
    thinning said substrate from said backside of said substrate to expose said through via.
  2. 2. The method of claim 1, further including:
    forming a device contact opening in said first dielectric layer and simultaneously with said filling said trench and co-planarizing, filling said device contact opening and co-planarizing a top surface of said filled device contact opening with a top surface of said first dielectric layer to form an electrically conductive device contact.
  3. 3. The method of claim 1, further including:
    before forming said through via, forming a device contact opening in said first dielectric layer, filling said device contact opening and co-planarizing a top surface of said filled device contact opening with a top surface of said first dielectric layer to form an electrically conductive device contact.
  4. 4. The method of claim 1, further including:
    after forming said through via, forming a device contact opening in said first dielectric layer, filling said device contact opening and co-planarizing a top surface of said filled device contact opening with a top surface of said first dielectric layer to form an electrically conductive device contact.
  5. 5. The method of claim 1, wherein said filling said trench includes:
    either forming a insulating layer on sidewalls and a bottom of said trench and forming a tungsten layer over said insulating layer, said tungsten layer of sufficient thickness to fill said trench; or
    forming said tungsten layer on said sidewalls and said bottom of said trench, said tungsten layer of sufficient thickness to fill said trench.
  6. 6. The method of claim 1, wherein said filling said trench includes:
    either forming a insulating layer on sidewalls and a bottom of said trench, forming a conformal polysilicon layer over said insulating layer, and forming a tungsten layer over said polysilicon layer, said tungsten layer of sufficient thickness to fill said trench; or
    forming said insulating layer on said sidewalls and said bottom of said trench; and forming a tungsten layer over said polysilicon layer, said tungsten layer of sufficient thickness to fill said trench.
  7. 7. The method of claim 1, wherein said filling said trench includes:
    either forming a insulating layer on sidewalls and a bottom of said trench; forming a conformal tungsten layer over said insulating layer, and
    forming an oxide layer over said tungsten layer, said oxide layer of sufficient thickness to fill said trench; or
    forming a conformal tungsten layer on said sidewalls and said bottom of said trench, and forming an oxide layer over said tungsten layer, said oxide layer of sufficient thickness to fill said trench.
  8. 8. The method of claim 1, wherein said filling said trench includes:
    either forming a insulating layer on sidewalls and a bottom of said trench, forming a conformal polysilicon layer over said insulating layer, forming a conformal tungsten layer over said polysilicon layer, and forming an oxide layer over said tungsten layer, said oxide layer of sufficient thickness to fill said trench; or
    forming a conformal polysilicon layer on said sidewalls and said bottom of said trench, forming a conformal tungsten layer over said polysilicon layer, and forming an oxide layer over said tungsten layer, said oxide layer of sufficient thickness to fill said trench.
  9. 9. The method of claim 1, further including:
    forming a hetero-junction bipolar transistor on an in said substrate;
    forming a device contact in said first dielectric layer, said device contact in physical and electrical contact to an emitter of said hetero-junction bipolar transistor; and
    forming a wire in a second dielectric layer, said second dielectric layer formed over said first dielectric layer and said wire in direct physical and electrical contact with said device contact and said through via.
  10. 10. The method of claim 1, wherein said trench extends to and contacts a buried oxide layer in said substrate and said thinning said substrate removes said buried oxide layer.
  11. 11. A structure, comprising:
    a dielectric isolation in a substrate, said substrate having a frontside and an opposing backside;
    a first dielectric layer on said frontside of said substrate; and
    an electrically conductive through via extending through said first dielectric layer, said dielectric isolation and said substrate exposed on said backside of said substrate.
  12. 12. The structure of claim 11, further including:
    a device contact extending through said first dielectric layer and electrically contacting a device formed in said substrate, in said first dielectric layer or both in said substrate and in said first dielectric layer.
  13. 13. The structure of claim 12, wherein said device contact and said through via both comprise layers of the same materials, said layers of the same materials layered upon each other in the same sequence.
  14. 14. The structure of claim 12, wherein said through via include a insulating layer on sidewalls of said through via, said insulating layer comprising TiN or hydrogen rich silicon.
  15. 15. The structure of claim 11, wherein said through via comprises either:
    a tungsten core and a titanium nitride liner on sidewalls and a bottom of said tungsten core; or
    said a tungsten core, a titanium nitride liner on said sidewalls and said bottom of said tungsten core and an insulating layer on said titanium nitride liner.
  16. 16. The structure of claim 11, wherein said through via comprises either:
    a tungsten core, a titanium nitride liner on sidewalls and a bottom of said tungsten core, a polysilicon layer on said titanium nitride liner; or
    said tungsten core, said titanium nitride liner on said sidewalls and said bottom of said tungsten core, said polysilicon layer on said titanium nitride liner and an insulating layer on said polysilicon layer.
  17. 17. The structure of claim 11, wherein said through via comprises either:
    an oxide core, a tungsten liner on sidewalls and a bottom of said oxide core, a titanium nitride liner on said tungsten liner; or
    said oxide core, said tungsten liner on said sidewalls and said bottom of said oxide core, said titanium nitride liner on said tungsten liner and an insulating layer on said titanium nitride liner.
  18. 18. The structure of claim 11, wherein said through via comprises either:
    an oxide core, a tungsten layer on sidewalls and a bottom of said oxide core, a polysilicon layer on said tungsten layer or;
    said oxide core, said tungsten layer on said sidewalls and said bottom of said oxide core, said polysilicon layer on said tungsten layer and an insulating layer on said polysilicon layer.
  19. 19. The structure of claim 11, further including:
    a hetero-junction bipolar transistor formed on and in said substrate;
    a device contact in said first dielectric layer, said device contact in physical and electrical contact to an emitter of said hetero-junction bipolar transistor; and
    a wire in a second dielectric layer, said second dielectric layer formed over said first dielectric layer and said wire in direct physical and electrical contact with said device contact and said through via.
  20. 20. A method for forming a contact, comprising:
    forming a first dielectric layer on a frontside of a substrate, said substrate having a backside opposing said frontside;
    forming an electrically conductive first stud contact in said first dielectric layer, said first stud contact extending through said first dielectric layer to said frontside of said substrate;
    thinning said substrate from said backside of said substrate to form a new backside of said substrate;
    forming a trench in said substrate, said trench extending from said new backside of said substrate to said first dielectric layer, a bottom surface of said first stud contact exposed in said trench; and
    forming a conformal electrically conductive layer on said new backside of said substrate, sidewalls of said trench, exposed surfaces of said first dielectric layer and exposed surfaces of said first stud contacts, said conductive layer not thick enough to completely fill said trench.
  21. 21. The method of claim 20, further including, removing said conductive layer from said new backside of said substrate.
  22. 22. The method of claim 20, further including:
    before said forming a conformal electrically conductive layer, forming a conformal dielectric layer on said sidewalls of said trench.
  23. 23. The method of claim 20, wherein said conformal electrically conductive layer comprises a first layer comprising copper over a second layer comprising a layer of W, a layer of Ti, a layer TiN, a layer of Ta, a layer of TaN or combinations thereof.
  24. 24. The method of claim 20, further including:
    forming a hetero-junction bipolar transistor on and in said substrate;
    forming a second stud contact in said first dielectric layer, said second stud contact in physical and electrical contact with an emitter of said hetero-junction bipolar transistor; and
    forming a wire in a second dielectric layer, said second dielectric layer formed over said first dielectric layer and said wire in direct physical and electrical contact with said first and second stud contacts.
  25. 25. A structure, comprising:
    a first dielectric layer on a frontside of a substrate, said substrate having a backside opposing said frontside;
    an electrically conductive first stud contact in said first dielectric layer, said first stud contact extending through said first dielectric layer to said frontside of said substrate;
    a trench in said substrate, said trench extending from said backside of said substrate to said first dielectric layer, a bottom surface of said first stud contact exposed in said trench; and
    a conformal electrically conductive layer over sidewalls of said trench, and on exposed surfaces of said first dielectric layer and exposed surfaces of said first stud contacts, said conductive layer not thick enough to completely fill said trench.
  26. 26. The structure of claim 25, further including, wherein said conductive layer extends over said backside of said substrate.
  27. 27. The structure of claim 25, further including:
    a conformal dielectric layer between said on said sidewalls of said trench and said conductive layer.
  28. 28. The structure of claim 25, wherein said conformal electrically conductive layer comprises a first layer comprising copper over a second layer comprising a layer of W, a layer of Ti, a layer TiN, a layer of Ta, a layer of TaN or combinations thereof.
  29. 29. The structure of claim 20, further including:
    a hetero-junction bipolar transistor formed on and in said substrate;
    a second stud contact in said first dielectric layer, said second stud contact in physical and electrical contact with an emitter of said hetero-junction bipolar transistor; and
    a wire in a second dielectric layer, said second dielectric layer formed over said first dielectric layer, said wire in direct physical and electrical contact with said first and second stud contacts.
  30. 30. A method for forming a contact, comprising:
    performing a first ion implantation into a region of a frontside of substrate to form a first doped region in said substrate, said substrate having a backside opposing said frontside;
    growing an epitaxial layer on said frontside of said substrate;
    performing a second ion implantation into a region of a said epitaxial layer to form a second doped region in said epitaxial later, said second doped region aligned over at least a portion of said first doped region; and
    heating said substrate and epitaxial layer in order to convert said first and second doped regions into a continuous diffused through via extending from a top surface of said epitaxial layer into said substrate.
  31. 31. The method of claim 30, further including:
    between said first and second ion implantations, growing an oxide layer on said substrate and then removing said oxide layer.
  32. 32. The method of claim 30, wherein:
    said substrate is doped P-type and has a resistivity between about 10 ohm-cm and about 500 ohm-cm;
    said epitaxial layer is doped is doped P-type and has a resistivity between about 10 ohm-cm and about 500 ohm-cm; and
    said through via is doped P-type and has a resistivity between about 0.005 ohm-cm and about 0.05 ohm-cm.
  33. 33. The method of claim 30, wherein said epitaxial layer is at least about 40 microns thick.
  34. 34. The method of claim 30, further including:
    forming a hetero-junction bipolar transistor on and in said substrate;
    forming a first dielectric layer on said top surface of said epitaxial layer;
    forming a first stud contact in said first dielectric layer, said first stud contact in physical and electrical contact with said diffused through via;
    forming a second stud contact in said first dielectric layer, said second stud contact in physical and electrical contact with an emitter of said hetero-junction bipolar transistor; and
    forming a wire in a second dielectric layer, said second dielectric layer formed over said first dielectric layer and said wire in direct physical and electrical contact with said first and second stud contacts.
  35. 35. The method of claim 30, further including:
    simultaneously with performing said first ion implantation into said region of a frontside of substrate to form said first doped region in said substrate, performing said first ion implantation into said substrate in an additional doped region of said frontside of substrate to form a second first doped region in said substrate and wherein after said growing said epitaxial layer on said frontside of said substrate, a depression is formed in a top surface of said epitaxial layer over said additional doped region.
  36. 36. The method of claim 35, further including:
    aligning a photomask to said depression.
  37. 37. A method for forming a contact, comprising:
    forming a dielectric isolation in an upper substrate, a bottom surface of said upper substrate bonded to a top surface of a lower substrate, said lower substrate doped to a first concentration and said upper substrate doped to a second concentration, said second concentration greater than said first concentration;
    forming a first dielectric layer on a top surface of said upper substrate;
    forming a trench in said first dielectric layer, said trench aligned over and within a perimeter of said dielectric isolation and extending to said dielectric isolation;
    extending said trench formed in said first dielectric layer through said dielectric isolation and into and through said upper substrate to or into said lower substrate a distance less than a first thickness of said lower substrate;
    filling said trench and co-planarizing a top surface of said trench with a top surface of said first dielectric layer to form an electrically conductive through via; and
    thinning said lower substrate from a bottom surface of said substrate.
  38. 38. The method of claim 37, further including:
    forming a device contact opening in said first dielectric layer and simultaneously with said filling said trench and co-planarizing, filling said device contact openings and co-planarizing a top surface of said filled contact opening with a top surface of said first dielectric layer to form an electrically conductive device contact.
  39. 39. The method of claim 37, further including:
    before forming said through via, forming a device contact opening in said first dielectric layer, filling said device contact opening and co-planarizing a top surface of said filled device contact opening with a top surface of said first dielectric layer to form an electrically conductive device contact.
  40. 40. The method of claim 37, further including:
    after forming said through via, forming a device contact opening in said first dielectric layer, filling said device contact opening and co-planarizing a top surface of said device contact opening with a top surface of said first dielectric layer to form an electrically conductive device contact.
  41. 41. The method of claim 37, wherein said filling said trench includes:
    forming a insulating layer on sidewalls and a bottom of said trench; and
    forming a tungsten layer over said insulating layer, said tungsten layer of sufficient thickness to fill said trench.
  42. 42. The method of claim 37, wherein said filling said trench includes:
    forming a insulating layer on sidewalls and a bottom of said trench;
    forming a conformal polysilicon layer over said insulating layer; and
    forming a tungsten layer over said polysilicon layer, said tungsten layer of sufficient thickness to fill said trench.
  43. 43. The method of claim 37, wherein said filling said trench includes:
    forming a insulating layer on sidewalls and a bottom of said trench;
    forming a conformal tungsten layer over said insulating layer; and
    forming an oxide layer over said tungsten layer, said oxide layer of sufficient thickness to fill said trench.
  44. 44. The method of claim 37, wherein said filling said trench includes:
    forming a insulating layer on sidewalls and a bottom of said trench;
    forming a conformal polysilicon layer over said insulating layer;
    forming a conformal tungsten layer over said polysilicon layer; and
    forming an oxide layer over said tungsten layer, said oxide layer of sufficient thickness to fill said trench.
  45. 45. The method of claim 37, further including:
    forming a hetero-junction bipolar transistor on and in said upper substrate;
    forming a device contact in said first dielectric layer, said device contact in physical and electrical contact to an emitter of said hetero-junction bipolar transistor; and
    forming a wire in a second dielectric layer, said second dielectric layer formed over said first dielectric layer and said wire in direct physical and electrical contact with said device contact and said through via.
  46. 46. A structure, comprising:
    a dielectric isolation in an upper substrate, a bottom surface of said upper substrate bonded to a top surface of a lower substrate, said lower substrate doped to a first concentration and said upper substrate doped to a second concentration, said second concentration greater than said first concentration;
    a first dielectric layer on a top surface of said upper substrate; and
    an electrically conductive through via extending through said first dielectric layer, said trench isolation and said upper substrate to or into said lower substrate a distance less than a first thickness of said lower substrate.
  47. 47. The structure of claim 46, further including:
    a device contact extending through said first dielectric layer and electrically contacting a device formed in said upper substrate, in said first dielectric layer or both in said upper substrate and in said first dielectric layer.
  48. 48. The structure of claim 47, wherein said device contact and said through via both comprise layers of the same materials, said layers of the same materials layered upon each other in the same sequence.
  49. 49. The structure of claim 47, wherein said through via include a insulating layer on sidewalls of said through via, said insulating layer comprising TiN or hydrogen rich silicon.
  50. 50. The structure of claim 46, wherein said through via comprises:
    a tungsten core; and
    insulating layer on sidewalls of said core.
  51. 51. The structure of claim 46, wherein said through via comprises:
    a tungsten core;
    a polysilicon layer on sidewalls of said tungsten core; and
    a insulating layer on polysilicon layer.
  52. 52. The structure of claim 46, wherein said through via comprises:
    an oxide core;
    a tungsten layer on sidewalls of said oxide core; and
    a insulating layer on tungsten layer.
  53. 53. The structure of claim 46, wherein said through via comprises:
    a oxide core;
    a tungsten layer on sidewalls of said oxide core;
    a polysilicon layer on said tungsten layer; and
    a insulating layer on polysilicon layer.
  54. 54. The structure of claim 46, further including:
    a hetero-junction bipolar transistor formed in and on said upper substrate;
    a device contact in said first dielectric layer, said device contact in physical and electrical contact to an emitter of said hetero-junction bipolar transistor; and
    a wire in a second dielectric layer, said second dielectric layer formed over said first dielectric layer and said wire in direct physical and electrical contact with said device contact and said through via.
  55. 55. The structure of claim 46, wherein said upper substrate has a thickness between about 40 microns and about 100 microns and said lower substrate has a thickness between about 40 microns and about 100 microns.
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Cited By (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090283871A1 (en) * 2008-05-14 2009-11-19 Hung-Pin Chang System, Structure, and Method of Manufacturing a Semiconductor Substrate Stack
US20100029075A1 (en) * 2008-07-29 2010-02-04 Lindgren Peter J Through wafer vias with dishing correction methods
US20100025857A1 (en) * 2008-07-29 2010-02-04 Lindgren Peter J Ic chip and design structure with through wafer vias dishing correction
US20100032764A1 (en) * 2008-08-08 2010-02-11 Paul Stephen Andry Through silicon via and method of fabricating same
US20100032810A1 (en) * 2008-08-08 2010-02-11 Hanyi Ding Through wafer vias and method of making same
WO2010017031A1 (en) * 2008-08-08 2010-02-11 International Business Machines Corporation Through wafer via and method of making same
US20100032811A1 (en) * 2008-08-08 2010-02-11 Hanyi Ding Through wafer vias and method of making same
US20100052108A1 (en) * 2008-08-29 2010-03-04 International Business Machines Corporation Vertical through-silicon via for a semiconductor structure
US20100072620A1 (en) * 2008-09-25 2010-03-25 Liang Wang Semiconductor Chip with Backside Conductor Structure
US20100084747A1 (en) * 2008-10-03 2010-04-08 Chih-Hua Chen Zigzag Pattern for TSV Copper Adhesion
US20100140775A1 (en) * 2008-12-10 2010-06-10 Jung Oh Jin Semiconductor device and method for manufacturing the same
US20100155940A1 (en) * 2008-12-19 2010-06-24 Renesas Technology Corp. Semiconductor device and method of manufacturing the same
US20100230760A1 (en) * 2009-03-13 2010-09-16 Cheng-Hui Hung Silicon Wafer Having Interconnection Metal
US20100267217A1 (en) * 2009-04-20 2010-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Backside Process for a Substrate
US20100308444A1 (en) * 2009-06-04 2010-12-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of Manufacturing an Electronic Device
US20100330740A1 (en) * 2007-03-27 2010-12-30 David Pratt Method and apparatus providing integrated circuit having redistribution layer with recessed connectors
US7863644B1 (en) * 2007-04-09 2011-01-04 National Semiconductor Corporation Bipolar transistor and method of forming the bipolar transistor with a backside contact
US20110037096A1 (en) * 2009-08-11 2011-02-17 International Business Machines Corporation Heterojunction Bipolar Transistors and Methods of Manufacture
US20110089572A1 (en) * 2008-03-19 2011-04-21 Imec Method for fabricating through substrate vias
US20110177655A1 (en) * 2007-06-27 2011-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of Through Via before Contact Processing
US20110260297A1 (en) * 2010-04-27 2011-10-27 Shian-Jyh Lin Through-substrate via and fabrication method thereof
US20110300710A1 (en) * 2009-12-14 2011-12-08 Dupont Air Products Nanomaterials, Llc Method for Forming Through-Base Wafer Vias for Fabrication of Stacked Devices
US20120037969A1 (en) * 2010-08-12 2012-02-16 Freescale Semiconductor, Inc. Monolithic microwave integrated circuit
CN102484095A (en) * 2009-08-21 2012-05-30 美光科技公司 Vias and conductive routing layers in semiconductor substrates
US8202766B2 (en) 2009-06-19 2012-06-19 United Microelectronics Corp. Method for fabricating through-silicon via structure
EP2500931A1 (en) * 2009-11-12 2012-09-19 Panasonic Corporation Semiconductor device and method for manufacturing semiconductor device
US8481425B2 (en) 2011-05-16 2013-07-09 United Microelectronics Corp. Method for fabricating through-silicon via structure
US8519515B2 (en) 2011-04-13 2013-08-27 United Microlectronics Corp. TSV structure and method for forming the same
US8518823B2 (en) 2011-12-23 2013-08-27 United Microelectronics Corp. Through silicon via and method of forming the same
US8525296B1 (en) 2012-06-26 2013-09-03 United Microelectronics Corp. Capacitor structure and method of forming the same
US8609529B2 (en) 2012-02-01 2013-12-17 United Microelectronics Corp. Fabrication method and structure of through silicon via
US20130341799A1 (en) * 2012-06-21 2013-12-26 Hsin-Yu Chen Through silicon via structure and method of fabricating the same
US8691688B2 (en) 2012-06-18 2014-04-08 United Microelectronics Corp. Method of manufacturing semiconductor structure
US8691600B2 (en) 2012-05-02 2014-04-08 United Microelectronics Corp. Method for testing through-silicon-via (TSV) structures
US8716104B1 (en) 2012-12-20 2014-05-06 United Microelectronics Corp. Method of fabricating isolation structure
US8822336B2 (en) 2011-06-16 2014-09-02 United Microelectronics Corp. Through-silicon via forming method
US8828745B2 (en) 2011-07-06 2014-09-09 United Microelectronics Corp. Method for manufacturing through-silicon via
WO2014100186A3 (en) * 2012-12-21 2014-09-25 Invensas Corporation Method and structure for carrier-less thin wafer handling
US8884398B2 (en) 2013-04-01 2014-11-11 United Microelectronics Corp. Anti-fuse structure and programming method thereof
US8912844B2 (en) 2012-10-09 2014-12-16 United Microelectronics Corp. Semiconductor structure and method for reducing noise therein
US8916471B1 (en) 2013-08-26 2014-12-23 United Microelectronics Corp. Method for forming semiconductor structure having through silicon via for signal and shielding structure
US8999766B2 (en) 2009-10-23 2015-04-07 Synopsys, Inc. ESD/antenna diodes for through-silicon vias
US9024416B2 (en) 2013-08-12 2015-05-05 United Microelectronics Corp. Semiconductor structure
US9035457B2 (en) 2012-11-29 2015-05-19 United Microelectronics Corp. Substrate with integrated passive devices and method of manufacturing the same
US9048223B2 (en) 2013-09-03 2015-06-02 United Microelectronics Corp. Package structure having silicon through vias connected to ground potential
US9117804B2 (en) 2013-09-13 2015-08-25 United Microelectronics Corporation Interposer structure and manufacturing method thereof
US9123730B2 (en) 2013-07-11 2015-09-01 United Microelectronics Corp. Semiconductor device having through silicon trench shielding structure surrounding RF circuit
US20150249049A1 (en) * 2012-11-15 2015-09-03 Taiwan Semiconductor Manufacturing Company, Ltd. Through-Substrate via Formation with Improved Topography Control
US9275933B2 (en) 2012-06-19 2016-03-01 United Microelectronics Corp. Semiconductor device
US9287173B2 (en) 2013-05-23 2016-03-15 United Microelectronics Corp. Through silicon via and process thereof
US9343359B2 (en) 2013-12-25 2016-05-17 United Microelectronics Corp. Integrated structure and method for fabricating the same
US20170040255A1 (en) * 2013-12-23 2017-02-09 Intel Corporation Through-body-via isolated coaxial capacitor and techniques for forming same
US9685370B2 (en) * 2014-12-18 2017-06-20 Globalfoundries Inc. Titanium tungsten liner used with copper interconnects

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7563714B2 (en) * 2006-01-13 2009-07-21 International Business Machines Corporation Low resistance and inductance backside through vias and methods of fabricating same
JP4585561B2 (en) * 2007-09-04 2010-11-24 株式会社東芝 A method of manufacturing a semiconductor device
JP5239744B2 (en) * 2008-10-27 2013-07-17 ソニー株式会社 Program transmitting device, switcher control method, and computer program
JP4905474B2 (en) * 2009-02-04 2012-03-28 ソニー株式会社 Image processing apparatus, image processing method, and program
JP2010182764A (en) * 2009-02-04 2010-08-19 Sony Corp Semiconductor element, method of manufacturing the same, and electronic apparatus
US9142586B2 (en) * 2009-02-24 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for backside illuminated image sensor
US8531565B2 (en) * 2009-02-24 2013-09-10 Taiwan Semiconductor Manufacturing Company, Ltd. Front side implanted guard ring structure for backside illuminated image sensor
US8664043B2 (en) * 2009-12-01 2014-03-04 Infineon Technologies Ag Method of manufacturing a laminate electronic device including separating a carrier into a plurality of parts
EP2378548A1 (en) * 2010-04-19 2011-10-19 Nanda Technologies GmbH Methods of processing and inspecting semiconductor substrates
CN101872744B (en) * 2010-06-03 2012-12-26 清华大学 Method for producing a compound semiconductor MMIC (Monolithic Microwave Integrated Circuit) chip on silicon substrate
US8535544B2 (en) 2010-07-26 2013-09-17 International Business Machines Corporation Structure and method to form nanopore
US8440532B2 (en) 2010-07-27 2013-05-14 International Business Machines Corporation Structure and method for making metal semiconductor field effect transistor (MOSFET) with isolation last process
KR20120034410A (en) 2010-10-01 2012-04-12 삼성전자주식회사 Semiconductor device and fabrication method thereof
US8853857B2 (en) 2011-05-05 2014-10-07 International Business Machines Corporation 3-D integration using multi stage vias
US20130015504A1 (en) * 2011-07-11 2013-01-17 Chien-Li Kuo Tsv structure and method for forming the same
US8618640B2 (en) * 2011-07-29 2013-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Method of shielding through silicon vias in a passive interposer
US8492272B2 (en) 2011-07-29 2013-07-23 International Business Machines Corporation Passivated through wafer vias in low-doped semiconductor substrates
US20130313614A1 (en) * 2012-05-22 2013-11-28 Tsinghua University METAL SILICIDE SELF-ALIGNED SiGe HETEROJUNCTION BIPOLAR TRANSISTOR AND METHOD OF FORMING THE SAME
CN103811413B (en) * 2012-11-15 2016-06-08 上海华虹宏力半导体制造有限公司 Process for producing a semiconductor substrate
CN103985700B (en) * 2013-02-07 2017-04-12 矽品精密工业股份有限公司 Online configuration of the package member fabrication method thereof
WO2014204620A1 (en) * 2013-06-17 2014-12-24 Applied Materials, Inc. Method for copper plating through silicon vias using wet wafer back contact
JP2016219693A (en) * 2015-05-25 2016-12-22 富士通株式会社 Semiconductor device and manufacturing method of the same
US9455187B1 (en) 2015-06-18 2016-09-27 International Business Machines Corporation Backside device contact
US9673275B2 (en) 2015-10-22 2017-06-06 Qualcomm Incorporated Isolated complementary metal-oxide semiconductor (CMOS) devices for radio-frequency (RF) circuits
US20170194270A1 (en) * 2015-12-31 2017-07-06 International Business Machines Corporation Effective medium semiconductor cavities for rf applications
US20180138171A1 (en) * 2016-11-17 2018-05-17 Taiwan Semiconductor Manufacturing Company Limited Semiconductor Structures and Methods of Forming the Same

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4982266A (en) * 1987-12-23 1991-01-01 Texas Instruments Incorporated Integrated circuit with metal interconnecting layers above and below active circuitry
US5897370A (en) * 1994-08-05 1999-04-27 International Business Machines Corporation High aspect ratio low resistivity lines/vias by surface diffusion
US5965930A (en) * 1997-11-04 1999-10-12 Motorola, Inc. High frequency bipolar transistor and method of forming the same
US6028348A (en) * 1993-11-30 2000-02-22 Texas Instruments Incorporated Low thermal impedance integrated circuit
US6100200A (en) * 1998-12-21 2000-08-08 Advanced Technology Materials, Inc. Sputtering process for the conformal deposition of a metallization or insulating layer
US6127716A (en) * 1998-10-09 2000-10-03 Kabushiki Kaisha Toshiba Heterojunction bipolar transistor and manufacturing method thereof
US20040062116A1 (en) * 2001-12-04 2004-04-01 Yoshinori Takano Semiconductor memory device and current mirror circuit
US20040065980A1 (en) * 2001-09-21 2004-04-08 Masayuki Osaki Method of making moldings
US6916704B2 (en) * 2001-06-12 2005-07-12 Infineon Technologies Ag Multiple deposition of metal layers for the fabrication of an upper capacitor electrode of a trench capacitor
US20050164490A1 (en) * 2003-09-17 2005-07-28 Patrick Morrow Methods of forming backside connections on a wafer stack
US20050253175A1 (en) * 2002-10-31 2005-11-17 Infineon Technologies Ag MOS-transistor on SOI substrate with source via
US7338896B2 (en) * 2004-12-17 2008-03-04 Interuniversitair Microelektronica Centrum (Imec) Formation of deep via airgaps for three dimensional wafer to wafer interconnect

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH065673B2 (en) * 1985-06-10 1994-01-19 日本電信電話株式会社 Semiconductor device and manufacturing method thereof
JPS6468948A (en) * 1987-09-09 1989-03-15 Nec Corp Manufacture of semiconductor device
JPH05152529A (en) * 1991-11-29 1993-06-18 Oki Electric Ind Co Ltd Semiconductor device
KR100260688B1 (en) 1996-12-23 2000-07-01 포만 제프리 엘 Mosfet with raised sti isolation self-aligned to the gate stack
JP2001189321A (en) * 1999-10-21 2001-07-10 Matsushita Electric Ind Co Ltd Horizontal heterobipolar transistor and manufacturing method therefor
JP2001326325A (en) * 2000-05-16 2001-11-22 Seiko Epson Corp Semiconductor device and its manufacturing method
JP3834589B2 (en) * 2001-06-27 2006-10-18 株式会社ルネサステクノロジ A method of manufacturing a semiconductor device
JP4408006B2 (en) * 2001-06-28 2010-02-03 富士通マイクロエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
JP2003023067A (en) * 2001-07-09 2003-01-24 Tokyo Electron Ltd Formation method for via metal layer and via metal layer formed substrate
JP4175134B2 (en) * 2002-05-20 2008-11-05 住友電気工業株式会社 Method for producing a dry etching method and a semiconductor device
US7045877B2 (en) 2002-05-31 2006-05-16 Renesas Technology Corp. Semiconductor protection device
US7132321B2 (en) 2002-10-24 2006-11-07 The United States Of America As Represented By The Secretary Of The Navy Vertical conducting power semiconductor devices implemented by deep etch
JP3696208B2 (en) * 2003-01-22 2005-09-14 株式会社東芝 Semiconductor device
JP2004253722A (en) * 2003-02-21 2004-09-09 Matsushita Electric Ind Co Ltd Bipolar transistor and its manufacturing method
JP4869546B2 (en) * 2003-05-23 2012-02-08 ルネサスエレクトロニクス株式会社 Semiconductor device
JP4439976B2 (en) * 2004-03-31 2010-03-24 Necエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US20060003566A1 (en) * 2004-06-30 2006-01-05 Ismail Emesh Methods and apparatuses for semiconductor fabrication utilizing through-wafer interconnects
US7563714B2 (en) * 2006-01-13 2009-07-21 International Business Machines Corporation Low resistance and inductance backside through vias and methods of fabricating same

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4982266A (en) * 1987-12-23 1991-01-01 Texas Instruments Incorporated Integrated circuit with metal interconnecting layers above and below active circuitry
US6028348A (en) * 1993-11-30 2000-02-22 Texas Instruments Incorporated Low thermal impedance integrated circuit
US5897370A (en) * 1994-08-05 1999-04-27 International Business Machines Corporation High aspect ratio low resistivity lines/vias by surface diffusion
US5965930A (en) * 1997-11-04 1999-10-12 Motorola, Inc. High frequency bipolar transistor and method of forming the same
US6127716A (en) * 1998-10-09 2000-10-03 Kabushiki Kaisha Toshiba Heterojunction bipolar transistor and manufacturing method thereof
US6100200A (en) * 1998-12-21 2000-08-08 Advanced Technology Materials, Inc. Sputtering process for the conformal deposition of a metallization or insulating layer
US6916704B2 (en) * 2001-06-12 2005-07-12 Infineon Technologies Ag Multiple deposition of metal layers for the fabrication of an upper capacitor electrode of a trench capacitor
US20040065980A1 (en) * 2001-09-21 2004-04-08 Masayuki Osaki Method of making moldings
US20040062116A1 (en) * 2001-12-04 2004-04-01 Yoshinori Takano Semiconductor memory device and current mirror circuit
US20050253175A1 (en) * 2002-10-31 2005-11-17 Infineon Technologies Ag MOS-transistor on SOI substrate with source via
US20050164490A1 (en) * 2003-09-17 2005-07-28 Patrick Morrow Methods of forming backside connections on a wafer stack
US7338896B2 (en) * 2004-12-17 2008-03-04 Interuniversitair Microelektronica Centrum (Imec) Formation of deep via airgaps for three dimensional wafer to wafer interconnect

Cited By (110)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7951709B2 (en) * 2007-03-27 2011-05-31 Micron Technology, Inc. Method and apparatus providing integrated circuit having redistribution layer with recessed connectors
US8779605B2 (en) 2007-03-27 2014-07-15 Micron Technology, Inc. Method and apparatus providing integrated circuit having redistribution layer with recessed connectors
US20100330740A1 (en) * 2007-03-27 2010-12-30 David Pratt Method and apparatus providing integrated circuit having redistribution layer with recessed connectors
US9355934B2 (en) 2007-03-27 2016-05-31 Micron Technology, Inc. Method and apparatus providing integrated circuit having redistribution layer with recessed connectors
US20110198759A1 (en) * 2007-03-27 2011-08-18 David Pratt Method and apparatus providing integrated circuit having redistribution layer with recessed connectors
US8274163B2 (en) 2007-03-27 2012-09-25 Micron Technology, Inc. Method and apparatus providing integrated circuit having redistribution layer with recessed connectors
US7863644B1 (en) * 2007-04-09 2011-01-04 National Semiconductor Corporation Bipolar transistor and method of forming the bipolar transistor with a backside contact
US20110177655A1 (en) * 2007-06-27 2011-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of Through Via before Contact Processing
US9793192B2 (en) 2007-06-27 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of through via before contact processing
US9209157B2 (en) * 2007-06-27 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of through via before contact processing
US20150035168A1 (en) * 2008-03-19 2015-02-05 Imec Semiconductor device having through-substrate vias
US8809188B2 (en) * 2008-03-19 2014-08-19 Imec Method for fabricating through substrate vias
US20110089572A1 (en) * 2008-03-19 2011-04-21 Imec Method for fabricating through substrate vias
US9646930B2 (en) * 2008-03-19 2017-05-09 Imec Semiconductor device having through-substrate vias
US20090283871A1 (en) * 2008-05-14 2009-11-19 Hung-Pin Chang System, Structure, and Method of Manufacturing a Semiconductor Substrate Stack
US9728457B2 (en) 2008-05-14 2017-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. System, structure, and method of manufacturing a semiconductor substrate stack
US8853830B2 (en) 2008-05-14 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. System, structure, and method of manufacturing a semiconductor substrate stack
US8631570B2 (en) * 2008-07-29 2014-01-21 International Business Machines Corporation Through wafer vias with dishing correction methods
US7859114B2 (en) 2008-07-29 2010-12-28 International Business Machines Corporation IC chip and design structure with through wafer vias dishing correction
US20100025857A1 (en) * 2008-07-29 2010-02-04 Lindgren Peter J Ic chip and design structure with through wafer vias dishing correction
US20100029075A1 (en) * 2008-07-29 2010-02-04 Lindgren Peter J Through wafer vias with dishing correction methods
US20120137515A1 (en) * 2008-07-29 2012-06-07 International Business Machines Corporation Through wafer vias with dishing correction methods
US8166651B2 (en) * 2008-07-29 2012-05-01 International Business Machines Corporation Through wafer vias with dishing correction methods
US8748308B2 (en) 2008-08-08 2014-06-10 International Business Machines Corporation Through wafer vias and method of making same
US8518787B2 (en) 2008-08-08 2013-08-27 International Business Machines Corporation Through wafer vias and method of making same
US8035198B2 (en) 2008-08-08 2011-10-11 International Business Machines Corporation Through wafer via and method of making same
US8637937B2 (en) 2008-08-08 2014-01-28 Ultratech, Inc. Through silicon via for use in integrated circuit chips
US20100032808A1 (en) * 2008-08-08 2010-02-11 Hanyi Ding Through wafer via and method of making same
US8735251B2 (en) 2008-08-08 2014-05-27 Ultratech, Inc. Through silicon via and method of fabricating same
US20100032811A1 (en) * 2008-08-08 2010-02-11 Hanyi Ding Through wafer vias and method of making same
WO2010017162A1 (en) * 2008-08-08 2010-02-11 International Business Machines Corporation Through silicon via and method of fabricating same
US20100032810A1 (en) * 2008-08-08 2010-02-11 Hanyi Ding Through wafer vias and method of making same
US20100032764A1 (en) * 2008-08-08 2010-02-11 Paul Stephen Andry Through silicon via and method of fabricating same
US8138036B2 (en) 2008-08-08 2012-03-20 International Business Machines Corporation Through silicon via and method of fabricating same
US8299566B2 (en) 2008-08-08 2012-10-30 International Business Machines Corporation Through wafer vias and method of making same
WO2010017031A1 (en) * 2008-08-08 2010-02-11 International Business Machines Corporation Through wafer via and method of making same
US8384224B2 (en) 2008-08-08 2013-02-26 International Business Machines Corporation Through wafer vias and method of making same
US8097525B2 (en) 2008-08-29 2012-01-17 International Business Machines Corporation Vertical through-silicon via for a semiconductor structure
US20100052108A1 (en) * 2008-08-29 2010-03-04 International Business Machines Corporation Vertical through-silicon via for a semiconductor structure
US8519391B2 (en) * 2008-09-25 2013-08-27 Globalfoundries Inc. Semiconductor chip with backside conductor structure
US20100072620A1 (en) * 2008-09-25 2010-03-25 Liang Wang Semiconductor Chip with Backside Conductor Structure
US20120007075A1 (en) * 2008-09-25 2012-01-12 Globalfoundries Inc. Semiconductor chip with backside conductor structure
US8048689B2 (en) * 2008-09-25 2011-11-01 Globalfoundries Inc. Semiconductor chip with backside conductor structure
US8653648B2 (en) * 2008-10-03 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Zigzag pattern for TSV copper adhesion
US20100084747A1 (en) * 2008-10-03 2010-04-08 Chih-Hua Chen Zigzag Pattern for TSV Copper Adhesion
US20100140775A1 (en) * 2008-12-10 2010-06-10 Jung Oh Jin Semiconductor device and method for manufacturing the same
US9691739B2 (en) 2008-12-19 2017-06-27 Tessera Advanced Technologies, Inc. Semiconductor device and method of manufacturing same
US9318418B2 (en) 2008-12-19 2016-04-19 Tessera Advanced Technologies, Inc. Semiconductor device and method of manufacturing same
US8816506B2 (en) 2008-12-19 2014-08-26 Tessera Advanced Technologies, Inc. Semiconductor device and method of manufacturing the same
US8106518B2 (en) * 2008-12-19 2012-01-31 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
US9076700B2 (en) 2008-12-19 2015-07-07 Tessera Advanced Technologies, Inc. Semiconductor device and method of manufacturing same
US20100155940A1 (en) * 2008-12-19 2010-06-24 Renesas Technology Corp. Semiconductor device and method of manufacturing the same
US20100230760A1 (en) * 2009-03-13 2010-09-16 Cheng-Hui Hung Silicon Wafer Having Interconnection Metal
US8691664B2 (en) 2009-04-20 2014-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Backside process for a substrate
US20100267217A1 (en) * 2009-04-20 2010-10-21 Taiwan Semiconductor Manufacturing Company, Ltd. Backside Process for a Substrate
US8564103B2 (en) * 2009-06-04 2013-10-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an electronic device
US20100308444A1 (en) * 2009-06-04 2010-12-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of Manufacturing an Electronic Device
US8202766B2 (en) 2009-06-19 2012-06-19 United Microelectronics Corp. Method for fabricating through-silicon via structure
US8633106B2 (en) * 2009-08-11 2014-01-21 International Business Machines Corporation Heterojunction bipolar transistors and methods of manufacture
US8237191B2 (en) * 2009-08-11 2012-08-07 International Business Machines Corporation Heterojunction bipolar transistors and methods of manufacture
US20110037096A1 (en) * 2009-08-11 2011-02-17 International Business Machines Corporation Heterojunction Bipolar Transistors and Methods of Manufacture
US8692288B2 (en) * 2009-08-11 2014-04-08 International Business Machines Corporation Heterojunction bipolar transistors and methods of manufacture
US20120190190A1 (en) * 2009-08-11 2012-07-26 International Business Machines Corporation Heterojunction bipolar transistors and methods of manufacture
US9799562B2 (en) 2009-08-21 2017-10-24 Micron Technology, Inc. Vias and conductive routing layers in semiconductor substrates
CN102484095A (en) * 2009-08-21 2012-05-30 美光科技公司 Vias and conductive routing layers in semiconductor substrates
EP2467874A2 (en) * 2009-08-21 2012-06-27 Micron Technology, Inc. Vias and conductive routing layers in semiconductor substrates
EP2467874A4 (en) * 2009-08-21 2014-10-29 Micron Technology Inc Vias and conductive routing layers in semiconductor substrates
US8999766B2 (en) 2009-10-23 2015-04-07 Synopsys, Inc. ESD/antenna diodes for through-silicon vias
EP2500931A1 (en) * 2009-11-12 2012-09-19 Panasonic Corporation Semiconductor device and method for manufacturing semiconductor device
EP2500931A4 (en) * 2009-11-12 2014-03-26 Panasonic Corp Semiconductor device and method for manufacturing semiconductor device
US8916473B2 (en) * 2009-12-14 2014-12-23 Air Products And Chemicals, Inc. Method for forming through-base wafer vias for fabrication of stacked devices
US20110300710A1 (en) * 2009-12-14 2011-12-08 Dupont Air Products Nanomaterials, Llc Method for Forming Through-Base Wafer Vias for Fabrication of Stacked Devices
US20110260297A1 (en) * 2010-04-27 2011-10-27 Shian-Jyh Lin Through-substrate via and fabrication method thereof
US9064712B2 (en) * 2010-08-12 2015-06-23 Freescale Semiconductor Inc. Monolithic microwave integrated circuit
US9508599B2 (en) 2010-08-12 2016-11-29 Freescale Semiconductor, Inc. Methods of making a monolithic microwave integrated circuit
US9871008B2 (en) 2010-08-12 2018-01-16 Nxp Usa, Inc. Monolithic microwave integrated circuits
US20120037969A1 (en) * 2010-08-12 2012-02-16 Freescale Semiconductor, Inc. Monolithic microwave integrated circuit
US8519515B2 (en) 2011-04-13 2013-08-27 United Microlectronics Corp. TSV structure and method for forming the same
US8481425B2 (en) 2011-05-16 2013-07-09 United Microelectronics Corp. Method for fabricating through-silicon via structure
US8822336B2 (en) 2011-06-16 2014-09-02 United Microelectronics Corp. Through-silicon via forming method
US8828745B2 (en) 2011-07-06 2014-09-09 United Microelectronics Corp. Method for manufacturing through-silicon via
US8841755B2 (en) 2011-12-23 2014-09-23 United Microelectronics Corp. Through silicon via and method of forming the same
US8518823B2 (en) 2011-12-23 2013-08-27 United Microelectronics Corp. Through silicon via and method of forming the same
US8609529B2 (en) 2012-02-01 2013-12-17 United Microelectronics Corp. Fabrication method and structure of through silicon via
US8691600B2 (en) 2012-05-02 2014-04-08 United Microelectronics Corp. Method for testing through-silicon-via (TSV) structures
US8691688B2 (en) 2012-06-18 2014-04-08 United Microelectronics Corp. Method of manufacturing semiconductor structure
US9275933B2 (en) 2012-06-19 2016-03-01 United Microelectronics Corp. Semiconductor device
US20130341799A1 (en) * 2012-06-21 2013-12-26 Hsin-Yu Chen Through silicon via structure and method of fabricating the same
US9312208B2 (en) 2012-06-21 2016-04-12 United Microelectronics Corp. Through silicon via structure
US8900996B2 (en) * 2012-06-21 2014-12-02 United Microelectronics Corp. Through silicon via structure and method of fabricating the same
US8525296B1 (en) 2012-06-26 2013-09-03 United Microelectronics Corp. Capacitor structure and method of forming the same
US8912844B2 (en) 2012-10-09 2014-12-16 United Microelectronics Corp. Semiconductor structure and method for reducing noise therein
US20150249049A1 (en) * 2012-11-15 2015-09-03 Taiwan Semiconductor Manufacturing Company, Ltd. Through-Substrate via Formation with Improved Topography Control
US9418933B2 (en) * 2012-11-15 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Through-substrate via formation with improved topography control
US9035457B2 (en) 2012-11-29 2015-05-19 United Microelectronics Corp. Substrate with integrated passive devices and method of manufacturing the same
US8716104B1 (en) 2012-12-20 2014-05-06 United Microelectronics Corp. Method of fabricating isolation structure
US9064933B2 (en) 2012-12-21 2015-06-23 Invensas Corporation Methods and structure for carrier-less thin wafer handling
US9355905B2 (en) 2012-12-21 2016-05-31 Invensas Corporation Methods and structure for carrier-less thin wafer handling
WO2014100186A3 (en) * 2012-12-21 2014-09-25 Invensas Corporation Method and structure for carrier-less thin wafer handling
US8884398B2 (en) 2013-04-01 2014-11-11 United Microelectronics Corp. Anti-fuse structure and programming method thereof
US9287173B2 (en) 2013-05-23 2016-03-15 United Microelectronics Corp. Through silicon via and process thereof
US9123730B2 (en) 2013-07-11 2015-09-01 United Microelectronics Corp. Semiconductor device having through silicon trench shielding structure surrounding RF circuit
US9024416B2 (en) 2013-08-12 2015-05-05 United Microelectronics Corp. Semiconductor structure
US8916471B1 (en) 2013-08-26 2014-12-23 United Microelectronics Corp. Method for forming semiconductor structure having through silicon via for signal and shielding structure
US9048223B2 (en) 2013-09-03 2015-06-02 United Microelectronics Corp. Package structure having silicon through vias connected to ground potential
US9117804B2 (en) 2013-09-13 2015-08-25 United Microelectronics Corporation Interposer structure and manufacturing method thereof
US20170040255A1 (en) * 2013-12-23 2017-02-09 Intel Corporation Through-body-via isolated coaxial capacitor and techniques for forming same
US9911689B2 (en) * 2013-12-23 2018-03-06 Intel Corporation Through-body-via isolated coaxial capacitor and techniques for forming same
US9343359B2 (en) 2013-12-25 2016-05-17 United Microelectronics Corp. Integrated structure and method for fabricating the same
US9685370B2 (en) * 2014-12-18 2017-06-20 Globalfoundries Inc. Titanium tungsten liner used with copper interconnects

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