US20070151861A1 - Reliability barrier integration for cu application - Google Patents

Reliability barrier integration for cu application Download PDF

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US20070151861A1
US20070151861A1 US11682005 US68200507A US2007151861A1 US 20070151861 A1 US20070151861 A1 US 20070151861A1 US 11682005 US11682005 US 11682005 US 68200507 A US68200507 A US 68200507A US 2007151861 A1 US2007151861 A1 US 2007151861A1
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method
substrate
barrier layer
copper
layer
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US11682005
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Ming Xi
Paul Smith
Ling Chen
Michael Yang
Mei Chang
Fusen Chen
Christophe Marcadal
Jenny Lin
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Applied Materials Inc
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Applied Materials Inc
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    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
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    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
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    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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Abstract

Embodiments of the present invention provide a process sequence and related hardware for filling a patterned feature on a substrate with a metal, such as copper. The sequence comprises first forming a reliable barrier layer in the patterned feature to prevent diffusion of the metal into the dielectric layer through which the patterned feature is formed. One sequence comprises forming a generally conformal barrier layer over a patterned dielectric, etching the barrier layer at the bottom of the patterned feature, depositing a second barrier layer, and then filling the patterned feature with a metal, such as copper.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation of co-pending U.S. patent application Ser. No. 10/841,086, filed May 7, 2004, which is a continuation of U.S. patent application Ser. No. 10/052,681, filed Jan. 17, 2002, now issued as U.S. Pat. No. 7,026,238, which is a continuation-in-part of U.S. patent application Ser. No. 08/856,116, filed May 14, 1997, which is hereby incorporated by reference.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • Embodiments of the invention relate to a deposition sequence and related hardware for manufacturing a plug and line typical of a dual damascene structure utilizing a thin conformal barrier layer formed on the walls of the feature.
  • 2. Description of the Related Art
  • Modern semiconductor integrated circuits usually involve multiple conductive layers separated by dielectric (insulating) layers, such as oxide layers. The conductive layers are electrically interconnected by holes penetrating the intervening oxide layers and contacting some underlying conductive feature. After the holes are etched, they are filled with a metal, typically aluminum or copper, to electrically connect the conductive layers with each other. In a circuit formed by a dual damascene process, there are two types of holes, vias and trenches, which penetrate dielectric layers of the circuit. Vias are holes which extend to an underlying conductive feature. Vias which are filled with a metal are called plugs, or via plugs. Trenches are holes which extend into the dielectric layer of the circuit, but do not extend to an underlying conductive feature. Trenches which are filled with a metal are called lines, which serve as horizontal interconnects in a circuit.
  • As sizes of features such as holes in integrated circuits continue to decrease, the characteristics of the material forming the plugs become increasingly important. The smaller the plug, the less resistive the material forming the plug should be for speed performance. Copper is a material which is becoming more important as a result. Copper has a resistivity of 1.7 μΩ-cm. Copper has a small RC time constant thereby increasing the speed of a device formed thereof. In addition, copper exhibits improved reliability over aluminum in that copper has excellent electromigration resistance and can drive more current in the lines.
  • One problem with the use of copper is that copper diffuses into silicon dioxide, silicon and other dielectric materials. Therefore, barrier layers become increasingly important to prevent copper from diffusing into the dielectric materials and compromising the integrity of the device. Barrier materials such as Ta, TaN, SiN, Ti, TiN, W, and WN on the interlayer dielectric will effectively inhibit interlayer diffusion. However, within the same dielectric layer it is difficult to provide an effective barrier to prevent leakage between lines. Several technologies, such as physical vapor deposition (PVD), are presently under investigation for adding a barrier layer to the via sidewall separating the copper metal from the interlayer dielectric. However, common PVD technologies are limited in high aspect structures due to the directional nature of their deposition. Thus, the thickness of a barrier layer deposited by PVD will depend directly upon the structure architecture, with the barrier becoming thinner on the sidewall near the structure bottom. The barrier thickness, and therefore the barrier integrity may be compromised on the sidewall near the structure bottom. Also, the bottom corners of vias often do not form precise right angles at their intersection. Instead, there may be recesses or “undercuts” 11 at the bottom corners of vias 10 formed in a dielectric layer 12, as shown in FIG. 1. As a result, it is difficult to deposit a barrier layer that covers these undercuts by PVD because of the limited directionality of deposition by PVD.
  • In contrast, chemical vapor deposition (CVD) and atomic layer deposition (ALD) deposited films are, by their nature, conformal in re-entrant structures. Silicon nitride (SixNy) and titanium nitride (TiN) prepared by decomposition of an organic material, tetrakis(dimethylamido) titantium (TDMAT) are common semiconductor manufacturing materials which display the described conformal performance. Both materials are perceived as being good barriers to Cu diffusion, but are considered unattractive due to their high resistivity. The highly resistive nature of these materials detrimentally affects the conductivity between the plug and the underlying conductive features, which must be maintained as low as possible to maximize logic device performance.
  • Therefore, there is a need for a process sequence and related hardware which provides a good barrier layer on the via sidewall, but which does not negatively affect the conductivity of the plug.
  • SUMMARY OF THE INVENTION
  • Embodiments of the present invention generally provide a process and related hardware for filling a patterned feature on a substrate with copper or other conductive materials. One embodiment of the present invention comprises forming a generally conformal CVD or ALD barrier layer over a patterned feature formed in a substrate, etching the barrier layer at the bottom of the patterned feature, depositing a second barrier layer that does not significantly impact conductivity between the plug and the underlying layer, but provides an adequate barrier on other surfaces, and then filling the patterned feature with a conductive material, such as copper. Another embodiment of the present invention comprises forming a generally conformal CVD or ALD barrier layer over a patterned feature formed in a substrate having an etch stop, etching the barrier layer and the etch stop at the bottom of the patterned feature, depositing a second barrier layer, and then filling the patterned feature with a conductive material, such as copper.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • So that the manner in which the features of the present invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings.
  • It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
  • FIG. 1 is a partial cross-sectional view of a substrate having undercuts at the bottom of its via, as known in the prior art;
  • FIGS. 2-8 are partial cross-sectional views of a substrate having one process sequence of the present invention performed thereon;
  • FIG. 9 is a schematic of a multichamber processing apparatus;
  • FIG. 10 is a cross-sectional view of a CVD process chamber; and
  • FIG. 11 is a cross-sectional view of a PVD process chamber.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • FIGS. 2-8 illustrate and describe one embodiment of a process sequence of the present invention. FIG. 2 is a partial cross sectional view of a substrate having a via 200 and a trench 202 formed thereon through a dielectric layer 204 to an underlying metal layer 206. A conformal barrier layer 208, shown in FIG. 3, is formed over the patterned surface by CVD techniques, such as conventional CVD and rapid CVD, or atomic layer deposition (ALD). The barrier layer deposited by CVD may be formed from materials such as SixNy, TiSixN, TiN(C), TiNSi(C), Ta, TaC, TaN(C), TaNSi(C), W, WNx, SiOxNy, SiC, AlN, or Al2O3.
  • While the barrier layer 208 deposited by CVD or ALD provides desired conformal coverage of a substrate, including the sidewalls 216 and 218 of the via and the trench, respectively (FIG. 4), the barrier layer 208 also covers the lower portion of the via (FIG. 3), which contacts the underlying metal layer 206. The barrier layer 208 on the underlying metal layer 206 increases the resistance of the overall structure, and negatively impacts the performance of the structure. Thus, the substrate is exposed to a pre-clean or other etching process, such as an argon/hydrogen etch process to remove a portion of the barrier layer formed on the horizontal surfaces of the patterned feature, i.e, the bottom of the via 210 at the interface with the underlying metal layer 206, the bottom of the trench 212, and the field surface 214, as shown in FIG. 4. The etching may also extend into and remove part of the underlying metal layer (not shown). Preferably, the etching process is performed within a system that also includes the chamber in which the barrier layer 208 is deposited by chemical vapor deposition, so that the substrate is not exposed to air. More preferably, the etching process is performed within the same chamber in which chemical vapor deposition of the barrier layer is performed. However, in another embodiment, there is an air break in which the substrate is moved out of the processing system after the deposition of the barrier layer 208 and before the etching process.
  • Removing the barrier layer 208 from the bottom of the via 210 ensures a good, low resistance electrical contact to the underlying metal layer 206. However, removing the barrier layer 208 from another surface of the patterned feature, i.e., the bottom of the trench 212, leaves the dielectric layer 204 exposed at the bottom of the trench 212.
  • In the present invention, following the etch process, a second barrier layer 220, such as Ta, TaN, TiSiNx, TaSiNx, W, or WNx is sputter deposited using PVD onto the first barrier layer 208 and the exposed dielectric layer at the bottom of the trench 212, as shown in FIG. 5. The PVD barrier layer 220 covers the bottom of the trench 212 and the field surface 214. The PVD barrier layer 220 on the bottom of the trench 212 covers the dielectric layer at the bottom of the trench which was previously exposed during the etching process to remove the barrier layer 208 from the bottom of the via 210. The PVD barrier layer 220 may also partially or completely cover the vertical surfaces of the patterned feature, such as the sidewalls 216, 218 of the trench 202 and the via 200, respectively. However, the deposition of the PVD barrier layer 220 is minimized at the bottom of the via 210. At this point in the process, the aspect ratio of the via will typically be in the range of about 4 to 1, and the aspect ratio of the trench will typically be in the range of about 1 to 1. Because of the high aspect ratio/narrow opening of the via 200, few of the atoms or molecules sputtered by PVD will be sputtered at the appropriate angle to reach the bottom of the via 210. High density plasma PVD (HDP-PVD) or other directional PVD techniques may be used to further minimize deposition on the bottom of the via.
  • In another embodiment, the second barrier layer is deposited, at least partially, at the bottom of the via (not shown). For example, the barrier layer may have a thickness of from about 20 Å to about 50 Å at the bottom of the via. Preferably, the PVD barrier layer covering the bottom of the via has a low resistance. Examples of barrier layers with a low resistance, e.g., less than about 250 μΩ-cm, include PVD Ta, TaN, W, WNx, Ti, and TiN layers. Preferably, the second barrier layer deposited by physical vapor deposition is sufficient to provide a barrier on the bottom of the trench without significantly impairing conduction between the conductive material that is deposited later in the via and the underlying metal layer.
  • A copper seed layer 222 is then deposited on the patterned substrate by a PVD, CVD, or electroless deposition, as shown in FIG. 6. A seed layer is a layer on which a subsequent metal layer can be deposited by a process such as PVD, CVD, or electroplating. Copper is deposited on the seed layer by PVD, CVD, or electroplating to fill the trench and via features on the patterned substrate (not shown).
  • A similar process sequence may be performed on a patterned substrate with an etch stop, such as a nitride etch stop, at the via level. FIG. 7 shows the starting material patterned substrate with an etch stop 224 disposed at the bottom of the feature. The steps of a preferred embodiment of this method are illustrated by FIGS. 2, 3, 8, and 5. FIG. 8 shows that the etch stop 224 is removed from the bottom of the via 210 during the etching step which removes the barrier layer 208 from the bottom of the via 210.
  • A schematic of a multichamber processing apparatus 35 suitable for performing the processes of the present invention is illustrated in FIG. 9. The apparatus is an “ENDURA” system commercially available from Applied Materials, Santa Clara, Calif. The particular embodiment of the apparatus 35 shown herein is suitable for processing planar substrates, such as semiconductor substrates, and is provided to illustrate the invention, and should not be used to limit the scope of the invention. The apparatus 35 typically comprises a cluster of interconnected process chambers 36, for example, CVD and PVD deposition and rapid thermal annealing chambers.
  • The apparatus comprises a CVD deposition chamber 41 (shown in FIG. 10) which is used to deposit the conformal barrier layer 208 in one embodiment. The CVD deposition chamber 41 has surrounding sidewalls 45 and a ceiling 50. The chamber 41 comprises a process gas distributor 55 for delivering process gases into the chamber. Mass flow controllers and air operated valves are used to control the flow of process gases into the deposition chamber 41. The gas distributor 55 is typically mounted above the substrate (as shown), or peripherally about the substrate (not shown). A support 65 is provided for supporting the substrate in the deposition chamber 41. The substrate is introduced into the chamber 41 through a substrate loading inlet in the sidewall 45 of the chamber 41 and placed on the support 65. The support 65 can be lifted or lowered by support lift bellows 70 so that the gap between the substrate and gas distributor 55 can be adjusted. A lift finger assembly 75 comprising lift fingers that are inserted through holes in the support 65 can be used to lift and lower the substrate onto the support to facilitate transport of the substrate into and out of the chamber 41. A thermal heater 80 is then provided in the chamber to rapidly heat the substrate. Rapid heating and cooling of the substrate is preferred to increase processing throughput, and to allow rapid cycling between successive processes operated at different temperatures. The temperature of the substrate is generally estimated from the temperature of the support 65.
  • The substrate is processed in a process zone 95 above a horizontal perforated barrier plate 105. The barrier plate 105 has exhaust holes 110 which are in fluid communication with an exhaust system 115 for exhausting spent process gases from the chamber 41. A typical exhaust system 115 comprises a rotary vane vacuum pump (not shown) capable of achieving a minimum vacuum of about 10 mTorr, and optionally a scrubber system for scrubbing byproduct gases. The pressure in the chamber 41 is sensed at the side of the substrate and is controlled by adjusting a throttle valve in the exhaust system 115.
  • A plasma generator 116 is provided for generating a plasma in the process zone 95 of the chamber 40 for plasma enhanced chemical vapor deposition processes. The plasma generator 116 can generate a plasma (i) inductively by applying an RF current to an inductor coil encircling the deposition chamber (not shown), (ii) capacitively by applying an RF current to process electrodes in the chamber, or (iii) both inductively and capacitively while the chamber wall or other electrode is grounded. A DC or RF current at a power level of from about 750 Watts to about 2000 Watts can be applied to an inductor coil (not shown) to inductively couple energy into the deposition chamber to generate a plasma in the process zone 95. When an RF current is used, the frequency of the RF current is typically from about 400 KHz to about 16 MHZ, and more typically about 13.56 MHZ Optionally, a gas containment or plasma focus ring (not shown), typically made of aluminum oxide or quartz, can be used to contain the flow of process gas or plasma around the substrate.
  • In another embodiment, a conformal barrier layer 208 is formed over the patterned surface by atomic layer deposition (ALD). The ALD barrier layer may be formed from materials such as Ta, TaN, W, or WN. Examples of ALD processes are described in commonly assigned U.S. patent application Ser. No. 09/754,230, entitled “Method of Forming Refractory Metal Nitride Layers Using Chemisorption Techniques,” filed on Jan. 3, 2001, U.S. patent application Ser. No. 09/960,469, entitled “Formation of Refractory Metal Nitrides Using Chemisorption Techniques,” filed on Sep. 19, 2001, and U.S. patent application Ser. No. 09/965,370, entitled “Integration of Barrier Layer and Seed Layer,” filed on Sep. 26, 2001, which are hereby incorporated by reference.
  • Generally, ALD can be used to deposit monolayers of materials, such as monolayers of a nitrogen-based compound and a metal containing compound, which are alternately chemisorbed on a substrate. For example, a monolayer of a nitrogen-based compound is chemisorbed on a substrate by introducing a pulse of a nitrogen-based gas into a processing chamber. After the monolayer is chemisorbed onto the substrate, excess nitrogen-based compound is removed from the processing chamber by introducing a pulse of purge gas thereto. Purge gases, such as, for example, helium (He), argon (Ar), nitrogen (N2), and hydrogen (H2), and other gases, may be used. After the pulse of purge gas, a pulse of a metal containing compound is introduced into the processing chamber to chemisorb a monolayer of metal containing compound on the substrate. The metal containing compound may be provided as a gas or may be provided with the aid of a carrier gas. Examples of carrier gases which may be used include, but are not limited to, helium (He), argon (Ar), nitrogen (N2), and hydrogen (H2).
  • In another embodiment of ALD, instead of using pulses of a purge gas between the pulses of a nitrogen-based compound and a metal containing compound, the purge gas is continuously flowed, i.e., both during the pulses of a nitrogen-based compound and the pulses of a metal containing compound, and in between these pulses.
  • One exemplary process of depositing a tantalum nitride barrier layer by atomic layer deposition in a processing chamber comprises sequentially providing pentadimethylamino-tantalum (PDMAT) at a flow rate between about 100 sccm and about 1000 sccm, and preferably between about 200 sccm (standard cubic centimeters per minute) and 500 sccm, for a time period of about 1.0 second or less, providing ammonia at a flow rate between about 100 sccm and about 1000 sccm, preferably between about 200 sccm and 500 sccm, for a time period of about 1.0 second or less, and a purge gas at a flow rate between about 100 sccm and about 1000 sccm, preferably between about 200 sccm and 500 sccm for a time period of about 1.0 second or less. The heater temperature preferably is maintained between about 100° C. and about 300° C. at a chamber pressure between about 1.0 and about 5.0 torr. This process provides a tantalum nitride layer in a thickness between about 0.5 Å and about 1.0 Å per cycle. The alternating sequence may be repeated until a desired thickness is achieved.
  • A pre-clean chamber which can be used to remove the barrier layer 208 from the bottom of the via 210 is the Pre-Clean II chamber available from Applied Materials, Inc. of Santa Clara, Calif. Additionally, other etch chambers known in the field could be used to remove the barrier layer as described. In a preferred embodiment, the CVD chamber 41 of FIG. 16 can be used to etch the CVD barrier layer deposited on the substrate. The support pedestal 82 may be used to bias the substrate. A plasma generator 116, as described above, is attached to the support pedestal 82. Argon is the principal etching gas. It ionizes in the chamber, and its positively charged ions are attracted to the negatively biased substrate with enough energy that the barrier layer 208 is removed from the horizontal surfaces of the patterned feature.
  • In another embodiment, the barrier layer 208 may be deposited and then removed from the bottom of the via 210 in an ALD chamber with plasma capability.
  • A conventional PVD deposition chamber commercially available from Applied Materials, Santa Clara, Calif. can be used to deposit a second barrier layer 220 on a substrate. FIG. 11 shows a simplified example of a PVD chamber 300. The PVD chamber 300 generally includes a chamber section 306. The chamber section 306 generally includes a substrate support member 302 for supporting a substrate (not shown) to be processed, a target 304 for providing a material to be deposited on the substrate and a process environment 303 wherein a plasma is created for ions to sputter the target 304.
  • The PVD chamber 300 generally includes the substrate support member 302, also known as a susceptor or heater, disposed within the chamber section 306. The substrate support member 302 may heat the substrate if required by the process being performed. A target 304 is disposed in the top of the chamber section 306 to provide material, such as aluminum, titanium or tungsten, to be sputtered onto the substrate during processing by the PVD chamber 300. A lift mechanism, including a guide rod 326, a bellows 328 and a lift actuator 330 mounted to the bottom of the chamber section 306, raises the substrate support member 302 to the target 304 for the PVD chamber 300 to perform the process and lowers the substrate support member 302 to exchange substrates. A set of shields 332, 334, 336, disposed within the chamber section 306, surround the substrate support member 302 and the substrate during processing in order to prevent the target material from depositing on the edge of the substrate and on other surfaces inside the chamber section 306.
  • Situated above the chamber section 306 and sealed from the processing region of the chamber is a cooling chamber 316. The cooling chamber 316 is generally defined by the target 304, a top 317 and sides 319. A cooling fluid, such as water or antifreeze, flows into the cooling chamber 316 through inlet 318 and out of the cooling chamber 316 through outlet 320.
  • A rotating magnetron 308 is disposed in the cooling chamber 316 on the non-process environment side of the target 304 and surrounded by the cooling fluid. The magnetron 308 is isolated from the vacuum in the chamber section 306 by seals (not shown) between the magnetron chamber and target and between the target and processing region. The magnetron 308 has a set of magnets 310 arranged within the magnetron 308 so that they create magnetic field lines spinning across the sputtering surface of the target. Electrons are captured along these lines, where they collide with gas atoms, creating ions. To create this effect about the circumference of the target, the target is rotated during processing. The magnetron 308 is situated above the top side of the target 304 with about a one millimeter gap therebetween, so the magnetic fields from the magnets 310 may penetrate through the target 304. A motor assembly 312 for rotating the magnetron 308 is mounted to the top 317 of the cooling chamber 316. A shaft 314, which mechanically couples the motor assembly 312 to the rotational center of the magnetron 308, extends through the top 317. The motor assembly 312 imparts a rotational motion to the magnetron 308 to cause it to spin during performance of the substrate process.
  • A negative DC bias voltage of about 200 V or more is typically applied to the target 304, and a ground is applied to an anode, the substrate support member 302, and the chamber surfaces. The combined action of the dc bias and the rotating magnetron 308 generate an ionized plasma discharge in a process gas, such as argon, between the target 304 and the substrate. The positively charged ions are attracted to the target 304 and strike the target 304 with sufficient energy to dislodge atoms of the target material, which sputters onto the substrate.
  • The process can be implemented using a computer program product that runs on a conventional computer system comprising a central processor unit (CPU) interconnected to a memory system with peripheral control components, such as for example a 68400 microprocessor, commercially available from Synenergy Microsystems, California.
  • EXAMPLE 1
  • In one example, a process according to the present invention was performed on a substrate having a 0.25 μm via with about a 4:1 aspect ratio and a trench. The patterned substrate was first introduced into a CVD chamber, such as a TxZ® chamber, commercially available from Applied Materials, Inc., Santa Clara, Calif., where about 50 Å to about 100 Å of SixNy was deposited on the substrate using CVD techniques. The substrate was then moved into a Pre-clean II chamber (available from Applied Materials, Inc., located in Santa Clara, Calif.), where the substrate was subjected to an argon/hydrogen etching environment for about 20 seconds. RF/DC powers of about 300/300 W were used. Next, the substrate was moved into a PVD chamber where about 400 Å of TaN was deposited on the substrate in the field. Next, the substrate was introduced into a CVD chamber where about 400 Å of CVD Cu was deposited on the substrate as a wetting layer. Then, Cu was sputtered onto the substrate to complete the fill the via and the trench.
  • EXAMPLE 2
  • In another example, a patterned substrate with a dual damascene trench structure and a via opened to an underlying Cu wiring was first introduced into a multichamber processing apparatus having a sputter clean chamber, a CVD barrier chamber, a PVD barrier chamber, and a PVD Cu chamber. 50 Å of TiSixN was deposited on the substrate in a CVD barrier chamber at a pressure of less than 10 Torr and at a temperature of about 300° C. to about 380° C. by reacting TDMAT in a N2/H2 environment to form a plasma. The substrate was then treated with a SiH4 soak. The deposited TiSixN conformally covered both the via and trench structure. In the next step, the substrate was moved to the sputter clean chamber, and subjected to argon/hydrogen etch to etch off the TiSixN film deposited at the bottom of the via. The etching was continued past the bottom of the via into the underlying Cu wiring to remove about 5 to 10 Å of the underlying Cu wiring. The etch process also removed the TiSixN film at the bottom of the trench structure. Next, the substrate was moved into a PVD Ta/TaN chamber to receive a Ta/TaN film having a thickness at the bottom of the trench structure of about 30 Å. Then, the substrate was transferred into a PVD Cu chamber where about 1500 Å of Cu was deposited on the substrate with minimal deposition at the bottom of the via.
  • While the foregoing is directed to the preferred embodiment of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims which follow.

Claims (27)

  1. 1. A method of forming a barrier on a substrate having a recessed feature formed therein, the method comprising:
    depositing a nitride barrier layer on the substrate;
    etching through the nitride barrier layer so as to expose at least a bottom portion of the recessed feature;
    depositing an additional nitride barrier layer on the substrate; and
    depositing a copper pre-layer on the substrate.
  2. 2. The method of claim 1, further comprising depositing copper on the copper pre-layer.
  3. 3. The method of claim 2, wherein the depositing copper on the copper pre-layer comprises electroplating copper.
  4. 4. The method of claim 1, wherein the deposition of the additional nitride barrier layer is performed in the presence of a high density plasma.
  5. 5. The method of claim 1, wherein the additional nitride barrier layer is a TaN layer.
  6. 6. The method of claim 1, wherein the depositing a nitride barrier layer comprises a vapor deposition.
  7. 7. A method of forming a barrier on a substrate having a recessed feature formed therein, the method comprising:
    depositing a nitride barrier layer on the substrate;
    etching through the nitride barrier layer so as to expose at least a bottom portion of the recessed feature;
    depositing an additional nitride barrier layer on the substrate, wherein the additional nitride barrier layer covers the bottom of the recessed feature; and
    depositing a copper layer on the substrate.
  8. 8. The method of claim 7, further comprising electroplating copper on the copper layer.
  9. 9. The method of claim 8, wherein the electroplating copper on the copper layer fills the recessed feature.
  10. 10. The method of claim 7, wherein the deposition of the additional nitride barrier layer is performed in the presence of a high density plasma.
  11. 11. The method of claim 7, wherein the additional nitride barrier layer is a TaN layer.
  12. 12. The method of claim 7, wherein the depositing a nitride barrier layer comprises a vapor deposition.
  13. 13. A method of forming a barrier on a substrate having a recessed feature formed therein, the method comprising:
    depositing a nitride barrier layer on the substrate, wherein the nitride barrier layer covers the bottom of the recessed feature, and wherein the depositing a nitride barrier layer comprises etching barrier material from the bottom of the recessed feature after deposition of the barrier material; and then
    depositing a copper pre-layer on the substrate.
  14. 14. The method of claim 13, wherein etching barrier material from the bottom of the recessed feature exposes the bottom of the recessed feature.
  15. 15. The method of claim 13, further comprising depositing copper on the copper pre-layer.
  16. 16. The method of claim 15, wherein the depositing copper on the copper pre-layer comprises electroplating copper.
  17. 17. The method of claim 15, wherein depositing copper on the copper pre-layer fills the recessed feature.
  18. 18. The method of claim 13, wherein the deposition of the nitride barrier layer is performed in the presence of a high density plasma.
  19. 19. The method of claim 13, wherein the nitride barrier layer comprises tantalum nitride.
  20. 20. The method of claim 13, where the depositing a nitride barrier layer comprises a vapor deposition.
  21. 21. A method of forming a barrier on a substrate having a recessed feature formed therein, the method comprising:
    depositing a nitride barrier layer on the substrate;
    etching through the nitride barrier layer so as to expose at least a bottom portion of the recessed feature;
    sputtering additional barrier material from a target onto the substrate; and
    depositing a copper pre-layer on the substrate.
  22. 22. The method of claim 21, wherein sputtering additional barrier material from a target onto the substrate comprises depositing an additional barrier layer on the substrate.
  23. 23. The method of claim 22, wherein the additional barrier layer is a TaN layer.
  24. 24. The method of claim 21, wherein the additional barrier material comprises tantalum.
  25. 25. The method of claim 21, further comprising depositing copper on the copper pre-layer to fill the recessed feature.
  26. 26. The method of claim 25, wherein the depositing copper on the copper pre-layer comprises electroplating copper.
  27. 27. The method of claim 21, wherein the sputtering comprises a high density plasma process.
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US10245119 Abandoned US20030017695A1 (en) 1997-05-14 2002-09-16 Reliability barrier integration for Cu application
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US10245119 Abandoned US20030017695A1 (en) 1997-05-14 2002-09-16 Reliability barrier integration for Cu application
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070087563A1 (en) * 2004-08-02 2007-04-19 Micron Technology, Inc. Zirconium-doped tantalum oxide films
US20080008823A1 (en) * 2003-01-07 2008-01-10 Ling Chen Deposition processes for tungsten-containing barrier layers
US20080182406A1 (en) * 2007-01-31 2008-07-31 Axel Preusse Method of forming a copper-based metallization layer including a conductive cap layer by an advanced integration regime
US7589029B2 (en) * 2002-05-02 2009-09-15 Micron Technology, Inc. Atomic layer deposition and conversion
US7687409B2 (en) 2005-03-29 2010-03-30 Micron Technology, Inc. Atomic layer deposited titanium silicon oxide films
US20110027976A1 (en) * 2008-04-18 2011-02-03 Ips Ltd. Method of forming chalcogenide thin film
CN102005411A (en) * 2009-09-01 2011-04-06 中芯国际集成电路制造(上海)有限公司 Forming method for barrier layer
US20120251967A1 (en) * 2011-03-29 2012-10-04 Tokyo Electron Limited Loading unit and processing system
US8501563B2 (en) 2005-07-20 2013-08-06 Micron Technology, Inc. Devices with nanocrystals and methods of formation

Families Citing this family (102)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999027579A1 (en) * 1997-11-26 1999-06-03 Applied Materials, Inc. Damage-free sculptured coating deposition
US6287977B1 (en) * 1998-07-31 2001-09-11 Applied Materials, Inc. Method and apparatus for forming improved metal interconnects
US6974766B1 (en) 1998-10-01 2005-12-13 Applied Materials, Inc. In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application
US6174811B1 (en) 1998-12-02 2001-01-16 Applied Materials, Inc. Integrated deposition process for copper metallization
US10047430B2 (en) 1999-10-08 2018-08-14 Applied Materials, Inc. Self-ionized and inductively-coupled plasma for sputtering and resputtering
US8696875B2 (en) 1999-10-08 2014-04-15 Applied Materials, Inc. Self-ionized and inductively-coupled plasma for sputtering and resputtering
US7732327B2 (en) 2000-06-28 2010-06-08 Applied Materials, Inc. Vapor deposition of tungsten materials
US7405158B2 (en) 2000-06-28 2008-07-29 Applied Materials, Inc. Methods for depositing tungsten layers employing atomic layer deposition techniques
US7964505B2 (en) 2005-01-19 2011-06-21 Applied Materials, Inc. Atomic layer deposition of tungsten materials
US7101795B1 (en) 2000-06-28 2006-09-05 Applied Materials, Inc. Method and apparatus for depositing refractory metal layers employing sequential deposition techniques to form a nucleation layer
US6551929B1 (en) 2000-06-28 2003-04-22 Applied Materials, Inc. Bifurcated deposition process for depositing refractory metal layers employing atomic layer deposition and chemical vapor deposition techniques
US6562715B1 (en) 2000-08-09 2003-05-13 Applied Materials, Inc. Barrier layer structure for copper metallization and method of forming the structure
US6498091B1 (en) * 2000-11-01 2002-12-24 Applied Materials, Inc. Method of using a barrier sputter reactor to remove an underlying barrier layer
US20020197402A1 (en) * 2000-12-06 2002-12-26 Chiang Tony P. System for depositing a film by modulated ion-induced atomic layer deposition (MII-ALD)
US6596643B2 (en) * 2001-05-07 2003-07-22 Applied Materials, Inc. CVD TiSiN barrier for copper integration
US7211144B2 (en) 2001-07-13 2007-05-01 Applied Materials, Inc. Pulsed nucleation deposition of tungsten layers
US6936538B2 (en) 2001-07-16 2005-08-30 Applied Materials, Inc. Method and apparatus for depositing tungsten after surface treatment to improve film characteristics
US9051641B2 (en) 2001-07-25 2015-06-09 Applied Materials, Inc. Cobalt deposition on barrier surfaces
US20090004850A1 (en) 2001-07-25 2009-01-01 Seshadri Ganguli Process for forming cobalt and cobalt silicide materials in tungsten contact applications
US8110489B2 (en) 2001-07-25 2012-02-07 Applied Materials, Inc. Process for forming cobalt-containing materials
US7049226B2 (en) * 2001-09-26 2006-05-23 Applied Materials, Inc. Integration of ALD tantalum nitride for copper metallization
US6916398B2 (en) * 2001-10-26 2005-07-12 Applied Materials, Inc. Gas delivery apparatus and method for atomic layer deposition
US7780785B2 (en) 2001-10-26 2010-08-24 Applied Materials, Inc. Gas delivery apparatus for atomic layer deposition
US7081271B2 (en) 2001-12-07 2006-07-25 Applied Materials, Inc. Cyclical deposition of refractory metal silicon nitride
WO2003065424A3 (en) * 2002-01-25 2004-03-11 Applied Materials Inc Apparatus for cyclical deposition of thin films
US6911391B2 (en) 2002-01-26 2005-06-28 Applied Materials, Inc. Integration of titanium and titanium nitride layers
US6833161B2 (en) 2002-02-26 2004-12-21 Applied Materials, Inc. Cyclical deposition of tungsten nitride for metal oxide gate electrode
US6972267B2 (en) 2002-03-04 2005-12-06 Applied Materials, Inc. Sequential deposition of tantalum nitride using a tantalum-containing precursor and a nitrogen-containing precursor
US7279432B2 (en) 2002-04-16 2007-10-09 Applied Materials, Inc. System and method for forming an integrated barrier layer
US6838125B2 (en) * 2002-07-10 2005-01-04 Applied Materials, Inc. Method of film deposition using activated precursor gases
US7186385B2 (en) 2002-07-17 2007-03-06 Applied Materials, Inc. Apparatus for providing gas to a processing chamber
US7504006B2 (en) 2002-08-01 2009-03-17 Applied Materials, Inc. Self-ionized and capacitively-coupled plasma for sputtering and resputtering
US6784096B2 (en) * 2002-09-11 2004-08-31 Applied Materials, Inc. Methods and apparatus for forming barrier layers in high aspect ratio vias
US7005375B2 (en) 2002-09-30 2006-02-28 Agere Systems Inc. Method to avoid copper contamination of a via or dual damascene structure
US6878620B2 (en) 2002-11-12 2005-04-12 Applied Materials, Inc. Side wall passivation films for damascene cu/low k electronic devices
US7204886B2 (en) * 2002-11-14 2007-04-17 Applied Materials, Inc. Apparatus and method for hybrid chemical processing
US6949461B2 (en) * 2002-12-11 2005-09-27 International Business Machines Corporation Method for depositing a metal layer on a semiconductor interconnect structure
DE10261466B4 (en) * 2002-12-31 2007-01-04 Advanced Micro Devices, Inc., Sunnyvale A method for producing a conductive barrier layer with improved adhesion and resistance properties
US7056826B2 (en) * 2003-01-07 2006-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming copper interconnects
WO2004064147A3 (en) * 2003-01-07 2004-09-02 Applied Materials Inc Integration of ald/cvd barriers with porous low k materials
US20040150103A1 (en) * 2003-02-03 2004-08-05 International Business Machines Corporation Sacrificial Metal Liner For Copper
US20040175926A1 (en) * 2003-03-07 2004-09-09 Advanced Micro Devices, Inc. Method for manufacturing a semiconductor component having a barrier-lined opening
CN100593235C (en) 2003-06-13 2010-03-03 应用材料公司 Integration of ALD tantalum nitride for copper metallization
JP2007523994A (en) * 2003-06-18 2007-08-23 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated Atomic layer deposition of the barrier material
US6987059B1 (en) * 2003-08-14 2006-01-17 Lsi Logic Corporation Method and structure for creating ultra low resistance damascene copper wiring
US7166528B2 (en) * 2003-10-10 2007-01-23 Applied Materials, Inc. Methods of selective deposition of heavily doped epitaxial SiGe
US20050082089A1 (en) * 2003-10-18 2005-04-21 Stephan Grunow Stacked interconnect structure between copper lines of a semiconductor circuit
US20050098427A1 (en) * 2003-11-11 2005-05-12 Taiwan Semiconductor Manufacturing Co., Ltd. RF coil design for improved film uniformity of an ion metal plasma source
US20050109276A1 (en) * 2003-11-25 2005-05-26 Applied Materials, Inc. Thermal chemical vapor deposition of silicon nitride using BTBAS bis(tertiary-butylamino silane) in a single wafer chamber
US20050118796A1 (en) * 2003-11-28 2005-06-02 Chiras Stefanie R. Process for forming an electrically conductive interconnect
US20050252449A1 (en) 2004-05-12 2005-11-17 Nguyen Son T Control of gas flow and delivery to suppress the formation of particles in an MOCVD/ALD system
US20060009030A1 (en) * 2004-07-08 2006-01-12 Texas Instruments Incorporated Novel barrier integration scheme for high-reliability vias
US7241686B2 (en) * 2004-07-20 2007-07-10 Applied Materials, Inc. Atomic layer deposition of tantalum-containing materials using the tantalum precursor TAIMATA
US20060019032A1 (en) * 2004-07-23 2006-01-26 Yaxin Wang Low thermal budget silicon nitride formation for advance transistor fabrication
US20060024953A1 (en) * 2004-07-29 2006-02-02 Papa Rao Satyavolu S Dual damascene diffusion barrier/liner process with selective via-to-trench-bottom recess
US7282802B2 (en) * 2004-10-14 2007-10-16 International Business Machines Corporation Modified via bottom structure for reliability enhancement
US20060084283A1 (en) * 2004-10-20 2006-04-20 Paranjpe Ajit P Low temperature sin deposition methods
US7312128B2 (en) 2004-12-01 2007-12-25 Applied Materials, Inc. Selective epitaxy process with alternating gas supply
US7560352B2 (en) * 2004-12-01 2009-07-14 Applied Materials, Inc. Selective deposition
US7682940B2 (en) * 2004-12-01 2010-03-23 Applied Materials, Inc. Use of Cl2 and/or HCl during silicon epitaxial film formation
US7429402B2 (en) * 2004-12-10 2008-09-30 Applied Materials, Inc. Ruthenium as an underlayer for tungsten film deposition
US7235492B2 (en) 2005-01-31 2007-06-26 Applied Materials, Inc. Low temperature etchant for treatment of silicon-containing surfaces
US20060246699A1 (en) * 2005-03-18 2006-11-02 Weidman Timothy W Process for electroless copper deposition on a ruthenium seed
US7651934B2 (en) 2005-03-18 2010-01-26 Applied Materials, Inc. Process for electroless copper deposition
US7651955B2 (en) * 2005-06-21 2010-01-26 Applied Materials, Inc. Method for forming silicon-containing materials during a photoexcitation deposition process
US7648927B2 (en) 2005-06-21 2010-01-19 Applied Materials, Inc. Method for forming silicon-containing materials during a photoexcitation deposition process
US20060286774A1 (en) * 2005-06-21 2006-12-21 Applied Materials. Inc. Method for forming silicon-containing materials during a photoexcitation deposition process
DE102006037722B4 (en) * 2005-08-06 2016-02-25 Samsung Electronics Co., Ltd. Wiring structure for an integrated circuit and method of producing same
KR100640662B1 (en) * 2005-08-06 2006-10-25 삼성전자주식회사 Semiconductor device having a barrier metal spacer and method of fabricating the same
KR100685902B1 (en) * 2005-08-29 2007-02-15 동부일렉트로닉스 주식회사 Metal line for semiconductor device and method for fabricating the same
US20070065576A1 (en) * 2005-09-09 2007-03-22 Vikram Singh Technique for atomic layer deposition
KR101019293B1 (en) 2005-11-04 2011-03-07 어플라이드 머티어리얼스, 인코포레이티드 Apparatus and process for plasma-enhanced atomic layer deposition
US20090078580A1 (en) * 2005-12-02 2009-03-26 Ulvac, Inc. Method for Forming Cu Film
US20070126120A1 (en) * 2005-12-06 2007-06-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device
US7417321B2 (en) * 2005-12-30 2008-08-26 Taiwan Semiconductor Manufacturing Co., Ltd Via structure and process for forming the same
US7959985B2 (en) * 2006-03-20 2011-06-14 Tokyo Electron Limited Method of integrating PEALD Ta-containing films into Cu metallization
US7674337B2 (en) * 2006-04-07 2010-03-09 Applied Materials, Inc. Gas manifolds for use during epitaxial film formation
US7798096B2 (en) 2006-05-05 2010-09-21 Applied Materials, Inc. Plasma, UV and ion/neutral assisted ALD or CVD in a batch tool
US7501355B2 (en) * 2006-06-29 2009-03-10 Applied Materials, Inc. Decreasing the etch rate of silicon nitride by carbon addition
US7588980B2 (en) * 2006-07-31 2009-09-15 Applied Materials, Inc. Methods of controlling morphology during epitaxial layer formation
WO2008016650A3 (en) * 2006-07-31 2008-04-10 Applied Materials Inc Methods of forming carbon-containing silicon epitaxial layers
US20080078325A1 (en) * 2006-09-29 2008-04-03 Tokyo Electron Limited Processing system containing a hot filament hydrogen radical source for integrated substrate processing
US20080081464A1 (en) * 2006-09-29 2008-04-03 Tokyo Electron Limited Method of integrated substrated processing using a hot filament hydrogen radical souce
US7521379B2 (en) * 2006-10-09 2009-04-21 Applied Materials, Inc. Deposition and densification process for titanium nitride barrier layers
US9087877B2 (en) * 2006-10-24 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Low-k interconnect structures with reduced RC delay
DE102006056626A1 (en) * 2006-11-30 2008-06-05 Advanced Micro Devices, Inc., Sunnyvale Conductive barrier layer producing method for manufacturing integrated circuit, involves depositing layer on exposed surfaces by self-restricted deposition technique, and providing surface with characteristics at reduced deposition rate
US20080145536A1 (en) * 2006-12-13 2008-06-19 Applied Materials, Inc. METHOD AND APPARATUS FOR LOW TEMPERATURE AND LOW K SiBN DEPOSITION
KR100853098B1 (en) * 2006-12-27 2008-08-19 동부일렉트로닉스 주식회사 Metal line in semiconductor device and method of manufacturing the metal line
DE102007004867B4 (en) * 2007-01-31 2009-07-30 Advanced Micro Devices, Inc., Sunnyvale A method for increasing the reliability of copper-based metallization structures in a microstructure device by applying aluminum nitride
US7678298B2 (en) * 2007-09-25 2010-03-16 Applied Materials, Inc. Tantalum carbide nitride materials by vapor deposition processes
US7585762B2 (en) * 2007-09-25 2009-09-08 Applied Materials, Inc. Vapor deposition processes for tantalum carbide nitride materials
US7824743B2 (en) * 2007-09-28 2010-11-02 Applied Materials, Inc. Deposition processes for titanium nitride barrier and aluminum
US7659158B2 (en) 2008-03-31 2010-02-09 Applied Materials, Inc. Atomic layer deposition processes for non-volatile memory devices
US20110117466A1 (en) 2008-05-30 2011-05-19 Michael Edward Badding Solid Oxide Fuel Cell Systems
US8491967B2 (en) 2008-09-08 2013-07-23 Applied Materials, Inc. In-situ chamber treatment and deposition process
US20100062149A1 (en) * 2008-09-08 2010-03-11 Applied Materials, Inc. Method for tuning a deposition rate during an atomic layer deposition process
US8146896B2 (en) 2008-10-31 2012-04-03 Applied Materials, Inc. Chemical precursor ampoule for vapor deposition processes
US8653664B2 (en) * 2009-07-08 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier layers for copper interconnect
US8653663B2 (en) 2009-10-29 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier layer for copper interconnect
US8361900B2 (en) 2010-04-16 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier layer for copper interconnect
US9190319B2 (en) * 2013-03-08 2015-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming interconnect structure
KR20160089034A (en) * 2015-01-16 2016-07-27 삼성디스플레이 주식회사 Thin film encapsulation manufacturing device and manufacturing method of thin film encapsulation

Citations (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5308793A (en) * 1991-07-24 1994-05-03 Sony Corporation Method for forming interconnector
US5913147A (en) * 1997-01-21 1999-06-15 Advanced Micro Devices, Inc. Method for fabricating copper-aluminum metallization
US5930669A (en) * 1997-04-03 1999-07-27 International Business Machines Corporation Continuous highly conductive metal wiring structures and method for fabricating the same
US5933753A (en) * 1996-12-16 1999-08-03 International Business Machines Corporation Open-bottomed via liner structure and method for fabricating same
US5972179A (en) * 1997-09-30 1999-10-26 Lucent Technologies Inc. Silicon IC contacts using composite TiN barrier layer
US5972178A (en) * 1995-06-07 1999-10-26 Applied Materials, Inc. Continuous process for forming improved titanium nitride barrier layers
US5985762A (en) * 1997-05-19 1999-11-16 International Business Machines Corporation Method of forming a self-aligned copper diffusion barrier in vias
US5989999A (en) * 1994-11-14 1999-11-23 Applied Materials, Inc. Construction of a tantalum nitride film on a semiconductor wafer
US5993916A (en) * 1996-07-12 1999-11-30 Applied Materials, Inc. Method for substrate processing with improved throughput and yield
US6002174A (en) * 1997-12-31 1999-12-14 Micron Technology, Inc. Barrier materials for semiconductor devices
US6007684A (en) * 1995-06-07 1999-12-28 Applied Materials, Inc. Process for forming improved titanium-containing barrier layers
US6013576A (en) * 1996-10-16 2000-01-11 Samsung Electronics Co., Ltd. Methods for forming an amorphous tantalum nitride film
US6017817A (en) * 1999-05-10 2000-01-25 United Microelectronics Corp. Method of fabricating dual damascene
US6023102A (en) * 1997-07-17 2000-02-08 Sharp Laboratories Of America, Inc. Low resistance contact between circuit metal levels
US6028003A (en) * 1997-07-03 2000-02-22 Motorola, Inc. Method of forming an interconnect structure with a graded composition using a nitrided target
US6143646A (en) * 1997-06-03 2000-11-07 Motorola Inc. Dual in-laid integrated circuit structure with selectively positioned low-K dielectric isolation and method of formation
US6157081A (en) * 1999-03-10 2000-12-05 Advanced Micro Devices, Inc. High-reliability damascene interconnect formation for semiconductor fabrication
US6157061A (en) * 1997-08-29 2000-12-05 Nec Corporation Nonvolatile semiconductor memory device and method of manufacturing the same
US6164138A (en) * 1997-04-15 2000-12-26 Dresser Industries, Inc. Self aligning dial for instrument gauge
US6164128A (en) * 1999-10-13 2000-12-26 Santa Cruz; Cathy D. Apparatus, method and formula relating to total-wind statistics
US6166423A (en) * 1998-01-15 2000-12-26 International Business Machines Corporation Integrated circuit having a via and a capacitor
US6184128B1 (en) * 2000-01-31 2001-02-06 Advanced Micro Devices, Inc. Method using a thin resist mask for dual damascene stop layer etch
US6184138B1 (en) * 1999-09-07 2001-02-06 Chartered Semiconductor Manufacturing Ltd. Method to create a controllable and reproducible dual copper damascene structure
US6200433B1 (en) * 1999-11-01 2001-03-13 Applied Materials, Inc. IMP technology with heavy gas sputtering
US6211071B1 (en) * 1999-04-22 2001-04-03 Advanced Micro Devices, Inc. Optimized trench/via profile for damascene filling
US6221775B1 (en) * 1998-09-24 2001-04-24 International Business Machines Corp. Combined chemical mechanical polishing and reactive ion etching process
US6229174B1 (en) * 1997-12-08 2001-05-08 Micron Technology, Inc. Contact structure for memory device
US6265757B1 (en) * 1999-11-09 2001-07-24 Agere Systems Guardian Corp. Forming attached features on a semiconductor substrate
US6268283B1 (en) * 1999-01-06 2001-07-31 United Microelectronics Corp. Method for forming dual damascene structure
US6271084B1 (en) * 2001-01-16 2001-08-07 Taiwan Semiconductor Manufacturing Company Method of fabricating a metal-insulator-metal (MIM), capacitor structure using a damascene process
US6271592B1 (en) * 1998-02-24 2001-08-07 Applied Materials, Inc. Sputter deposited barrier layers
US6274483B1 (en) * 2000-01-18 2001-08-14 Taiwan Semiconductor Manufacturing Company Method to improve metal line adhesion by trench corner shape modification
US6297114B1 (en) * 1995-07-05 2001-10-02 Sharp Kabushiki Kaisha Semiconductor device and process and apparatus of fabricating the same
US6309801B1 (en) * 1998-11-18 2001-10-30 U.S. Philips Corporation Method of manufacturing an electronic device comprising two layers of organic-containing material
US20020008611A1 (en) * 2000-05-12 2002-01-24 Luc Wuidart Validation of the presence of an electromagnetic transponder in the field of an amplitude demodulation reader
US6498091B1 (en) * 2000-11-01 2002-12-24 Applied Materials, Inc. Method of using a barrier sputter reactor to remove an underlying barrier layer
US6509267B1 (en) * 2001-06-20 2003-01-21 Advanced Micro Devices, Inc. Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer
US20030049931A1 (en) * 2001-09-19 2003-03-13 Applied Materials, Inc. Formation of refractory metal nitrides using chemisorption techniques
US20030059538A1 (en) * 2001-09-26 2003-03-27 Applied Materials, Inc. Integration of barrier layer and seed layer
US6562715B1 (en) * 2000-08-09 2003-05-13 Applied Materials, Inc. Barrier layer structure for copper metallization and method of forming the structure
US6586334B2 (en) * 2000-11-09 2003-07-01 Texas Instruments Incorporated Reducing copper line resistivity by smoothing trench and via sidewalls
US6607977B1 (en) * 2001-03-13 2003-08-19 Novellus Systems, Inc. Method of depositing a diffusion barrier for copper interconnect applications
US6727177B1 (en) * 2001-10-18 2004-04-27 Lsi Logic Corporation Multi-step process for forming a barrier film for use in copper layer formation

Family Cites Families (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US185370A (en) * 1876-12-12 Improvement in bungs and bushes
US29958A (en) * 1860-09-11 Brick-mold
US87520A (en) * 1869-03-02 Improved rocking-chair
US3607384A (en) * 1968-07-11 1971-09-21 Western Electric Co Thin-film resistors having positive resistivity profiles
US4169032A (en) * 1978-05-24 1979-09-25 International Business Machines Corporation Method of making a thin film thermal print head
DE3063506D1 (en) * 1979-08-31 1983-07-07 Fujitsu Ltd A tantalum thin film capacitor and process for producing the same
US4419202A (en) * 1980-12-22 1983-12-06 The Secretary Of State For Defence In Her Britannic Majesty's Government Of The United Kingdom Of Great Britain And Northern Ireland Metal coatings
US4491509A (en) * 1984-03-09 1985-01-01 At&T Technologies, Inc. Methods of and apparatus for sputtering material onto a substrate
US4760369A (en) * 1985-08-23 1988-07-26 Texas Instruments Incorporated Thin film resistor and method
US4951601A (en) * 1986-12-19 1990-08-28 Applied Materials, Inc. Multi-chamber integrated process system
US4782380A (en) * 1987-01-22 1988-11-01 Advanced Micro Devices, Inc. Multilayer interconnection for integrated circuit structure having two or more conductive metal layers
US4962060A (en) * 1987-03-10 1990-10-09 Advanced Micro Devices, Inc. Making a high speed interconnect system with refractory non-dogbone contacts and an active electromigration suppression mechanism
JP2602276B2 (en) * 1987-06-30 1997-04-23 株式会社日立製作所 Supatsutaringu method and apparatus
US5186718A (en) * 1989-05-19 1993-02-16 Applied Materials, Inc. Staged-vacuum wafer processing system and method
US5178739A (en) * 1990-10-31 1993-01-12 International Business Machines Corporation Apparatus for depositing material into high aspect ratio holes
JPH05179437A (en) 1991-01-18 1993-07-20 Citizen Watch Co Ltd Formation of tantalum film
JP2785919B2 (en) * 1991-07-26 1998-08-13 ローム株式会社 Method of manufacturing a semiconductor device having a grown layer on the insulating layer
CA2067565C (en) * 1992-04-29 1999-02-16 Ismail T. Emesh Deposition of tungsten
US5371042A (en) * 1992-06-16 1994-12-06 Applied Materials, Inc. Method of filling contacts in semiconductor devices
US5397962A (en) * 1992-06-29 1995-03-14 Texas Instruments Incorporated Source and method for generating high-density plasma with inductive power coupling
US5486492A (en) * 1992-10-30 1996-01-23 Kawasaki Steel Corporation Method of forming multilayered wiring structure in semiconductor device
US5354712A (en) * 1992-11-12 1994-10-11 Northern Telecom Limited Method for forming interconnect structures for integrated circuits
US5391517A (en) * 1993-09-13 1995-02-21 Motorola Inc. Process for forming copper interconnect structure
US5654232A (en) * 1994-08-24 1997-08-05 Intel Corporation Wetting layer sidewalls to promote copper reflow into grooves
US5613296A (en) * 1995-04-13 1997-03-25 Texas Instruments Incorporated Method for concurrent formation of contact and via holes
US5534460A (en) * 1995-04-27 1996-07-09 Vanguard International Semiconductor Corp. Optimized contact plug process
US5565074A (en) * 1995-07-27 1996-10-15 Applied Materials, Inc. Plasma reactor with a segmented balanced electrode for sputtering process materials from a target surface
KR0175030B1 (en) * 1995-12-07 1999-04-01 김광호 How high-melting metal wire structure and the formation of the semiconductor element
KR0179795B1 (en) 1995-12-28 1999-04-15 문정환 Method of diffusion barrier film
US5674787A (en) * 1996-01-16 1997-10-07 Sematech, Inc. Selective electroless copper deposited interconnect plugs for ULSI applications
US6008117A (en) * 1996-03-29 1999-12-28 Texas Instruments Incorporated Method of forming diffusion barriers encapsulating copper
US5602053A (en) * 1996-04-08 1997-02-11 Chartered Semidconductor Manufacturing Pte, Ltd. Method of making a dual damascene antifuse structure
US5846332A (en) * 1996-07-12 1998-12-08 Applied Materials, Inc. Thermally floating pedestal collar in a chemical vapor deposition chamber
JPH1041389A (en) * 1996-07-24 1998-02-13 Sony Corp Manufacture of semiconductor device
US6093639A (en) * 1996-10-30 2000-07-25 United Microelectronics Corp. Process for making contact plug
US5818110A (en) * 1996-11-22 1998-10-06 International Business Machines Corporation Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same
US6139699A (en) 1997-05-27 2000-10-31 Applied Materials, Inc. Sputtering methods for depositing stress tunable tantalum and tantalum nitride films
US5910880A (en) * 1997-08-20 1999-06-08 Micron Technology, Inc. Semiconductor circuit components and capacitors
WO1999027579A1 (en) * 1997-11-26 1999-06-03 Applied Materials, Inc. Damage-free sculptured coating deposition
US6372301B1 (en) 1998-12-22 2002-04-16 Applied Materials, Inc. Method of improving adhesion of diffusion layers on fluorinated silicon dioxide
WO2000041235A1 (en) 1999-01-08 2000-07-13 Applied Materials, Inc. Method of depositing a copper seed layer which promotes improved feature surface coverage
US6451177B1 (en) * 2000-01-21 2002-09-17 Applied Materials, Inc. Vault shaped target and magnetron operable in two sputtering modes
JP3967879B2 (en) * 2000-11-16 2007-08-29 株式会社ルネサステクノロジ Method for producing a copper plating solution and a semiconductor integrated circuit device using the same
US6949450B2 (en) * 2000-12-06 2005-09-27 Novellus Systems, Inc. Method for integrated in-situ cleaning and subsequent atomic layer deposition within a single processing chamber

Patent Citations (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5308793A (en) * 1991-07-24 1994-05-03 Sony Corporation Method for forming interconnector
US5989999A (en) * 1994-11-14 1999-11-23 Applied Materials, Inc. Construction of a tantalum nitride film on a semiconductor wafer
US6007684A (en) * 1995-06-07 1999-12-28 Applied Materials, Inc. Process for forming improved titanium-containing barrier layers
US5972178A (en) * 1995-06-07 1999-10-26 Applied Materials, Inc. Continuous process for forming improved titanium nitride barrier layers
US6297114B1 (en) * 1995-07-05 2001-10-02 Sharp Kabushiki Kaisha Semiconductor device and process and apparatus of fabricating the same
US5993916A (en) * 1996-07-12 1999-11-30 Applied Materials, Inc. Method for substrate processing with improved throughput and yield
US6013576A (en) * 1996-10-16 2000-01-11 Samsung Electronics Co., Ltd. Methods for forming an amorphous tantalum nitride film
US5933753A (en) * 1996-12-16 1999-08-03 International Business Machines Corporation Open-bottomed via liner structure and method for fabricating same
US5913147A (en) * 1997-01-21 1999-06-15 Advanced Micro Devices, Inc. Method for fabricating copper-aluminum metallization
US5930669A (en) * 1997-04-03 1999-07-27 International Business Machines Corporation Continuous highly conductive metal wiring structures and method for fabricating the same
US6164138A (en) * 1997-04-15 2000-12-26 Dresser Industries, Inc. Self aligning dial for instrument gauge
US5985762A (en) * 1997-05-19 1999-11-16 International Business Machines Corporation Method of forming a self-aligned copper diffusion barrier in vias
US6143646A (en) * 1997-06-03 2000-11-07 Motorola Inc. Dual in-laid integrated circuit structure with selectively positioned low-K dielectric isolation and method of formation
US6028003A (en) * 1997-07-03 2000-02-22 Motorola, Inc. Method of forming an interconnect structure with a graded composition using a nitrided target
US6023102A (en) * 1997-07-17 2000-02-08 Sharp Laboratories Of America, Inc. Low resistance contact between circuit metal levels
US6157061A (en) * 1997-08-29 2000-12-05 Nec Corporation Nonvolatile semiconductor memory device and method of manufacturing the same
US5972179A (en) * 1997-09-30 1999-10-26 Lucent Technologies Inc. Silicon IC contacts using composite TiN barrier layer
US6229174B1 (en) * 1997-12-08 2001-05-08 Micron Technology, Inc. Contact structure for memory device
US6002174A (en) * 1997-12-31 1999-12-14 Micron Technology, Inc. Barrier materials for semiconductor devices
US6166423A (en) * 1998-01-15 2000-12-26 International Business Machines Corporation Integrated circuit having a via and a capacitor
US6271592B1 (en) * 1998-02-24 2001-08-07 Applied Materials, Inc. Sputter deposited barrier layers
US6221775B1 (en) * 1998-09-24 2001-04-24 International Business Machines Corp. Combined chemical mechanical polishing and reactive ion etching process
US6309801B1 (en) * 1998-11-18 2001-10-30 U.S. Philips Corporation Method of manufacturing an electronic device comprising two layers of organic-containing material
US6268283B1 (en) * 1999-01-06 2001-07-31 United Microelectronics Corp. Method for forming dual damascene structure
US6157081A (en) * 1999-03-10 2000-12-05 Advanced Micro Devices, Inc. High-reliability damascene interconnect formation for semiconductor fabrication
US6211071B1 (en) * 1999-04-22 2001-04-03 Advanced Micro Devices, Inc. Optimized trench/via profile for damascene filling
US6017817A (en) * 1999-05-10 2000-01-25 United Microelectronics Corp. Method of fabricating dual damascene
US6184138B1 (en) * 1999-09-07 2001-02-06 Chartered Semiconductor Manufacturing Ltd. Method to create a controllable and reproducible dual copper damascene structure
US6164128A (en) * 1999-10-13 2000-12-26 Santa Cruz; Cathy D. Apparatus, method and formula relating to total-wind statistics
US6200433B1 (en) * 1999-11-01 2001-03-13 Applied Materials, Inc. IMP technology with heavy gas sputtering
US6265757B1 (en) * 1999-11-09 2001-07-24 Agere Systems Guardian Corp. Forming attached features on a semiconductor substrate
US6274483B1 (en) * 2000-01-18 2001-08-14 Taiwan Semiconductor Manufacturing Company Method to improve metal line adhesion by trench corner shape modification
US6184128B1 (en) * 2000-01-31 2001-02-06 Advanced Micro Devices, Inc. Method using a thin resist mask for dual damascene stop layer etch
US20020008611A1 (en) * 2000-05-12 2002-01-24 Luc Wuidart Validation of the presence of an electromagnetic transponder in the field of an amplitude demodulation reader
US6562715B1 (en) * 2000-08-09 2003-05-13 Applied Materials, Inc. Barrier layer structure for copper metallization and method of forming the structure
US6498091B1 (en) * 2000-11-01 2002-12-24 Applied Materials, Inc. Method of using a barrier sputter reactor to remove an underlying barrier layer
US6586334B2 (en) * 2000-11-09 2003-07-01 Texas Instruments Incorporated Reducing copper line resistivity by smoothing trench and via sidewalls
US6271084B1 (en) * 2001-01-16 2001-08-07 Taiwan Semiconductor Manufacturing Company Method of fabricating a metal-insulator-metal (MIM), capacitor structure using a damascene process
US6607977B1 (en) * 2001-03-13 2003-08-19 Novellus Systems, Inc. Method of depositing a diffusion barrier for copper interconnect applications
US6509267B1 (en) * 2001-06-20 2003-01-21 Advanced Micro Devices, Inc. Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer
US20030049931A1 (en) * 2001-09-19 2003-03-13 Applied Materials, Inc. Formation of refractory metal nitrides using chemisorption techniques
US20030059538A1 (en) * 2001-09-26 2003-03-27 Applied Materials, Inc. Integration of barrier layer and seed layer
US6727177B1 (en) * 2001-10-18 2004-04-27 Lsi Logic Corporation Multi-step process for forming a barrier film for use in copper layer formation

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7589029B2 (en) * 2002-05-02 2009-09-15 Micron Technology, Inc. Atomic layer deposition and conversion
US20080008823A1 (en) * 2003-01-07 2008-01-10 Ling Chen Deposition processes for tungsten-containing barrier layers
US7507660B2 (en) * 2003-01-07 2009-03-24 Applied Materials, Inc. Deposition processes for tungsten-containing barrier layers
US8288809B2 (en) 2004-08-02 2012-10-16 Micron Technology, Inc. Zirconium-doped tantalum oxide films
US8765616B2 (en) 2004-08-02 2014-07-01 Micron Technology, Inc. Zirconium-doped tantalum oxide films
US7727905B2 (en) 2004-08-02 2010-06-01 Micron Technology, Inc. Zirconium-doped tantalum oxide films
US7776762B2 (en) 2004-08-02 2010-08-17 Micron Technology, Inc. Zirconium-doped tantalum oxide films
US20070087563A1 (en) * 2004-08-02 2007-04-19 Micron Technology, Inc. Zirconium-doped tantalum oxide films
US7687409B2 (en) 2005-03-29 2010-03-30 Micron Technology, Inc. Atomic layer deposited titanium silicon oxide films
US8399365B2 (en) 2005-03-29 2013-03-19 Micron Technology, Inc. Methods of forming titanium silicon oxide
US8076249B2 (en) 2005-03-29 2011-12-13 Micron Technology, Inc. Structures containing titanium silicon oxide
US8501563B2 (en) 2005-07-20 2013-08-06 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US8921914B2 (en) 2005-07-20 2014-12-30 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US7745327B2 (en) * 2007-01-31 2010-06-29 Advanced Micro Devices, Inc. Method of forming a copper-based metallization layer including a conductive cap layer by an advanced integration regime
US20080182406A1 (en) * 2007-01-31 2008-07-31 Axel Preusse Method of forming a copper-based metallization layer including a conductive cap layer by an advanced integration regime
US8772077B2 (en) * 2008-04-18 2014-07-08 Ips Ltd. Method of forming chalcogenide thin film
US20110027976A1 (en) * 2008-04-18 2011-02-03 Ips Ltd. Method of forming chalcogenide thin film
CN102005411A (en) * 2009-09-01 2011-04-06 中芯国际集成电路制造(上海)有限公司 Forming method for barrier layer
US20120251967A1 (en) * 2011-03-29 2012-10-04 Tokyo Electron Limited Loading unit and processing system

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