US20070066024A1 - Phosphorus Activated NMOS Using SiC Process - Google Patents

Phosphorus Activated NMOS Using SiC Process Download PDF

Info

Publication number
US20070066024A1
US20070066024A1 US11/558,179 US55817906A US2007066024A1 US 20070066024 A1 US20070066024 A1 US 20070066024A1 US 55817906 A US55817906 A US 55817906A US 2007066024 A1 US2007066024 A1 US 2007066024A1
Authority
US
United States
Prior art keywords
forming
substrate
source
gate structure
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11/558,179
Inventor
Srinivasan Chakravarthi
P. Chidambaram
Original Assignee
Srinivasan Chakravarthi
Chidambaram P R
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US10/943,278 priority Critical patent/US7179696B2/en
Application filed by Srinivasan Chakravarthi, Chidambaram P R filed Critical Srinivasan Chakravarthi
Priority to US11/558,179 priority patent/US20070066024A1/en
Publication of US20070066024A1 publication Critical patent/US20070066024A1/en
Application status is Abandoned legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66636Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66651Lateral single gate silicon transistors with a single crystalline channel formed on the silicon substrate after insulating device isolation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A method (10) of forming a transistor (100) includes treating (12) at least some of a semiconductor substrate (102) with carbon and then forming (18) a gate structure (114) over the semiconductor substrate. A channel region (122) is thereby being defined within the semiconductor substrate (102) below the gate structure (114). Source and drain regions (140, 142) are then formed (26) within the semiconductor substrate (102) on opposing sides of the channel (122) with a phosphorus dopant.

Description

    FIELD OF INVENTION
  • The present invention relates generally to semiconductor fabrication and more particularly to utilizing a phosphorus dopant in a semiconductor substrate that has been treated to include silicon carbon material in a transistor fabrication process.
  • BACKGROUND OF THE INVENTION
  • A conventional MOS transistor generally includes a semiconductor substrate, such as silicon, having a gate structure or gate stack formed there-over. The gate structure comprises a conductive gate electrode overlying a thin gate dielectric. The gate electrode typically includes polysilicon and the gate dielectric an oxide based material. Source and drain regions are formed in the substrate substantially aligned with the gate structure. The source and drain regions are generally formed by applying a dopant to the select regions of the substrate. A channel is defined within the substrate under the gate structure between the source and drain regions.
  • A voltage applied to the gate electrode induces an electric field across the channel of the MOS transistor, and the amount of current that flows through the channel is directly proportional to an activation level of the source and drain regions. Thus, the higher the activation level of the source and drain regions, the more current can flow and the faster a circuit can perform wherein such a MOS transistor is incorporated. Phosphorous is a dopant that causes source and drain regions to have a high activation level as compared to conventional source/drain dopants, such as arsenic, for example. However, phosphorus has a high diffusity which can lead to non-abrupt junctions. Non-abrupt junctions can be detrimental to the performance of the transistor by adversely affecting channel characteristics, injection velocity, carrier mobility and/or drive current.
  • It would thus be advantageous to have a phosphorus doped transistor wherein diffusity is substantially mitigated.
  • SUMMARY OF THE INVENTION
  • The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended neither to identify key or critical elements of the invention nor to delineate the scope of the invention. Rather, its primary purpose is merely to present one or more concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
  • The present invention relates to a device and method of fabrication, wherein a transistor device exhibits a high level of activity due to the use of phosphorus as a source/drain dopant. One or more portions of a silicon substrate upon which the device is formed are treated to include carbon which mitigates the proclivity of phosphorus to diffuse. In this manner, a transistor device having a high level of activity is produced having more abrupt junctions. As such, channel characteristics, injection velocity, carrier mobility and/or drive current are thereby enhanced. Further, the carbon within the substrate may produce a tensile stress therein which may further enhance mobility and lower channel resistance.
  • To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth and detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which one or more aspects of the present invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the annexed drawings.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a flow chart illustrating an exemplary methodology of forming a transistor according to one or more aspects of the present invention.
  • FIGS. 2-10 are a plurality of fragmentary cross sectional diagrams illustrating a transistor device being formed in accordance with the methodology set forth in FIG. 1.
  • FIG. 11 is a flow chart illustrating another exemplary methodology of forming a transistor according to one or more aspects of the present invention.
  • FIGS. 12-20 are a plurality of fragmentary cross sectional diagrams illustrating a transistor device being formed in accordance with the methodology set forth in FIG. 11.
  • FIG. 21 is a flow chart illustrating yet another exemplary methodology of forming a transistor in accordance with one or more aspects of the present invention.
  • FIGS. 22-27 are a plurality of fragmentary cross sectional diagrams illustrating a transistor device being formed in accordance with the methodology set forth in FIG. 21.
  • FIG. 28 is a flow chart illustrating still another exemplary methodology of forming a transistor according to one or more aspects of the present invention.
  • FIGS. 29-34 are a plurality of fragmentary cross sectional diagrams illustrating a transistor device being formed in accordance with the methodology set forth in FIG. 28.
  • DETAILED DESCRIPTION OF THE INVENTION
  • One or more aspects of the present invention are described with reference to the drawings, wherein like reference numerals are generally utilized to refer to like elements throughout, and wherein the various structures are not necessarily drawn to scale. It will be appreciated that where like acts, events, elements, layers, structures, etc. are reproduced in the Figs., subsequent (redundant) discussions of the same may be omitted for the sake of brevity. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects of the present invention. It may be evident, however, to one of ordinary skill in the art that one or more aspects of the present invention may be practiced with a lesser degree of these specific details. In other instances, known structures are shown in diagrammatic form in order to facilitate describing one or more aspects of the present invention.
  • The present invention relates to forming a transistor in a manner that mitigates phosphorus diffusion. In particular, a phosphorus dopant is utilized in forming source and drain regions of the transistor. To mitigate phosphorus diffusion, a substrate into which the phosphorus is implanted and in which the source and drain regions are formed is treated to include carbon prior to the source/drain implantation. The carbon acts as a gettering agent for phosphorus interstitials that have a tendency to diffuse. In this manner, the highly active phosphorus can be desirably implanted while the carbon facilitates maintaining substantially abrupt source/drain junctions. Further, the carbon may produce a tensile stress within the substrate that may further enhance carrier mobility and lower channel resistance.
  • Turning to FIGS. 1-10, an exemplary methodology 10 is illustrated for forming a transistor 100 (FIG. 10) according to one or more aspects of the present invention, wherein FIG. 1 illustrates the exemplary methodology 10 and FIGS. 2-10 illustrate the exemplary transistor device at various stages of fabrication. Although the methodology 10 is illustrated and described hereinafter as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated steps may be required to implement a methodology in accordance with one or more aspects of the present invention. Further, one or more of the acts may be carried out in one or more separate acts or phases. It will be appreciated that a methodology carried out according to one or more aspects of the present invention may be implemented in association with the formation and/or processing of structures illustrated and described herein as well as in association with other structures not illustrated or described herein.
  • The methodology 10 begins at 12 wherein a semiconductor substrate 102 is treated to include carbon to produce a layer of silicon carbon material 104 over or at a top portion of the substrate. (FIG. 2). It is to be appreciated that substrate or semiconductor substrate as used herein can include a base semiconductor wafer or any portion thereof (e.g., one or more wafer die) as well as any epitaxial layers or other type of semiconductor layers formed thereover and/or associated therewith. The substrate can comprise, for example, silicon, silicon germanium, etc. The silicon carbon layer 104 may be formed to a thickness of between about 400 angstroms to about 600 angstroms via an epitaxial process performed over an entire wafer, for example. Epitaxy is a process by which a thin layer of single-crystal material is deposited on a single-crystal substrate. Epitaxial growth occurs in such way that the crystallographic structure of the substrate is reproduced in the growing material.
  • To establish the silicon carbon layer 104, a carbon containing source gas such as HCl and/or disilane can be added to an epitaxial deposition chamber, for example, such that carbon is incorporated into the silicon in-situ. It will be appreciated that doing a silicon carbide epi deposition is different from masking off an area and doing a carbon implant because different equipment is used and the amount of carbon obtainable is much higher. For example, the amount of carbon produced within/upon the substrate in accordance with one or more aspects of the present invention, may be on the order of about 0.5 to about 2 atomic percent for a layer having a thickness of between about 100 to about 300 angstroms. Such a concentration of carbon may provide a tensile strain in the substrate, and more particularly within a channel region established within the substrate (discussed below), of about 300 megapascals to about 2 gigapascals, for example, where such a tensile strain can improve electron mobility within the channel and thus the operating speed of a resulting NMOS transistor.
  • The methodology 10 then advances to 14, wherein a layer of silicon capping material 106 is formed over the carbon including semiconductor substrate (FIG. 3). For example, a subsequent silicon deposition may be performed within the same processing chamber with the carbon source (e.g., HCl feed gas) turned off. The layer of silicon capping material 106 may be formed to a thickness of between about 100 angstroms to about 400 angstroms, for example, depending upon the device being formed and how it is to be optimized. In this manner, the silicon carbide layer 104 is operative to provide stress to the channel region established within the substrate (discussed below), while not giving rise to contamination issues within the channel.
  • An isolation process (e.g., STI, LOCOS) is then performed at 16 to establish areas of dielectric material 110 within the substrate 102 (FIG. 4). The isolation regions 110 electrically isolate active regions from one another (e.g., the region where the transistor is formed). The isolation process is, however, generally performed at a relatively high temperature (e.g., on the order of about 1000 degrees Celsius for about 30 minutes), which can deactivate the carbon. Thus, amorphizing dopants (not shown) may be implanted to reactivate the carbon. By way of example, Germanium can be implanted at about 1E14 atoms/cm3 and/or Indium can be implanted at about 1E13 atoms/cm3. Such amorphizing implants can be implanted along with VtADJUST implants (not shown) that are utilized to adjust a threshold voltage at which the transistor begins to conduct current or “turns on”.
  • Subsequently, at 18, a gate structure or gate stack 114 is formed over the layer of capping material 106 and silicon carbon layer 104 (FIG. 5). Although not shown, it will be appreciated that the gate structure 114 is created by forming a layer of gate dielectric material over the layer of capping material 106, and then forming a layer of gate electrode material over the layer of gate dielectric material. The layer of gate dielectric material can include any of a number of suitable dielectric or non-conductive materials. Some examples include silicon dioxide, high-k dielectric materials, or a stack of such layers. By way of further example, the layer of gate dielectric material may include any one or more of the following, either alone or in combination: SiO2, aluminum oxide (Al2O3), zirconium silicate, hafnium silicate, hafnium silicon oxynitride, hafnium oxynitride, zirconium oxynitride, zirconium silicon oxynitride, hafnium silicon nitride, lanthanum oxide (La2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), cerium oxide (CeO2), bismuth silicon oxide (Bi4Si2O12), titanium dioxide (TiO2), tantalum oxide (Ta2O5), tungsten oxide (WO3), yttrium oxide (Y2O3), lanthanum aluminum oxide (LaAlO3), barium strontium titanate, barium strontium oxide, barium titanate, strontium titanate, PbZrO3, PST, PZN, PZT and PMN.
  • Additionally, the layer of gate dielectric material can be formed to a thickness of about 1 nanometer or more, and can have an equivalent oxide thickness (EOT) of about 1 nanometer or less, for example, while the gate electrode layer can be formed to a thickness of between about 50 to about 200 nanometers, for example. The gate electrode layer generally includes polysilicon, SiGe and/or metal. The gate electrode and gate dielectric layers are then patterned to establish the gate stack 114. Generally, the layer of gate electrode material is patterned first and the layer of gate dielectric material becomes at least partially patterned as part of this process. For example, an etchant utilized to pattern the layer of gate electrode material may also remove some of the layer of gate dielectric material. Similarly, clean up steps associated with patterning the layer of gate electrode material as well as clean up steps associated with a hard mask removal process may also remove some of the layer of gate dielectric material. The gate structure or stack 114 is thereby established which comprises a gate dielectric 116 under a gate electrode 118. The gate electrode 118 is somewhat electrically conductive, and may be made more conductive via doping. The gate electrode 118 provides a contact area or surface for applying a voltage to the transistor. Additionally, a channel region 122 is defined within the substrate under the gate stack 114.
  • Offset spacers 124 are then formed adjacent to the gate structure 114 at 20 (FIG. 6). For example, a thin layer of offset material (e.g., oxide and/or nitride) is formed generally conformally over the patterned gate structure 114 and then etched using a generally directional etch, such as an anisotropic dry etch, for example, to remove the layer of offset material at all places other than adjacent to the gate structure 114. As such, thin offset spacers 124 are left on lateral edges of the gate stack 114. Such spacers 124 may have a width of between about 10 angstroms to about 50 nanometers, for example.
  • A source/drain extension region implant, for example, is then performed at 22 to establish extension regions 130 on opposing sides of the channel region 122 (FIG. 6). According to one or more aspects of the present invention a phosphorus dopant is utilized in forming the extension regions. It will be appreciated that lightly doped, medium doped or heavily doped extension region implants may be performed wherein the offset spacers 124 block the dopant materials so that the extension regions 130 are substantially self aligned with the offset spacers 124. A thermal process, such as a rapid thermal anneal, for example, may then be employed to activate the extension region dopants, which may cause the extension regions 130 to diffuse laterally underneath the offset spacers 124 and even slightly under the gate structure 114 toward the channel 122 (FIG. 7). It will be appreciated that the extension region may be between about 150 angstroms to about 400 angstroms thick after diffusion, for example.
  • Sidewall spacers 134 are then formed on the offset spacers 124 at 24 (FIG. 8). The sidewall spacers comprise an insulating material such as an oxide, a nitride or a combination of such layers. The spacers 134 are formed by depositing a layer of such spacer material(s) in a generally conformal manner, followed by a directional (e.g., anisotropic) etch thereof, thereby removing such spacer material at all locations except adjacent to the offset spacers 124. The sidewall spacers 134 are substantially thicker than the offset spacers 124, and may have a thickness of between about 40 nanometers to about 140 nanometers, for example.
  • Source and drain regions 140, 142 are then formed by implanting a phosphorus dopant within the substrate at 26 (FIG. 9). The source/drain dopants are blocked by the sidewall spacers 134 so that the source and drain regions 140, 142 are substantially aligned with the sidewall spacers 134. Generally the source/drain dopants are implanted at a higher energy and/or concentration than the extension region implants so that the source and drain regions 140, 142 are formed to a greater depth and/or concentration than the extension regions 130. The source and drain regions 140, 142 may be formed to a depth of between about 500 angstroms to about 1500 angstroms, for example.
  • A thermal (annealing) process is then employed at 28 to activate the source/drain dopants, which may cause some lateral diffusion thereof (e.g., under the sidewall spacers 134, and toward the channel 122) (FIG. 10). The methodology 10 then advances to 30 wherein further back end processing can be performed, such as siliciding, for example. It will be appreciated that one or more aspects of the present invention are advantageous because while phosphorus is desirable as a dopant due to its high activity, its propensity to diffuse can lead to non-abrupt junctions (e.g., between the source and drain regions 140, 142 and the channel region 122), which can adversely affect transistor performance. Thus, treating the substrate to include carbon as disclosed herein allows the desirable properties of phosphorus to be taken advantage of while maintaining substantially abrupt junctions.
  • By way of further discussion, phosphorus is thought to diffuse primarily by an interstitial mechanism. More particularly, while not intending to be limited to any one theory, it is believed that phosphorus has a higher diffusity as compared to more conventional dopants because it is generally smaller in size. For example, a phosphorus atom is generally smaller than an arsenic atom. As such, the larger arsenic atom is more prone to come to “rest” or reside within a vacancy in the silicon lattice structure, where such a vacancy may be created, for example, when the dopant atoms are implanted into the substrate thereby disturbing the lattice structure. Some of the dopant atoms that bombard the substrate result in interstitials or atoms that are un-attached (e.g., those that do not fill respective vacancies). Due to its (smaller) size, phosphorus atoms have a greater tendency to remain as interstitials. Carbon tends to reduce the diffusion of phosphorus because the carbon acts as a sink or gettering agent for interstitials and thereby captures at least some of the phosphorus interstitials. Thus, interstitial atoms gettered by carbon atoms have a lower diffusity due to their (larger) size, for example. Additionally, carbon interstitials readily react with other carbon atoms to form an immobile pair. This is because carbon interstitials diffuse faster than substitutional carbon. Accordingly, utilizing phosphorus in forming a transistor on a carbon containing substrate in accordance with one or more aspects of the present invention reduces the number of phosphorus interstitials thereby making the phosphorus diffuse less aggressively, which in turn facilitates the creation of more abrupt junctions.
  • Turning to FIGS. 11-20, another exemplary methodology 10′ is illustrated for forming a MOS transistor 100′ (FIG. 20) in accordance with one or more aspects of the present invention, wherein FIG. 11 illustrates the exemplary methodology 10′ and FIGS. 12-20 illustrate the exemplary transistor device at various stages of fabrication. Many of the acts of methodology 10′ are similar to those of methodology 10 and thus are addressed with the same reference characters, but having a prime “′” notation. Similarly, many of the layers, elements, etc. within the corresponding cross sectional FIGS. 12-20 are similar to those referred to within FIGS. 2-10 with regard to methodology 10 and thus are also labeled with the same reference characters, but also having a prime “′” designation. For purposes of brevity where the same layers, features, elements, acts, etc. of methodology 10 are reproduced in methodology 10′ and the accompanying figures, they are not once again elaborated upon.
  • At 16′ isolation regions 110′ are formed within a substrate 102′ to separate electrically active regions from one another (FIG. 12). For example, the substrate 102′ can be selectively etched and dielectric materials can be formed within the etched areas to form the isolation regions 110′. A VtADJUST implant is then performed at 15′ for setting or adjusting a threshold voltage of the transistor. As such, VtADJUST dopant atoms 111′ are established within the substrate 102′ (FIG. 12). The substrate 102′ is then subjected to an optional etching process at 8′ to form a recess 113′ therein to a depth 109′ of between about 200 angstroms to about 600 angstroms, for example (FIG. 13). The recess 113′ is then filled with a silicon carbon material 104′ at 12′ (e.g., via an epitaxial process) (FIG. 14). It will be appreciated that the etching at 8′ is optional because the layer of silicon carbon material 104′ can be formed directly onto the substrate 102′ as discussed above with regard to FIG. 2. Further, the VtADJUST implant is likewise optional and may also be performed before the isolation regions 110′ are formed at 16′ as well as after the silicon carbon material 104′ is formed at 12′. Should dopant atoms be implanted before isolation regions are formed, subsequent amorphizing can be performed to re-activate the dopant atoms that may have become de-activated during the (high temperature) isolation processing.
  • A layer of silicon capping material 106′ is then formed over the layer of silicon carbon material at 14′ (FIG. 15). A gate structure or gate stack 114′ is subsequently formed over the layer of capping material 106′ at 18′ (FIG. 16). The gate structure 114′ comprises a gate dielectric 116′ under a gate electrode 118′ and defines a channel region 122′ thereunder within the substrate 102′. Offset spacers 124′ are formed adjacent to the gate structure 114′ at 20′ (FIG. 17). Source/drain extension regions 130′ are then formed at 22′ within the substrate 102′ on opposing sides of the channel region 122′ with the offset spacers 124′ serving as guides (FIG. 17). According to one or more aspects of the present invention, the extension regions 130′ are formed with a phosphorus dopant. A thermal (anneal) may be performed to activate the dopants within the extension regions 130′ which may cause the extension regions 130′ to diffuse laterally under the offset spacers 124′ toward the channel region 122′ (FIG. 18).
  • Sidewall spacers 134′ are then formed on the offset spacers 124′ at 24′ (FIG. 18). Source and drain regions 140′, 142′ are then formed within the substrate 102′ on opposing sides of the channel region 122′ with the sidewall spacers 134′ serving as guides (FIG. 19). According to one or more aspects of the present invention, the source and drain regions 140′, 142′ are formed with a phosphorus dopant. A thermal (anneal) is subsequently performed at 28′ to activate source/drain dopants which may cause the source and drain regions 140′, 142′ to diffuse laterally under the sidewall spacers 134′ toward the channel region 122′ (FIG. 20). The methodology 10′ then advances to 30′ wherein further back end processing can be performed, such as siliciding, for example. The carbon within the silicon mitigates phosphorus diffusion and thereby facilitates sharper junctions between the source and drain regions 140′, 142′ and the channel region 122′.
  • Turning to FIGS. 21-27, another exemplary methodology 10″ is illustrated for forming a MOS transistor 100″ (FIG. 27) in accordance with one or more aspects of the present invention, wherein FIG. 21 illustrates the exemplary methodology 10″ and FIGS. 22-27 illustrate the exemplary transistor device at various stages of fabrication. Many of the acts of methodology 10″ are similar to those of methodology 10 and thus are addressed with the same reference characters, but having a double prime “″” notation. Similarly, many of the layers, elements, etc. within the corresponding cross sectional FIGS. 22-27 are similar to those referenced within FIGS. 2-10 with regard to methodology 10 and thus are also labeled with the same reference characters, but also having a double prime “″” designation. For purposes of brevity the same layers, features, elements, acts, etc. of methodology 10 that are reproduced in methodology 10″ and the accompanying figures, are not discussed in great detail.
  • At 18″ a gate structure 114″ is formed over a substrate 102″ at the beginning of the methodology 10″ (FIG. 22). The gate structure 114″ is formed within an active area of the substrate 102″ which is electrically isolated from other active areas by isolation regions 110″ formed in and on the substrate 102″. Offset spacers 124″ are formed adjacent to the gate structure 114″ at 20″ (FIG. 23). Source/drain extension regions 130″ are then formed in the substrate 102″ on opposing sides of a channel region 122″ underlying the gate structure 114″ at 22″ (FIG. 23). The extension regions 130″ are formed with a phosphorus dopant and are generally aligned with the offset spacers 124″, but may creep under the spacers 124″ as a result of thermal processing (e.g., a high temperature anneal) (FIG. 23).
  • The substrate 102″ is then etched at 8″ to form recesses 113″ therein between the offset spacers 124″ and the isolation regions 110″ (FIG. 24). Such recesses may be formed to a depth 109″ of between about 200 angstroms to about 600 angstroms, for example. The recesses 113″ are then filled with silicon carbon material 104″ at 12″ (e.g., via an epitaxial process) (FIG. 25). Sidewall spacers 134″ are formed adjacent to the offset spacers 124″ at 24″ (FIG. 26). Source and drain regions 140″, 142″ are formed in the substrate 102″ at 26″ on opposing sides of the channel region 122″ at 26″ with a phosphorus dopant (FIG. 26). An anneal is then performed at 28″ to activate source/drain dopants which may cause the source and drain regions 140″, 142″ to diffuse laterally under the sidewall spacers 134″ toward the channel region 122″ (FIG. 27). The methodology 10″ then proceeds to 30″ wherein further back end processing can be performed.
  • Turning to FIGS. 28-34, yet another exemplary methodology 10′″ is illustrated for forming a MOS transistor 100″ (FIG. 34) in accordance with one or more aspects of the present invention, wherein FIG. 28 illustrates the exemplary methodology 10′″ and FIGS. 29-34 illustrate the exemplary transistor device at various stages of fabrication. Many of the acts of methodology 10′″ are similar to those of methodology 10 and thus are addressed with the same reference characters, but this time having a triple prime “′″” notation. Similarly, many of the layers, elements, etc. within the corresponding cross sectional FIGS. 29-34 are similar to those referenced within FIGS. 2-10 with regard to methodology 10 and thus are also labeled with the same reference characters, but also having a triple prime “′″” designation. For purposes of brevity the same layers, features, elements, acts, etc. of methodology 10 that are reproduced in methodology 10′″ and the accompanying figures, are discussed in substantially less detail.
  • At the outset, a gate structure 114′″ is formed over a substrate 102′″ at 18′″ (FIG. 29). The gate structure 114′″ is formed between isolation regions 110′″ formed in and on the substrate 102′″ that electrically isolate active regions from one another. At 20′″ offset spacers 124′″ are formed adjacent to the gate structure 114′″ (FIG. 30). At 22′″ source/drain extension regions 130′″ are formed in the substrate 102′″ on opposing sides of a channel region 122′″ underlying the gate structure 114′″ (FIG. 30). The extension regions 130′″ are formed with a phosphorus dopant and are generally aligned with the offset spacers 124′″, but may migrate under the spacers 124′″ as a result of a thermal anneal (FIG. 30). Sidewall spacers 134′″ are then formed adjacent to the offset spacers 124′″ at 24′″ (FIG. 31).
  • Recesses 113′″ are then formed within the substrate 102′″ (e.g., via etching) at 8′″ (FIG. 32). In this example, the recesses 113′″ are formed between the sidewall spacers 124′″ and the isolation regions 110′″ (FIG. 32). Such recesses may be formed to a depth 109′″ of between about 200 angstroms to about 600 angstroms, for example. The recesses 113′″ are then filled with silicon carbon material 104′″ at 12′″ (e.g., via an epitaxial deposition process) (FIG. 33). Source and drain regions 140′″, 142′″ are subsequently formed with a phosphorus dopant in the substrate 102′″ at 26′″ on opposing sides of the channel region 122′″ at 26′″ (FIG. 34). An anneal is then performed at 28′″ to activate source/drain dopants which may cause the source and drain regions 140′″, 142′″ to diffuse laterally under the sidewall spacers 134′″ toward the channel region 122′″ (FIG. 34). The methodology 10′″ then proceeds to 30′″ wherein further back end processing can be performed.
  • It will be appreciated that an amorphizing implant can be performed to activate carbon atoms formed into the recesses 113′″. An energy utilized in such an implant can be tuned so that the complete depth of the silicon carbide within the source/drain regions 140′″, 142′″ is fully amorphized. Atoms such as Germanium and/or Indium can be implanted, for example, at relatively high dosages, such as at about 1E15 atoms/cm3 or 1E14 atoms/cm3, respectively, for example, to achieve a depth of about 1000 angstroms. It will be appreciated that the gate structure would be masked off for the amorphizing implant. Further, while not intending to be limited to any one theory, it is believed that the silicon carbon material 104′″ within the recesses 113′″ form an alloy that has a lattice with the same structure as the silicon substrate lattice. However, the silicon carbon alloy has a smaller spacing. Consequently, it is believed that the silicon carbon material 104′″ within the recesses 113′″ will tend to contract, thereby creating a tensile stress within the channel 122′″ of the semiconductor substrate 102′″.
  • It will be appreciated that while reference is made throughout this document to exemplary structures in discussing aspects of methodologies described herein (e.g., those structures presented in FIGS. 2-10 while discussing the methodology set forth in FIG. 1, those structures presented in FIGS. 12-20 while discussing the methodology set forth in FIG. 11, those structures presented in FIGS. 22-28 while discussing the methodology set forth in FIG. 21 and those structures presented in FIGS. 29-34 while discussing the methodology set forth in FIG. 28), that those methodologies are not to be limited by the corresponding structures presented. Rather, the methodologies (and structures) are to be considered independent of one another and able to stand alone and be practiced without regard to any of the particular aspects depicted in the accompanying figures.
  • Further, from time to time throughout this specification and the claims that follow, one or more layers or structures may be described as being or containing a substance such as “carbon”, etc. These descriptions are to be understood in context and as they are used in the semiconductor manufacturing industry. For example, in the semiconductor industry, when a layer is described as containing carbon, it is understood that the layer comprises pure carbon as a principle component, but that the pure carbon may be, and typically is, alloyed, doped, or otherwise made impure. The carbon material is not, however, treated to such an extent that its basic properties are substantially different from that of high purity stoichiometric carbon.
  • Also, the term “exemplary” as used herein is merely meant to mean an example, rather than the best. It is also to be appreciated that layers and/or elements depicted herein are illustrated with particular dimensions relative to one another (e.g., layer to layer dimensions and/or orientations) for purposes of simplicity and ease of understanding, and that the actual dimensions of the elements may differ substantially from that illustrated herein. Additionally, unless stated otherwise and/or specified to the contrary, any one or more of the elements and/or layers set forth herein can be formed in any number of suitable ways, such as with spin-on techniques, sputtering techniques (e.g., magnetron and/or ion beam sputtering), thermal growth techniques and/or deposition techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD) and/or plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD), for example.
  • The layers described herein are also generally conformal (e.g., to underlying features) when formed, unless stated to the contrary. Additionally, the layers described herein can be patterned in any suitable manner (unless indicated to the contrary), such as with etching and/or lithographic techniques. Lithography refers to processes for pattern transfer between various media. A radiation sensitive resist coating is formed over one or more layers to which the pattern is to be transferred. The resist is itself first patterned by exposing it to radiation, where the radiation (selectively) passes through an intervening mask containing the pattern. As a result, the exposed or unexposed areas of the resist coating become more or less soluble, depending on the type of resist used. A developer is then used to remove the more soluble areas leaving the patterned resist. The pattered resist can then serve as a mask for the underlying layers which can be selectively etched to transfer the pattern thereto.
  • Although one or more aspects of the invention have been illustrated and described with respect to one or more implementations, equivalent alterations and/or modifications may occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. The invention is intended to include all such modifications and alterations. In addition, while a particular feature or aspect of the invention may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and/or advantageous for any given or particular application. Furthermore, to the extent that the terms “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.”

Claims (10)

1-14. (canceled)
15. A method of forming a transistor, comprising:
forming a gate structure over a semiconductor substrate, a channel region thereby being defined within the semiconductor substrate under the gate structure;
etching portions of the substrate on opposing sides of the channel region;
forming silicon carbon material within the etched portions of the substrate; and
forming source and drain regions within the semiconductor substrate on opposing sides of the channel with a phosphorus dopant.
16. The method of claim 15, wherein the silicon carbon material is epitaxially grown.
17. The method of claim 15, further comprising:
forming sidewall spacers adjacent to the gate structure prior to etching the substrate, etched portions of the substrate thereby being substantially aligned with the sidewall spacers.
18. The method of claim 17, wherein the silicon carbon material is epitaxially grown.
19. The method of claim 15, further comprising:
forming offset spacers adjacent to the gate structure prior to etching the substrate, etched portions of the substrate thereby being substantially aligned with the offset spacers.
20. The method of claim 19, wherein the substrate is etched to a depth of between about 200 angstroms to about 400 angstroms.
21. A method of forming a transistor comprising:
forming a gate structure over a semiconductor substrate, a channel region thereby being defined within the semiconductor substrate below the gate structure;
etching portions of the substrate on opposing sides of the channel region;
forming silicon carbon material within the etched portions of the substrate;
forming sidewall spacers adjacent to the gate structure;
forming source and drain regions within the semiconductor substrate on opposing sides of the channel with a phosphorus dopant, the source and drain regions being substantially aligned with the sidewall spacers;
etching away the sidewall spacers;
forming offset spacers adjacent to the gate structure; and
forming source and drain extension regions within the semiconductor substrate on opposing sides of the channel with a phosphorus dopant, the source and drain extension regions being substantially aligned with the offset spacers.
22. A method of forming a transistor comprising:
forming a gate structure over a semiconductor substrate, a channel region thereby being defined within the semiconductor substrate below the gate structure;
forming sidewall spacers adjacent to the gate structure;
forming source and drain regions within the semiconductor substrate on opposing sides of the channel with a phosphorus dopant, the source and drain regions being substantially aligned with the sidewall spacers;
etching the sidewall spacers and portions of the source and drain regions within the substrate;
forming silicon carbon material within etched portions of the substrate;
forming offset spacers adjacent to the gate structure; and
forming source and drain extension regions within the semiconductor substrate on opposing sides of the channel with a phosphorus dopant, the source and drain extension regions being substantially aligned with the offset spacers.
23. A method of forming a transistor comprising:
forming a gate structure over a semiconductor substrate, a channel region thereby being defined within the semiconductor substrate below the gate structure;
forming sidewall spacers adjacent to the gate structure;
forming source and drain regions within the semiconductor substrate on opposing sides of the channel with a phosphorus dopant, the source and drain regions being substantially aligned with the sidewall spacers;
etching away the sidewall spacers;
forming offset spacers adjacent to the gate structure;
forming source and drain extension regions within the semiconductor substrate on opposing sides of the channel with a phosphorus dopant, the source and drain extension regions being substantially aligned with the offset spacers;
etching the portions of the source and drain regions and extension regions within the substrate; and
forming silicon carbon material within etched portions of the substrate.
US11/558,179 2004-09-17 2006-11-09 Phosphorus Activated NMOS Using SiC Process Abandoned US20070066024A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/943,278 US7179696B2 (en) 2004-09-17 2004-09-17 Phosphorus activated NMOS using SiC process
US11/558,179 US20070066024A1 (en) 2004-09-17 2006-11-09 Phosphorus Activated NMOS Using SiC Process

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/558,179 US20070066024A1 (en) 2004-09-17 2006-11-09 Phosphorus Activated NMOS Using SiC Process
US12/364,772 US20110212584A9 (en) 2004-09-17 2009-02-03 Phosphorus Activated NMOS Using SiC Process

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10/943,278 Division US7179696B2 (en) 2004-09-17 2004-09-17 Phosphorus activated NMOS using SiC process

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/364,772 Division US20110212584A9 (en) 2004-09-17 2009-02-03 Phosphorus Activated NMOS Using SiC Process

Publications (1)

Publication Number Publication Date
US20070066024A1 true US20070066024A1 (en) 2007-03-22

Family

ID=36073022

Family Applications (4)

Application Number Title Priority Date Filing Date
US10/943,278 Active 2024-11-12 US7179696B2 (en) 2004-09-17 2004-09-17 Phosphorus activated NMOS using SiC process
US11/558,161 Active 2024-10-20 US7902576B2 (en) 2004-09-17 2006-11-09 Phosphorus activated NMOS using SiC process
US11/558,179 Abandoned US20070066024A1 (en) 2004-09-17 2006-11-09 Phosphorus Activated NMOS Using SiC Process
US12/364,772 Abandoned US20110212584A9 (en) 2004-09-17 2009-02-03 Phosphorus Activated NMOS Using SiC Process

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US10/943,278 Active 2024-11-12 US7179696B2 (en) 2004-09-17 2004-09-17 Phosphorus activated NMOS using SiC process
US11/558,161 Active 2024-10-20 US7902576B2 (en) 2004-09-17 2006-11-09 Phosphorus activated NMOS using SiC process

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/364,772 Abandoned US20110212584A9 (en) 2004-09-17 2009-02-03 Phosphorus Activated NMOS Using SiC Process

Country Status (1)

Country Link
US (4) US7179696B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090093095A1 (en) * 2007-10-08 2009-04-09 Borna Obradovic Method to improve transistor tox using si recessing with no additional masking steps
US20090309161A1 (en) * 2008-06-16 2009-12-17 Samsung Electronics Co., Ltd. Semiconductor integrated circuit device
CN106158604A (en) * 2015-04-08 2016-11-23 司红康 Phosphorus diffusion method

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7479431B2 (en) * 2004-12-17 2009-01-20 Intel Corporation Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drain
DE102005020058B4 (en) * 2005-04-29 2011-07-07 Globalfoundries Inc. Production method for a semiconductor device with gate dielectrics with different blocking properties
US20070224785A1 (en) * 2006-03-21 2007-09-27 Liu Mark Y Strain-inducing film formation by liquid-phase epitaxial re-growth
DE102006035669B4 (en) * 2006-07-31 2014-07-10 Globalfoundries Inc. Transistor having a deformed channel region having a performance enhancing material composition and methods of manufacture
WO2008016512A1 (en) * 2006-07-31 2008-02-07 Advanced Micro Devices, Inc. A transistor having a strained channel region including a performance enhancing material composition
KR100934789B1 (en) 2007-08-29 2009-12-31 주식회사 동부하이텍 A semiconductor device and a method of manufacturing the same
US8705715B2 (en) * 2008-04-30 2014-04-22 Lg Electronics Inc. Home appliance, home appliance system, and diagnosis method of a home appliance
JP2010062529A (en) * 2008-08-04 2010-03-18 Toshiba Corp Method of manufacturing semiconductor device
US20110011886A1 (en) * 2009-07-14 2011-01-20 Harold Zaima Portable data collection sterilization dispenser and holder assembly
US8844766B2 (en) 2009-07-14 2014-09-30 Sterilogy, Llc Dispenser assembly for dispensing disinfectant fluid and data collection and monitoring system for monitoring and reporting dispensing events
DE102010040064B4 (en) * 2010-08-31 2012-04-05 Globalfoundries Inc. Reduced threshold voltage-width dependence in transistors having high-k metal gate electrode structures
US8455952B2 (en) 2010-11-22 2013-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Spacer elements for semiconductor device
US9537004B2 (en) 2011-05-24 2017-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain formation and structure
US9012310B2 (en) 2012-06-11 2015-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxial formation of source and drain regions
US9064796B2 (en) 2012-08-13 2015-06-23 Infineon Technologies Ag Semiconductor device and method of making the same
US8900958B2 (en) 2012-12-19 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxial formation mechanisms of source and drain regions
US9252008B2 (en) 2013-01-11 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxial formation mechanisms of source and drain regions
US8853039B2 (en) 2013-01-17 2014-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. Defect reduction for formation of epitaxial layer in source and drain regions
US9029226B2 (en) 2013-03-13 2015-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for doping lightly-doped-drain (LDD) regions of finFET devices
US9093468B2 (en) 2013-03-13 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Asymmetric cyclic depositon and etch process for epitaxial formation mechanisms of source and drain regions
US8877592B2 (en) 2013-03-14 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxial growth of doped film for source and drain regions
USD736636S1 (en) 2013-03-15 2015-08-18 iMOLZ, LLC Aerosol container
US9293534B2 (en) 2014-03-21 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of dislocations in source and drain regions of FinFET devices
US9299587B2 (en) 2014-04-10 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Microwave anneal (MWA) for defect recovery
USD762481S1 (en) 2014-04-11 2016-08-02 iMOLZ, LLC Oval shaped can
KR20160058307A (en) 2014-11-14 2016-05-25 삼성전자주식회사 Semiconductor device and method for fabricating the same
KR20170065070A (en) 2015-12-02 2017-06-13 삼성전자주식회사 Field effect transistor and semiconductor device comprising the same

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4769686A (en) * 1983-04-01 1988-09-06 Hitachi, Ltd. Semiconductor device
US5387807A (en) * 1991-04-30 1995-02-07 Texas Instruments Incorporated P-N junction diffusion barrier employing mixed dopants
US6229197B1 (en) * 1993-04-30 2001-05-08 Texas Instruments Incorporated Epitaxial overgrowth method and devices
US20030098479A1 (en) * 1999-12-30 2003-05-29 Anand Murthy Novel MOS transistor structure and method of fabrication
US6576535B2 (en) * 2001-04-11 2003-06-10 Texas Instruments Incorporated Carbon doped epitaxial layer for high speed CB-CMOS
US6605498B1 (en) * 2002-03-29 2003-08-12 Intel Corporation Semiconductor transistor having a backfilled channel material
US6621131B2 (en) * 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
US20040262694A1 (en) * 2003-06-25 2004-12-30 Chidambaram Pr Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel
US20040262683A1 (en) * 2003-06-27 2004-12-30 Bohr Mark T. PMOS transistor strain optimization with raised junction regions
US20050079692A1 (en) * 2003-10-10 2005-04-14 Applied Materials, Inc. Methods to fabricate MOSFET devices using selective deposition process
US20050127449A1 (en) * 2003-01-31 2005-06-16 Fujitsu Limited Semiconductor device and manufacturing method of the same
US20050151175A1 (en) * 2002-07-23 2005-07-14 Narumi Ohkawa Image sensor and image sensor module
US20050287752A1 (en) * 2004-06-24 2005-12-29 Applied Materials, Inc. Methods for forming a transistor
US6989322B2 (en) * 2003-11-25 2006-01-24 International Business Machines Corporation Method of forming ultra-thin silicidation-stop extensions in mosfet devices
US20060057811A1 (en) * 2003-12-10 2006-03-16 International Business Machines Corporation Selective post-doping of gate structures by means of selective oxide growth

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3881840B2 (en) * 2000-11-14 2007-02-14 独立行政法人産業技術総合研究所 Semiconductor device
US7112495B2 (en) * 2003-08-15 2006-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit
US7176522B2 (en) * 2003-11-25 2007-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having high drive current and method of manufacturing thereof
US7005333B2 (en) * 2003-12-30 2006-02-28 Infineon Technologies Ag Transistor with silicon and carbon layer in the channel region
US7220650B2 (en) * 2004-04-09 2007-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Sidewall spacer for semiconductor device and fabrication method thereof
US7227205B2 (en) * 2004-06-24 2007-06-05 International Business Machines Corporation Strained-silicon CMOS device and method
US7491988B2 (en) * 2004-06-28 2009-02-17 Intel Corporation Transistors with increased mobility in the channel zone and method of fabrication
US7579617B2 (en) * 2005-06-22 2009-08-25 Fujitsu Microelectronics Limited Semiconductor device and production method thereof

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4769686A (en) * 1983-04-01 1988-09-06 Hitachi, Ltd. Semiconductor device
US5387807A (en) * 1991-04-30 1995-02-07 Texas Instruments Incorporated P-N junction diffusion barrier employing mixed dopants
US6229197B1 (en) * 1993-04-30 2001-05-08 Texas Instruments Incorporated Epitaxial overgrowth method and devices
US20030098479A1 (en) * 1999-12-30 2003-05-29 Anand Murthy Novel MOS transistor structure and method of fabrication
US6576535B2 (en) * 2001-04-11 2003-06-10 Texas Instruments Incorporated Carbon doped epitaxial layer for high speed CB-CMOS
US6621131B2 (en) * 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
US6605498B1 (en) * 2002-03-29 2003-08-12 Intel Corporation Semiconductor transistor having a backfilled channel material
US20050151175A1 (en) * 2002-07-23 2005-07-14 Narumi Ohkawa Image sensor and image sensor module
US20050127449A1 (en) * 2003-01-31 2005-06-16 Fujitsu Limited Semiconductor device and manufacturing method of the same
US20040262694A1 (en) * 2003-06-25 2004-12-30 Chidambaram Pr Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel
US20040262683A1 (en) * 2003-06-27 2004-12-30 Bohr Mark T. PMOS transistor strain optimization with raised junction regions
US20050079692A1 (en) * 2003-10-10 2005-04-14 Applied Materials, Inc. Methods to fabricate MOSFET devices using selective deposition process
US6989322B2 (en) * 2003-11-25 2006-01-24 International Business Machines Corporation Method of forming ultra-thin silicidation-stop extensions in mosfet devices
US20060057811A1 (en) * 2003-12-10 2006-03-16 International Business Machines Corporation Selective post-doping of gate structures by means of selective oxide growth
US20050287752A1 (en) * 2004-06-24 2005-12-29 Applied Materials, Inc. Methods for forming a transistor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090093095A1 (en) * 2007-10-08 2009-04-09 Borna Obradovic Method to improve transistor tox using si recessing with no additional masking steps
US20110027954A1 (en) * 2007-10-08 2011-02-03 Texas Instruments Incorporated Method to improve transistor tox using si recessing with no additional masking steps
US7892930B2 (en) * 2007-10-08 2011-02-22 Texas Instruments Incorporated Method to improve transistor tox using SI recessing with no additional masking steps
US20090309161A1 (en) * 2008-06-16 2009-12-17 Samsung Electronics Co., Ltd. Semiconductor integrated circuit device
CN106158604A (en) * 2015-04-08 2016-11-23 司红康 Phosphorus diffusion method

Also Published As

Publication number Publication date
US7179696B2 (en) 2007-02-20
US7902576B2 (en) 2011-03-08
US20090142890A1 (en) 2009-06-04
US20110212584A9 (en) 2011-09-01
US20060060893A1 (en) 2006-03-23
US20070072383A1 (en) 2007-03-29

Similar Documents

Publication Publication Date Title
TWI483399B (en) Semiconductor device having tipless epitaxial source/drain regions
TWI309091B (en) Non-planar mos structure with a strained channel region
US6392271B1 (en) Structure and process flow for fabrication of dual gate floating body integrated MOS transistors
US6784101B1 (en) Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation
JP3737721B2 (en) Method of manufacturing a distortion SiCMOS structure
CN100463215C (en) Field effect transistor and producing method thereof
CN101572269B (en) Source/drain carbon implant and RTA anneal, pre-SIGe deposition
EP1433196B1 (en) Apparatus to prevent lateral oxidation in a transistor utilizing an ultra thin oxygen-diffusion barrier
US6998305B2 (en) Enhanced selectivity for epitaxial deposition
JP4391745B2 (en) Manufacturing method of FET with notch gate
US8404535B2 (en) Metal gate transistor and method for fabricating the same
US6759695B2 (en) Integrated circuit metal oxide semiconductor transistor
US5846857A (en) CMOS processing employing removable sidewall spacers for independently optimized N- and P-channel transistor performance
US6627488B2 (en) Method for fabricating a semiconductor device using a damascene process
US7635632B2 (en) Gate electrode for a semiconductor fin device
KR101060439B1 (en) Active regions with compatible dielectric layers
US7208356B2 (en) Method of manufacturing multiple-gate MOS transistor having an improved channel structure
US20080076216A1 (en) Method to fabricate high-k/metal gate transistors using a double capping layer process
US20050218438A1 (en) Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US8247285B2 (en) N-FET with a highly doped source/drain and strain booster
TWI545761B (en) The method of forming a semiconductor device therewith and p-type metal oxide semiconductor transistor
CN105448835B (en) Semiconductor device
US20100052074A1 (en) Metal gate transistor and method for fabricating the same
DE102009055392B4 (en) Semiconductor component and method for producing the semiconductor device
CN100527437C (en) Semiconductor device having a laterally modulated gate workfunction and method of fabrication

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION