US20070045856A1 - Mixed metal nitride and boride barrier layers - Google Patents

Mixed metal nitride and boride barrier layers Download PDF

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US20070045856A1
US20070045856A1 US11509066 US50906606A US2007045856A1 US 20070045856 A1 US20070045856 A1 US 20070045856A1 US 11509066 US11509066 US 11509066 US 50906606 A US50906606 A US 50906606A US 2007045856 A1 US2007045856 A1 US 2007045856A1
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method
precursor
titanium
metal
aluminum
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Brian Vaartstra
Donald Westmoreland
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Vaartstra Brian A
Westmoreland Donald L
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    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/932Boron nitride semiconductor

Abstract

Mixed metal aluminum nitride and boride diffusion barriers and electrodes for integrated circuits, particularly for DRAM cell capacitors. Also provided are methods for CVD deposition of MxAlyNzBw alloy diffusion barriers, wherein M is Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, or W; x is greater than zero; y is greater than or equal to zero; the sum of z and w is greater than zero; and wherein when y is zero, z and w are both greater than zero.

Description

    FIELD OF THE INVENTION
  • The invention relates generally to integrated circuits and more particularly to the use of amorphous ternary aluminum nitride and boride alloy materials for diffusion barrier layers in such circuits.
  • BACKGROUND OF THE INVENTION
  • In semiconductor devices, it is common for the design to require interfaces of silicon and a metal such as aluminum or tungsten. For example, aluminum and tungsten are commonly used as the material of choice for electrical contacts, which contacts interface with electrically active areas made of doped silicon. It is also common in the fabrication of semiconductor devices to anneal the devices at elevated temperatures, such as 500° C. At these temperatures, the metal and silicon will rapidly interdiffuse into each other at the interface. Even at room temperature, the metal and silicon will interdiffuse over time. Such interdiffusion changes the semiconductive properties of the silicon and causes defective devices.
  • Capacitors are used in a wide variety of integrated circuits and present special interdiffusion concerns. Capacitors are of particular concern in DRAM (dynamic random access memory) circuits. The electrodes in a DRAM cell capacitor must protect the dielectric film (e.g., Ta2O5 and (Ba, Sr)TiO3) from interaction with surrounding materials and from the harsh thermal processing encountered in subsequent steps of DRAM process flow. In order to function well as a bottom electrode, the electrode film or film stack must act as an effective barrier to the diffusion of oxygen and silicon. Oxidation of the underlying Si results in decreased series capacitance, thus degrading the capacitor.
  • It is common practice to provide diffusion barriers in semiconductor devices. A thin film of titanium nitride (TiN) or titanium tungsten (TiW) is conventionally used as diffusion barrier. Conventional barrier materials, however, tend to be polycrystalline with grain boundaries through which diffusion of Si and O atomic species can occur.
  • The conventional diffusion barriers for silicon/metal interfaces and capacitor dielectrics, while generally relatively effective at room temperature, can fail at more elevated temperatures. Many preferred semiconductor fabrication processes, such as deposition, reflow, and annealing, require elevated temperatures. Thus conventional diffusion barriers can create limits on the processes that can be used to fabricate a semiconductor device. There is a need for a diffusion barrier that is more effective than conventional polycrystalline barriers, especially at elevated temperatures.
  • What is needed are improved diffusion barrier layers and fabrication methods that offer a combination of good conformality, high conductivity, and excellent barrier properties for protecting against interdiffusion at capacitor dielectrics and silicon/metal interfaces in semiconductor devices, particularly during high temperature fabrication processes.
  • SUMMARY OF THE INVENTION
  • The present invention provides mixed-metal nitride, boride and boride-nitride alloy barrier layers of the formula MxAlyNzBw, wherein M is Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, or W; x is greater than zero; y is greater than or equal to zero; the sum of z and w is greater than zero; and wherein when y is zero, z and w are both greater than zero, and when M is Ti, w is greater than 0.
  • The preferred metals (M) are Ti, Zr, Hf, Ta, Nb, Mo and W. Preferably, when M is Ti, Zr, Hf, Ta, or Nb, x+y=1, and z+w/2=1; and when M is Mo or W, x+y=1, and z+2w=1. Most preferably, M is Ti, Zr, Hf, Ta, or Nb and MxAlyNzBw has the formula M0.7Al0.3N0.3B1.4, or M is Mo, or W, and MxAlyNzBw has the formula M0.7Al0.3N0.3B0.35.
  • The invention also provides semiconductor capacitors and methods for fabricating capacitors and other devices containing MxAlyNzBw barrier layers in order to protect capacitor cell dielectrics, such as SiO2, Ta2O5, SrTiO3 (“ST”), (Ba,Sr)TiO3 (“BST”), Pb(Z,Ti)O3 (“PZT”), SrBi2Ta2O9 (“SBT”) and Ba(Zr,Ti)O3 (“BZT”).
  • The mixed-metal nitride and boride layers of the invention provide excellent barrier protection, conductivity as capacitor electrodes, and conformality, and so may be employed either as capacitor electrodes, or as separate barrier layers formed adjacent to conventional capacitor electrodes, either a top these electrodes or interposed between the electrode and the capacitor dielectric. Preferably, the MxAlyNzBw layer according to the invention comprises a thin barrier film between a cell dielectric and an underlying polysilicon (poly) plug or drain in a DRAM cell array, as well as acting as a lower electrode.
  • The barrier layers and methods of the invention are also useful in any device containing a Si/metal interface, and any other semiconductor device where protection against degradation through diffusion and thermal effects is desired.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a schematic of a chemical vapor deposition system suitable for use in the method of the present invention.
  • FIG. 2 is a schematic of an alternative chemical vapor deposition system suitable for use in the method of the present invention.
  • FIG. 3 is a diagrammatic cross-sectional view taken along a portion of a semiconductor wafer at an early processing step according to one embodiment of the present invention.
  • FIG. 4 is a diagrammatic cross-sectional view of a portion of a semiconductor wafer at a processing step subsequent to that shown in FIG. 3.
  • FIG. 5 is a diagrammatic cross-sectional view of a portion of a semiconductor wafer at a processing step subsequent to that shown in FIG. 4.
  • FIG. 6 is a diagrammatic cross-sectional view of a portion of a semiconductor wafer at a processing step subsequent to that shown in FIG. 5.
  • FIG. 7 is a diagrammatic cross-sectional view of a portion of a semiconductor wafer at a processing step subsequent to that shown in FIG. 6.
  • FIG. 8 is a diagrammatic cross-sectional view of a portion of a semiconductor wafer at a processing step subsequent to that shown in FIG. 7.
  • FIG. 9 is a diagrammatic cross-sectional view of a portion of a semiconductor wafer at a processing step subsequent to that shown in FIG. 8.
  • FIG. 10 is a diagrammatic cross-sectional view of a portion of a semiconductor wafer at a processing step subsequent to that shown in FIG. 9.
  • FIG. 11 is a diagrammatic cross-sectional view of a portion of a semiconductor wafer at a processing step subsequent to that shown in FIG. 10.
  • FIG. 12 is a diagrammatic cross-sectional view of a portion of a semiconductor wafer at a processing step subsequent to that shown in FIG. 11.
  • FIG. 13 is a diagrammatic cross-sectional view of a portion of a semiconductor wafer at a processing step subsequent to that shown in FIG. 12.
  • FIG. 14 is a diagrammatic cross-sectional view taken along a portion of a semiconductor wafer at a processing step according to another embodiment of the present invention.
  • FIG. 15 is a diagrammatic cross-sectional view taken along a portion of a semiconductor wafer at processing step according to still another embodiment of the present invention.
  • FIG. 16 is a diagrammatic cross-sectional view taken along a portion of a semiconductor wafer at processing step according to yet a further embodiment of the present invention.
  • FIG. 17 is a diagrammatic cross-sectional view of a portion of a semiconductor wafer at a processing step subsequent to that shown in FIG. 16.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • The mixed metal boride, nitride, and boride-nitride barrier materials of the invention generally have the formula MxAlyNzBw, wherein M is Ti, Zr, Hf, V, Nb, Ta, Cr, Mo or W, and x, y, z, and w are any suitable value such that x is greater than zero; y is greater than or equal to zero; the sum of z and w is greater than zero; and wherein when y is zero, z and w are both greater than zero, and when M is Ti, w is greater than 0. The preferred metals (“M”) are Ti, Zr, Hf, Ta, Nb, Mo and W. Preferably, when M is Ti, Zr, Hf, Ta, or Nb, x+y=1, and z+w/2=1, and when M is Mo or W, x+y=1, and z+2w=1. Most preferably, M is Ti, Zr, Hf, Ta, or Nb and MxAlyNzBw has the formula M0.7Al0.3N0.3B1.4, or M is Mo, or W, and MxAlyNzBw has the formula M0.7Al0.3N0.3B0.35.
  • The MxAlyNzBw barrier material can be deposited by a sputter process from metal nitride and metal boride targets, or sputtered from metal targets in the presence of boron and nitrogen containing gases, such as diborane, ammonia and nitrogen. The barrier material can also be deposited by chemical vapor deposition utilizing a volatile source for M and Al and a reactive gas source for N and B. Examples of metal sources for Al deposition include, such as, dimethylaluminumhydride (DMAH) and triethylaluminum (TEAL). Sources for M include any metal halide or organometallic compound suitable for a CVD process. The MxAlyNzBw barrier material can also be deposited by liquid spin-on or dip coat processes utilizing a metalorganic solution that is baked and annealed after application. Chemical vapor deposition techniques are preferred, because they generally are more suitable for deposition on semiconductor substrates or substrate assemblies, particularly in contact openings which are extremely small and require conformally filled layers.
  • The methods of the present invention can be used to deposit a barrier material film on a variety of substrates, such as a semiconductor wafer (e.g., silicon wafer, gallium arsenide wafer, etc.), glass plate, etc., and on a variety of surfaces of the substrates, whether it be directly on the substrate itself or on a layer of material deposited on the substrate as in a semiconductor substrate assembly. Metal and other components of the barrier film may be deposited from either a volatile liquid, a sublimable solid, or a solid that is soluble in a suitable solvent that is not detrimental to the substrate, and other layers thereon. Preferably, however, solvents are not used; rather, the metal components are liquid and used neat. Methods of the present invention preferably utilize vapor deposition techniques, such as flash vaporization, bubbling, etc.
  • A typical chemical vapor deposition (CVD) system that can be used to perform the process of the present invention is shown in FIG. 1. The system includes an enclosed chemical vapor deposition chamber 210, which may be a cold wall-type CVD reactor. As is conventional, the CVD process may be carried out at pressures of from atmospheric pressure down to about 10−3 torr, and preferably from about 10 torr to about 0.1 torr. A vacuum may be created in chamber 210 using turbo pump 212 and backing pump 214.
  • One or more substrates 216 (e.g., semiconductor substrates or substrate assemblies) are positioned in chamber 210. A constant nominal temperature is established for the substrate, preferably at a temperature of about 100° C. to about 600° C., and more preferably at a temperature of about 250° C. to about 550° C. Substrate 216 may be heated, for example, by an electrical resistance heater 218 on which substrate 216 is mounted. Other known methods of heating the substrate may also be utilized.
  • In this process, the precursor composition 240, which contains one or more metal or metalloid complexes, is stored in liquid form (a neat liquid at room temperature or at an elevated temperature if solid at room temperature) in vessel 242. A source 244 of a suitable inert gas is pumped into vessel 242 and bubbled through the neat liquid (i.e., without solvent) picking up the precursor composition and carrying it into chamber 210 through line 245 and gas distributor 246. Additional inert carrier gas or reaction gas may be supplied from source 248 as needed to provide the desired concentration of precursor composition and regulate the uniformity of the deposition across the surface of substrate 216. As shown, a series of valves 250-254 are opened and closed as required.
  • Generally, the precursor composition is pumped into the CVD chamber 210 at a flow rate of about 1 sccm (standard cubic centimeters) to about 1000 sccm. The semiconductor substrate is exposed to the precursor composition at a pressure of about 0.001 torr to about 100 torr for a time of about 0.01 minute to about 100 minutes. In chamber 210, the precursor composition will form an adsorbed layer on the surface of the substrate 216. As the deposition rate is temperature dependent, increasing the temperature of the substrate will increase the rate of deposition. Typical deposition rates are about 10 Angstroms/minute to about 1000 Angstroms/minute. The carrier gas containing the precursor composition is terminated by closing valve 253.
  • An alternative CVD system that can be used to perform the mixed metal nitride and boride CVD process of the present invention is shown in FIG. 2. The system includes an enclosed chemical vapor deposition chamber 210, which may be a cold wall-type CVD reactor, in which a vacuum may be created using turbo pump 212 and backing pump 214. One or more substrates 216 (e.g., semiconductor substrates or substrate assemblies) are positioned in chamber 210. Substrate 216 may be heated as described with reference to FIG. 1 (for example, by an electrical resistance heater 218).
  • In this process, one or more solutions 260 of one or more precursor metal or metalloid complexes are stored in vessels 262. The solutions are transferred to a mixing manifold 264 using pumps 266. The resultant precursor compositions containing one or more precursor complexes and one or more organic solvents is then transferred along line 268 to vaporizer 270, to volatilize the precursor composition. A source 274 of a suitable inert gas is pumped into vaporizer 270 for carrying a volatilized precursor composition into chamber 210 through line 275 and gas distributor 276. Reaction gas may be supplied from source 278 as needed. As shown, a series of valves 280-285 are opened and closed as required. Similar pressures and temperatures to those described with reference to FIG. 1 can be used.
  • Various combinations of carrier gases and/or reaction gases can be used in certain methods of the present invention. They can be introduced into the chemical vapor deposition chamber in a variety of manners, such as directly into the vaporization chamber or in combination with the precursor composition. Although specific vapor deposition processes are described by reference to FIGS. 1-2, methods of the present invention are not limited to being used with the specific vapor deposition systems shown. Various CVD process chambers or reaction chambers can be used, including hot wall or cold wall reactors, atmospheric or reduced pressure reactors, as well as plasma enhanced reactors.
  • The use of the mixed metal nitride and boride materials and methods of forming layers and films of the present invention are beneficial for a wide variety of applications in semiconductor structures, particularly those using high dielectric materials or ferroelectric materials. Such applications include capacitors such as planar cells, trench cells (e.g., double sidewall trench capacitors), stacked cells (e.g., crown, V-cell, delta cell, multi-fingered, or cylindrical container stacked capacitors), as well as field effect transistor devices, and any semiconductor device having a silicon-metal interface.
  • Examples of fabrication processes for capacitors and other semiconductor devices containing mixed metal nitride, boride and nitride-boride barrier layers of the formula MxAlyNzBw are described below. It is to be understood, however, that these processes are only examples of many possible configurations and processes utilizing the barriers or electrodes of the invention. For example, in the DRAM cell stacked container capacitor process described next, a mixed metal nitride and boride material is utilized as a barrier below the bottom electrode of a capacitor. Alternatively, the top electrode may also include a barrier material. The invention is not intended to be limited by the particular processes described below.
  • Referring to FIG. 3, a typical semiconductor wafer fragment at an early processing step is indicated generally by reference numeral 100. The semiconductor wafer 100 is comprised of a bulk silicon substrate 112 with field isolation oxide regions 114 and active areas 116, 118, 120. Word lines 122, 124, 126, 128 have been constructed on the wafer 100 in a conventional manner. Each word line consists of a lower gate oxide 130, a lower poly layer 132, a higher conductivity silicide layer 134 and an insulating silicon nitride cap 136. Each word line has also been provided with insulating spacers 138, also of silicon nitride.
  • Two FETs are depicted in FIG. 3. One FET is comprised of two active areas (source/drain) 116, 118 and one word line (gate) 124. The second FET is comprised of two active areas (source/drain) 118, 120 and a second word line (gate) 126. The active area 118 common to both FETs is the active area over which a bit line contact will be formed.
  • Referring to FIG. 4, a thin layer 140 of nitride or TEOS is provided atop the wafer 100. Next a layer of insulating material 142 is deposited. The insulating material preferably consists of borophosphosilicate glass (BPSG). The insulating layer 142 is subsequently planarized by chemical-mechanical polishing (CMP).
  • Referring to FIG. 5, a bit line contact opening 144 and capacitor openings 146 have been formed through the insulating layer 142. The openings 144, 146 are formed through the insulating layer 142 by photomasking and dry chemical etching the BPSG relative to the thin nitride or TEOS layer 140. Referring now to FIG. 6, a layer 150 of conductive material is deposited to provide conductive material within the bit line contact and capacitor openings 144, 146. The conductive layer 150 is in contact with the active areas 116, 118, 120. An example of the material used to form layer 150 is in situ arsenic or phosphorous doped poly. Referring now to FIG. 7, the conductive layer 150 is etched away to the point that the only remaining material forms plugs 150 over the active areas 116, 118, 120.
  • Referring now to FIG. 8, a thin barrier film 151 of a mixed metal boride, nitride or boride-nitride of the formula MxAlyNzBw as defined above is formed as a barrier layer atop conductive layer 150. Barrier film 151 is preferably deposited by CVD to form a conformal layer which protects the subsequently deposited capacitor dielectric against diffusion from underlying plug 150 and other surrounding materials. Perhaps more importantly for some applications of the invention, barrier film 151 also protects the underlying plug 150 from diffusion of oxygen from the capacitor dielectric.
  • The preferred method for depositing barrier layer 15, includes positioning the wafer assembly within a vacuum CVD reactor chamber. In one preferred implementation, the CVD reactor will be a cold wall reactor. Preferably, the substrate will be heated by a resistive-type ceramic heater to a temperature of 250-550° C. Hydrogen gas will inlet to the chamber at a rate of approximately 50-500 sccm. Subsequently, the metal (M), aluminum, nitrogen, and boron precursors will be admitted into the CVD chamber. Preferably, if the metal (M) is Ti, the titanium precursor will be of the formula Ti(NR2)4, where R is selected from the group consisting of H an alkyl and/or aryl group. However, any suitable organometallic or inorganic titanium containing source may be substituted for Ti(NR2)4. In such case, the same gas will serve as both the titanium and nitrogen precursor. Most preferably, the titanium precursor will be a titanium organometallic precursor, having the formula Ti(N(CH3)2)4, which is commonly referred to as TDMAT. The aluminum precursor will preferably be dimethylethylaminealane, commonly known as DMEAA. However, any suitable organometallic or inorganic aluminum containing source may be substituted for DMEAA. Both of these reaction precursors are liquids at room temperature, and must be bubbled with helium, or otherwise vaporized, such as through injection into a vaporizer to facilitate transport as gases into the CVD chamber for deposition on the substrate. Sources as precursors for Ti, Zr, Hf, V, Nb, Ta, Cr, Mo and W, can be any suitable metal halide or organometallic compound containing Ti, Zr, Hf, V, Nb, Ta, Cr, Mo or W.
  • In a particularly preferred CVD process according to the present invention, a bubbler will be used for each precursor, and each bubbler will be held at the same pressure as that within the CVD chamber. A TDMAT bubbler will preferably be maintained at a temperature of 35-55° C., with helium being flowed through at a rate of approximately 20-200 sccm. Simultaneously, the DMEAA vessel will be maintained at a temperature of approximately 5-30° C., with the helium passed through at a rate of 10-100 sccm. Other systems may be utilized for introducing one or more precursors into the CVD chamber. For example, in addition to the use of a vaporizer or evaporator, a precursor may be introduced into the CVD chamber by direct liquid injection. Additionally, although the use of gaseous precursors is currently preferred, precursors may be introduced in vapor or liquid form, such as in liquid source CVD (LSCVD) operations.
  • When deposition is to occur, the precursors are bubbled into the CVD chamber, and are mixed in a gas distributor, such as a gas “showerhead”, and are directed onto the heated substrate. Deposition may be continued for the desired period of time. The metal, aluminum, nitrogen, and boron will thus preferably be deposited generally simultaneously, as an amorphous material. In one exemplary implementation, where the MxAlyNzBw will be deposited upon a wafer, the deposition may continue for approximately 3-10 minutes, after which time the gas flows will be stopped, and the substrate allowed to cool.
  • Although the DMEAA precursor gas is described relative to the exemplary embodiment above, an aluminum precursor, aluminum alkyls or alkyl hydride compounds, or their Lewis-based adducts may also be utilized in their place. Other examples of acceptable aluminum precursors can be, but are not limited to, trimethylaluminum, tris(dimethylamino)aluminum, trimethylaminealane, dimethylalane, or (dimethylethylamine)dimethylalane.
  • Other examples of the exemplary products for titanium precursors are, but are not limited to: the ethyl analog of TDMAT, tetrakisdiethylamidotitanium (also conventionally known as TDEAT); bis(2,4-dimethyl-1,3-pentadienyl)titanium (also conventionally known as BDPT); titanium tetrachloride; titanium tetrabromide; titanium tetraiodide; and cyclopentadienylcycloheptatrienyltitanium (also conventionally known as CpTiChT). Examples of exemplary products for other metal precursors include CpZr(BH4)2, CpHf(BH4)2, TaCl5, WF6, and MoF6.
  • Examples of reactive gas sources for nitrogen and boron include, but are not limited to NF3, N2 (especially with plasma assist), NH3, hydrazine, methyl hydrazine, B2H6, and BCl3.
  • Following chemical vapor deposition of a mixed metal nitride and boride barrier film 151, a layer 152 of conductive material that will eventually form one of the electrodes of the capacitor is deposited at a thickness such that the capacitor openings 144, 146 are not closed off. Referring to FIG. 9, the layer 152 may be formed of various refractive metals, conductive metal oxides, metal nitrides, noble metals and may include, such as, Pt, Rh, Ir, Ru, Os, Pd, IrO2, RhO2, RuO2, Ta, TiN, TaN, Ti and others. The conductive layer 152 is in electrical contact with the previously formed plugs 150 or, as previously mentioned, the MxAlyNzBw layer will itself be the lower electrode.
  • Referring to FIG. 10, the portion of the conductive layer 152 above the top of the BPSG layer 142 is removed through a planarized etching process, thereby electrically isolating the portions of layer 152 remaining in the bit line contact and capacitor openings 144, 146. Referring now to FIG. 11, a capacitor dielectric layer 154 is provided over conductive layer 152 and capacitor openings 144, 146.
  • Dielectric layer 154 is deposited with a thickness such that the openings 146 are again not completely filled. Dielectric layer 154 may comprise tantalum pentoxide (Ta2O5). Other suitable dielectric materials such as Strontium Titanate (ST), Barium Strontium Titanate (BST), Lead Zirconium Titanate (PZT), Strontium Bismuth Tantalate (SBT) and Bismuth Zirconium Titanate (BZT) may also be used. Dielectric layer 154 may be deposited by a low-pressure CVD process using Ta(OC2H5)5 and O2 at about 430° C., and may be subsequently annealed in order to reduce leakage current characteristics.
  • A second conductive electrode layer 156 is then deposited by CVD over the dielectric layer 154, again at a thickness which less than completely fills the capacitor openings 146. The second conductive layer 156 may be comprised of TiN, Pt, or other conventional electrode materials, such as many of those previously described for use as conductive layer 152. In addition to serving as the top electrode or second plate of the capacitor, the second conductive layer 156 also forms the interconnection lines between the second plates of all capacitors.
  • Referring to FIG. 12, the second conductive layer 156 and underlying capacitor dielectric layer 154 are patterned and etched such that the remaining portions of each group of the first conductive layer 152, capacitor dielectric layer 154, and second conductive layer 156 over the bit line contact and capacitor openings 144, 146 are electrically isolated from each other. In this manner, each of the active areas 116, 118, 120 are also electrically isolated (without the influence of the gate). Furthermore, a portion of the first conductive layer 152 in contact with the plug 150 over the bit line active area 118 is outwardly exposed.
  • Referring now to FIG. 12, a bit line insulating layer 158 is provided over the second conductive layer 156 and into the bit line contact opening 144. The bit line insulating layer 158 is preferably comprised of BPSG. The BPSG is typically reflowed by conventional techniques, i.e., heating to about 800° C. Other insulating layers such as PSG, or other compositions of doped SiO2 may similarly be employed as the insulating layer 158.
  • Referring to FIG. 13, a bit line contact opening 160 is patterned through the bit line insulating layer 158 such that the barrier film 151 above plug conductive layer 150 is once again outwardly exposed. Then a bit line contact is provided in the bit line contact opening 160 such that the bit line contact is in electrical contact with the outwardly exposed portion of the barrier film 151 above conductive plug layer 150. Thus, the plug 150 over the active area 118 common to both FETs acts as a bit line contact. The DRAM array and associated circuitry may then be completed by a variety of well established techniques, such as metalization, and attachment to peripheral circuitry.
  • Another specific example of where a film formed from the MxAlyNzBw materials of the present invention is useful is the ferroelectric memory cell 310 of FIG. 14. The memory cell 310 includes a ferroelectric material 311, which is prepared by depositing one or more of the materials discussed herein preferably using chemical vapor techniques, between two electrodes 312 and 313, which are typically made of platinum, although other metals such as gold or aluminum can also be used. The bottom electrode 313 is typically in contact with a silicon-containing layer 314, such as an n-type or p-type silicon substrate, silicon dioxide, glass, etc. A conductive mixed metal nitride and boride barrier layer 315, preferably deposited by CVD, is positioned between the bottom electrode 313 and the silicon-containing layer 314 to act as a barrier layer to diffusion of atoms such as silicon into the electrode and ferroelectric material.
  • Yet another specific example of where a film formed from the material of the present invention is useful is the structure shown in FIG. 15. The substrate 416 may be in the form of an n-channel MOSFET (n-channel metal-oxide semiconductor field-effect transistor), which may be used in a DRAM memory device. As shown, substrate 416 is a p-type silicon having two n-type silicon islands 420 and 422, representing the transistor source and drain. Such a construction is well known. The gate for the transistor is formed by a metal/polysilicon layer 424 deposited over a silicon dioxide layer 426. A relatively thick layer of an insulating silicon dioxide 428 overlies the active areas on substrate 416.
  • To connect the MOSFET of FIG. 15 with conductive paths on the surface of the device, contacts 430 and 432 have been etched through oxide layer 428 down to the surface of substrate 416. A metal or metal silicide layer 434, such as titanium silicide, is deposited and formed at the base of contacts 430 and 432. A thin, conformal barrier layer of a mixed metal boride and nitride 436 is deposited by CVD over the walls of the contacts. Because of the presence of the conductive barrier layer, the electrical contact path is excellent and the aluminum metal 438 which is deposited over the mixed metal boride and nitride barrier layer 436 is prevented from attacking the substrate surfaces.
  • In still another example, as depicted in FIG. 16, after deposition of the MxAlyNzBw barrier layer 516 within the opening within layer 514, a conductive layer 518 may be deposited to fill the cavity formed in layer 514 over the substrate contact region 515. Conductive layer 518 may be, for example, aluminum or tungsten. Subsequently, layers 516 and 518 may removed, such as by being patterned and etched in a desired manner to form interconnects between substrate regions. Alternatively, conductive layer 518 and barrier layer 516 could be etched away to form a conductive plug structure as shown in FIG. 17.
  • The mixed-metal nitride and boride barrier layer and electrode materials according to the invention have excellent conductivity, and therefor reduce depletion effects and enhance frequency response. The materials possess excellent barrier properties for protection of cell dielectrics and substrate during oxidation/recrystallization steps for dielectrics and during BPGS reflow and other high temperature steps after capacitor formation. In addition, the barriers according to the invention also substantially prevent diffusion to protect cell dielectrics from interaction with Si and other surrounding materials which may degrade the dielectric materials or produce an additional SiO2 dielectric layer. Thus, the barriers/electrodes of the invention are not limited to use as barrier films for bottom electrodes, but may also be employed both as top and bottom electrodes, and as additional barrier layers applied to any other top and/or bottom electrodes. The compositions and methods of forming barrier films of the present invention are also beneficial for a wide variety of thin film applications in integrated circuit structures, particularly those using high dielectric materials and/or silicon-metal interfaces. The method of the preferred embodiments of the invention prevent degradation of an electrical connection between a conductive layer and a semiconductor substrate by providing a diffusion barrier between the two regions.
  • Accordingly, the above description and accompanying drawings are only illustrative of preferred embodiments which can achieve and provide the objects, features and advantages of the present invention. It is not intended that the invention be limited to the embodiments shown and described in detail herein. The invention is only limited by the spirit and scope of the following claims.

Claims (25)

  1. 1-91. (canceled)
  2. 92. A method of depositing an amorphous alloy, comprising the steps of:
    placing an object within a vapor deposition chamber;
    injecting gaseous precursors of a metal, aluminum, nitrogen and boron into said chamber, wherein each of said gaseous precursors is transferred from a respective bubbler, each said respective bubbler and said chamber being at about a same pressure; and
    depositing an amorphous alloy layer from said precursors on said object.
  3. 93. The method of claim 92, wherein said metal precursor is titanium and a single gas serves as said metal precursor and said nitrogen precursor.
  4. 94. The method of claim 93, wherein said metal and nitrogen precursor is of the formula Ti(NR2)4, where R is selected from the group consisting of one or more of hydrogen, an alkyl group and an aryl group.
  5. 95. The method of claim 93, wherein said metal and nitrogen precursor is Ti(N(CH3)2)4.
  6. 96. The method of claim 92, wherein said wafer is heated to a temperature of approximately 250-550° C.
  7. 97. The method of claim 92, wherein said aluminum precursor is selected from the group consisting of DMEAA, dimethylaluminumhydride ethyldimethylamine adduct, dimethyl aluminum hydride, an alkyl aluminum compound, an alkylaminealuminum compound, and any adducted complexes of the above-named aluminum-containing compounds.
  8. 98. The method of claim 92, wherein said metal precursor is selected from the group consisting of tetrakisdiethylamidotitanium, bis(2,4-dimethyl)(1,3-pentadienyl)titanium, titanium tetrachloride, titanium tetrabromide, titanium tetraiodide, and cyclopentadienylcycloheptatrienyltitanium.
  9. 99. The method of claim 92, wherein said metal precursor is selected from the group consisting of metal halide compounds and organometallic compounds.
  10. 100. The method of claim 92, wherein said boron precursor is a boron reactant gas.
  11. 101. The method of claim 92, wherein said nitrogen precursor is a nitrogen reactant gas.
  12. 102. The method of claim 92, wherein said amorphous alloy layer comprises MxAlyNzBw, wherein M is said first metal, x, y and z are each greater than zero, and w is between about 0.35 and about 1.4.
  13. 103. The method of claim 92, wherein said precursors are introduced into said chamber substantially simultaneously.
  14. 104. A method of depositing a layer on a semiconductor wafer, comprising:
    placing said wafer within a vapor deposition reactor;
    heating said wafer to a temperature of about 250° C. to about 550° C.;
    establishing a pressure of 100 millitorr to 10 torr within said reactor;
    injecting a gaseous organometallic precursor from a first bubbler into said reactor;
    injecting an aluminum precursor from a second bubbler into said reactor, said first bubbler and said second bubbler being at a pressure substantially the same as that within said reactor; and
    depositing a layer comprising MxAlyNzBw, wherein M is a first metal, x, y and z are each greater than zero, and w is between about 0.35 and about 1.4.
  15. 105. The method of claim 104, wherein said aluminum precursor is selected from the group consisting of DMEAA, dimethylaluminumhydride ethyldimethylamine adduct, dimethyl aluminum hydride, an alkyl aluminum compound, an alkylaminealuminum compound, and adducted complexes of any of the above-named aluminum-containing compounds.
  16. 106. The method of claim 104, wherein said first metal is titanium and is deposited from a titanium precursor selected from the group consisting of tetrakisdiethylamidotitanium, bis(2,4-dimethyl)(1,3-pentadienyl)titanium, titanium tetrachloride, titanium tetrabromide, titanium tetraiodide, cyclopentadienylcycloheptatrienyltitanium, and a precursor of the formula Ti(NR2), where R is selected from the group consisting of one or more of hydrogen, an alkyl group and an aryl group.
  17. 107. The method of claim 104, wherein said organometallic precursor comprises titanium and nitrogen.
  18. 108. The method of claim 107, wherein said organometallic precursor is Ti(N(CH3)2)4.
  19. 109. The method of claim 107, wherein said organometallic precursor is of the formula Ti(NR2)4, where R is selected from the group consisting of one or more of hydrogen, an alkyl group and an aryl group.
  20. 110. The method of claim 104, wherein said aluminum precursor is selected from the group consisting of DMEAA, dimethylaluminumhydride ethyldimethylamine adduct, dimethyl aluminum hydride, an alkyl aluminum compound, an alkylaminealuminum compound, and any adducted complexes of the above-named aluminum-containing compounds.
  21. 111. The method of claim 104, wherein said selected organometallic precursor is selected from the group consisting of tetrakisdiethylamidotitanium, bis(2,4-dimethyl)(1,3-pentadienyl)titanium, titanium tetrachloride, titanium tetrabromide, titanium tetraiodide, and cyclopentadienylcycloheptatrienyltitanium.
  22. 112. The method of claim 104, wherein said organometallic precursor is selected from the group consisting of metal halide compounds and organometallic compounds.
  23. 113. The method of claim 104, wherein said boron is included in said layer comprising MxAlyNzBw by utilizing a boron reactant gas.
  24. 114. The method of claim 104 wherein said nitrogen is included in said layer comprising MxAlyNzBw by utilizing a nitrogen reactant gas.
  25. 115. The method of claim 104, wherein said precursors are introduced into said reactor substantially simultaneously.
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060086961A1 (en) * 2004-10-21 2006-04-27 Elpida Memory, Inc. Semiconductor device having a stacked capacitor
US20090127105A1 (en) * 2004-08-20 2009-05-21 Micron Technology, Inc. Systems and methods for forming niobium and/or vanadium containing layers using atomic layer deposition
US20090263974A1 (en) * 2001-08-28 2009-10-22 Shusaku Kido Substrate processing system for performing exposure process in gas atmosphere
WO2010135576A2 (en) * 2009-05-21 2010-11-25 Cornell Research Foundation, Inc. Conducting metal oxide and metal nitride nanoparticles
US20110169132A1 (en) * 2010-01-14 2011-07-14 Renesas Electronics Corporation Semiconductor device and manufacturing method of semiconductor device
US20130115383A1 (en) * 2011-11-08 2013-05-09 Xinliang Lu Deposition of metal films using alane-based precursors
WO2014008365A1 (en) * 2012-07-06 2014-01-09 Applied Materials, Inc. Deposition of n-metal films comprising aluminum alloys
US8940601B2 (en) 2011-07-07 2015-01-27 Renesas Electronics Corporation Manufacturing method of semiconductor device

Families Citing this family (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6281142B1 (en) * 1999-06-04 2001-08-28 Micron Technology, Inc. Dielectric cure for reducing oxygen vacancies
US7554829B2 (en) 1999-07-30 2009-06-30 Micron Technology, Inc. Transmission lines for CMOS integrated circuits
DE10022655C2 (en) * 2000-04-28 2002-03-07 Infineon Technologies Ag A process for producing capacitor structures
US6756088B2 (en) * 2000-08-29 2004-06-29 Micron Technology, Inc. Methods of forming coatings on gas-dispersion fixtures in chemical-vapor-deposition systems
US6524912B1 (en) 2000-08-31 2003-02-25 Micron Technology, Inc. Planarization of metal container structures
US6787833B1 (en) * 2000-08-31 2004-09-07 Micron Technology, Inc. Integrated circuit having a barrier structure
DE10058782B4 (en) * 2000-11-27 2006-03-23 Infineon Technologies Ag A method for manufacturing a capacitor arrangement
KR100531419B1 (en) * 2001-06-12 2005-11-28 주식회사 하이닉스반도체 semiconductor device and method for fabricating the same
US8026161B2 (en) 2001-08-30 2011-09-27 Micron Technology, Inc. Highly reliable amorphous high-K gate oxide ZrO2
US6844203B2 (en) 2001-08-30 2005-01-18 Micron Technology, Inc. Gate oxides, and methods of forming
US6717193B2 (en) * 2001-10-09 2004-04-06 Koninklijke Philips Electronics N.V. Metal-insulator-metal (MIM) capacitor structure and methods of fabricating same
KR100422597B1 (en) * 2001-11-27 2004-03-16 주식회사 하이닉스반도체 Method of forming semiconductor device with capacitor and metal-interconnection in damascene process
US6953730B2 (en) 2001-12-20 2005-10-11 Micron Technology, Inc. Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics
US6767795B2 (en) 2002-01-17 2004-07-27 Micron Technology, Inc. Highly reliable amorphous high-k gate dielectric ZrOXNY
US6812100B2 (en) 2002-03-13 2004-11-02 Micron Technology, Inc. Evaporation of Y-Si-O films for medium-k dielectrics
US7045430B2 (en) 2002-05-02 2006-05-16 Micron Technology Inc. Atomic layer-deposited LaAlO3 films for gate dielectrics
US7160577B2 (en) 2002-05-02 2007-01-09 Micron Technology, Inc. Methods for atomic-layer deposition of aluminum oxides in integrated circuits
US7205218B2 (en) 2002-06-05 2007-04-17 Micron Technology, Inc. Method including forming gate dielectrics having multiple lanthanide oxide layers
US7135421B2 (en) 2002-06-05 2006-11-14 Micron Technology, Inc. Atomic layer-deposited hafnium aluminum oxide
US6804136B2 (en) 2002-06-21 2004-10-12 Micron Technology, Inc. Write once read only memory employing charge trapping in insulators
US6970370B2 (en) * 2002-06-21 2005-11-29 Micron Technology, Inc. Ferroelectric write once read only memory for archival storage
US7221017B2 (en) 2002-07-08 2007-05-22 Micron Technology, Inc. Memory utilizing oxide-conductor nanolaminates
US7221586B2 (en) 2002-07-08 2007-05-22 Micron Technology, Inc. Memory utilizing oxide nanolaminates
US6921702B2 (en) 2002-07-30 2005-07-26 Micron Technology Inc. Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
US6884739B2 (en) 2002-08-15 2005-04-26 Micron Technology Inc. Lanthanide doped TiOx dielectric films by plasma oxidation
US6790791B2 (en) 2002-08-15 2004-09-14 Micron Technology, Inc. Lanthanide doped TiOx dielectric films
US20040036129A1 (en) * 2002-08-22 2004-02-26 Micron Technology, Inc. Atomic layer deposition of CMOS gates with variable work functions
US6967154B2 (en) * 2002-08-26 2005-11-22 Micron Technology, Inc. Enhanced atomic layer deposition
US7199023B2 (en) 2002-08-28 2007-04-03 Micron Technology, Inc. Atomic layer deposited HfSiON dielectric films wherein each precursor is independendently pulsed
US6958302B2 (en) 2002-12-04 2005-10-25 Micron Technology, Inc. Atomic layer deposited Zr-Sn-Ti-O films using TiI4
US7101813B2 (en) 2002-12-04 2006-09-05 Micron Technology Inc. Atomic layer deposited Zr-Sn-Ti-O films
JP4031704B2 (en) * 2002-12-18 2008-01-09 東京エレクトロン株式会社 Film formation method
JP4290421B2 (en) * 2002-12-27 2009-07-08 Necエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US6863725B2 (en) * 2003-02-04 2005-03-08 Micron Technology, Inc. Method of forming a Ta2O5 comprising layer
US7192892B2 (en) 2003-03-04 2007-03-20 Micron Technology, Inc. Atomic layer deposited dielectric layers
US7135369B2 (en) 2003-03-31 2006-11-14 Micron Technology, Inc. Atomic layer deposited ZrAlxOy dielectric layers including Zr4AlO9
US7105403B2 (en) * 2003-07-28 2006-09-12 Micron Technology, Inc. Double sided container capacitor for a semiconductor device and method for forming same
US7230292B2 (en) 2003-08-05 2007-06-12 Micron Technology, Inc. Stud electrode and process for making same
US7208427B2 (en) * 2003-08-18 2007-04-24 Advanced Technology Materials, Inc. Precursor compositions and processes for MOCVD of barrier materials in semiconductor manufacturing
US20050233477A1 (en) * 2004-03-05 2005-10-20 Tokyo Electron Limited Substrate processing apparatus, substrate processing method, and program for implementing the method
US7374964B2 (en) 2005-02-10 2008-05-20 Micron Technology, Inc. Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics
US7687409B2 (en) 2005-03-29 2010-03-30 Micron Technology, Inc. Atomic layer deposited titanium silicon oxide films
US20060223267A1 (en) * 2005-03-31 2006-10-05 Stefan Machill Method of production of charge-trapping memory devices
US7662729B2 (en) 2005-04-28 2010-02-16 Micron Technology, Inc. Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer
US7572695B2 (en) 2005-05-27 2009-08-11 Micron Technology, Inc. Hafnium titanium oxide films
US7510983B2 (en) 2005-06-14 2009-03-31 Micron Technology, Inc. Iridium/zirconium oxide structure
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US7473637B2 (en) * 2005-07-20 2009-01-06 Micron Technology, Inc. ALD formed titanium nitride films
US7410910B2 (en) 2005-08-31 2008-08-12 Micron Technology, Inc. Lanthanum aluminum oxynitride dielectric films
US7615438B2 (en) * 2005-12-08 2009-11-10 Micron Technology, Inc. Lanthanide yttrium aluminum oxide dielectric films
US7592251B2 (en) * 2005-12-08 2009-09-22 Micron Technology, Inc. Hafnium tantalum titanium oxide films
US7531416B2 (en) * 2005-12-21 2009-05-12 E. I. Du Pont De Nemours And Company Thick film capacitors on ceramic interconnect substrates
US7709402B2 (en) 2006-02-16 2010-05-04 Micron Technology, Inc. Conductive layers for hafnium silicon oxynitride films
US8399056B2 (en) 2006-06-02 2013-03-19 L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude Method of forming high-k dielectric films based on novel titanium, zirconium, and hafnium precursors and their use for semiconductor manufacturing
US7759747B2 (en) 2006-08-31 2010-07-20 Micron Technology, Inc. Tantalum aluminum oxynitride high-κ dielectric
US7563730B2 (en) 2006-08-31 2009-07-21 Micron Technology, Inc. Hafnium lanthanide oxynitride films
JP5109394B2 (en) * 2007-02-14 2012-12-26 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof
WO2008127935A1 (en) * 2007-04-13 2008-10-23 The Board Of Trustees Of The University Of Illinois Metal complex compositions and methods for making metal-containing films
US7759237B2 (en) * 2007-06-28 2010-07-20 Micron Technology, Inc. Method of forming lutetium and lanthanum dielectric structures
KR100939773B1 (en) * 2007-06-29 2010-01-29 주식회사 하이닉스반도체 Metal line of semiconductor device and method for manufacturing the same
US8026168B2 (en) * 2007-08-15 2011-09-27 Tokyo Electron Limited Semiconductor device containing an aluminum tantalum carbonitride barrier film and method of forming
KR100924557B1 (en) 2008-01-04 2009-11-02 주식회사 하이닉스반도체 Metal wiring of semiconductor device and method of manufacturing the same
JP5535945B2 (en) 2008-02-27 2014-07-02 レール・リキード−ソシエテ・アノニム・プール・レテュード・エ・レクスプロワタシオン・デ・プロセデ・ジョルジュ・クロード A method of forming a titanium-containing layer on a substrate using an atomic layer deposition (ald) Method
US20090246952A1 (en) * 2008-03-28 2009-10-01 Tokyo Electron Limited Method of forming a cobalt metal nitride barrier film
US7985680B2 (en) * 2008-08-25 2011-07-26 Tokyo Electron Limited Method of forming aluminum-doped metal carbonitride gate electrodes
US8618661B2 (en) * 2011-10-03 2013-12-31 Texas Instruments Incorporated Die having coefficient of thermal expansion graded layer
DE112011105710T5 (en) * 2011-10-07 2014-06-26 Intel Corporation Forming a DRAM capacitor under a metal interconnect
US9286285B1 (en) * 2012-10-30 2016-03-15 Google Inc. Formula editor
US8728927B1 (en) * 2012-12-10 2014-05-20 International Business Machines Corporation Borderless contacts for semiconductor transistors
US9236467B2 (en) * 2013-02-19 2016-01-12 Applied Materials, Inc. Atomic layer deposition of hafnium or zirconium alloy films
US9311289B1 (en) 2013-08-16 2016-04-12 Google Inc. Spreadsheet document tab conditional formatting
US9959265B1 (en) 2014-05-08 2018-05-01 Google Llc Populating values in a spreadsheet using semantic cues
US9663547B2 (en) 2014-12-23 2017-05-30 L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude Silicon- and Zirconium-containing compositions for vapor deposition of Zirconium-containing films
US9499571B2 (en) 2014-12-23 2016-11-22 L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude Germanium- and zirconium-containing compositions for vapor deposition of zirconium-containing films
WO2017171767A1 (en) * 2016-03-31 2017-10-05 Intel Corporation Diffusion barriers

Citations (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US498562A (en) * 1893-05-30 Hitching device
US5142438A (en) * 1991-11-15 1992-08-25 Micron Technology, Inc. Dram cell having a stacked capacitor with a tantalum lower plate, a tantalum oxide dielectric layer, and a silicide buried contact
US5187638A (en) * 1992-07-27 1993-02-16 Micron Technology, Inc. Barrier layers for ferroelectric and pzt dielectric on silicon
US5198386A (en) * 1992-06-08 1993-03-30 Micron Technology, Inc. Method of making stacked capacitors for DRAM cell
US5362632A (en) * 1994-02-08 1994-11-08 Micron Semiconductor, Inc. Barrier process for Ta2 O5 capacitor
US5406447A (en) * 1992-01-06 1995-04-11 Nec Corporation Capacitor used in an integrated circuit and comprising opposing electrodes having barrier metal films in contact with a dielectric film
US5414301A (en) * 1985-03-15 1995-05-09 National Semiconductor Corporation High temperature interconnect system for an integrated circuit
US5464786A (en) * 1994-10-24 1995-11-07 Micron Technology, Inc. Method for forming a capacitor having recessed lateral reaction barrier layer edges
US5478772A (en) * 1993-04-02 1995-12-26 Micron Technology, Inc. Method for forming a storage cell capacitor compatible with high dielectric constant materials
US5486492A (en) * 1992-10-30 1996-01-23 Kawasaki Steel Corporation Method of forming multilayered wiring structure in semiconductor device
US5489548A (en) * 1994-08-01 1996-02-06 Texas Instruments Incorporated Method of forming high-dielectric-constant material electrodes comprising sidewall spacers
US5504041A (en) * 1994-08-01 1996-04-02 Texas Instruments Incorporated Conductive exotic-nitride barrier layer for high-dielectric-constant materials
US5506166A (en) * 1993-04-02 1996-04-09 Micron Technology, Inc. Method for forming capacitor compatible with high dielectric constant materials having a low contact resistance layer
US5567964A (en) * 1993-06-29 1996-10-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US5568352A (en) * 1995-01-26 1996-10-22 Samsung Electronics Co., Ltd. Capacitor and manufacturing method thereof
US5585300A (en) * 1994-08-01 1996-12-17 Texas Instruments Incorporated Method of making conductive amorphous-nitride barrier layer for high-dielectric-constant material electrodes
US5605857A (en) * 1993-02-12 1997-02-25 Micron Technology, Inc. Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells
US5654222A (en) * 1995-05-17 1997-08-05 Micron Technology, Inc. Method for forming a capacitor with electrically interconnected construction
US5663088A (en) * 1995-05-19 1997-09-02 Micron Technology, Inc. Method of forming a Ta2 O5 dielectric layer with amorphous diffusion barrier layer and method of forming a capacitor having a Ta2 O5 dielectric layer and amorphous diffusion barrier layer
US5686339A (en) * 1995-10-18 1997-11-11 Lg Semicon Co., Ltd. High dielectric constant capacitor and a fabricating method thereof
US5688724A (en) * 1992-07-02 1997-11-18 National Semiconductor Corporation Method of providing a dielectric structure for semiconductor devices
US5690727A (en) * 1991-12-13 1997-11-25 Symetrix Corporation Thin films of ABO3 with excess B-site modifiers and method of fabricating integrated circuits with same
US5696018A (en) * 1994-08-01 1997-12-09 Texas Instruments Incorporated Method of forming conductive noble-metal-insulator-alloy barrier layer for high-dielectric-constant material electrodes
US5717250A (en) * 1994-08-15 1998-02-10 Micron Technology, Inc. Sputter and CVD deposited titanium nitride barrier layer between a platinum layer and a polysilicon plug
US5760474A (en) * 1996-07-09 1998-06-02 Micron Technology, Inc. Capacitor, integrated circuitry, diffusion barriers, and method for forming an electrically conductive diffusion barrier
US5834803A (en) * 1994-11-11 1998-11-10 Fuji Xerox Co., Ltd. Oriented ferroelectric thin film element and process for preparing the same
US5895938A (en) * 1996-02-16 1999-04-20 Kabushiki Kaisha Toshiba Semiconductor device using semiconductor BCN compounds
US5899740A (en) * 1997-03-04 1999-05-04 Samsung Electronics Co., Ltd. Methods of fabricating copper interconnects for integrated circuits
US6054331A (en) * 1997-01-15 2000-04-25 Tong Yang Cement Corporation Apparatus and methods of depositing a platinum film with anti-oxidizing function over a substrate
US6090697A (en) * 1997-06-30 2000-07-18 Texas Instruments Incorporated Etchstop for integrated circuits
US6100200A (en) * 1998-12-21 2000-08-08 Advanced Technology Materials, Inc. Sputtering process for the conformal deposition of a metallization or insulating layer
US6194754B1 (en) * 1999-03-05 2001-02-27 Telcordia Technologies, Inc. Amorphous barrier layer in a ferroelectric memory cell
US6284646B1 (en) * 1997-08-19 2001-09-04 Samsung Electronics Co., Ltd Methods of forming smooth conductive layers for integrated circuit devices
US6294420B1 (en) * 1997-01-31 2001-09-25 Texas Instruments Incorporated Integrated circuit capacitor
US6320213B1 (en) * 1997-12-19 2001-11-20 Advanced Technology Materials, Inc. Diffusion barriers between noble metal electrodes and metallization layers, and integrated circuit and semiconductor devices comprising same
US6365527B1 (en) * 2000-10-06 2002-04-02 United Microelectronics Corp. Method for depositing silicon carbide in semiconductor devices
US6455419B1 (en) * 1998-01-12 2002-09-24 Texas Instruments Incorporated System and method of forming a tungsten plug
US6580111B2 (en) * 2000-06-07 2003-06-17 Samsung Electronics Co., Ltd. Metal-insulator-metal capacitor

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5290588A (en) * 1991-12-19 1994-03-01 Advanced Micro Devices, Incorporated TiW barrier metal process
US5498562A (en) 1993-04-07 1996-03-12 Micron Technology, Inc. Semiconductor processing methods of forming stacked capacitors
US5246881A (en) * 1993-04-14 1993-09-21 Micron Semiconductor, Inc. Low-pressure chemical vapor deposition process for depositing high-density, highly-conformal, titanium nitride films of low bulk resistivity
WO1996035932A1 (en) 1995-05-11 1996-11-14 Matsushita Electric Industrial Co., Ltd. Temperature sensor element, temperature sensor having the same and method for producing the same temperature sensor element
US5877087A (en) * 1995-11-21 1999-03-02 Applied Materials, Inc. Low temperature integrated metallization process and apparatus
US6017818A (en) * 1996-01-22 2000-01-25 Texas Instruments Incorporated Process for fabricating conformal Ti-Si-N and Ti-B-N based barrier films with low defect density
US6313035B1 (en) * 1996-05-31 2001-11-06 Micron Technology, Inc. Chemical vapor deposition using organometallic precursors
US6087674A (en) * 1996-10-28 2000-07-11 Energy Conversion Devices, Inc. Memory element with memory material comprising phase-change material and dielectric material
EP0854505A3 (en) * 1997-01-21 1998-11-11 Texas Instruments Incorporated Process of depositing a TiN based film during the fabrication of a semiconductor device
US5933365A (en) * 1997-06-19 1999-08-03 Energy Conversion Devices, Inc. Memory element with energy control mechanism
US6156630A (en) * 1997-08-22 2000-12-05 Micron Technology, Inc. Titanium boride gate electrode and interconnect and methods regarding same
US6235631B1 (en) * 1997-10-30 2001-05-22 Texas Instruments Incorporated Method for forming titanium aluminum nitride layers
US6117772A (en) * 1998-07-10 2000-09-12 Ball Semiconductor, Inc. Method and apparatus for blanket aluminum CVD on spherical integrated circuits
US6090474A (en) * 1998-09-01 2000-07-18 International Business Machines Corporation Flowable compositions and use in filling vias and plated through-holes

Patent Citations (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US498562A (en) * 1893-05-30 Hitching device
US5414301A (en) * 1985-03-15 1995-05-09 National Semiconductor Corporation High temperature interconnect system for an integrated circuit
US5142438A (en) * 1991-11-15 1992-08-25 Micron Technology, Inc. Dram cell having a stacked capacitor with a tantalum lower plate, a tantalum oxide dielectric layer, and a silicide buried contact
US5690727A (en) * 1991-12-13 1997-11-25 Symetrix Corporation Thin films of ABO3 with excess B-site modifiers and method of fabricating integrated circuits with same
US5406447A (en) * 1992-01-06 1995-04-11 Nec Corporation Capacitor used in an integrated circuit and comprising opposing electrodes having barrier metal films in contact with a dielectric film
US5198386A (en) * 1992-06-08 1993-03-30 Micron Technology, Inc. Method of making stacked capacitors for DRAM cell
US5688724A (en) * 1992-07-02 1997-11-18 National Semiconductor Corporation Method of providing a dielectric structure for semiconductor devices
US5187638A (en) * 1992-07-27 1993-02-16 Micron Technology, Inc. Barrier layers for ferroelectric and pzt dielectric on silicon
US5486492A (en) * 1992-10-30 1996-01-23 Kawasaki Steel Corporation Method of forming multilayered wiring structure in semiconductor device
US5605857A (en) * 1993-02-12 1997-02-25 Micron Technology, Inc. Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells
US5478772A (en) * 1993-04-02 1995-12-26 Micron Technology, Inc. Method for forming a storage cell capacitor compatible with high dielectric constant materials
US5506166A (en) * 1993-04-02 1996-04-09 Micron Technology, Inc. Method for forming capacitor compatible with high dielectric constant materials having a low contact resistance layer
US5567964A (en) * 1993-06-29 1996-10-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US5362632A (en) * 1994-02-08 1994-11-08 Micron Semiconductor, Inc. Barrier process for Ta2 O5 capacitor
US5489548A (en) * 1994-08-01 1996-02-06 Texas Instruments Incorporated Method of forming high-dielectric-constant material electrodes comprising sidewall spacers
US5585300A (en) * 1994-08-01 1996-12-17 Texas Instruments Incorporated Method of making conductive amorphous-nitride barrier layer for high-dielectric-constant material electrodes
US5696018A (en) * 1994-08-01 1997-12-09 Texas Instruments Incorporated Method of forming conductive noble-metal-insulator-alloy barrier layer for high-dielectric-constant material electrodes
US5504041A (en) * 1994-08-01 1996-04-02 Texas Instruments Incorporated Conductive exotic-nitride barrier layer for high-dielectric-constant materials
US5851896A (en) * 1994-08-01 1998-12-22 Texas Instruments Incorporated Conductive exotic-nitride barrier layer for high-dielectric-constant material electrodes
US5665628A (en) * 1994-08-01 1997-09-09 Texas Instruments Incorporated Method of forming conductive amorphous-nitride barrier layer for high-dielectric-constant material electrodes
US5679980A (en) * 1994-08-01 1997-10-21 Texas Instruments Incorporated Conductive exotic-nitride barrier layer for high-dielectric-constant material electrodes
US5717250A (en) * 1994-08-15 1998-02-10 Micron Technology, Inc. Sputter and CVD deposited titanium nitride barrier layer between a platinum layer and a polysilicon plug
US5464786A (en) * 1994-10-24 1995-11-07 Micron Technology, Inc. Method for forming a capacitor having recessed lateral reaction barrier layer edges
US5654224A (en) * 1994-10-24 1997-08-05 Micron Technology, Inc. Capacitor construction with oxidation barrier blocks
US5834803A (en) * 1994-11-11 1998-11-10 Fuji Xerox Co., Ltd. Oriented ferroelectric thin film element and process for preparing the same
US5568352A (en) * 1995-01-26 1996-10-22 Samsung Electronics Co., Ltd. Capacitor and manufacturing method thereof
US5654222A (en) * 1995-05-17 1997-08-05 Micron Technology, Inc. Method for forming a capacitor with electrically interconnected construction
US5663088A (en) * 1995-05-19 1997-09-02 Micron Technology, Inc. Method of forming a Ta2 O5 dielectric layer with amorphous diffusion barrier layer and method of forming a capacitor having a Ta2 O5 dielectric layer and amorphous diffusion barrier layer
US5686339A (en) * 1995-10-18 1997-11-11 Lg Semicon Co., Ltd. High dielectric constant capacitor and a fabricating method thereof
US5895938A (en) * 1996-02-16 1999-04-20 Kabushiki Kaisha Toshiba Semiconductor device using semiconductor BCN compounds
US5760474A (en) * 1996-07-09 1998-06-02 Micron Technology, Inc. Capacitor, integrated circuitry, diffusion barriers, and method for forming an electrically conductive diffusion barrier
US6054331A (en) * 1997-01-15 2000-04-25 Tong Yang Cement Corporation Apparatus and methods of depositing a platinum film with anti-oxidizing function over a substrate
US6294420B1 (en) * 1997-01-31 2001-09-25 Texas Instruments Incorporated Integrated circuit capacitor
US5899740A (en) * 1997-03-04 1999-05-04 Samsung Electronics Co., Ltd. Methods of fabricating copper interconnects for integrated circuits
US6090697A (en) * 1997-06-30 2000-07-18 Texas Instruments Incorporated Etchstop for integrated circuits
US6284646B1 (en) * 1997-08-19 2001-09-04 Samsung Electronics Co., Ltd Methods of forming smooth conductive layers for integrated circuit devices
US6320213B1 (en) * 1997-12-19 2001-11-20 Advanced Technology Materials, Inc. Diffusion barriers between noble metal electrodes and metallization layers, and integrated circuit and semiconductor devices comprising same
US6455419B1 (en) * 1998-01-12 2002-09-24 Texas Instruments Incorporated System and method of forming a tungsten plug
US6100200A (en) * 1998-12-21 2000-08-08 Advanced Technology Materials, Inc. Sputtering process for the conformal deposition of a metallization or insulating layer
US6194754B1 (en) * 1999-03-05 2001-02-27 Telcordia Technologies, Inc. Amorphous barrier layer in a ferroelectric memory cell
US6580111B2 (en) * 2000-06-07 2003-06-17 Samsung Electronics Co., Ltd. Metal-insulator-metal capacitor
US6365527B1 (en) * 2000-10-06 2002-04-02 United Microelectronics Corp. Method for depositing silicon carbide in semiconductor devices

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090263974A1 (en) * 2001-08-28 2009-10-22 Shusaku Kido Substrate processing system for performing exposure process in gas atmosphere
US20090127105A1 (en) * 2004-08-20 2009-05-21 Micron Technology, Inc. Systems and methods for forming niobium and/or vanadium containing layers using atomic layer deposition
US7837797B2 (en) 2004-08-20 2010-11-23 Micron Technology, Inc. Systems and methods for forming niobium and/or vanadium containing layers using atomic layer deposition
US20060086961A1 (en) * 2004-10-21 2006-04-27 Elpida Memory, Inc. Semiconductor device having a stacked capacitor
WO2010135576A2 (en) * 2009-05-21 2010-11-25 Cornell Research Foundation, Inc. Conducting metal oxide and metal nitride nanoparticles
WO2010135576A3 (en) * 2009-05-21 2011-02-24 Cornell Research Foundation, Inc. Conducting metal oxide and metal nitride nanoparticles
CN102459085A (en) * 2009-05-21 2012-05-16 康奈尔大学 Conducting metal oxide and metal nitride nanoparticles
US9850140B2 (en) 2009-05-21 2017-12-26 Cornell University Conducting metal oxide and metal nitride nanoparticles
US9142609B2 (en) * 2010-01-14 2015-09-22 Renesas Electronics Corporation MIM capacitor device
US20110169132A1 (en) * 2010-01-14 2011-07-14 Renesas Electronics Corporation Semiconductor device and manufacturing method of semiconductor device
US9379178B2 (en) 2010-01-14 2016-06-28 Renesas Electronics Corporation Manufacturing method of semiconductor device comprising a capacitor element
US8940601B2 (en) 2011-07-07 2015-01-27 Renesas Electronics Corporation Manufacturing method of semiconductor device
CN103946957A (en) * 2011-11-08 2014-07-23 应用材料公司 Deposition of metal films using alane-based precursors
US8927059B2 (en) * 2011-11-08 2015-01-06 Applied Materials, Inc. Deposition of metal films using alane-based precursors
US20130115383A1 (en) * 2011-11-08 2013-05-09 Xinliang Lu Deposition of metal films using alane-based precursors
WO2013070702A1 (en) * 2011-11-08 2013-05-16 Applied Materials, Inc. Deposition of metal films using alane-based precursors
US9145612B2 (en) 2012-07-06 2015-09-29 Applied Materials, Inc. Deposition of N-metal films comprising aluminum alloys
WO2014008365A1 (en) * 2012-07-06 2014-01-09 Applied Materials, Inc. Deposition of n-metal films comprising aluminum alloys

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