Connect public, paid and private patent data with Google Patents Public Datasets

Efficient subprogram return in microprocessors

Download PDF

Info

Publication number
US20060282821A1
US20060282821A1 US11149611 US14961105A US2006282821A1 US 20060282821 A1 US20060282821 A1 US 20060282821A1 US 11149611 US11149611 US 11149611 US 14961105 A US14961105 A US 14961105A US 2006282821 A1 US2006282821 A1 US 2006282821A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
return
register
operation
instruction
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11149611
Inventor
Erik Renno
Oyvind Strom
Morten Lund
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30072Arrangements for executing specific machine instructions to perform conditional operations, e.g. using guard
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/3005Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30054Unconditional branch instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/30094Condition code generation, e.g. Carry, Zero flag
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802Instruction prefetching
    • G06F9/3804Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer

Abstract

A method and medium for performing subroutine return operations. Test operations are performed in parallel with other operations in a return operation. These test operations and the return operations are performed in response to a single instruction.

Description

    FIELD OF THE INVENTION
  • [0001]
    This invention relates to subprogram return operations in microprocessors.
  • BACKGROUND
  • [0002]
    Programs frequently feature subroutines which perform a specific task. After the task is performed, program flow returns from the subroutine to the main program. One common mechanism for performing a subroutine return involves conditionally or unconditionally moving the contents of a return address register into a program counter and then continuing program execution. A return value register may also be updated with a constant literal that may represent a Boolean value. Another approach to subprogram returns is to “pop” a return address from the stack and into the program counter and continue program execution from there. This operation may also pop any spooled-out register file contents from the stack into the register file.
  • [0003]
    These methods for performing subroutine returns take several cycles to execute. In FIG. 1, when a traditional return (“RET”) instruction is executed in a typical pipelined CPU, five cycles 10 are required to execute the instruction. In FIG. 2, a typical pipelined CPU contains a Program Counter (“PC”) 42 and an instruction memory 44. The CPU has four different pipeline registers 46, 52, 56, and 60 separating the different pipeline stages. The Instruction Decode stage (between registers 46 and 52) contains both a control/decode unit (“CU”) 48 for decoding the current instruction and generating control signals and a register file 50. The Execution Stage (between registers 52 and 56) contains an Arithmetic Logic Unit (“ALU”) 54. The Memory Stage (between registers 56 and 60) contains a data memory 58.) With continued reference to FIG. 1, during cycle 1, in the Instruction Fetch (“IF”) stage 12, the RET instruction is fetched (block 22). In cycle 2, in the Instruction Decode (“ID”) stage 14, correct control signals are generated and the return address register is read from the register file (block 24). In cycle 3, in the Execution (“EX”) stage 16, the return address register content is written through the Arithmetic Logic Unit (“ALU”) with no change (block 26). During cycle 4, in the Memory (“MEM”) stage, the return address register content is written past the data memory. Finally, in cycle 5, in the Writeback (“WB”) 20 stage, the return address register content is written to the Program Counter (“PC”) and the pipeline is flushed (block 30). Once the pipeline is flushed, the pipeline does not contain any instructions until the instruction at the return address is read from program memory. Therefore, several clock cycles are wasted in the pipeline flush process.
  • [0004]
    A similar issue exists for a return instruction (“RETMEM”) popping the return address register from a stack in memory. As shown in FIG. 3, in cycle 1, in the IF stage, the RETMEM instruction is fetched (block 32). During cycle 2, in the ID stage, the correct control signals are generated. In cycle 3, during the EX stage, the control signals to the data memory are routed past the ALU (block 36). In cycle 4, in the MEM stage, the return address is read from data memory (block 38). Finally, in cycle 5, in the WB stage, the return address read from memory is written to PC and the pipeline is flushed (block 40). As with the return instruction discussed in FIG. 1, several cycles are wasted after the pipeline flush.
  • [0005]
    It would be advantageous to provide a more efficient subroutine return operation.
  • SUMMARY
  • [0006]
    In an exemplary embodiment, an instruction is fetched which requires a return operation and sets status flags based on the contents of a return value register. The status flags are set in parallel with at least one other operation required to process the return instruction. The status flags are set before one of the following occurs: i) contents of a return address register are moved into a program counter; or ii) a return address is popped from a stack and into the program counter. In another embodiment, a processor-readable storage medium causes a processor to perform this subroutine return operation.
  • [0007]
    In yet another exemplary embodiment of the invention, a subroutine return operation places a return address into a program counter. A test operation is executed on a return value register; the test operation is performed in parallel with at least one other operation required to process the return operation. The program flow is changed to a target address. Each of the above-mentioned steps is performed in response to a single instruction. In one embodiment, a processor-readable storage medium stores an instruction that causes a processor to perform this subroutine return operation.
  • BRIEF DESCRIPTION OF HTE DRAWINGS
  • [0008]
    FIG. 1 is a chart showing how a return instruction is executed in the prior art.
  • [0009]
    FIG. 2 is a block diagram of a pipelined CPU in the prior art.
  • [0010]
    FIG. 3 is a chart showing how a return instruction popping the return address register from a stack in memory is executed in the prior art.
  • [0011]
    FIG. 4 is a block diagram of a pipelined CPU in an exemplary embodiment of the present invention.
  • [0012]
    FIG. 5 is a chart showing an exemplary execution of a return instruction in an embodiment of the present invention.
  • [0013]
    FIG. 6 is a chart showing an exemplary execution of a return instruction popping the return address register from a stack in memory is executed in an embodiment of the present invention.
  • DETAILED DESCRIPTION
  • [0014]
    A more efficient subroutine return operation is provided in which status flags are updated (in the processor's status register) according to a test of the return value register during the subroutine return operation. (In the prior art, test operations, for instance, a test of the return value register, are performed in response to a separate instruction.) In one embodiment, the status flags are set in parallel with operations to execute single instructions such as conditional return instructions as well as single instructions incorporating a return operation. The instructions are stored in a processor-readable medium, which includes any medium that can store or transfer information, such as an electronic circuit, a semiconductor memory device, a ROM, a flash memory, a floppy diskette, a compact disc, an optical disc, etc.
  • [0015]
    These instructions can be executed by existing hardware. In FIG. 4, an exemplary CPU for executing these instructions includes a PC 62 and instruction memory 64. The CPU contains four pipeline registers (IF/ID 66, ID/EX 70, EX/MEM 74, and MEM/WB 78) separating the different stages. The ID stage, between registers 66 and 70, contains a control/decode unit 68 for decoding the current instruction and generating the correct control signals. The ID stage also contains a register file 132. The EX stage, between registers 70 and 74, contains an ALU 72 and a flag register 84. The MEM stage, between registers 74 and 78, contains data memory 76. When an address has reached the WB stage (after register 78), the pipeline has been flushed and the fetch address is written to PC 62. A multiplexer 118 determines which address is written into the register file or the program counter (this is discussed in greater detail, below). In other embodiments, the processor may have different features, such as data forwarding; as noted above, the CPU described in FIG. 4 is exemplary and is not the only processor which can execute the more efficient subroutine return operation described herein.
  • [0016]
    In one embodiment of the invention, test operations are performed in parallel with other operations during execution of instructions with the more efficient subroutine return operation. In one embodiment, shown in FIG. 5, when a return (“return_with_test”) instruction is executed, during cycle 1 in the IF stage, the return_with_test instruction is fetched (block 86). In cycle, 2, the return_with_test has entered the ID stage; the correct control signals are generated and the return address register is read from the register file (block 88). In cycle 3, the return_with_test is kept in the ID stage an additional cycle (in one embodiment, this may be done in the decode stage by splitting the instruction into two “micro-operations”: one micro-operation performs the test operation, the other micro-operation performs the return operation); in this second cycle, the return value register is read from the register file and control signals to instruct the ALU to perform the test operation are generated (block 90). In cycle 3 in the EX stage, the return address content is written through the ALU with no change (block 92). During cycle 4 in the EX stage, the ALU sets the flags corresponding to the test of the value register (block 94). (In this embodiment, the status flags are set according to a comparison of the return value register's contents with zero. Status flags used in this embodiment indicate overflow (“V”), a negative value (“N”), a zero result (“Z”), and a carry after an arithmetic or logic operation (“C”). Different status flags may be used in other embodiments and/or status flags may be set differently in other embodiments.) During cycle 4 in the MEM stage, the return address register content is written past the data memory (block 96). During cycle 5, in the WB stage, the return address register content is written to the PC and the pipeline is flushed (block 98). A test operation has been performed using cycles that would otherwise be unused due to the pipeline flush.
  • [0017]
    In another embodiment, a test operation may be performed during execution of a return instruction (“pop_with_test”) popping the return address register from a stack in memory. In FIG. 6, in cycle 1 in the IF stage, the pop_with_test instruction is fetched (block 100). During cycle 2, in the ID stage, the correct control signals are generated (block 102). In cycle 3, the pop_with_test is kept in the ID an additional cycle (in one embodiment, the instruction is decoded into two micro-operations (the subroutine return operation and the test operation) in the ID stage); the return value register is read from the register file and control signals to instruct the ALU to perform the test operation are generated (block 104). In cycle 3, in the EX stage, the control signals to data memory are routed past the ALU (block 106). In cycle 4, in the EX stage, the ALU sets the flags corresponding to the test of the return value register (block 108). During the same cycle, in the MEM stage, the return address is read from data memory (block 110). In cycle 5, in the WB stage, the return address read from memory is written to PC and the pipeline is flushed (block 112).
  • [0018]
    Other embodiments of the invention may vary from the embodiments discussed above. These embodiments may require fewer or additional clock cycles to execute instructions. Other embodiments may require different hardware to execute the instructions. Still other embodiments may be incorporated into different subprogram return operations and instructions.
  • [0019]
    FIGS. 5 and 6 are exemplary embodiments of “return_with_test” and “pop_with_test” instructions, respectively. In the “return_with_test” instruction, a “return” is performed together with testing the value in the return value register. The “test” tests the specified register and sets the condition code flags accordingly. The “pop_with_test” instruction performs a “pop” (loading a word from the stack into a specified register or a program counter; popping to PC flushes the pipeline and starts fetching instructions from the address loaded from the stack) together with testing the value in the return value register.
  • [0020]
    Various signals are required from the control/decode unit. Returning to FIG. 4, the following signals required in one embodiment are:
    • pcmux_sel 114—Selector signal used to choose if the program counter is going to be updated with the sequential program address or the address given by the return instruction.
    • wbmux_sel 116—Selector signal used by the writeback stage to determine which address is to be written into the register file or into the program counter. If signal is logic “0,” the address comes from the ALU result from the EX/MEM pipeline stage. If the signal is logic “1,” the address comes from the data memory.
    • as_ctrl 120—Control signal used to choose if the adder in the ALU will perform subtraction or addition on the operands from the register file.
    • zeromux_sel 122—Signal used to force input operand B to the ALU to integer value zero.
    • readreg1 124—Register file register number for operand 1.
    • readreg2 126—Register file register for operand 2.
    • loadflag 128—Control signal to allow the status register to update the flag settings.
    • writeaddr130—Register file register number for the register where the result is written back.
  • [0029]
    The following table lists exemplary outputs from the control/decode unit in the cycles of the RET instruction. The registers identified in the table are:
    • R12—the Return Value Register. Test operations are performed on this register.
    • LR—the Link Register. Keeps the address to return to after the subprogram has completed. LR may also be referred to as the Return Address Register (RAR)
    • PC—the Program Counter. Holds the address of the currently executing instruction.
  • [0033]
    The following table lists exemplary outputs from the control/decode unit in the cycles of the return_with_test instruction.
    Textual
    Cycle Control signal output instruction
    1 pcmux_sel = 1 Write the contents
    wbmux_sel = 0 of LR into the PC
    as_ctrl = add register so that
    zeromux_sel = 0 instruction fetch
    readreg1 = X (don't care value) will restart from
    readreg2 = LR this address.
    loadflag = 0
    writeadr = X (don't care value)
    2 pcmux_sel = 0 Test the contents
    wbmux_sel = X (don't care value) of the Return
    as_ctrl = sub Value Register by
    zeromux_sel = 0 comparing it with
    readreg1 = X (don't care value) the value 0.
    readreg2 = Return Value Write the
    Register resulting flags
    loadflag = 1 into the Flag
    writeadr = X (don't care value) Register.
  • [0034]
    The following table lists exemplary outputs from the control/decode unit in the cycles of the pop_with_test instruction.
    Textual
    Cycle Control signal output instruction
    1 pcmux_sel = 1 Write the contents
    wbmux_sel = 1 of the return
    as_ctrl = add address read from
    zeromux_sel = 0 memory into the PC
    readreg1 = X (don't care value) register so that
    readreg2 = Pointer Register instruction fetch
    loadflag = 0 will restart from
    writeadr = X (don't care value) this address. The
    return address
    resides in a
    memory address
    pointed to by the
    pointer register.
    2 pcmux_sel = 0 Test the contents
    wbmux_sel = X (don't care value) of the Return
    as_ctrl = sub Value Register by
    zeromux_sel = 0 comparing it with
    readreg1 = X (don't care value) the value 0.
    readreg2 = Return Value Write the
    Register resulting flags
    loadflag = 1 into the Flag
    writeadr = X (don't care value) Register.
  • [0035]
    The “return_with_test” and “pop_with_test” instructions can be executed as part of other instructions. For instance, the “return_with_test” instruction can be executed as part of a conditional return instruction, in which there is a return from the subroutine if a specified condition is true. Values are moved into the return register, the return value is tested, and flags are set. A specific example of this instruction is the “ret{cond4}” instruction in the ATMEL AVR32 instruction set. The following pseudocode describes the ret{cond4} instruction (SP is the stack pointer register):
  • [0036]
    Operation:
    I. If (cond4)
    If (Rs != {LR, SP, PC})
    R12 Rs;
    else if (Rs == LR)
    R12 −1;
    else if (Rs == SP)
    R12 0;
    else
    R12 4 1;
    Test R12 and set flags;
    PC 4 LR;
    Syntax:
    I. ret{cond4} Rs
    Operands:
    I. cond4 ε {eq, ne, cc/hs, cs/lo, ge, lt, mi, pl, ls, gt,
    le, hi, vs, vc, qs, ab}
    s ε{0, 1, . . . , 15}
    Status Flags:
    Flags are set as result of the operation CP R12, 0.
    V: V 0
    N: N 4 RES[31]
    Z: Z 4 (RES[31:0] == 0)
    C: C 4 0
  • [0037]
    The following table explains some of the mnemonics used above and the pseudocode for the “Load Multiple Registers” instruction, below:
    Mnemonic Meaning
    eq Equal
    ne Not equal
    cc/hs Higher or same
    cs/lo Lower
    ge Greater than
    or equal
    lt Less than
    mi Minus/negative
    pl Plus/positive
    ls Lower or same
    gt Greater than
    le Less than or
    equal
    hi Higher
    vs Overflow
    vc No overflow
    qs Saturation
    al Always

    The operation CP R12, 0 is a comparison or subtraction operation without operation. In this particular case, the result of the operation=R12−0.
  • [0038]
    Another instruction in which the “return_with_test” operation may be employed is the “Load Multiple Registers” instruction from the AVR 32 instruction set. This instruction loads consecutive words pointed to by the register pointer into the register specified in the instruction. The PC can be loaded, resulting in a jump to the loaded target address. If the PC is loaded, the return value in R12 is tested and the flags are updated. The return value optionally may be set to −1, 0, or 1. The following pseudocode describes this instruction (SP is a stack pointer):
    I. Loadaddress Rp;
    if Reglist16[PC] == 1 then
    if Rp == PC then
    Loadaddress SP;
    PC * (Loadaddress++);
    if Rp == PC then
    if Reglist16[LR,R12] == B′00
    R12 0;
    else if Reglist16[LR,R12] == B′01
    R12 1;
    else
    R12 −1;
    Test R12 and update flags;
    else
    Test R12 and update flags;
    if Reglist16[LR] == 1
    LR *(Loadaddress++);
    if Reglist16[SP] == 1
    SP *(Loadaddress++);
    if Reglist16[R12] == 1
    R12 *(Loadaddress++);
    else
    if Reglist16[LR] == 1
    LR *(Loadaddress++);
    if Reglist16[SP] == 1
    SP *(Loadaddress++);
    if Reglist16[R12] == 1
    R12 *(Loadaddress++);
    for (i = 11 to 0)
    if Reglist16[i] == 1 then
    Ri *(Loadaddress++);
    if Opcode[++] == 1 then
    if Rp == PC then
    SP Loadaddress;
    else
    Rp Loadaddress;
    Syntax:
    I. ldm Rp{++}, Reglist16
    Operands:
    I. Reglist16 ε {R0, R1, R2, . . . , R12, LR, SP, PC}
    p ε {0, 1, . . . , 15}
    Status Flags:
    Flags are only updated if Reglist16[PC] == 1.
    They are set as the result of the operation CP R12, 0.
    V: V 0
    N: N RES [31]
    Z: Z (RES[31:0] == 0)
    C: C 0
  • [0039]
    Similar instructions employing the “pop_with_test” operation may be employed in which words pointed to by SP are loaded into registers specified in the instruction.
  • [0040]
    An instruction in which the “pop_with_test” operation may be employed is the Pop Multiple Registers from Stack (“POPM”) instruction from the AVR 32 instruction set. This instruction loads the consecutive words pointed to by SP into the registers specified in the instruction.
  • [0041]
    While specific examples have been cited above showing how the subroutine return operation may be employed in different instructions, other embodiments may incorporate the subroutine operation into different instructions.
  • [0042]
    One advantage of the more efficient subroutine return operations is the reduction in code size, since an explicit “test return register” instruction can be eliminated since the test operation may be performed implicitly by the return operation. Another advantage is that execution time is reduced since the return register test is performed in parallel with the fetching of the instruction to which the program will return.
  • [0043]
    The instructions and operations described above may be employed in both RISC and CISC machines.
  • [0044]
    Although the present invention has been described in terms of specific exemplary embodiments, one skilled in the art will recognize variations and additions to the embodiments may be made without departing from the principles of the present invention. For instance, return operations may require more or fewer cycles to be executed, or the return operations may be part of different instructions, or the processors executing the return operations may have different architectures. In another embodiment, more hardware may be added so the return operations could be completed in one cycle (i.e., the two micro-operations performed in response to a single instruction are completed in one cycle).

Claims (27)

1. A method for performing a subroutine return operation, the method comprising:
a) fetching an instruction which requires the return operation; and
b) setting status flags based on contents of a return value register in parallel with at least one other operation required to process the return operation, the status flags set before one of the following occurs:
i) contents of a return address register are moved into a program counter; or
ii) a return address is popped from a stack and into the program counter.
2. The method of claim 1 wherein either the contents of the return address register are moved into the program counter or a return address is popped from the stack and into the program counter only when a test operation determines return conditions are satisfied.
3. The method of claim 1 wherein the return operation is split into two micro-operations, one micro-operation for performing the return operation, the other micro-operation for performing a test operation.
4. The method of claim 1 wherein the status flags are set in parallel with writing contents of a return address register through an Arithmetic Logic Unit of a microprocessor.
5. The method of claim 1 wherein the status flags are set in parallel with routing control signals to data memory of a microprocessor past an Arithmetic Logic Unit of the microprocessor.
6. The method of claim 1 wherein steps a) and b) are performed in response to a single instruction.
7. A processor-readable storage medium storing an instruction that, when executed by a processor, causes the processor to perform a method for performing a subroutine return operation, the method comprising:
a) fetching an instruction which requires the return operation; and
b) setting status flags based on contents of a return value register in parallel with at least one other operation required to process the return instruction, the status flags set before one of the following occurs:
i) contents of a return address register are moved into a program counter; or
ii) a return address is popped from a stack and into the program counter.
8. The processor-readable storage medium of claim 7 wherein either the contents of the return address register are moved into the program counter or a return address is popped from the stack and into the program counter only when a test operation determines return conditions are satisfied.
9. The processor-readable storage medium of claim 7 wherein the return operation is split into two micro-operations, one micro-operation for performing the return operation, the other micro-operation for performing a test operation.
10. The processor-readable storage medium of claim 7 wherein the status flags are set in parallel with writing contents of a return address register through an Arithmetic Logic Unit of a microprocessor.
11. The processor-readable storage medium of claim 7 wherein the status flags are set in parallel with routing control signals to data memory of the microprocessor past the Arithmetic Logic Unit of the microprocessor.
12. The processor-readable storage medium of claim 7, the method further comprising flushing a pipeline before either the contents of the return address register or the return address is written into the program counter.
13. The processor-readable storage medium of claim 7 wherein steps a) and b) are performed in response to a single instruction.
14. A method for performing a subroutine return operation comprising:
a) placing a return address into a program counter;
b) executing a test operation on a return value register, the test operation performed in parallel with at least one other operation required to process a return operation;
c) changing a flow of a program to a target address; and
d) performing steps a), b), and c) in response to a single instruction.
15. The method of claim 14 wherein the step of changing the flow of the program is performed only if the test operation determines return conditions are satisfied.
16. The method of claim 14 wherein the subroutine return operation is kept in an instruction decode stage for an additional cycle.
17. The method of claim 14 wherein status flags for the test operation are set in parallel with writing contents of a return address register through an Arithmetic Logic Unit of a microprocessor.
18. The method of claim 14 wherein status flags for the test operation are set in parallel with routing control signals to data memory of a microprocessor located downstream of an Arithmetic Logic Unit of the microprocessor.
19. The method of claim 14 further comprising loading multiple registers.
20. The method of claim 14 further comprising setting a return value in a return value register.
21. A processor-readable storage medium storing an instruction that, when executed by a processor, causes the processor to perform a method for performing a subroutine return operation, the method comprising:
a) placing a return address into a program counter;
b) executing a test operation on a return value register, the test operation performed in parallel with at least one other operation required to process a return operation;
c) changing a flow of a program to a target address; and
d) performing steps a), b), and c) in response to a single instruction.
22. The processor-readable storage medium of claim 21 wherein the step of changing the flow of the program is performed only if the test operation determines return conditions are satisfied.
23. The processor-readable storage medium of claim 21 wherein the return operation is kept in an instruction decode stage for an additional cycle.
24. The processor-readable storage medium of claim 21 wherein status flags for the test operation are set in parallel with writing contents of a return address register through an Arithmetic Logic Unit of a microprocessor.
25. The processor-readable storage medium of claim 21 wherein status flags for the test operation are set in parallel with routing control signals to data memory of the microprocessor located downstream of Arithmetic Logic Unit of the microprocessor.
26. The processor-readable storage medium of claim 23, the method further comprising loading multiple registers.
27. The processor-readable storage medium of claim 23, the method further comprising setting a return value in a return value register.
US11149611 2005-06-10 2005-06-10 Efficient subprogram return in microprocessors Abandoned US20060282821A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11149611 US20060282821A1 (en) 2005-06-10 2005-06-10 Efficient subprogram return in microprocessors

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US11149611 US20060282821A1 (en) 2005-06-10 2005-06-10 Efficient subprogram return in microprocessors
EP20060771282 EP1891519B1 (en) 2005-06-10 2006-05-25 Efficient subprogram return in microprocessors
CN 200680020713 CN101194228B (en) 2005-06-10 2006-05-25 Performance microprocessor and device of fast return of microcontroller subroutine
JP2008515743A JP2009508180A (en) 2005-06-10 2006-05-25 Efficient subprogram return in a microprocessor
PCT/US2006/020427 WO2006135549A8 (en) 2005-06-10 2006-05-25 Efficient subprogram return in microprocessors
KR20077029999A KR20080014062A (en) 2005-06-10 2006-05-25 Efficient subprogram return in microprocessors
US12795582 US8555041B2 (en) 2005-06-10 2010-06-07 Method for performing a return operation in parallel with setting status flags based on a return value register test

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12795582 Continuation US8555041B2 (en) 2005-06-10 2010-06-07 Method for performing a return operation in parallel with setting status flags based on a return value register test

Publications (1)

Publication Number Publication Date
US20060282821A1 true true US20060282821A1 (en) 2006-12-14

Family

ID=37525517

Family Applications (2)

Application Number Title Priority Date Filing Date
US11149611 Abandoned US20060282821A1 (en) 2005-06-10 2005-06-10 Efficient subprogram return in microprocessors
US12795582 Active 2026-02-03 US8555041B2 (en) 2005-06-10 2010-06-07 Method for performing a return operation in parallel with setting status flags based on a return value register test

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12795582 Active 2026-02-03 US8555041B2 (en) 2005-06-10 2010-06-07 Method for performing a return operation in parallel with setting status flags based on a return value register test

Country Status (6)

Country Link
US (2) US20060282821A1 (en)
JP (1) JP2009508180A (en)
KR (1) KR20080014062A (en)
CN (1) CN101194228B (en)
EP (1) EP1891519B1 (en)
WO (1) WO2006135549A8 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100088739A1 (en) * 2008-10-06 2010-04-08 International Business Machines Corporation Hardware Based Mandatory Access Control
US20100250904A1 (en) * 2005-06-10 2010-09-30 Atmel Corporation Methods and processor-related media to perform rapid returns from subroutines in microprocessors and microcontrollers

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101551749B (en) 2009-05-11 2012-08-22 中国科学院计算技术研究所 Method and system of random test program generation and design verification method

Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4814976A (en) * 1986-12-23 1989-03-21 Mips Computer Systems, Inc. RISC computer with unaligned reference handling and method for the same
US4891754A (en) * 1987-07-02 1990-01-02 General Datacomm Inc. Microinstruction sequencer for instructing arithmetic, logical and data move operations in a conditional manner
US4926355A (en) * 1987-07-02 1990-05-15 General Datacomm, Inc. Digital signal processor architecture with an ALU and a serial processing section operating in parallel
US5070451A (en) * 1984-11-21 1991-12-03 Harris Corporation Forth specific language microprocessor
US5386563A (en) * 1992-10-13 1995-01-31 Advanced Risc Machines Limited Register substitution during exception processing
US5515519A (en) * 1993-03-19 1996-05-07 Hitachi, Ltd. Data processor and method utilizing coded no-operation instructions
US5644699A (en) * 1991-08-07 1997-07-01 Mitsubishi Denki Kabushiki Kaisha Memory apparatus and data processor using the same
US5680599A (en) * 1993-09-15 1997-10-21 Jaggar; David Vivian Program counter save on reset system and method
US5701493A (en) * 1995-08-03 1997-12-23 Advanced Risc Machines Limited Exception handling method and apparatus in data processing systems
US5778208A (en) * 1995-12-18 1998-07-07 International Business Machines Corporation Flexible pipeline for interlock removal
US5884089A (en) * 1997-10-14 1999-03-16 Motorola, Inc. Method for calculating an L1 norm and parallel computer processor
US5926642A (en) * 1995-10-06 1999-07-20 Advanced Micro Devices, Inc. RISC86 instruction set
US6112289A (en) * 1994-11-09 2000-08-29 Mitsubishi Denki Kabushiki Kaisha Data processor
US6195744B1 (en) * 1995-10-06 2001-02-27 Advanced Micro Devices, Inc. Unified multi-function operation scheduler for out-of-order execution in a superscaler processor
US20020103991A1 (en) * 2000-12-06 2002-08-01 Intel Corporation And Analog Devices, Inc. Multi-cycle instructions
US20030236967A1 (en) * 2002-06-25 2003-12-25 Samra Nicholas G. Intra-instruction fusion
US20040153494A1 (en) * 2002-12-12 2004-08-05 Adaptec, Inc. Method and apparatus for a pipeline architecture

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5193205A (en) * 1988-03-01 1993-03-09 Mitsubishi Denki Kabushiki Kaisha Pipeline processor, with return address stack storing only pre-return processed address for judging validity and correction of unprocessed address
US5925125A (en) * 1993-06-24 1999-07-20 International Business Machines Corporation Apparatus and method for pre-verifying a computer instruction set to prevent the initiation of the execution of undefined instructions
US6434584B1 (en) * 1998-06-04 2002-08-13 Texas Instruments Incorporated Flexible accumulator register file for use in high performance microprocessors
US6954849B2 (en) * 2002-02-21 2005-10-11 Intel Corporation Method and system to use and maintain a return buffer
CN1266595C (en) 2002-06-28 2006-07-26 联想(北京)有限公司 Semi-open automatic upgrading method for embedded type operation system
US20060282821A1 (en) 2005-06-10 2006-12-14 Renno Erik K Efficient subprogram return in microprocessors

Patent Citations (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5070451A (en) * 1984-11-21 1991-12-03 Harris Corporation Forth specific language microprocessor
US4814976A (en) * 1986-12-23 1989-03-21 Mips Computer Systems, Inc. RISC computer with unaligned reference handling and method for the same
US4814976C1 (en) * 1986-12-23 2002-06-04 Mips Tech Inc Risc computer with unaligned reference handling and method for the same
US4891754A (en) * 1987-07-02 1990-01-02 General Datacomm Inc. Microinstruction sequencer for instructing arithmetic, logical and data move operations in a conditional manner
US4926355A (en) * 1987-07-02 1990-05-15 General Datacomm, Inc. Digital signal processor architecture with an ALU and a serial processing section operating in parallel
US5644699A (en) * 1991-08-07 1997-07-01 Mitsubishi Denki Kabushiki Kaisha Memory apparatus and data processor using the same
US5991902A (en) * 1991-08-07 1999-11-23 Mitsubishi Denki Kabushiki Kaisha Memory apparatus and data processor using the same
US5954435A (en) * 1991-08-07 1999-09-21 Mitsubishi Denki Kabushiki Kaisha Memory apparatus and data processor using the same
US5386563A (en) * 1992-10-13 1995-01-31 Advanced Risc Machines Limited Register substitution during exception processing
US5515519A (en) * 1993-03-19 1996-05-07 Hitachi, Ltd. Data processor and method utilizing coded no-operation instructions
US5680599A (en) * 1993-09-15 1997-10-21 Jaggar; David Vivian Program counter save on reset system and method
US6178492B1 (en) * 1994-11-09 2001-01-23 Mitsubishi Denki Kabushiki Kaisha Data processor capable of executing two instructions having operand interference at high speed in parallel
US6112289A (en) * 1994-11-09 2000-08-29 Mitsubishi Denki Kabushiki Kaisha Data processor
US5701493A (en) * 1995-08-03 1997-12-23 Advanced Risc Machines Limited Exception handling method and apparatus in data processing systems
US6336178B1 (en) * 1995-10-06 2002-01-01 Advanced Micro Devices, Inc. RISC86 instruction set
US6195744B1 (en) * 1995-10-06 2001-02-27 Advanced Micro Devices, Inc. Unified multi-function operation scheduler for out-of-order execution in a superscaler processor
US5926642A (en) * 1995-10-06 1999-07-20 Advanced Micro Devices, Inc. RISC86 instruction set
US5778208A (en) * 1995-12-18 1998-07-07 International Business Machines Corporation Flexible pipeline for interlock removal
US5884089A (en) * 1997-10-14 1999-03-16 Motorola, Inc. Method for calculating an L1 norm and parallel computer processor
US20020103991A1 (en) * 2000-12-06 2002-08-01 Intel Corporation And Analog Devices, Inc. Multi-cycle instructions
US20030236967A1 (en) * 2002-06-25 2003-12-25 Samra Nicholas G. Intra-instruction fusion
US20040153494A1 (en) * 2002-12-12 2004-08-05 Adaptec, Inc. Method and apparatus for a pipeline architecture

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100250904A1 (en) * 2005-06-10 2010-09-30 Atmel Corporation Methods and processor-related media to perform rapid returns from subroutines in microprocessors and microcontrollers
US8555041B2 (en) 2005-06-10 2013-10-08 Atmel Corporation Method for performing a return operation in parallel with setting status flags based on a return value register test
US20100088739A1 (en) * 2008-10-06 2010-04-08 International Business Machines Corporation Hardware Based Mandatory Access Control

Also Published As

Publication number Publication date Type
WO2006135549A8 (en) 2008-01-10 application
EP1891519A2 (en) 2008-02-27 application
US20100250904A1 (en) 2010-09-30 application
EP1891519B1 (en) 2016-12-07 grant
WO2006135549A2 (en) 2006-12-21 application
CN101194228B (en) 2011-10-19 grant
KR20080014062A (en) 2008-02-13 application
JP2009508180A (en) 2009-02-26 application
WO2006135549A3 (en) 2007-08-16 application
US8555041B2 (en) 2013-10-08 grant
CN101194228A (en) 2008-06-04 application
EP1891519A4 (en) 2010-05-19 application

Similar Documents

Publication Publication Date Title
US5608886A (en) Block-based branch prediction using a target finder array storing target sub-addresses
US5604909A (en) Apparatus for processing instructions in a computing system
US5727194A (en) Repeat-bit based, compact system and method for implementing zero-overhead loops
US5600806A (en) Method and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction buffer
US6675376B2 (en) System and method for fusing instructions
US5136696A (en) High-performance pipelined central processor for predicting the occurrence of executing single-cycle instructions and multicycle instructions
US5826089A (en) Instruction translation unit configured to translate from a first instruction set to a second instruction set
US5287467A (en) Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
US5826074A (en) Extenstion of 32-bit architecture for 64-bit addressing with shared super-page register
US6968444B1 (en) Microprocessor employing a fixed position dispatch unit
US5619664A (en) Processor with architecture for improved pipelining of arithmetic instructions by forwarding redundant intermediate data forms
US5887160A (en) Method and apparatus for communicating integer and floating point data over a shared data path in a single instruction pipeline processor
US6839828B2 (en) SIMD datapath coupled to scalar/vector/address/conditional data register file with selective subpath scalar processing mode
US5461722A (en) Parallel processing apparatus suitable for executing in parallel a plurality of instructions including at least two branch instructions
US6279100B1 (en) Local stall control method and structure in a microprocessor
US6279105B1 (en) Pipelined two-cycle branch target address cache
US6862677B1 (en) System and method for eliminating write back to register using dead field indicator
US20050076193A1 (en) Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence
US7028165B2 (en) Processor stalling
US5740461A (en) Data processing with multiple instruction sets
US6282634B1 (en) Apparatus and method for processing data having a mixed vector/scalar register file
US6338136B1 (en) Pairing of load-ALU-store with conditional branch
US5023828A (en) Microinstruction addressing in high-speed CPU
US5321823A (en) Digital processor with bit mask for counting registers for fast register saves
US5940311A (en) Immediate floating-point operand reformatting in a microprocessor

Legal Events

Date Code Title Description
AS Assignment

Owner name: ATMEL CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:RENNO, ERIK K.;STROM, OYVIND;LUND, MORTEN W.;REEL/FRAME:016881/0668

Effective date: 20050629