US20060258123A1 - Wafer gettering using relaxed silicon germanium epitaxial proximity layers - Google Patents

Wafer gettering using relaxed silicon germanium epitaxial proximity layers Download PDF

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US20060258123A1
US20060258123A1 US11460398 US46039806A US2006258123A1 US 20060258123 A1 US20060258123 A1 US 20060258123A1 US 11460398 US11460398 US 11460398 US 46039806 A US46039806 A US 46039806A US 2006258123 A1 US2006258123 A1 US 2006258123A1
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Leonard Forbes
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Micron Technology Inc
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02441Group 14 semiconducting materials
    • H01L21/0245Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02658Pretreatments
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/933Germanium or silicon or Ge-Si on III-V

Abstract

One aspect of this disclosure relates to a method for creating proximity gettering sites in a semiconductor wafer. In various embodiments of this method, a relaxed silicon germanium region is formed to be proximate to a device region on the semiconductor wafer. The relaxed silicon germanium region generates defects to getter impurities from the device region. In various embodiments, an ultra high vacuum chemical vapor deposition (UHV CVD) process is performed to epitaxially form the relaxed silicon germanium gettering region. In various embodiments, forming the relaxed silicon germanium gettering region includes implanting germanium ions into a silicon substrate with a desired dose and energy to form a silicon region containing germanium ions and heat treating the substrate to regrow a crystalline silicon layer over a resulting silicon germanium layer using a solid phase epitaxial (SPE) process. Other aspects are provided herein.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation under 37 C.F.R. 1.53(b) of U.S. application Ser. No. 10/443,339 filed May 21, 2003, which application is incorporated herein by reference.
  • This application is related to the following commonly assigned U.S. patent applications which are herein incorporated by reference in their entirety: “Strained Si/SiGe Structures by Ion Implantation,” U.S. application Ser. No. 10/431,134 filed on May 7, 2003, now U.S. Pat. No. 6,987,037 (Attorney Docket 1303.094US1); and “Gettering of Silicon On Insulator Using Relaxed Silicon Germanium Epitaxial Proximity Layers,” U.S. application Ser. No. 10/443,337 filed on May 21, 2003 (Attorney Docket 1303.103US1).
  • TECHNICAL FIELD
  • This disclosure relates generally to semiconductors, and more particularly, to wafer gettering by relaxed silicon germanium layers in close proximity to device layers.
  • BACKGROUND
  • Unwanted crystalline defects and impurities can be introduced during crystal growth or subsequent wafer fabrication processes. These defects and impurities can degrade device characteristics and overall yield. Gettering has been described as a process for moving contaminants and/or defects in a semiconductor into its bulk and away from its top surface to create a denuded zone cleared from contaminants and/or defects. Preferably, devices are built in the denuded zone.
  • Historically, extrinsic backside gettering was used to getter silicon wafers. Various extrinsic backside gettering processes involve damaging the backside of the wafer mechanically or by implanting argon, germanium, hydrogen or other implants, or providing a gettering layer on the backside of the wafer using a phophorosilicate glass or oxide backside layer, a polysilicon backside layer, and a silicon germanium (SiGe) backside epitaxial layer. Subsequently, “intrinsic” gettering was developed, which employed oxygen precipitation and “bulk microdefects” precipitated into the bulk of the wafer after the surface was “denuded” of oxygen. The precipitation process, the gettering effects, and the electrical characterization of defects and gettering silicon wafers have been investigated. Recently, intrinsic gettering modifications have been developed, including neutron irradiation, high boron doping, nitrogen doping, and the use of magnetic fields during crystal growth.
  • These gettering processes depend on the diffusion of unwanted impurities over significant distances to the gettering sites. However, modem low temperature processes have small thermal budgets, and do not afford an opportunity for significant diffusion of dopants and/or unwanted impurities. Thus, it is desirable to reduce the distance between the gettering sites and the device area. It has been previously proposed to implant various impurities in proximity to the device areas, to co-implant oxygen and silicon to form a gettering layer in close proximity to the device area, to implant helium to form cavities close to the device areas which getter impurities, and to getter material in trench isolation areas in close proximity to the device areas.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 illustrates a semiconductor structure having an epitaxial silicon germanium (SiGe) proximity gettering region, according to various embodiments of the present invention.
  • FIG. 2 illustrates a semiconductor structure having an epitaxial silicon germanium (SiGe) proximity gettering region, according to various embodiments of the present invention.
  • FIGS. 3A-3C illustrate a method for forming an epitaxial silicon germanium (SiGe) proximity gettering layer by ion implantation, according to various embodiments of the present invention.
  • FIG. 4 illustrates a doping profile for forming an epitaxial silicon germanium (SiGe) proximity gettering layer of FIG. 3C in which a single germanium implant process provides the silicon germanium layer, according to various embodiments of the present invention.
  • FIG. 5 illustrates a doping profile for forming an epitaxial silicon germanium (SiGe) proximity gettering layer of FIG. 3C in which multiple germanium implants provide a graded germanium concentration, according to various embodiments of the present invention.
  • FIG. 6 illustrates a doping profile for forming an epitaxial silicon germanium (SiGe) proximity gettering layer of FIG. 3C in which multiple germanium implants provide a graded germanium concentration, a first silicon implant reduces germanium ion channeling, and a second silicon implant further amorphizes the silicon layer, according to various embodiments of the present subject mater.
  • FIGS. 7A-7B illustrate a transistor structure with a silicon layer on a relaxed (partially strained and fully strained) silicon germanium layer, including a silicon layer on a partially strained silicon germanium layer and a silicon layer on a relaxed silicon germanium layer having a graded germanium concentration, respectively, according to various embodiments of the present invention.
  • FIG. 8 illustrates a method for forming a semiconductor structure with a proximity gettering region according to various embodiments of the present invention.
  • FIG. 9 illustrates a method for forming a semiconductor structure with a proximity gettering region that is formed using an ultra high vacuum chemical vapor deposition (UHV CVD) process according to various embodiments of the present invention.
  • FIG. 10 illustrates a method for forming a semiconductor structure with a proximity gettering region that is formed using a process that includes implanting germanium ions into a silicon substrate and heat treating to perform a solid phase epitaxial (SPE) process according to various embodiments of the present invention.
  • FIG. 11 illustrates a method for forming a device with a relaxed epitaxial silicon germanium (SiGe) proximity gettering layer according to various embodiments of the present invention.
  • FIG. 12 illustrates a method for amorphizing the silicon layer and forming a silicon germanium layer beneath the silicon layer, according to various embodiments of the present invention.
  • FIG. 13 illustrates a method for forming a silicon region containing germanium ions beneath a silicon layer, and amorphizing the silicon layer over the silicon region containing germanium ions, according to various embodiments of the present invention.
  • FIG. 14 illustrates a method for forming a silicon region containing germanium ions beneath a silicon layer, and amorphizing the silicon layer over the silicon region containing germanium ions, according to various embodiments of the present invention.
  • FIG. 15 illustrates a method for forming a silicon region containing germanium ions beneath a silicon layer, and amorphizing the silicon layer over the silicon region containing germanium ions, according to various embodiments of the present invention.
  • FIG. 16 is a simplified block diagram of a high-level organization of various embodiments of a memory device according to various embodiments of the present invention.
  • FIG. 17 is a simplified block diagram of a high-level organization of various embodiments of an electronic system according to the present invention.
  • DETAILED DESCRIPTION
  • The following detailed description refers to the accompanying drawings which show, by way of illustration, specific aspects and embodiments in which the present invention may be practiced. The various embodiments are not necessarily mutually exclusive as aspects of one embodiment can be combined with aspects of another embodiment. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. In the following description, the terms wafer and substrate are interchangeably used to refer generally to any structure on which integrated circuits are formed, and also to such structures during various stages of integrated circuit fabrication. Both terms include doped and undoped semiconductors, epitaxial layers of a semiconductor on a supporting semiconductor or insulating material, combinations of such layers, as well as other such structures that are known in the art. The terms “horizontal” and “vertical”, as well as prepositions such as “on”, “over” and “under” are used in relation to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
  • This application discloses the use of relaxed silicon germanium as gettering sites in close proximity to device areas. Various embodiments use ultra high vacuum chemical vapor deposition (UHV CVD) epitaxial techniques to place a relaxed silicon germanium layer immediately under the device areas. Various embodiments use ion implantation and solid phase epitaxial (SPE) regrowth to form a relaxed silicon germanium layer immediately below a silicon layer within a silicon substrate. The ion implantation and SPE regrowth method is less costly and complex than the UHV CVD process. The relaxed silicon germanium generates defects by relaxation of the silicon germanium lattice strain and/or the injection of silicon interstitials when the germanium is substitutionally incorporated into the lattice. These defects serve to getter unwanted impurities.
  • One aspect of this disclosure relates to a method for creating proximity gettering sites in a semiconductor wafer. In various embodiments of this method, a relaxed silicon germanium region is formed to be proximate to a device region on the semiconductor wafer. The relaxed silicon germanium region generates defects to getter impurities from the device region.
  • One aspect of this disclosure relates to a method for forming a semiconductor structure. A relaxed silicon germanium gettering region is formed to be proximate to a device region. Subsequent semiconductor fabrication processes are performed, including processes to fabricate a semiconductor device in the device region. Defects generated by the relaxed silicon germanium gettering region getters unwanted impurities from the device region during the subsequent semiconductor fabrication processes.
  • One aspect of this disclosure relates to a method for forming a transistor. A proximity gettering region is formed to be proximate to a crystalline silicon region in a wafer. The proximity gettering region includes relaxed silicon germanium. A gate dielectric is formed over the crystalline silicon region, and a gate is formed over the gate dielectric. A first diffusion region and a second diffusion region are formed in the strained crystalline silicon region. The first and second diffusion regions are separated by a channel region formed in the crystalline silicon region between the gate and the proximity gettering region. In various embodiments, the crystalline silicon region is sufficiently thin and is positioned on the silicon germanium such that a lattice mismatch strains the crystalline silicon region. In various embodiments, the crystalline silicon region is sufficiently thick such that the crystalline silicon region is not strained. Aspects of this disclosure incorporate such transistors into memory cells and/or control circuitry of memory devices.
  • A relaxed silicon germanium region or layer is formed to be proximate to a device area such that defects generated by the relaxed silicon germanium getter impurities from the device area even with the small thermal budgets associated with modem low temperature processes. In various embodiments, a UHV CVD process is used to epitaxially form a relaxed silicon germanium layer and a silicon layer on the relaxed silicon germanium layer such that the silicon germanium layer forms a proximity gettering site. In various embodiments, germanium ions are implanted into a silicon substrate, and an SPE process is performed to regrow a crystalline silicon layer over a resulting silicon germanium layer in the substrate. The defects generated by relaxation of the silicon germanium lattice strain and/or the injection of silicon interstitials when the germanium is substitutionally incorporated into the lattice serves to getter unwanted impurities.
  • FIG. 1 illustrates a semiconductor structure having an epitaxial silicon germanium (SiGe) proximity gettering region, according to various embodiments of the present invention. The illustrated structure 100 includes a semiconductor wafer, also referred to here as a substrate 101. A proximity gettering region 102 is located near to the device region 103 such that unwanted impurities can travel a short distance from the device region 103 to the gettering region 102, even with modem low temperature processes. In various embodiments, the device region includes crystalline silicon. Semiconductor devices, such as transistors, are fabricated in the crystalline silicon. Thus, it is desired to getter unwanted impurities from the device region. The illustrated proximate gettering region includes an epitaxial relaxed silicon germanium layer. The relaxed silicon germanium layer 102 functions as a proximity gettering region as it generates defects that getter impurities from the device region 103. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, how to form the illustrated device.
  • FIG. 2 illustrates a semiconductor structure having an epitaxial silicon germanium (SiGe) proximity gettering region, according to various embodiments of the present invention. The illustrated structure 200 includes a semiconductor wafer, also referred to here as a substrate 201. A number of proximity gettering regions 202 are located near to a number of device regions 203 such that unwanted impurities can travel a short distance from the device regions 203 to the gettering regions 202, even with modem low temperature processes. In various embodiments, the device region includes crystalline silicon, and semiconductor devices, such as transistors, are capable of being fabricated in the crystalline silicon. The relaxed silicon germanium regions 202 function as proximity gettering regions as it generates defects that getter impurities from the device regions 203. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, how to form the illustrated device.
  • FIGS. 3A-3C illustrate a method for forming an epitaxial silicon germanium (SiGe) proximity gettering layer by ion implantation, according to various embodiments of the present invention. In the illustrated embodiment, germanium ions 304 are implanted into a silicon wafer 301, such as a p-type wafer for an n-channel device, as represented in FIG. 3A. In various embodiments, the dose of the germanium ion implant is approximately 1020/cm2, and the energy of the germanium ion implant is greater than 200 KeV.
  • As represented in FIG. 3B, the relatively high dose and energy of the germanium ion implant in the silicon substrate 301 results in a region of silicon that contains germanium ions, represented as 302A, on the silicon substrate 301 and further results in an amorphized, or at least a partially amorphized, silicon layer 303A at the surface. In various embodiments, if the germanium ion implant did not completely amorphize the surface silicon layer, a silicon ion implant is used to further amorphize the silicon layer. In various embodiments, the dose of this silicon ion implant to amorphize the silicon layer 303A is approximately 1015/cm2 and the energy of this silicon ion implant is greater than approximately 170 KeV.
  • During an ion implantation process, the ions can channel along the crystal directions of the substrate, such that the ions do not encounter nuclei and are slowed down mainly by electronic stopping. Channeling can be difficult to control, and can cause the ions to penetrate several times deeper than intended. In various embodiments, to avoid channeling during the germanium ion implant, the silicon substrate is amorphized using a silicon ion implant to prepare the substrate for the germanium ion implant. In various embodiments, the dose of this silicon ion implant is approximately 1015/cm2 and the energy of this silicon ion implant is greater than 170 KeV. Preparing the substrate using the silicon ion implant to amorphize the substrate results in better depth control during the germanium ion implant process.
  • The structure 300 is heat treated, or annealed, such that the amorphized layers are regrown by a solid phase epitaxy (SPE) process. In various embodiments, the SPE process involves heating the structures at temperatures within a range of approximately 550° C. to 700° C. for a time within a range from approximately one hour to approximately two hours. The resulting structure 300 is illustrated in FIG. 3C. The silicon region that contains germanium ions forms a silicon germanium (Si1−XGeX) layer 302B and the amorphous silicon layer regrows into a crystalline silicon layer 303B over the silicon germanium layer 302B.
  • In various embodiments, the crystalline silicon layer is approximately 20 nm thick. However, the present invention is not limited to a particular thickness. The thickness of the crystalline silicon layer is controlled by the energy of the implant. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, how to control the germanium implant to achieve a desired thickness of the crystalline silicon layer 303B.
  • The devices are formed in the silicon layer on the silicon germanium gettering layer. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that thicker silicon wafers on the relaxed silicon germanium gettering layer are not strained, and thinner silicon wafers on the relaxed silicon germanium gettering layer are strained. For example, ultra thin silicon layers having a thickness of approximately 2000 Å or less are strained by the lattice mismatch with the relaxed silicon germanium gettering layer. In various embodiments, the silicon layer has a thickness of approximately 1000 Å or less. In various embodiments, the silicon layer has a thickness within a range of approximately 300 Å to approximately 1000 Å.
  • One area of interest for improving the speed and performance of semiconductor devices includes strained silicon technology, which has been shown to enhance carrier mobility in both n-channel and p-channel devices, and is being considered to improve the electron mobility and drift velocity in n-channel MOSFETs in CMOS technology.
  • Thin layers of strained silicon are being considered for CMOS n-channel devices. Thinner layers of silicon are more tolerant of strain. One technique for producing strained silicon involves epitaxially growing the silicon and silicon germanium layers using an ultra-high vacuum chemical vapor deposition (UHV CVD) process, a costly and complex process, to form silicon layers on relaxed silicon germanium layers. A large mismatch in the cell structure causes a pseudo-morphic layer of silicon on relaxed silicon germanium to be under biaxial tensile strain. The biaxial strain modifies the band structure and enhances carrier transport in the silicon layer. The strain on the silicon layer depends of the lattice constant difference between silicon and silicon germanium. The lattice constant of silicon germanium is between the lattice constant of silicon (5.43095 Å) and the lattice constant of germanium (5.64613 Å), and depends on the percentage of germanium in the silicon germanium layer.
  • Upon reading and comprehending this disclosure, one of ordinary skill in the art will appreciate the benefits of strained silicon. The strained silicon layer improves the electron mobility in the n-channel transistors in CMOS technology. A pseudo-morphic layer of silicon on relaxed silicon germanium is under biaxial tensile strain, which modifies the band structure and enhances carrier transport. In an electron inversion layer, the subband splitting is large in strained silicon because of the strain-induced band splitting in addition to that provided by quantum confinement. The ground level splitting in a MOS inversion layer at 1 MV/cm transverse field is about 120 and 250 meV for unstrained and strained silicon, respectively. The increase in energy splitting reduces inter-valley scattering and enhances NMOSFET mobility, as demonstrated at low (<0.6 MV/cm) and higher (approximately 1 MV/cm) vertical fields. The scaled gm is also improved due to the reduced density of states and enhanced non-equilibrium transport. The germanium content can be graded in steps to form a fully relaxed silicon germanium buffer layer before a thin strained silicon channel layer is grown. X-ray diffraction analysis is used to quantify the germanium content and strain relaxation in the silicon germanium layer. The strain state of the silicon channel layer can be confirmed by Raman spectroscopy.
  • The lattice mismatch of the silicon surface layer with the underlying silicon germanium layer 302B causes the silicon layer 303B to be strained. In various embodiments, N-channel CMOS devices are fabricated in this strained silicon layer 303B using conventional techniques, which are not described here for the sake of brevity.
  • One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that the concentration (X) of germanium in the silicon is controlled by the dose and energy of the germanium ion implant process. Additionally, one of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that the concentration (X) of germanium in the silicon can be graded by controlling the dose and energy of two or more germanium ion implant process. A benefit of grading germanium concentration involves forming a silicon germanium layer on a silicon substrate to have a relaxed silicon germanium surface upon which the crystalline silicon layer is regrown.
  • FIG. 4 illustrates a doping profile for forming an epitaxial silicon germanium (SiGe) proximity gettering layer of FIG. 3C in which a single germanium implant process provides the silicon germanium layer, according to various embodiments of the present invention. The left side of the figure illustrates a silicon substrate 401, and the right side of the figure represents a germanium ion doping profile 405. The profile 405 illustrates a single germanium ion implantation process step 406, in which germanium ions are implanted at a desired dose and energy to form the silicon region containing germanium ions, represented at 302A in FIG. 3B.
  • FIG. 5 illustrates a doping profile for forming an epitaxial silicon germanium (SiGe) proximity gettering layer of FIG. 3C in which multiple germanium implants provide a graded germanium concentration, according to various embodiments of the present invention. The left side of the figure illustrates a silicon substrate 501, and the right side of the figure represents a germanium ion doping profile 505. The profile 505 illustrates a first germanium ion implantation process step 507 in which germanium ions are implanted at a first desired dose and energy and a second germanium ion implantation step 508 in which germanium ions are implanted at a second desired dose and energy. These germanium ion implant steps form the silicon region containing germanium ions, represented at 302A in FIG. 3B. The concentration of the germanium in the silicon is graded. One of ordinary skill in the art will appreciate, upon reading and comprehending this disclosure, that additional germanium ion implant steps can be performed to control the germanium concentration, and that a relaxed silicon germanium layer can be formed by appropriately grading the germanium ion content such that less germanium ions are implanted near the silicon substrate, and more and more germanium ions are implanted closer to the silicon layer. One of ordinary skill in the art will appreciate, upon reading and comprehending this disclosure, that without grading the germanium concentration, the resulting silicon germanium layer has a slight strain attributable to the lattice mismatch of the silicon germanium layer and the silicon substrate beneath the silicon germanium layer. Various embodiments include silicon germanium layer that have a relaxed surface and that have a slightly strained surface.
  • FIG. 6 illustrates a doping profile for forming an epitaxial silicon germanium (SiGe) proximity gettering layer of FIG. 3C in which multiple germanium implants provide a graded germanium concentration, a first silicon implant reduces germanium ion channeling, and a second silicon implant further amorphizes the silicon layer, according to various embodiments of the present subject mater. The left side of the figure illustrates a silicon substrate 601 and the right side of the figure illustrates a doping profile 605. The first silicon implant 610 prepares the silicon substrate 601 for the germanium ion implantion by amorphizing the substrate to a desired depth. Thus, undesirable channeling is reduced, and the depth of the germanium ion implants 607 and 608 can be more accurately controlled. As discussed above with respect to FIG. 5, the multiple germanium ion implant steps provide a graded germanium concentration, which results in a relaxed, or at least partially relaxed, silicon germanium surface upon which a crystalline silicon layer is regrown from an amorphized silicon layer located over the silicon region that contains germanium ions. The implantation of the germanium ions at least partially amorphizes the silicon layer. The second silicon implant 611 further amorphizes the silicon layer in preparation for regrowing the crystalline silicon layer.
  • FIGS. 7A-7B illustrate a transistor structure with a silicon layer on a relaxed (partially strained and fully strained) silicon germanium layer, including a silicon layer on a partially strained silicon germanium layer and a silicon layer on a relaxed silicon germanium layer having a graded germanium concentration, respectively, according to various embodiments of the present invention. Both FIGS. 7A and 7B illustrate a transistor structure 712 such as may be formed on a p-type silicon substrate 701. One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that the transistor structure 712 may be formed on a n-type silicon substrate. A silicon germanium layer (Si1−XGeX) 702 is positioned over the silicon substrate 701, and a silicon layer 703 is positioned over the silicon germanium layer (Si1−XGeX) layer. The formation of the silicon germanium (Si1−XGeX) layer 702 and the silicon layer 703 has been described above. First and second diffusion regions 713 and 714 are formed by implanting n-type impurities. The illustrated structures show each diffusion region with an n-type area and an n+ type area. If the silicon substrate is an n-type substrate, the first and second diffusion regions are formed by implanting p-type impurities. The illustrated diffusion regions are formed in the silicon layer, and extend into the silicon germanium layer. The silicon layer 703 forms a channel region 715 which extends between the diffusion regions 713 and 714. A gate dielectric 716 (such as a gate oxide), is formed over the channel region 715, and a gate 717 is formed over the gate dielectric 716 to control electron current through the channel region 715 between the n-type diffusion regions 713 and 714.
  • The silicon germanium layer 702 in the structure illustrated in FIG. 7A is formed without grading the germanium ion content. The lattice mismatch of the silicon substrate 701 beneath the silicon germanium layer 702 causes the surface of the silicon germanium layer to be partially strained. The germanium ion content is graded to form the relaxed silicon germanium layer 702 in the structure illustrated in FIG. 7B. As represented by the arrow and the reference “X”, the germanium content increases further away from the silicon substrate. This grading of the germanium content reduces the effect that the lattice mismatch between the silicon substrate 701 and the silicon germanium layer 702. Thus, the surface of the silicon germanium layer is relaxed, or at least partially relaxed.
  • In various embodiments, the silicon layer 703 is sufficiently thick such that it is not strained by a lattice mismatch between the silicon germanium 702 and the silicon layer 703. In various embodiments, the silicon layer 703 is sufficiently thin to be strained by a lattice mismatch between the silicon germanium 702 and the silicon layer 703. In various embodiments, the thin silicon layer is ultra thin. In various embodiments, the thin silicon layer has a thickness of approximately 2000 Å or less. In various embodiments, the thin silicon layer has a thickness of approximately 1000 Å or less. In various embodiments, the thin silicon layer has a thickness in a range of approximately 300 Å to approximately 1000 Å.
  • FIG. 8 illustrates a method for forming a semiconductor structure with a proximity gettering region according to various embodiments of the present invention. In the illustrated embodiment, a relaxed silicon germanium gettering region is formed to be proximate to a device region at 818. At 819, subsequent semiconductor fabrication processes are performed. In various embodiments, these subsequent semiconductor processes include fabricating device(s) in the device region, as represented at 820. The relaxed silicon germanium generates defects that function to getter impurities from the device region. The proximity of the gettering region to the device region allow the gettering region to remove unwanted impurities from the device region even in modem semiconductor fabrication processes that have small thermal budgets.
  • FIG. 9 illustrates a method for forming a semiconductor structure with a proximity gettering region that is formed using an ultra high vacuum chemical vapor deposition (UHV CVD) process according to various embodiments of the present invention. At 918, a UHV CVD process is performed to epitaxially form a relaxed silicon germanium gettering region. This generally corresponds to 818 previously shown in FIG. 8. At 919, subsequent semiconductor fabrication processes are performed. This generally corresponds to 819 previously shown in FIG. 8.
  • FIG. 10 illustrates a method for forming a semiconductor structure with a proximity gettering region that is formed using a process that includes implanting germanium ions into a silicon substrate and heat treating to perform a solid phase epitaxial (SPE) process according to various embodiments of the present invention. At 1018, a relaxed silicon germanium gettering region is formed to be proximate to a device region. In the illustrated embodiment, forming the gettering region includes implanting germanium ions into a silicon substrate at 1021, and heat treating the substrate to perform a solid phase epitaxial (SPE) process at 1022. This was previously illustrated and described in FIGS. 3A-3C, and as such will not be described here for the sake of brevity. At 1019, subsequent semiconductor fabrication processes are performed. This generally corresponds to 819 previously shown in FIG. 8.
  • FIG. 11 illustrates a method for forming a device with a relaxed epitaxial silicon germanium (SiGe) proximity gettering layer according to various embodiments of the present invention. At 1118, a relaxed silicon germanium gettering region is formed to be proximate to a device region. In the illustrated embodiment, a silicon region containing germanium ions is formed beneath a silicon layer, and the silicon layer over the silicon region containing germanium ions is amorphized, as represented at 1123. In various embodiments, as represented at 1124, germanium ions are implanted into a p-type silicon substrate with a desired dose and energy to form the silicon region containing germanium ions. Various embodiments implant germanium ions into an n-type silicon substrate. The implantation of the germanium ions also amorphizes, or at least partially amorphizes, the silicon layer over the silicon region containing germanium ions. This silicon layer serves as a device region. Thus, it is desired to remove unwanted impurities from the silicon layer. At 1125, a solid phase epitaxy (SPE) growth process is performed to form a crystalline silicon layer over a silicon germanium region. Defects generated by the relaxed silicon germanium proximity layer getter impurities from the crystalline silicon layer. In various embodiments, the crystalline silicon layer is sufficiently thin such that the lattice mismatch between the crystalline silicon layer and the silicon germanium causes the crystalline silicon layer to be strained. At 1126, a device is formed using the silicon layer. In various embodiments, the silicon layer is strained such that the device incorporates strained silicon that enhances mobility.
  • FIG. 12 illustrates a method for amorphizing the silicon layer and forming a silicon germanium layer beneath the silicon layer, according to various embodiments of the present invention. The illustrated method is represented generally at 1223, which generally corresponds to 1123 in FIG. 11. At 1227, a first germanium ion implant is performed with a first desired dose and energy. At 1228, a second germanium ion implant is performed with a second desired dose and energy. Additional germanium implants can be performed according to various embodiments. Thus, the figure illustrates, at 1229, an Nth germanium ion implant performed with an Nth desired does and energy. The illustrated method is useful to create a silicon region with a graded concentration of germanium ions, such that upon annealing, a resulting silicon germanium layer has a desired graded germanium concentration.
  • FIG. 13 illustrates a method for forming a silicon region containing germanium ions beneath a silicon layer, and amorphizing the silicon layer over the silicon region containing germanium ions, according to various embodiments of the present invention. The illustrated method is represented generally at 1323, which generally corresponds to 1123 in FIG. 11. At 1330, a germanium ion implant is performed with a desired dose and energy to form a silicon region containing germanium ions within a silicon substrate. This germanium ion implant partially amorphizes the silicon layer positioned over the silicon region containing germanium ions. At 1331, a silicon ion implant is performed with a desired dose and energy to further amorphize the silicon layer in preparation for the SPE growth process, illustrated at 1125 in FIG. 11.
  • FIG. 14 illustrates a method for forming a silicon region containing germanium ions beneath a silicon layer, and amorphizing the silicon layer over the silicon region containing germanium ions, according to various embodiments of the present invention. The illustrated method is represented generally at 1423, which generally corresponds to 1123 in FIG. 11. At 1432, a silicon ion implant is performed with a desired dose and energy to prepare the silicon substrate for germanium ion implantation. The silicon ion implant amorphizes the silicon substrate to a desired depth to reduce channeling of the germanium ions. At 1430, a germanium ion implant is performed with a desired dose and energy to form a silicon region containing germanium ions within the amorphized silicon substrate. Reducing the unpredictable channeling by amorphizing the substrate permits better control of the depth of the germanium ion implant.
  • FIG. 15 illustrates a method for forming a silicon region containing germanium ions beneath a silicon layer, and amorphizing the silicon layer over the silicon region containing germanium ions, according to various embodiments of the present invention. The illustrated method is represented generally at 1523, which generally corresponds to 1123 in FIG. 11. At 1532, a first silicon ion implant is performed with a desired dose and energy to prepare the silicon substrate for germanium ion implantation. The silicon ion implant amorphizes the silicon substrate to a desired depth to reduce channeling of the germanium ions. At 1533, a number of germanium ion implant steps are performed to create a silicon region with a graded concentration of germanium ions in the amorphized silicon substrate, such that upon annealing, a resulting silicon germanium layer has a desired graded germanium concentration. The first silicon implant reduces the unpredictable channeling and permits better control of the depth of the germanium ion implants These germanium ion implant steps at least partially amorphize the silicon layer positioned over the silicon region containing germanium ions. At 1531, a second silicon ion implant is performed with a desired dose and energy to further amorphize the silicon layer in preparation for the SPE growth process, illustrated at 1125 in FIG. 11.
  • FIG. 16 is a simplified block diagram of a high-level organization of various embodiments of a memory device according to various embodiments of the present invention. The illustrated memory device 1668 includes a memory array 1670 and read/write control circuitry 1672 to perform operations on the memory array via communication line(s) 1674. The illustrated memory device 1668 may be a memory card or a memory module such as a single inline memory module (SIMM) and dual inline memory module (DIMM). One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that semiconductor components in the memory array 1670 and/or the control circuitry 1672 are able to be fabricated using the relaxed silicon germanium proximity gettering regions, as described above. The structure and fabrication methods for these strained body layers have been described above.
  • The memory array 1670 includes a number of memory cells 1678. The memory cells in the array are arranged in rows and columns. In various embodiments, word lines 1680 connect the memory cells in the rows, and bit lines 1682 connect the memory cells in the columns. The read/write control circuitry 1672 includes word line select circuitry 1674, which functions to select a desired row. The read/write control circuitry 1672 further includes bit line select circuitry 1676, which functions to select a desired column.
  • FIG. 17 is a simplified block diagram of a high-level organization of various embodiments of an electronic system according to the present invention. In various embodiments, the system 1784 is a computer system, a process control system or other system that employs a processor and associated memory. The electronic system 1784 has functional elements, including a processor or arithmetic/logic unit (ALU) 1785, a control unit 1786, a memory device unit 1787 (such as illustrated in FIG. 14) and an input/output (I/O) device 1788. Generally such an electronic system 1784 will have a native set of instructions that specify operations to be performed on data by the processor 1785 and other interactions between the processor 1785, the memory device unit 1787 and the I/O devices 1788. The control unit 1786 coordinates all operations of the processor 1785, the memory device 1787 and the I/O devices 1788 by continuously cycling through a set of operations that cause instructions to be fetched from the memory device 1787 and executed. According to various embodiments, the memory device 1787 includes, but is not limited to, random access memory (RAM) devices, read-only memory (ROM) devices, and peripheral devices such as a floppy disk drive and a compact disk CD-ROM drive. As one of ordinary skill in the art will understand, upon reading and comprehending this disclosure, any of the illustrated electrical components are capable of being fabricated to include the silicon germanium proximity gettering region in accordance with various embodiments of the present invention.
  • The illustration of the system 1784 is intended to provide a general understanding of one application for the structure and circuitry, and is not intended to serve as a complete description of all the elements and features of an electronic system using proximity gettering regions according to the various embodiments of the present invention. As one of ordinary skill in the art will understand, such an electronic system can be fabricated in single-package processing units, or even on a single semiconductor chip, in order to reduce the communication time between the processor and the memory device.
  • Applications containing a gettering region as described in this disclosure include electronic systems for use in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. Such circuitry can further be a subcomponent of a variety of electronic systems.
  • CONCLUSION
  • Various embodiments disclosed herein provide methods to getter silicon wafers using a relaxed silicon germanium epitaxial layer immediately under the device areas. In various embodiments, the relaxed silicon germanium epitaxial layer are formed by implantation and solid phase epitaxial regrowth. In various embodiments, the relaxed silicon germanium layers are formed by UHV CVD epitaxial techniques. The relaxation of the silicon germanium lattice strain and/or the injection of silicon interstitials when the germanium is substitutionally incorporated into the lattice to generate defects. These defects serve to getter unwanted impurities from the device areas.
  • This disclosure includes several processes, circuit diagrams, and structures. The present invention is not limited to a particular process order or logical arrangement. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover adaptations or variations. It is to be understood that the above description is intended to be illustrative, and not restrictive. Combinations of the above embodiments, and other embodiments, will be apparent to those of skill in the art upon reviewing the above description. The scope of the present invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims (21)

  1. 1. A method, comprising:
    defining a device region in a silicon wafer;
    generating desired defects in the silicon wafer and proximate to the device region to provide a gettering site proximate to the device region, including forming a relaxed silicon germanium region in the silicon wafer and proximate to the device region; and
    forming a device in the device region, and gettering the device region to diffuse unwanted impurities from the device region to the gettering site when the device is formed.
  2. 2. The method of claim 1, wherein generating desired defects includes epitaxially forming the relaxed silicon germanium gettering region.
  3. 3. The method of claim 1, wherein generating desired defects includes implanting germanium ions into the silicon wafer and heat treating to form a crystalline silicon layer over a silicon germanium layer.
  4. 4. The method of claim 1, wherein generating desired defects includes bonding the silicon germanium region to the silicon wafer.
  5. 5. The method of claim 1, wherein forming the device includes forming the device in a strained crystalline silicon layer having a thickness within a range of approximately 300 Å to 1000 Å.
  6. 6. A method, comprising:
    defining a device region in a silicon wafer;
    generating desired defects, by relaxation of the silicon germanium lattice strain or injection of silicon interstitials, in the silicon wafer and proximate to the device region to provide a gettering site proximate to the device region, including forming a relaxed silicon germanium region in the silicon wafer and proximate to the device region; and
    forming a device in the device region, and gettering the device region to diffuse unwanted impurities from the device region to the gettering site when the device is formed.
  7. 7. The method of claim 6, wherein generating desired defects includes generating desired defects by relaxation of the silicon germanium lattice strain and injection of silicon interstitials when the device is formed.
  8. 8. The method of claim 6, wherein forming the device includes forming the device in a strained crystalline silicon layer having a thickness less than approximately 2000 Å.
  9. 9. The method of claim 6, wherein generating desired defects includes epitaxially forming the relaxed silicon germanium gettering region.
  10. 10. The method of claim 6, wherein generating desired defects includes implanting germanium ions into the silicon wafer using a first implant of a first desired dose and energy and a second implant of a second desired dose and energy, and heat treating to form a crystalline silicon layer over a silicon germanium layer.
  11. 11. The method of claim 6, wherein generating desired defects includes bonding the silicon germanium region to the silicon wafer using a bond cut process.
  12. 12. A method, comprising:
    defining a device region in a silicon wafer;
    generating desired defects in the silicon wafer and proximate to the device region to provide a gettering site proximate to the device region, including forming a relaxed silicon germanium region in the silicon wafer and proximate to the device region; and
    forming a device on the gettering site in the device region, and gettering the device region to diffuse unwanted impurities from the device region to the gettering site when the device is formed.
  13. 13. The method of claim 12, wherein forming the device includes forming the device in a strained crystalline silicon layer having a thickness less than approximately 2000 Å.
  14. 14. The method of claim 12, wherein generating desired defects includes epitaxially forming the relaxed silicon germanium gettering region using an ultra high vacuum chemical vapor deposition (UHV CVD) process).
  15. 15. The method of claim 12, wherein generating desired defects includes implanting germanium ions into the silicon wafer and heating treating with a temperature within a range from approximately 550° C. to approximately 700° C. to form a crystalline silicon layer over a silicon germanium layer.
  16. 16. The method of claim 12, wherein generating desired defects includes bonding the silicon germanium region to the silicon wafer using a bond cut process.
  17. 17. A method, comprising:
    defining a device region in a silicon wafer;
    generating desired defects in the silicon wafer and proximate to the device region to provide a gettering site proximate to the device region, including forming a relaxed silicon germanium region in the silicon wafer and proximate to the device region; and
    forming a device in a strained silicon layer in the device region, and gettering the device region to diffuse unwanted impurities from the device region to the gettering site when the device is formed.
  18. 18. The method of claim 17, wherein the strained silicon layer has a thickness less than approximately 1000 Å.
  19. 19. The method of claim 17, wherein generating desired defects includes epitaxially forming the relaxed silicon germanium gettering region.
  20. 20. The method of claim 17, wherein generating desired defects includes implanting germanium ions into the silicon wafer and heat treating to form a crystalline silicon layer over a silicon germanium layer.
  21. 21. The method of claim 17, wherein generating desired defects includes bonding the silicon germanium region to the silicon wafer.
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