US20060254716A1 - Processing system and method for chemically treating a tera layer - Google Patents

Processing system and method for chemically treating a tera layer Download PDF

Info

Publication number
US20060254716A1
US20060254716A1 US11486105 US48610506A US2006254716A1 US 20060254716 A1 US20060254716 A1 US 20060254716A1 US 11486105 US11486105 US 11486105 US 48610506 A US48610506 A US 48610506A US 2006254716 A1 US2006254716 A1 US 2006254716A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
approximately
substrate
system
layer
comprise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11486105
Inventor
Aelan Mosden
Asao Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02167Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
    • H01L21/0276Photolithographic processes using an anti-reflective coating
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/314Inorganic layers
    • H01L21/3148Silicon Carbide layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • H01L21/31633Deposition of carbon doped silicon oxide, e.g. SiOC

Abstract

A processing system and method for chemically treating a TERA layer on a substrate. The chemical treatment of the substrate chemically alters exposed surfaces on the substrate. In one embodiment, the system for processing a TERA layer includes a plasma-enhanced chemical vapor deposition (PECVD) system for depositing the TERA layer on the substrate, an etching system for creating features in the TERA layer, and a processing subsystem for reducing the size of the features in the TERA layer.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • [0001]
    This is a divisional of U.S. patent application Ser. No. 10/883,784, filed Jul. 6, 2004, for which the Issue Fee has been paid. This application is related to U.S. Pat. No. 7,029,536, which issued on Apr. 18, 2006, U.S. Pat. No. 7,079,760, which issued on Jul. 18, 2006, co-pending U.S. patent application Ser. No. 10/705,397, filed on Nov. 12, 2003, and co-pending U.S. patent application Ser. No. 10/644,958, filed on Aug. 21, 2003. The contents of all of these patents and applications are herein incorporated by reference in their entireties.
  • BACKGROUND OF THE INVENTION
  • [0002]
    1. Field of the Invention
  • [0003]
    The present invention relates to a system and method for treating a Tunable Etch Rate ARC (TERA) layer, and more particularly to a system and method for chemical treatment of a TERA layer.
  • [0004]
    2. Description of the Related Art
  • [0005]
    During semiconductor processing, a (dry) plasma etch process can be utilized to remove or etch material along fine lines or within vias or contacts patterned on a silicon substrate. The plasma etch process generally involves positioning a semiconductor substrate with an overlying patterned, protective layer, for example a photoresist layer, in a processing chamber. Once the substrate is positioned within the chamber, an ionizable, dissociative gas mixture is introduced within the chamber at a pre-specified flow rate, while a vacuum pump is throttled to achieve an ambient process pressure. Thereafter, a plasma is formed when a fraction of the gas species present are ionized by electrons heated via the transfer of radio frequency (RF) power either inductively or capacitively, or microwave power using, for example, electron cyclotron resonance (ECR). Moreover, the heated electrons serve to dissociate some species of the ambient gas species and create reactant specie(s) suitable for the exposed surface etch chemistry. Once the plasma is formed, selected surfaces of the substrate are etched by the plasma. The process is adjusted to achieve appropriate conditions, including an appropriate concentration of desirable reactant and ion populations to etch various features (e.g., trenches, vias, contacts, gates, etc.) in the selected regions of the substrate. Such substrate materials where etching is required include silicon dioxide (SiO2), low-k dielectric materials, poly-silicon, and silicon nitride. During material processing, etching such features generally comprises the transfer of a pattern formed within a mask layer to the underlying film within which the respective features are formed. The mask can, for example, comprise a light-sensitive material such as (negative or positive) photo-resist, multiple layers including such layers as photo-resist and an anti-reflective coating (ARC), or a hard mask formed from the transfer of a pattern in a first layer, such as photo-resist, to the underlying hard mask layer.
  • SUMMARY OF THE INVENTION
  • [0006]
    The principles of the present invention, as embodied and broadly described herein, provide a method of processing a Tunable Etch Rate ARC (TERA) layer on a substrate. The TERA layer processing method includes depositing the TERA layer on the substrate using a plasma enhanced chemical vapor deposition (PECVD) system, creating features in the TERA layer using an etching system, and reducing the size of the features in the TERA layer.
  • [0007]
    Additionally, a system for processing a TERA layer is presented. The system includes a plasma enhanced chemical vapor deposition (PECVD) system for depositing the TERA layer on the substrate, an etching system for creating features in the TERA layer, and a processing subsystem for reducing the size of the features in the TERA layer.
  • [0008]
    Numerous other aspects of the invention will be made apparent from the description that follows and from the drawings appended hereto, as would be appreciated by those skilled in the art.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0009]
    Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings, in which corresponding reference symbols indicate corresponding parts, and in which:
  • [0010]
    FIG. 1 illustrates a schematic representation of a processing system according to an embodiment of the invention;
  • [0011]
    FIG. 2 illustrates a simplified flow diagram of a method for operating a processing system in accordance with an embodiment of the invention;
  • [0012]
    FIGS. 3A-3F illustrate simplified schematic views of a method for processing a substrate in accordance with an embodiment of the invention;
  • [0013]
    FIGS. 4A-4G illustrate simplified schematic views of a method for processing a substrate in accordance with another embodiment of the invention;
  • [0014]
    FIG. 5 illustrates a simplified block diagram of a PECVD system in accordance with an embodiment of the invention;
  • [0015]
    FIG. 6 illustrates a simplified block diagram for a treatment system in accordance with an embodiment of the invention; and
  • [0016]
    FIG. 7 illustrates a simplified block diagram of a processing subsystem in accordance with an embodiment of the invention.
  • DETAILED DESCRIPTION
  • [0017]
    In material processing methodologies, pattern etching comprises the application of a thin layer of light-sensitive material, such as photoresist, to an upper surface of a substrate that is subsequently patterned in order to provide a mask for transferring this pattern to the underlying thin film during etching. The patterning of the light-sensitive material generally involves exposure by a radiation source through a reticle (and associated optics) of the light-sensitive material using, for example, a micro-lithography system, followed by the removal of the irradiated regions of the light-sensitive material (as in the case of positive photoresist), or non-irradiated regions (as in the case of negative resist) using a developing solvent.
  • [0018]
    Additionally, multi-layer and hard masks can be implemented for etching features in a thin film. For example, when etching features in a thin film using a hard mask, the mask pattern in the light-sensitive layer is transferred to the hard mask layer using a separate etch step preceding the main etch step for the thin film. The hard mask can, for example, comprise a TERA layer that can be selected from several materials for silicon processing including silicon dioxide (SiO2), silicon nitride (Si3N4), and carbon, for example.
  • [0019]
    In order to reduce the feature size formed in the thin film, the hard mask can be trimmed laterally using, for example, a two-step process involving a chemical treatment of the exposed surfaces of the hard mask layer in order to alter the surface chemistry of the hard mask layer, and a post treatment of the exposed surfaces of the hard mask layer in order to desorb the altered surface chemistry.
  • [0020]
    FIG. 1 illustrates a schematic representation of a processing system according to an embodiment of the invention. In the illustrated embodiment, a processing system 1 for processing a substrate using, for example, TERA layer trimming is shown. Processing system 1 can comprise a multi-element manufacturing system 10, a deposition system 20 coupled to the multi-element manufacturing system 10, a treatment system 30 coupled to the multi-element manufacturing system 10, and an etching system 70 coupled to the multi-element manufacturing system 10.
  • [0021]
    The treatment system 30 can comprise a transfer module 40, a thermal treatment module 50, and a chemical treatment module 60. Also, as illustrated in FIG. 1, the transfer module 40 can be coupled to the thermal treatment module 50 in order to transfer substrates into and out of the thermal treatment module 50 and the chemical treatment module 60, and exchange substrates with a multi-element manufacturing system 10.
  • [0022]
    As should be apparent to those skilled in the art, the multi-element manufacturing system 10 can comprise additional processing elements (not shown) including such devices as etch systems, deposition systems, coating systems, cleaning systems, polishing systems, patterning systems, metrology systems, alignment systems, lithography systems, and transfer systems. Also, the multi-element manufacturing system 10 can permit the transfer of substrates to and from the processing elements (20, 30, and 70) and the additional processing elements (not shown).
  • [0023]
    As should be appreciated by those skilled in the art, the exact type and arrangement of components for processing system 1 may vary without departing from the scope of the invention. As such, processing system 1 is not limited solely to components 20, 30, 40, 50, 60 and 70 as described or the layout depicted. The invention is intended to encompass a plethora of variations too numerous to list here.
  • [0024]
    In one embodiment, deposition system 20 can comprise a chemical vapor deposition (CVD) system, a plasma enhanced chemical vapor deposition (PECVD) system, a physical vapor deposition (PVD) system, an ionized physical vapor deposition (iPVD) system, or an atomic layer deposition (ALD) system, or a combination of two or more thereof. The process gas can comprise an oxygen-containing gas, a nitrogen containing gas, a fluorine-containing gas, or a chlorine-containing gas, or a combination of two or more thereof. Alternately, an inert gas can also be included.
  • [0025]
    For example, an oxygen-containing gas can comprise O2, CO, NO, N2O, or CO2, or a combination of two or more thereof. The nitrogen-containing gas can comprise NO, N2O, N2, or NF3, or a combination of two or more thereof. The fluorine-containing gas can comprise NF3, SF6, CHF3, or C4F8, or a combination of two or more thereof. It will be appreciated that similar combinations to the fluorine-containing gas can be used for the chlorine-containing gas. Moreover, hybrids of gas containing both fluorine and chlorine may be employed.
  • [0026]
    The flow rate for an oxygen-containing gas can vary from approximately 0 sccm to approximately 500 sccm and alternately from approximately 0 sccm to approximately 300 sccm. The flow rate for an nitrogen-containing gas can vary from approximately 0 sccm to approximately 200 sccm and alternately from approximately 0 sccm to approximately 100 sccm. The flow rate for a fluorine-containing gas can vary from approximately 0 sccm to approximately 200 sccm and alternately from approximately 0 sccm to approximately 100 sccm. The flow rate for a chlorine-containing gas can vary from approximately 0 sccm to approximately 200 sccm and alternately from approximately 0 sccm to approximately 100 sccm.
  • [0027]
    In order to isolate the processes occurring in the deposition system 20, an isolation assembly 25 can be utilized to couple the deposition system 20 to the multi-element manufacturing system 10. The isolation assembly 25 can comprise a thermal insulation assembly to provide thermal isolation and/or a gate valve assembly to provide vacuum isolation. In alternate embodiments, the processing element 20 can comprise multiple modules.
  • [0028]
    As indicated above, in one embodiment, the treatment system 30 can comprise the transfer module 40, the thermal treatment module 50, which may be a physical heat treatment (PHT) module, and the chemical treatment module 60, which may be a chemical oxide removal (COR) module. In order to isolate the processes occurring in the different modules, isolation assemblies 35, 45, 55 can be utilized to couple the different modules. The isolation assembly 35 can be used to couple the transfer module 40 to the multi-element manufacturing system 10; the isolation assembly 45 can be used to couple the transfer module 40 to the PHT module 50; and the isolation assembly 55 can be used to couple the PHT module 50 to the COR module 60. The isolation assemblies 35, 45, 55 can comprise a thermal insulation assembly to provide thermal isolation and/or a gate valve assembly to provide vacuum isolation. In alternate embodiments, a different number of isolation assemblies 35, 45, 55 can be used.
  • [0029]
    In general, the transfer module 40 and/or the PHT module 50 of the processing system 1 depicted in FIG. 1 can comprise at least two transfer openings to permit the passage of the substrate therethrough. For example, as depicted in FIG. 1, the PHT module 50 comprises two transfer openings. The first transfer opening permits the passage of the substrate between the PHT module 50 and the transfer system 40, and the second transfer opening permits the passage of the substrate between the PHT module 50 and the COR module 60. Alternately, each treatment system element can comprise at least one transfer opening to permit the passage of the substrate therethrough.
  • [0030]
    In one embodiment, the transfer system 40, the PHT module 50, and the COR module 60 can be configured as in-line elements. Alternately, the transfer system 40, the PHT module 50, and the COR module 60 can be configured in any number of arrangements. For example, a stacked arrangement or a side-by-side arrangement can be used.
  • [0031]
    In one embodiment, the etching system 70 can comprise a dry etching system and/or a wet etching system. For example, the etching system 70 can comprise a plasma etching system. In order to isolate the processes occurring in the etching system 70, an isolation assembly 65 can be utilized to couple the etching system 70 to the multi-element manufacturing system 10. The isolation assembly 65 can comprise a thermal insulation assembly to provide thermal isolation and/or a gate valve assembly to provide vacuum isolation. In alternate embodiments, the etching system 70 can comprise multiple modules.
  • [0032]
    In the embodiment shown in FIG. 1, a controller 90 can be coupled to the multi-element manufacturing system 10, the deposition system 20, the transfer module 40, the PHT module 50, the COR module 60, and the etching system 70. For example, the controller 90 can be used to control the multi-element manufacturing system 10, the deposition system 20, the transfer module 40, the PHT module 50, the COR module 60, and the etching system 70. The controller 90 can also be connected to various components in any of a number of different ways without departing from the scope of the invention.
  • [0033]
    Additionally, the multi-element manufacturing system 10 can exchange substrates with one or more substrate cassettes (not shown). Additionally, for example, an isolation assembly can serve as part of a processing element.
  • [0034]
    FIG. 2 illustrates a simplified flow diagram of a method for operating a processing system in accordance with an embodiment of the invention. In the illustrated embodiment, a procedure is shown for reducing the size of features on a TERA layer.
  • [0035]
    Procedure 200 begins at task 210. In task 220, a TERA layer is deposited on a substrate. TERA layers can be deposited on top of many different layers of a substrate. For example, a TERA layer can be deposited on an oxide layer, a dielectric layer, or a metallic layer. The deposition of the TERA layer is discussed in greater detail herein.
  • [0036]
    Features are then created in a TERA layer, as indicated by task 230. In one embodiment, a photoresist layer can be deposited on the TERA layer and a pattern may be transferred into the photoresist layer using at least one photolithography step. The pattern can be developed to form features in the photoresist layer; and an etching process can be used to create features in the TERA layer. In an alternate embodiment, a hard mask layer can be deposited on the TERA layer.
  • [0037]
    While performing process 200, a stabilization step can be performed before and/or after an individual processing step. Alternately, the stabilization step may be avoided altogether.
  • [0038]
    Stabilization processes may encompass a variety of operational parameters, such as process time and chamber pressure. For example, the process time can vary from approximately 2 seconds to approximately 150 seconds and alternately from approximately 4 seconds to approximately 15 seconds. The chamber pressure can vary from approximately 2 mTorr to approximately 800 mTorr and alternately from approximately 10 mTorr to approximately 90 mTorr.
  • [0039]
    As discussed at length above, the process gas can comprise an oxygen-containing gas, a nitrogen containing gas, a fluorine-containing gas, or a chlorine-containing gas, or a combination of two or more thereof. Alternately, an inert gas can also be included. For example, an oxygen-containing gas can comprise O2, CO, NO, N2O, or CO2, or a combination of two or more thereof; the nitrogen-containing gas can comprise NO, N2O, N2, or NF3, or a combination of two or more thereof; and the fluorine-containing gas can comprise NF3, SF6, CHF3, or C4F8, or a combination of two or more thereof. The chlorine-containing gas can comprise similar combinations as the fluorine-containing gas.
  • [0040]
    The flow rate for an oxygen-containing gas can vary from approximately 0 sccm to approximately 500 sccm and alternately from approximately 0 sccm to approximately 300 sccm. The flow rate for an nitrogen-containing gas can vary from approximately 0 sccm to approximately 200 sccm and alternately from approximately 0 sccm to approximately 100 sccm. The flow rate for a fluorine-containing gas can vary from approximately 0 sccm to approximately 200 sccm and alternately from approximately 0 sccm to approximately 100 sccm. The flow rate for a chlorine-containing gas can vary from approximately 0 sccm to approximately 200 sccm and alternately from approximately 0 sccm to approximately 100 sccm.
  • [0041]
    In one embodiment, a photoresist trim process can be performed. Alternately, the photoresist trim process can be avoided altogether. Photoresist processes may also encompass a variety of operational parameters, such as process time and chamber pressure. For example, the process time can vary from approximately 0 seconds to approximately 180 seconds and alternately from approximately 10 seconds to approximately 40 seconds. The chamber pressure can vary from approximately 10 mTorr to approximately 120 mTorr and alternately from approximately 10 mTorr to approximately 90 mTorr. Also, as discussed above, the process gas can comprise an oxygen-containing gas, a nitrogen-containing gas and/or an inert gas. And, the flow rates for an oxygen-containing gas can vary from approximately 0 sccm to approximately 500 sccm and alternately from approximately 0 sccm to approximately 300 sccm, while the flow rates for a nitrogen-containing gas can vary from approximately 0 sccm to approximately 1000 sccm and alternately from approximately 0 sccm to approximately 200 sccm.
  • [0042]
    RF power can be supplied to an upper electrode and the upper RF power can vary from approximately 0 watts to approximately 1500 watts and alternately from approximately 100 watts to approximately 300 watts. In addition, RF power can be supplied to a lower electrode and the lower RF power can vary from approximately 0 watts to approximately 500 watts and alternately from approximately 40 watts to approximately 150 watts.
  • [0043]
    In one embodiment, a TERA cap etch process can be performed. Alternately, the TERA cap etch process may be avoided altogether. The TERA cap etch process may also encompass a variety of operational parameters, such as process time and chamber pressure. For example, the process time can vary from approximately 0 seconds to approximately 50 seconds and alternately from approximately 0 seconds to approximately 18 seconds. The chamber pressure can vary from approximately 10 mTorr to approximately 120 mTorr and alternately from approximately 10 mTorr to approximately 90 mTorr.
  • [0044]
    Also, as discussed above, the process gas can comprise an oxygen-containing gas, a nitrogen-containing gas, a fluorine-containing gas, or a chlorine-containing gas, an inert gas, or a combination of two or more thereof. And the flow rate for an oxygen-containing gas can vary from approximately 0 sccm to approximately 500 sccm and alternately from approximately 0 sccm to approximately 300 sccm. The flow rate for a nitrogen-containing gas can vary from approximately 0 sccm to approximately 200 sccm and alternately from approximately 0 sccm to approximately 100 sccm. The flow rate for a fluorine-containing gas can vary from approximately 0 sccm to approximately 200 sccm and alternately from approximately 0 sccm to approximately 100 sccm. The flow rate for a chlorine-containing gas can vary from approximately 0 sccm to approximately 200 sccm and alternately from approximately 0 sccm to approximately 100 sccm.
  • [0045]
    In task 240, the size of the features in the TERA layer can be reduced. In one embodiment, the exposed surfaces of the features in the TERA layer can be oxidized, and a removal process can be performed to remove at least a part of the oxidized portion of the TERA features. A trimming amount can be established and the oxidation process can be controlled so that the correct trimming amount is achieved. During a removal process, a chemical oxide removal (COR) process can be performed. In an alternate embodiment, the oxidation process and the COR process can be performed a number of times to reduce the size of the features in the TERA layer to predetermined dimensions.
  • [0046]
    During an exemplary TERA oxidation process, the process time can vary from approximately 0 seconds to approximately 180 seconds and alternately from approximately 0 seconds to approximately 18 seconds. The chamber pressure can vary from approximately 10 mtorr to approximately 300 mtorr and alternately from approximately 150 mtorr to approximately 250 mtorr. The process gas can comprise an oxygen-containing gas. Alternately, an inert gas can also be included. The flow rate for an oxygen-containing gas can vary from approximately 0.0 sccm to approximately 500 sccm and alternately from approximately 150 sccm to approximately 300 sccm. RF power can be supplied to an upper electrode and the upper RF power can vary from approximately 0.0 watts to approximately 1500 watts and alternately from approximately 200 watts to approximately 400 watts. In addition, RF power can be supplied to a lower electrode and the lower RF power can vary from approximately 0.0 watts to approximately 500 watts and alternately from approximately 30 watts to approximately 100 watts.
  • [0047]
    During the oxidation process, the TERA layer can be partially or fully oxidized. For example, TERA layers ranging from approximately 1 nm to approximately 5 nm can be fully oxidized in less than 12 seconds. The COR process does not remove non-oxidized TERA material. The COR process can be used to remove all or part of the oxidized TERA layer, as would be appreciated by those skilled in the art.
  • [0048]
    For example, the transfer module 40, the PHT module 50, and the COR module 60 can be used to perform a removal process. The removal process can use a COR recipe to perform the processing and the COR recipe can begin when a substrate is transferred to the COR module. The substrate can be received by lift pins that are housed within a substrate holder, and the substrate can be lowered to the substrate holder. Thereafter, the substrate can be secured to the substrate holder using a clamping system, such as an electrostatic clamping system, and a heat transfer gas can be supplied to the backside of the substrate.
  • [0049]
    Next, the COR recipe can be used to set one or more chemical processing parameters for the chemical treatment of the substrate, and these parameters can include a chemical treatment processing pressure, a chemical treatment wall temperature, a chemical treatment substrate holder temperature, a chemical treatment substrate temperature, a chemical treatment gas distribution system temperature, a chemical treatment process gas, or a chemical treatment process gas flow rate, or a combination of two or more thereof. Then, the substrate can be chemically treated for a first period of time. The first period of time can range from 30 to 360 seconds, for example.
  • [0050]
    Next, the substrate can be transferred from the chemical treatment chamber to the PHT module 50. During which time, the substrate clamp can be removed, and the flow of heat transfer gas to the backside of the substrate can be terminated. The substrate can be vertically lifted from the substrate holder to the transfer plane using the lift pin assembly housed within the substrate holder. The transfer system can receive the substrate from the lift pins and can position the substrate within the PHT module. Therein, a substrate lifter assembly can receive the substrate from the transfer system, and can lower the substrate to the substrate holder.
  • [0051]
    Then, the PHT recipe can be used to set one or more thermal processing parameters for thermal treatment of the substrate by the PHT module. In the PHT recipe, the substrate can be treated thermally for a second period of time. For example, the one or more thermal processing parameters can comprise a thermal treatment wall temperature, a thermal treatment upper assembly temperature, a thermal treatment substrate temperature, a thermal treatment substrate holder temperature, a thermal treatment substrate temperature, a thermal treatment processing pressure, a thermal treatment process gas, or a thermal treatment process gas flow rate, or a combination of two or more thereof. The second period of time can range from 30 to 360 seconds, for example.
  • [0052]
    In an exemplary process, the treatment system 30 can comprise a chemical oxide removal (COR) system for trimming an oxidized TERA film. The treatment system 30 can comprise the COR module 50 for chemically treating exposed surface layers, such as oxidized surface layers, on a substrate, whereby adsorption of the process chemistry on the exposed surfaces affects a chemical alteration of the surface layers. Additionally, the treatment system 30 can comprise the PHT module 60 for thermally treating the substrate, whereby the substrate temperature is elevated in order to desorb (or evaporate) the chemically altered exposed surfaces on the substrate.
  • [0053]
    In one embodiment, a COR module can use a process gas comprising HF and NH3, and the processing pressure can range from approximately 1 to approximately 100 mTorr and, for example, can range from approximately 2 to approximately 25 mTorr. The process gas flow rates can range from approximately 1 to approximately 200 sccm for each specie and, for example, can range from approximately 10 to approximately 100 sccm. In addition, a substantially uniform pressure field can be achieved. Additionally, the COR module chamber can be heated to a temperature ranging from 30° to 100° C. and, for example, the temperature can be approximately 40° C. Additionally, the gas distribution system can be heated to a temperature ranging from approximately 40° to approximately 100° C. and, for example, the temperature can be approximately 50° C. The substrate can be maintained at a temperature ranging from approximately 10° to approximately 50° C. and, for example, the substrate temperature can be approximately 20° C.
  • [0054]
    In addition, in the PHT module 50, the thermal treatment chamber can be heated to a temperature ranging from approximately 50° to approximately 100° C. and, for example, the temperature can be approximately 80° C. Additionally, the upper assembly can be heated to a temperature ranging from approximately 50° to approximately 100° C. and, for example, the temperature can be approximately 80° C. The substrate can be heated to a temperature in excess of approximately 100° C. Alternatively, the substrate can be heated in a range from approximately 100° to approximately 200° C., and, for example, the temperature can be approximately 135° C.
  • [0055]
    The COR and PHT processes described herein can produce an etch amount of an exposed oxidized surface in excess of approximately 10 nm per 60 seconds of chemical treatment for oxidized TERA. The treatments can also produce an etch variation across the substrate of less than approximately 2.5 percent.
  • [0056]
    FIGS. 3A-3F illustrate simplified schematic views of a method for processing a substrate in accordance with an embodiment of the invention. In FIG. 3A, a simplified schematic view of a partially processed semiconductor device is shown. In the illustrated embodiment, the semiconductor device has been processed using a photoresist development process and an etch process. A substrate layer 310 is shown, and the substrate layer can comprise silicon (Si), germanium (Ge), or gallium arsenide (GaAs), or a combination of two or more thereof. An additional layer 320 is shown on top of the substrate layer 310. The additional layer can comprise one or more layers and each layer can comprise an oxide, a metal, or a dielectric material, or a combination of two or more thereof.
  • [0057]
    A TERA layer 330 is shown on top of the additional layer, and the TERA layer can comprise TERA features 332. In addition, a photoresist layer 340 is shown on top of the TERA layer 330, and the photoresist layer 340 can comprise photoresist features 342. For example, the photoresist features 342 can be produced when the photoresist layer is developed, and the TERA features 332 can be produced when the photoresist features 342 are transferred into the TERA layer 330 using an etch process.
  • [0058]
    In FIG. 3B, another simplified schematic view of a partially processed semiconductor device is shown. In the illustrated embodiment, the semiconductor device has been processed using an etching process. Features 332 have been created in the TERA layer 330A by transferring the photoresist features 342 using an etch process. A substrate layer 310 is shown, and the substrate layer can comprise of silicon (Si), germanium (Ge), or gallium arsenide (GaAs), or a combination of two or more thereof. An additional layer 320 is shown on top of the substrate layer 310. The additional layer can comprise one or more layers and each layer can comprise an oxide, a metal, or a dielectric material, or a combination of two or more thereof.
  • [0059]
    A processed (etched) TERA layer 330A is shown on top of the additional layer, and the processed TERA layer 330A can comprise features 332. In addition, a photoresist layer 340 is shown on top of the processed TERA layer 330A, and the photoresist layer 340 can comprise photoresist features 342.
  • [0060]
    In FIG. 3C, another simplified schematic view of a partially processed semiconductor device is shown. In the illustrated embodiment, the semiconductor device has been processed using an oxidation process. The photoresist features have been removed by the oxidation (ashing) process, and oxidized areas 333 and 335 have been created in the TERA features 332 in the TERA layer 330B. The oxidized areas 333 on the sides of the TERA feature can have a different thickness than the oxidized areas 335 on the top of the TERA features. For example, the top portion of the TERA layer can comprise a cap portion that has a higher resistance to etching than the other portions of the TERA layer.
  • [0061]
    In FIG. 3C, a substrate layer 310 is shown, and the substrate layer can comprise silicon (Si), germanium (Ge), or gallium arsenide (GaAs), or a combination of two or more thereof. An additional layer 320 is shown on top of the substrate layer 310. The additional layer can comprise one or more layers and each layer can comprise an oxide, a metal, or a dielectric material, or a combination of two or more thereof. A processed TERA layer 330B is shown on top of the additional layer, and the processed TERA layer 330B can comprise features 332 having oxidized areas 333 and 335.
  • [0062]
    In FIG. 3D, another simplified schematic view of a partially processed semiconductor device is shown. In the illustrated embodiment, the semiconductor device has been processed using a COR process. Oxidized areas have been removed creating reduced TERA features 337 in the TERA layer 330C by removing the oxidized areas of the TERA features using a COR process. A substrate layer 310 is shown, and the substrate layer can comprise silicon (Si), germanium (Ge), or gallium arsenide (GaAs), or a combination of two or more thereof. An additional layer 320 is shown on top of the substrate layer 310. The additional layer can comprise one or more layers and each layer can comprise an oxide, a metal, or a dielectric material, or a combination of two or more thereof. A processed TERA layer 330C is shown on top of the additional layer, and the processed TERA layer 330C can comprise reduced size TERA features 337.
  • [0063]
    In FIG. 3E, another simplified schematic view of a partially processed semiconductor device is shown. In the illustrated embodiment, the semiconductor device has been processed using an etch process, and one or more of the layers in the additional layer 320 has been etched using the reduced size TERA features 337 as a mask. The reduced size TERA features 337 can be used as mask features and a dry etching process and/or a wet etching process can be performed. A substrate layer 310 is shown, and the substrate layer can comprise silicon (Si), germanium (Ge), or gallium arsenide (GaAs), or a combination of two or more thereof.
  • [0064]
    A processed (etched) additional layer 320A is shown on top of the substrate layer 310. The processed (etched) additional layer 320A can comprise vias 324 and additional layer features 322. The additional layer features 322 can comprise one or more layers and each layer can comprise an oxide, a metal, or a dielectric material, or a combination of two or more thereof. A processed (partially etched) TERA layer 330C is shown on top of the additional layer, and the processed (partially etched) TERA layer 330C can comprise reduced size TERA features 337. For example, the additional layer features can comprise a nitride layer and a doped poly layer.
  • [0065]
    In FIG. 3F, another simplified schematic view of a partially processed semiconductor device is shown. In the illustrated embodiment, the semiconductor device has been processed using a removal process, and the reduced size TERA features 337 have been removed. A substrate layer 310 is shown, and the substrate layer can comprise silicon (Si), germanium (Ge), or gallium arsenide (GaAs), or a combination of two or more thereof. A processed (etched) additional layer 320A is shown on top of the substrate layer 310. The processed (etched) additional layer 320A can comprise vias 324 and additional layer features 322. The additional layer features 322 can comprise one or more layers and each layer can comprise an oxide, a metal, or a dielectric material, or a combination of two or more thereof. In this manner, reduced size features can be created in the additional layer and smaller critical dimensions (gate widths) can be achieved. In one embodiment, further processing can be performed.
  • [0066]
    FIGS. 4A-4G illustrate simplified schematic views of a method for processing a substrate in accordance with another embodiment of the invention.
  • [0067]
    In FIG. 4A, a simplified schematic view of a partially processed semiconductor device is shown. In the illustrated embodiment, the semiconductor device has been processed using a hard mask development process. A substrate layer 410 is shown, and the substrate layer can comprise silicon (Si), germanium (Ge), or gallium arsenide (GaAs), or a combination of two or more thereof. An additional layer 420 is shown on top of the substrate layer 410. The additional layer can comprise one or more layers, and each layer can comprise an oxide, a metal, or a dielectric material, or a combination of two or more thereof. A TERA layer 430 is shown on top of the additional layer, and the TERA layer can be used as a hard mask. In addition, a hard mask layer 440 is shown on top of the TERA layer 430, and the hard mask layer 440 can comprise hard mask features 442. For example, the hard mask features 442 can be produced using a photoresist layer (not shown).
  • [0068]
    In FIG. 4B, another simplified schematic view of a partially processed semiconductor device is shown. In the illustrated embodiment, the semiconductor device has been processed using an etching process. Features 432 have been created in the TERA layer 430A by transferring the hard mask features 442 using an etch process. A substrate layer 410 is shown, and the substrate layer can comprise silicon (Si), germanium (Ge), or gallium arsenide (GaAs), or a combination of two or more thereof.
  • [0069]
    An additional layer 420 is shown on top of the substrate layer 410. The additional layer can comprise one or more layers, and each layer can comprise an oxide, a metal, or a dielectric material, or a combination of two or more thereof. In addition, a photoresist layer 440 is shown on top of the processed TERA layer 430A, and the photoresist layer 440 can comprise photoresist features 442.
  • [0070]
    In FIG. 4C, another simplified schematic view of a partially processed semiconductor device is shown. In the illustrated embodiment, the semiconductor device has been processed using an oxidation process. Oxidized areas 435 have been created in the TERA features 432 in the TERA layer 430B by oxidizing the exposed surfaces of the TERA features 432 using an oxidation process. A substrate layer 410 is shown, and the substrate layer can comprise silicon (Si), germanium (Ge), or gallium arsenide (GaAs), or a combination of two or more thereof.
  • [0071]
    An additional layer 420 is shown on top of the substrate layer 410. The additional layer can comprise one or more layers, and each layer can comprise an oxide, a metal, or a dielectric material, or a combination of two or more thereof. A processed TERA layer 430B is shown on top of the additional layer, and the processed TERA layer 430B can comprise features 432 having oxidized areas 435. In addition, a photoresist layer 440 is shown on top of the processed TERA layer 430B, and the photoresist layer 440 can comprise photoresist features 442.
  • [0072]
    In FIG. 4D, another simplified schematic view of a partially processed semiconductor device is shown. In the illustrated embodiment, the semiconductor device has been processed using a COR process. Oxidized areas can be removed using a COR process thereby creating reduced size TERA features 437 in the TERA layer 430C. Alternately, another substantially lateral etch process can be performed in which the oxidized areas 435 can be removed creating the reduced TERA features 437 in the TERA layer 430C. A substrate layer 410 is shown, and the substrate layer can comprise silicon (Si), germanium (Ge), or gallium arsenide (GaAs), or a combination of two or more thereof.
  • [0073]
    An additional layer 420 is shown on top of the substrate layer 410. The additional layer can comprise one or more layers, and each layer can comprise an oxide, a metal, or a dielectric material, or a combination of two or more thereof. A processed (laterally etched) TERA layer 430C is shown on top of the additional layer, and the processed (laterally etched) TERA layer 430C can comprise reduced size TERA features 437. In addition, hard mask features can be shown on top of the reduced size TERA features 437.
  • [0074]
    In FIG. 4E, another simplified schematic view of a partially processed semiconductor device is shown. In the illustrated embodiment, the semiconductor device has been processed using a removal process, and the hard mask features 442 have been removed. The hard mask features can be removed using an ashing process, a dry etching process, or a wet etching process, or a combination of two or more thereof. A substrate layer 410 is shown, and the substrate layer can comprise silicon (Si), germanium (Ge), or gallium arsenide (GaAs), or a combination of two or more thereof.
  • [0075]
    An additional layer 420 is shown on top of the substrate layer 410. The additional layer can comprise one or more layers, and each layer can comprise an oxide, a metal, or a dielectric material, or a combination of two or more thereof. A processed (laterally etched) TERA layer 430C is shown on top of the additional layer, and the processed (laterally etched) TERA layer 430C can comprise reduced size TERA features 437. In FIG. 4E, hard mask features have been removed from the top surfaces of the reduced size TERA features 437.
  • [0076]
    In FIG. 4F, another simplified schematic view of a partially processed semiconductor device is shown. In the illustrated embodiment, the semiconductor device has been processed using an etch process, and the additional layer 420 has been etched using the reduced size TERA features 437 as a mask. The reduced size TERA features 437 can be used as mask features and a dry etching process and/or a wet etching process can be performed. A substrate layer 410 is shown, and the substrate layer can comprise silicon (Si), germanium (Ge), or gallium arsenide (GaAs), or a combination of two or more thereof.
  • [0077]
    A processed (etched) additional layer 420A is shown on top of the substrate layer 410. The processed (etched) additional layer 420A can comprise vias 424 and additional layer features 422. The additional layer features 422 can comprise one or more layers, and each layer can comprise an oxide, a metal, or a dielectric material, or a combination of two or more thereof. A processed (laterally etched) TERA layer 430C is shown on top of the additional layer, and the processed (laterally etched) TERA layer 430C can comprise reduced size TERA features 437. For example, the additional layer features can comprise a nitride layer and a doped poly layer.
  • [0078]
    In FIG. 4G, another simplified schematic view of a partially processed semiconductor device is shown.
  • [0079]
    In the illustrated embodiment, the semiconductor device has been processed using a removal process, and the reduced size TERA features 437 have been removed. A substrate layer 410 is shown, and the substrate layer can comprise silicon (Si), germanium (Ge), or gallium arsenide (GaAs), or a combination of two or more thereof. A processed (etched) additional layer 420A is shown on top of the substrate layer 410. The processed (etched) additional layer 420A can comprise vias 424 and additional layer features 422. The additional layer features 422 can comprise one or more layers, and each layer can comprise an oxide, a metal, or a dielectric material, or a combination of two or more thereof. In this manner, reduced size features can be created in the additional layer and smaller critical dimensions (gate widths) can be achieved.
  • [0080]
    FIG. 5 illustrates a simplified block diagram of a PECVD system in accordance with an embodiment of the invention. In the illustrated embodiment, the PECVD system 500 comprises a processing chamber 510, an upper electrode 540 as part of a capacitively coupled plasma source, a shower plate assembly 520, a substrate holder 530 for supporting a substrate 535, a pressure control system 580, and a controller 590.
  • [0081]
    In one embodiment, the PECVD system 500 can comprise a remote plasma system 575 that can be coupled to the processing chamber 510 using a valve 578. In another embodiment, a remote plasma system and valve are not included.
  • [0082]
    In one embodiment, the PECVD system 500 can comprise the pressure control system 580 that can be coupled to the processing chamber 510. For example, the pressure control system 580 can comprise a throttle valve (not shown) and a turbomolecular pump (TMP) (not shown) and can provide a controlled pressure in processing chamber 510. In alternate embodiments, the pressure control system 580 can comprise a dry pump (not shown). For example, the chamber pressure can range from approximately 0.1 mTorr to approximately 100 mTorr. Alternatively, the chamber pressure can range from approximately 0.1 mTorr to approximately 20 mTorr.
  • [0083]
    The processing chamber 510 can facilitate the formation of plasma in the process space 502. The PECVD system 500 can be configured to process substrates of any size, such as 200 mm substrates, 300 mm substrates, or larger substrates. Alternately, the PECVD system 500 can operate by generating plasma in one or more processing chambers.
  • [0084]
    The PECVD system 500 comprises the shower plate assembly 520 coupled to the processing chamber 510. The shower plate assembly 520 is mounted opposite the substrate holder 530. The shower plate assembly 520 comprises a center region 522, an edge region 524, and a sub region 526. A shield ring 528 can be used to couple the shower plate assembly 520 to the processing chamber 510.
  • [0085]
    The center region 522 is coupled to a gas supply system 531 by a first process gas line 523. The edge region 524 is coupled to the gas supply system 531 by a second process gas line 525. The sub region 526 is coupled to the gas supply system 531 by a third process gas line 527.
  • [0086]
    The gas supply system 531 provides a first process gas to the center region 522, a second process gas to the edge region 524, and a third process gas to the sub region 526. The gas chemistries and flow rates can be individually controlled to these regions. Alternately, the center region 522 and the edge region 524 can be coupled together as a single primary region, and the gas supply system 531 can provide the first process gas and/or the second process gas to the primary region. In alternate embodiments, any of the regions can be coupled together and the gas supply system 531 can provide one or more process gasses, as appropriate.
  • [0087]
    The gas supply system 531 can comprise at least one vaporizer (not shown) for providing precursors. Alternately, a vaporizer is not required. In an alternate embodiment, a bubbling system can be used.
  • [0088]
    The PECVD system 500 comprises an upper electrode 540 that can be coupled to the shower plate assembly 520 and also to the processing chamber 510. The upper electrode 540 can comprise temperature control elements 542. The upper electrode 540 can be coupled to a first RF source 546 using a first match network 544. As would be appreciated by those skilled in the art, the first match network 544 need not be provided between the first RF source 546 and the upper electrode 540.
  • [0089]
    The first RF source 546 provides a TRF signal to the upper electrode 540, and the first RF source 546 can operate in a frequency range from approximately 0.1 MHz. to approximately 200 MHz. The TRF signal can be in the frequency range from approximately 1 MHz. to approximately 100 MHz. or alternatively in the frequency range from approximately 2 MHz. to approximately 60 MHz. The first RF source 546 can operate in a power range from approximately 0 watts to approximately 10000 watts, or alternatively the first RF source 546 can operate in a power range from approximately 0 watts to approximately 5000 watts.
  • [0090]
    The upper electrode 540 and the RF source 546 are parts of a capacitively-coupled plasma source. The capacitively-coupled plasma source may be replaced with or augmented by other types of plasma sources, such as an inductively coupled plasma (ICP) source, a transformer-coupled plasma (TCP) source, a microwave powered plasma source, an electron cyclotron resonance (ECR) plasma source, a Helicon wave plasma source, and a surface wave plasma source. As is well known in the art, the upper electrode 540 may be eliminated or reconfigured in the various suitable plasma sources.
  • [0091]
    The substrate 535 can be, for example, transferred into and out of the processing chamber 510 through a slot valve (not shown) and chamber feed-through (not shown) via a robotic substrate transfer system (not shown), and it can be received by the substrate holder 530 and mechanically translated by devices coupled thereto. Once the substrate 535 is received from the substrate transfer system, the substrate 535 can be raised and/or lowered using a translation device 550 that can be coupled to the substrate holder 530 by a coupling assembly 552.
  • [0092]
    The substrate 535 can be held or affixed to the substrate holder 530 via an electrostatic clamping system. For example, the electrostatic clamping system can comprise an electrode 516 and an ESC supply 556. Clamping voltages that can range from approximately −2000 V to approximately +2000 V, for example, can be provided to the clamping electrode 516. Alternatively, the clamping voltage can range from approximately −1000 V to approximately +1000 V. In alternate embodiments, the ESC system and the ESC supply 556 are not required.
  • [0093]
    The substrate holder 530 can comprise lift pins (not shown) for lowering and/or raising the substrate 535 to and/or from the surface of the substrate holder 530. In alternate embodiments, different lifting devices can be provided in the substrate holder 530, as would be appreciated by those skilled in the art. In alternate embodiments, gas can, for example, be delivered to the backside of the substrate 535 via a backside gas system to improve the gas-gap thermal conductance between the substrate 535 and the substrate holder 530.
  • [0094]
    A temperature control system can also be provided. Such a system can be utilized when temperature control of the substrate 535 is required at elevated or reduced temperatures. For example, a heating element 532, such as resistive heating elements, or thermoelectric heaters/coolers can be included, and the substrate holder 530 can further include a heat exchange system 534. The heating element 532 can be coupled to a heater supply 558. The heat exchange system 534 can include re-circulating coolant flow passages that receive heat from the substrate holder 530 and transfer the heat to a heat exchanger system (not shown), or when heating, transfers the heat from the heat exchanger system to the substrate holder 530.
  • [0095]
    Also, the electrode 516 can be coupled to a second RF source 560 using a second match network 562. Alternately, the second match network 562 is not required.
  • [0096]
    The second RF source 560 provides a bottom RF signal (BRF) to the lower electrode 516, and the second RF source 560 can operate in a frequency range from approximately 0.1 MHz. to approximately 200 MHz. The BRF signal can be in the frequency range from approximately 0.2 MHz. to approximately 30 MHz. or alternatively, in the frequency range from approximately 0.3 MHz. to approximately 15 MHz. The second RF source 560 can operate in a power range from approximately 0.0 watts to approximately 1000 watts, or alternatively, the second RF source 560 can operate in a power range from approximately 0.0 watts to approximately 500 watts. In various embodiments, the lower electrode 516 may not be used, or may be the sole source of plasma within the chamber 510, or may augment any additional plasma source.
  • [0097]
    The PECVD system 500 can further comprise the translation device 550 that can be coupled by a bellows 554 to the processing chamber 510. Also, coupling assembly 552 can couple the translation device 550 to the substrate holder 530. The bellows 554 are configured to seal the vertical translation device 550 from the atmosphere outside the processing chamber 510.
  • [0098]
    The translation device 550 allows a variable gap 504 to be established between the shower plate assembly 520 and the substrate 535. The gap 504 can range from approximately 10 mm to approximately 200 mm, and alternatively, the gap 504 can range from approximately 20 mm to approximately 80 mm. The gap 504 can remain fixed or the gap 504 can be changed during a deposition process.
  • [0099]
    Additionally, the substrate holder 530 can further comprise a focus ring 506 and a ceramic cover 508. Alternately, the focus ring 506 and/or the ceramic cover 508 need not be included, as would be appreciated by those skilled in the art.
  • [0100]
    At least one chamber wall 512 can comprise a coating 514 to protect the wall. For example, the coating 514 can comprise a ceramic material. In an alternate embodiment, the coating 514 is not required. Furthermore, a ceramic shield (not shown) can be used within the processing chamber 510.
  • [0101]
    In addition, the temperature control system can be used to control the chamber wall 512 temperature. For example, ports can be provided in the chamber wall 512 for controlling temperature. The chamber wall 512 temperature can be maintained relatively constant while a process is being performed in the chamber 510.
  • [0102]
    Also, the temperature control system can be used to control the temperature of the upper electrode 540. The temperature control elements 542 can be used to control the upper electrode 540 temperature. The upper electrode 540 temperature can be maintained relatively constant while a process is being performed in the chamber 510.
  • [0103]
    In addition, the PECVD system 500 can also comprise the remote plasma system 575 that can be used for chamber 510 cleaning.
  • [0104]
    Furthermore, the PECVD system 500 can also comprise a purging system (not shown) that can be used for controlling contamination and/or chamber 510 cleaning.
  • [0105]
    In an alternate embodiment, the processing chamber 510 can, for example, further comprise a monitoring port (not shown). The monitoring port can, for example, permit optical monitoring of the process space 502.
  • [0106]
    The PECVD system 500 also comprises the controller 590. The controller 590 can be coupled to the chamber 510, the shower plate assembly 520, the substrate holder 530, the gas supply system 531, the upper electrode 540, the first RF match 544, the first RF source 546, the translation device 550, the ESC supply 556, the heater supply 558, the second RF match 562, the second RF source 560, the purging system 595, the remote plasma device 575, and the pressure control system 580. The controller 590 can be configured to provide control data to these components and receive data such as process data from these components. For example, the controller 590 can comprise a microprocessor, a memory, and a digital I/O port capable of generating control voltages sufficient to communicate and activate inputs to the processing system 500 as well as monitor outputs from the PECVD system 500.
  • [0107]
    Moreover, the controller 590 can exchange information with system components. Also, a program stored in the memory can be utilized to control the aforementioned components of the PECVD system 500 according to a process recipe. In addition, controller 590 can be configured to analyze the process data, to compare the process data with target process data, and to use the comparison to change a process and/or control the deposition tool. Also, the controller 590 can be configured to analyze the process data, to compare the process data with historical process data, and to use the comparison to predict, prevent, and/or declare a fault.
  • [0108]
    During the deposition of a TERA layer, the substrate 535 can be placed on the translatable substrate holder 530. For example, the translatable substrate holder 530 can be used to establish the gap between the upper electrode 540 surface and the surface of the translatable substrate holder 530. The gap 504 can range from approximately 10 mm to approximately 200 mm, or alternatively, the gap 504 can range from approximately 20 mm to approximately 80 mm. In alternate embodiments, the gap 504 size can be changed.
  • [0109]
    During a TERA layer deposition process, a TRF signal can be provided to the upper electrode 540 using the first RF source 544. For example, the first RF source 544 can operate in a frequency range from approximately 0.1 MHz. to approximately 200 MHz. Alternatively, the first RF source 544 can operate in a frequency range from approximately 1 MHz. to approximately 100 MHz., or the first RF source 544 can operate in a frequency range from approximately 2 MHz. to approximately 60 MHz. The first RF source 544 can operate in a power range from approximately 10 watts to approximately 10000 watts, or alternatively, the first RF source 544 can operate in a power range from approximately 10 watts to approximately 5000 watts
  • [0110]
    Also, during a TERA layer deposition process, a BRF signal can be provided to the lower electrode 530 using the second RF source 560. For example, the second RF source 560 can operate in a frequency range from approximately 0.1 MHz. to approximately 200 MHz. Alternatively, the second RF source 560 can operate in a frequency range from approximately 0.2 MHz. to approximately 30 MHz. or the second RF source can operate in a frequency range from approximately 0.3 MHz. to approximately 15 MHz. The second RF source 560 can operate in a power range from approximately 0.0 watts to approximately 1000 watts, or alternatively, the second RF source 560 can operate in a power range from approximately 0.0 watts to approximately 500 watts. In an alternate embodiment, a BRF signal is not required.
  • [0111]
    In addition, a process gas can be provided to the processing chamber 510 using the shower plate assembly 520. For example, process gas can comprise a silicon-containing precursor, a carbon-containing precursor, or oxygen containing gas, or a combination of two or more thereof. An inert gas can also be included. For example, the flow rate for the silicon-containing precursor and the carbon-containing precursor can range from approximately 0 sccm to approximately 5000 sccm and the flow rate for the inert gas can range from approximately 0 sccm to approximately 10000 sccm. The silicon-containing precursor can comprise monosilane (SiH4), tetraethylorthosilicate (TEOS), monomethylsilane (1 MS), dimethylsilane (2MS), trimethylsilane (3MS), tetramethylsilane (4MS), octamethylcyclotetrasiloxane (OMCTS), dimethyldimethoxysilane (DMDMOS), or tetramethylcyclotetrasilane (TMCTS), or a combination of two or more thereof. The carbon-containing precursor can comprise CH4, C2H4, C2H2, C6H6, or C6H5OH, or a combination of two or more thereof. The inert gas can comprise argon, helium, or nitrogen, or a combination of two or more thereof. For example, the oxygen containing gas can comprise at O2, CO, NO, N2O, or CO2, or a combination of two or more thereof, and the flow rate can range from approximately 0 sccm to approximately 10000 sccm.
  • [0112]
    The TERA layer can comprise a material having a refractive index (n) ranging from approximately 1.5 to approximately 2.5 when measured at a wavelength of at least one of 248 nm, 193 nm, or 157 nm, and an extinction coefficient (k) ranging from approximately 0.10 to approximately 0.9 when measured at a wavelength of at least one of 248 nm, 193 nm, or 157 nm. For example, a TERA layer can comprise a SiCOH material, or a SiCH material, or a combination thereof. The TERA layer can comprise a thickness ranging from approximately 30 nm to approximately 500 nm, and the deposition rate can range from approximately 100 Å/min to approximately 10000 Å/min. The TERA layer can comprise one or more layers having different etch-resistance and/or optical properties.
  • [0113]
    Furthermore, the chamber pressure and substrate temperature can be controlled during the deposition of the TERA layer. For example, the chamber pressure can range from approximately 0.1 mTorr to approximately 100.0 mTorr, and the substrate temperature can range from approximately 0° C. to approximately 500° C.
  • [0114]
    FIG. 6 illustrates a simplified block diagram for a processing system 600 in accordance with an embodiment of the invention. In the illustrated embodiment, the processing system 600 for performing a chemical treatment and a thermal treatment of a substrate 642 is presented. The processing system 600 comprises a chemical treatment system 610, and a thermal treatment system 620 coupled to the chemical treatment system 610. The chemical treatment system 610 comprises a chemical treatment chamber 611, which can be temperature-controlled. The thermal treatment system 620 comprises a thermal treatment chamber 621, which can be temperature-controlled. The chemical treatment chamber 611 and the thermal treatment chamber 621 can be thermally insulated from one another using a thermal insulation assembly 630, and vacuum isolated from one another using a gate valve assembly 696.
  • [0115]
    As illustrated in FIG. 6, the chemical treatment system 610 further comprises a temperature controlled substrate holder 640 configured to be substantially thermally isolated from the chemical treatment chamber 611 and configured to support the substrate 642. A vacuum pumping system 650 is coupled to the chemical treatment chamber 611 to evacuate the chemical treatment chamber 611. A gas distribution system 660 is also connected to the chemical treatment chamber 611 for introducing a process gas into a process space 662 within the chemical treatment chamber 611.
  • [0116]
    Also, the thermal treatment system 620 further comprises a temperature controlled substrate holder 670 mounted within the thermal treatment chamber 621. The substrate holder 670 is configured to be substantially thermally insulated from the thermal treatment chamber 621 and is configured to support a substrate 642′. A vacuum pumping system 680 is used to evacuate the thermal treatment chamber 621. A substrate lifter assembly 690 is coupled to the thermal treatment chamber 621. The lifter assembly 690 can vertically translate the substrate 642″ between a holding plane (solid lines) and the substrate holder 670 (dashed lines), or a transfer plane located therebetween. The thermal treatment chamber 621 can further comprise an upper assembly 684.
  • [0117]
    Additionally, the chemical treatment chamber 611, thermal treatment chamber 621, and thermal insulation assembly 630 define a common opening 694 through which a substrate 642 can be transferred. During processing, the common opening 694 can be sealed closed using the gate valve assembly 696 in order to permit independent processing in the two chambers 611, 621. Furthermore, a transfer opening 698 can be formed in the thermal treatment chamber 621 in order to permit substrate exchanges with a transfer system as illustrated in FIG. 1. For example, a second thermal insulation assembly 631 can be implemented to thermally insulate the thermal treatment chamber 621 from a transfer system (not shown). Although the opening 698 is illustrated as part of the thermal treatment chamber 621, the transfer opening 698 can be formed in the chemical treatment chamber 611 and not the thermal treatment chamber 621, or the transfer opening 698 can be formed in both the chemical treatment chamber 611 and the thermal treatment chamber 621.
  • [0118]
    As illustrated in FIG. 6, the chemical treatment system 610 comprises the substrate holder 640 and the substrate holder assembly 644 in order to provide several operational functions for thermally controlling and processing the substrate 642. The substrate holder 640 and the substrate holder assembly 644 can comprise an electrostatic clamping system (or mechanical clamping system) in order to electrically (or mechanically) clamp the substrate 642 to the substrate holder 640. Furthermore, the substrate holder 640 can, for example, further include a cooling system having a re-circulating coolant flow that receives heat from the substrate holder 640 and transfers heat to a heat exchanger system (not shown), or when heating, transfers heat from the heat exchanger system.
  • [0119]
    Moreover, a heat transfer gas can, for example, be delivered to the back-side of the substrate 642 via a backside gas system to improve the gas-gap thermal conductance between the substrate 642 and the substrate holder 640. For instance, the heat transfer gas supplied to the back-side of the substrate 642 can comprise an inert gas such as helium, argon, xenon, krypton, a process gas, or other gas such as oxygen, nitrogen, or hydrogen. Such a system can be utilized when temperature control of the substrate 642 is required at elevated or reduced temperatures. For example, the backside gas system can comprise a multi-zone gas distribution system such as a two-zone (center-edge) system, wherein the back-side gas gap pressure can be independently varied between the center and the edge of the substrate 642. In other embodiments, heating/cooling elements, such as resistive heating elements, or thermo-electric heaters/coolers can be included in the substrate holder 640, as well as the chamber wall of the chemical treatment chamber 611.
  • [0120]
    Also, the substrate holder 640 can further comprise a lift pin assembly (not shown) capable of raising and lowering three or more lift pins (not shown) in order to vertically translate the substrate 642 to and from an upper surface of the substrate holder 640 and a transfer plane in the processing system 600.
  • [0121]
    In addition, the temperature of the temperature-controlled substrate holder 640 can be monitored using a temperature sensing device (not shown) such as a thermocouple (e.g. a K-type thermocouple, Pt sensor, etc.). Furthermore, a controller can utilize the temperature measurement as feedback to the substrate holder 640 assembly in order to control the temperature of substrate holder 640. For example, a fluid flow rate, fluid temperature, heat transfer gas type, heat transfer gas pressure, clamping force, resistive heater element current or voltage, thermoelectric device current or polarity, or a combination of two or more thereof can be adjusted in order to affect a change in the temperature of substrate holder 640 and/or the temperature of the substrate 642.
  • [0122]
    Referring again to FIG. 6, chemical treatment system 610 comprises a gas distribution system 660. In one embodiment, a gas distribution system 660 can comprise a showerhead gas injection system (not shown). The gas distribution system 660 can further comprise one or more gas distribution orifices to distribute a process gas to the process space 662 within the chemical treatment chamber 611. Additionally, the process gas can, for example, comprise NH3, HF, H2, O2, CO, CO2, Ar, He, etc.
  • [0123]
    As shown in FIG. 6, the chemical treatment system 620 further comprises the temperature controlled chemical treatment chamber 611 that is maintained at an elevated temperature. For example, a wall heating element 666 can be coupled to a wall temperature control unit 668, and the wall heating element 666 can be configured to couple to the chemical treatment chamber 611. The heating element 666 can, for example, comprise a resistive heater element such as a tungsten, nickel-chromium alloy, aluminum-iron alloy, aluminum nitride, etc., filament. Examples of commercially available materials to fabricate resistive heating elements include Kanthal, Nikrothal, Akrothal, which are registered trademark names for metal alloys produced by Kanthal Corporation of Bethel, Conn. The Kanthal family includes ferritic alloys (FeCrAl) and the Nikrothal family includes austenitic alloys (NiCr, NiCrFe).
  • [0124]
    When an electrical current flows through the filament, power is dissipated as heat, and, therefore, the wall temperature control unit 668 can, for example, comprise a controllable DC power supply. For example, wall heating element 666 can comprise at least one Firerod cartridge heater commercially available from Watlow (1310 Kingsland Dr., Batavia, Ill., 60510). A cooling element can also be employed in the chemical treatment chamber 611. The temperature of the chemical treatment chamber 611 can be monitored using a temperature-sensing device such as a thermocouple (e.g. a K-type thermocouple, Pt sensor, etc.). Furthermore, a controller can utilize the temperature measurement as feedback to the wall temperature control unit 668 in order to control the temperature of the chemical treatment chamber 611.
  • [0125]
    Referring again to FIG. 6, the chemical treatment system 610 can further comprise a temperature controlled gas distribution system 660 that can be maintained at any selected temperature.
  • [0126]
    Furthermore, in FIG. 6, the vacuum pumping system 650 is shown that can comprise a vacuum pump 652 and a gate valve 654 for throttling the chamber pressure. The vacuum pump 652 can, for example, include a turbo-molecular vacuum pump (TMP) capable of a pumping speed up to 5000 liters per second (and greater). For example, the TMP can be a Seiko STP-A803 vacuum pump, or an Ebara ET1301W vacuum pump. TMPs are useful for low pressure processing, typically less than 50 mTorr. For high pressure (i.e., greater than 100 mTorr) or low throughput processing (i.e., no gas flow), a mechanical booster pump and dry roughing pump can be used.
  • [0127]
    In one embodiment, the processing system 600 can be controlled using a controller, such as controller 90 in FIG. 1. In an alternate embodiment, the processing system 600 can comprise a controller (not shown) that can be coupled to the chemical treatment system 610 and the thermal treatment system 620. For example, the controller can comprise a processor, memory, and a digital I/O port capable of exchanging information with the chemical treatment system 610 as well as the thermal treatment system 620.
  • [0128]
    As shown in FIG. 6, the thermal treatment system 620 further comprises a temperature controlled substrate holder 670. The substrate holder 670 can further comprise a heating element 676 embedded therein and a substrate holder temperature control unit 678 coupled thereto. The heating element 676 can, for example, comprise a resistive heater element such as a tungsten, nickel-chromium alloy, aluminum-iron alloy, aluminum nitride, etc., filament. Examples of commercially available materials to fabricate resistive heating elements include Kanthal, Nikrothal, and Akrothal, which are registered trademark names for metal alloys produced by Kanthal Corporation of Bethel, Conn. The Kanthal family includes ferritic alloys (FeCrAl) and the Nikrothal family includes austenitic alloys (NiCr, NiCrFe).
  • [0129]
    As discussed above, when an electrical current flows through the filament, power is dissipated as heat, and, therefore, the substrate holder temperature control unit 678 can, for example, comprise a controllable DC power supply. Alternately, the temperature controlled substrate holder 670 can, for example, be a cast-in heater commercially available from Watlow (1310 Kingsland Dr., Batavia, Ill., 60510) capable of a maximum operating temperature of 400 to 450 C, or a film heater comprising aluminum nitride materials that is also commercially available from Watlow and capable of operating temperatures as high as 300 C and power densities of up to 23.25 W/cm2. Alternatively, a cooling element can be incorporated in the substrate holder 670.
  • [0130]
    The temperature of the substrate holder 670 can be monitored using a temperature-sensing device such as a thermocouple (e.g. a K-type thermocouple). Furthermore, a controller can utilize the temperature measurement as feedback to the substrate holder temperature control unit 678 in order to control the temperature of the substrate holder 670.
  • [0131]
    Referring again to FIG. 6, the thermal treatment system 620 can further comprise a temperature controlled thermal treatment chamber 621 that is maintained at a selected temperature. For example, a thermal wall heating element 683 can be coupled to a thermal wall temperature control unit 681, and the thermal wall heating element 683 can be configured to couple to the thermal treatment chamber 621. The heating element 683 can, for example, comprise a resistive heater element such as a tungsten, nickel-chromium alloy, aluminum-iron alloy, aluminum nitride, etc., filament. Examples of commercially available materials to fabricate resistive heating elements include Kanthal, Nikrothal, Akrothal, which are registered trademark names for metal alloys produced by Kanthal Corporation of Bethel, Conn. The Kanthal family includes ferritic alloys (FeCrAl) and the Nikrothal family includes austenitic alloys (NiCr, NiCrFe).
  • [0132]
    When an electrical current flows through the filament, power is dissipated as heat, and, therefore, the thermal wall temperature control unit 681 can, for example, comprise a controllable DC power supply. For example, thermal wall heating element 683 can comprise at least one Firerod cartridge heater commercially available from Watlow (1310 Kingsland Dr., Batavia, Ill., 60510). Alternatively, or in addition, cooling elements may be employed in thermal treatment chamber 621. The temperature of the thermal treatment chamber 621 can be monitored using a temperature-sensing device such as a thermocouple (e.g. a K-type thermocouple, Pt sensor, etc.). Furthermore, a controller can utilize the temperature measurement as feedback to the thermal wall temperature control unit 681 in order to control the temperature of the thermal treatment chamber 621.
  • [0133]
    In addition, thermal treatment system 620 can further comprise an upper assembly 684. The upper assembly 684 can, for example, comprise a gas injection system for introducing a purge gas, process gas, or cleaning gas to the thermal treatment chamber 621. Alternately, the thermal treatment chamber 621 can comprise a gas injection system separate from the upper assembly. For example, a purge gas, process gas, or cleaning gas can be introduced to the thermal treatment chamber 621 through a side-wall thereof.
  • [0134]
    In an alternate embodiment, the upper assembly 684 can comprise a radiant heater such as an array of tungsten halogen lamps for heating the substrate 642″ positioned on the substrate lifter assembly 690. The thermal treatment system 620 can further comprise a temperature controlled upper assembly 684 that can be maintained at a selected temperature. For example, the upper assembly 684 can comprise a heating element. The temperature of the upper assembly 684 can be monitored using a temperature-sensing device. Furthermore, a controller can utilize the temperature measurement as feedback to control the temperature of the upper assembly 684. The upper assembly 684 may additionally or alternatively include a cooling element.
  • [0135]
    Referring again to FIG. 6, the thermal treatment system 620 can further comprise a substrate lifter assembly 690. The substrate lifter assembly 690 can be configured to lower a substrate 642′ to an upper surface of the substrate holder 670, as well as raise a substrate 642″ from an upper surface of the substrate holder 670 to a holding plane, or a transfer plane therebetween. At the transfer plane, the substrate 642″ can be exchanged with a transfer system utilized to transfer substrates into and out of the chemical and thermal treatment chambers 611, 621. At the holding plane, the substrate 642″ can be cooled while another substrate is exchanged between the transfer system and the chemical and thermal treatment chambers 611, 621.
  • [0136]
    The thermal treatment system 620 further comprises a vacuum pumping system 680. The vacuum pumping system 680 can, for example, comprise a vacuum pump, and a throttle valve such as a gate valve or butterfly valve. The vacuum pump can, for example, include a turbo-molecular vacuum pump (TMP) capable of a pumping speed up to 5000 liters per second (and greater). TMPs are useful for low pressure processing, typically less than 50 mTorr. For high pressure processing (i.e., greater than 100 mTorr), a mechanical booster pump and dry roughing pump can be used.
  • [0137]
    In addition, a gate valve assembly 696 can be utilized to vertically translate a gate valve in order to open and close the common opening 694. The gate valve assembly 696 can vacuum seal the common opening 694.
  • [0138]
    In one embodiment, the processing system 600 can comprise a chemical oxide removal (COR) system 610 for trimming oxidized features of a TERA layer. The processing system 600 comprises the chemical treatment system 610 for chemically treating exposed surfaces of features on a TERA layer, such as oxidized surfaces, whereby adsorption of the process chemistry on the exposed surfaces of the features on a TERA layer affects chemical alteration of the exposed surfaces. Additionally, the processing system 600 comprises the thermal treatment system 620 for thermally treating the substrate, whereby the substrate temperature is elevated in order to desorb (or evaporate) the chemically altered exposed surfaces of the features on a TERA layer.
  • [0139]
    An exemplary COR process can comprise a number of process steps. For example, the substrate 642 can be transferred into the chemical treatment system 610 using the substrate transfer system. The substrate 642 can be received by lift pins that are housed within the substrate holder 640, and the substrate 642 is lowered to the substrate holder 640. Thereafter, the substrate 642 can be secured to the substrate holder 660 using a clamping system, such as an electrostatic clamping system, and a heat transfer gas can be supplied to the backside of the substrate 642.
  • [0140]
    Next, one or more chemical processing parameters for chemical treatment of the substrate 642 can be established. For example, the one or more chemical processing parameters comprise a chemical treatment processing pressure, a chemical treatment wall temperature, a chemical treatment substrate holder temperature, a chemical treatment substrate temperature, a chemical treatment gas distribution system temperature, or a chemical treatment gas flow rate, or a combination of two or more thereof. Then, the substrate 642 can be chemically treated for a first period of time. The first period of time can range from 10 to 480 seconds, for example.
  • [0141]
    Next, the substrate 642 can be transferred from the chemical treatment chamber 611 to the thermal treatment chamber 621. During which time, the substrate clamp can be removed, and the flow of heat transfer gas to the backside of the substrate 642 can be terminated. The substrate 642 can be vertically lifted from the substrate holder 640 to the transfer plane using the lift pin assembly housed within the substrate holder 640. The transfer system can receive the substrate 642 from the lift pins and can position the substrate 642 within the thermal treatment system 620. Therein, the substrate lifter assembly 690 receives the substrate 641′, 642″ from the transfer system, and lowers the substrate 642′ to the substrate holder 670
  • [0142]
    Then, the thermal processing parameters for a thermal treatment of the substrate 642′ can be set. For example, the one or more thermal processing parameters comprise a thermal treatment wall temperature, a thermal treatment upper assembly temperature, a thermal treatment substrate temperature, a thermal treatment substrate holder temperature, a thermal treatment substrate temperature, or a thermal treatment processing pressure, or a combination of two or more thereof. Next, the substrate 642′ can be thermally treated for a second period of time. The second period of time can range from 10 to 480 seconds, for example.
  • [0143]
    FIG. 7 illustrates a simplified block diagram of a processing subsystem 700 in accordance with an embodiment of the invention. In the illustrated embodiment, the processing subsystem 700 for performing a number of processes, such as etching, ashing, cleaning, and oxidizing, is presented. In the illustrated embodiment, the processing subsystem 700 can comprise a processing chamber 710, an upper assembly 720, a gas supply system 750, a shower plate assembly 756, a substrate holder 730 for supporting a substrate 705, a pressure control system 780, and a controller 790.
  • [0144]
    In one embodiment, the processing subsystem 700 can comprise the pressure control system 780 that can be coupled to the processing chamber 710. For example, the pressure control system 780 can comprise a throttle valve (not shown) and a turbomolecular pump (TMP) (not shown) and can provide a controlled pressure in the processing chamber 710. In alternate embodiments, the pressure control system 700 can comprise a dry pump. For example, the chamber pressure can range from approximately 0.1 mTorr to approximately 100 mTorr. Alternatively, the chamber pressure can range from approximately 0.1 mTorr to approximately 20 mTorr.
  • [0145]
    The processing chamber 710 can facilitate the formation of plasma in a process space 702. The processing subsystem 700 can be configured to process substrates of any size, such as 200 mm substrates, 300 mm substrates, or larger substrates. Alternately, the processing subsystem 700 can operate by generating plasma in one or more processing chambers.
  • [0146]
    The processing subsystem 700 can comprise a shower plate 758 coupled to gas distribution system components 756 and 752. For example, the gas distribution system component 752 can be coupled to a gas distribution system 750. the shower plate 758 can comprise quartz and can be mounted opposite the substrate holder 730. the shower plate 758 can comprise one or more distribution regions (not shown). A shield ring 744 can be used to couple the shower plate 758 to the gas distribution system component 756. Ceramic insulators 740, 742, and 746 can be used to couple the gas distribution system component 756 and the shower plate 758 to the processing chamber 710.
  • [0147]
    The gas distribution system 750 can provide process gas to the gas distribution system components 756, 752 and to the shower plate 758. The gas chemistries and flow rates can be individually controlled.
  • [0148]
    The processing subsystem 700 can comprise an upper electrode 725 that can be coupled to the gas distribution system components 756, 752, to the shower plate 758 and to the processing chamber 710. The upper electrode 725 can comprise temperature control elements (not shown). The upper electrode 725 can be coupled to a first RF source 770 using a first match network 772. Alternately, a separate match network 772 is not required.
  • [0149]
    The first RF source 770 can provide a TRF signal to the upper electrode, and the first RF source 770 can operate in a frequency range from approximately 0.1 MHz. to approximately 200 MHz. The TRF signal can be in the frequency range from approximately 1 MHz. to approximately 100 MHz. or alternatively in the frequency range from approximately 10 MHz. to approximately 100 MHz. The first RF source 790 can operate in a power range from approximately 0 watts to approximately 10000 watts, or alternatively the first RF source 770 can operate in a power range from approximately 0 watts to approximately 5000 watts.
  • [0150]
    The upper electrode 725 and the first RF source 770 can be parts of a capacitively coupled plasma source. The capacitively couple plasma source may be replaced with or augmented by other types of plasma sources, such as an inductively coupled plasma (ICP) source, a transformer-coupled plasma (TCP) source, a microwave powered plasma source, an electron cyclotron resonance (ECR) plasma source, a Helicon wave plasma source, and a surface wave plasma source. As is well known in the art, the upper electrode 725 may be eliminated or reconfigured in the various suitable plasma sources.
  • [0151]
    The substrate 705 can be, for example, transferred into and out of processing chamber 710 through a slot valve (not shown) and chamber feed-through (not shown) via robotic substrate transfer system (not shown), and it can be received by the substrate holder 730. In an alternate embodiment, the processing chamber 710 can comprise a translation device (not shown), and when the substrate 705 is received from the substrate transfer system, the substrate 705 can be raised and/or lowered using a translation device (not shown) that can be coupled to the substrate holder 730.
  • [0152]
    The substrate 705 can be affixed to the substrate holder 730 via an electrostatic clamping system 764. For example, the electrostatic clamping system 764 can comprise an electrode and an ESC supply. Clamping voltages that can range from approximately −5000 V to approximately +5000 V, for example, can be provided to the clamping electrode. Alternatively, the clamping voltage can range from approximately −2500 V to approximately +2500 V. In alternate embodiments, an ESC system and supply may be omitted altogether.
  • [0153]
    The substrate holder 730 can comprise lift pins (not shown) for lowering and/or raising the substrate 705 to and/or from the surface of the substrate holder 730. In alternate embodiments, different lifting means can be provided in the substrate holder 730. In alternate embodiments, gas can, for example, be delivered to the backside of the substrate 705 via a backside gas system to improve the gas-gap thermal conductance between the substrate 705 and the substrate holder 730.
  • [0154]
    A temperature control system can also be provided. Such a system can be utilized when temperature control of the substrate is required at elevated or reduced temperatures. For example, temperature control elements (not shown) can be included in the substrate holder 730, the processing chamber 710 and/or the upper assembly 720.
  • [0155]
    Also, an electrode 768 can be coupled to a second RF source 775 using a second match network 777. Alternately, the match network 777 may be omitted altogether.
  • [0156]
    The second RF source 775 can provide a bottom RF signal (BRF) to the lower electrode 768, and the second RF source 775 can operate in a frequency range from approximately 0.1 MHz. to approximately 200 MHz. The BRF signal can be in the frequency range from approximately 0.2 MHz. to approximately 30 MHz. or alternatively, in the frequency range from approximately 0.3 MHz. to approximately 15 MHz. The second RF source 775 can operate in a power range from approximately 0.0 watts to approximately 2500 watts, or alternatively, the second RF source 775 can operate in a power range from approximately 0.0 watts to approximately 500 watts. In various embodiments, the lower electrode 768 may be not used, or may be the sole source of plasma within the chamber, or may augment any additional plasma source.
  • [0157]
    Additionally, the substrate holder 730 can further comprise a quartz focus ring 762 and quartz isolators 760, 766. Alternately, the focus ring 762 and/or quartz isolators 760, 766 may be omitted altogether.
  • [0158]
    The processing chamber 710 can further comprise a chamber liner 714 and at least one protective element 716. For example, the protective element 716 can comprise a ceramic material, and can be used to protect the substrate holder 730 and the wall. In an alternate embodiment, the protective element 716 may be omitted altogether.
  • [0159]
    In one embodiment, a gap can be established between the shower plate 758 and the substrate holder 730 using different wall heights for the processing chamber 710. For example, a 170 mm gap can be established. In alternate embodiments, different gap sizes can be used. In other embodiments, a translation device (not shown) can be used to provide a variable gap, and the gap can remain fixed or the gap can be changed during a process.
  • [0160]
    In an alternate embodiment, the processing chamber 710 can, for example, further comprise a monitoring port (not shown). A monitoring port can, for example, permit optical monitoring of the process space 702.
  • [0161]
    The processing subsystem 700 can also comprise the controller 790. The controller 790 can be coupled to the processing chamber 710, the gas supply system 750, the first RF match 772, the first RF source 770, the second RF match 787, the second RF source 785, and the pressure control system 780. The controller 790 can be configured to provide control data to these components and receive data such as process data from these components. For example, controller 790 can comprise a microprocessor, a memory, and a digital I/O port capable of generating control voltages sufficient to communicate and activate inputs to the processing system 700 as well as monitor outputs from the processing subsystem 700.
  • [0162]
    Moreover, the controller 790 can exchange information with system components. Also, a program stored in the memory can be utilized to control the aforementioned components of the processing subsystem 700 according to a process recipe. In addition, controller 790 can be configured to analyze the process data, to compare the process data with target process data, and to use the comparison to change a process and/or control the deposition tool. Also, the controller 790 can be configured to analyze the process data, to compare the process data with historical process data, and to use the comparison to predict, prevent, and/or declare a fault. During the etching of a TERA layer, the substrate 705 can be placed on the substrate holder 730 in the processing chamber 710. For example, the processing chamber 710 can be chosen based on the gap size between the upper electrode surface 725 and a surface of the substrate holder 730. The gap can range from approximately 10 mm to approximately 200 mm, or alternatively, the gap can range from approximately 150 mm to approximately 190 mm. In alternate embodiments, the gap size can be different.
  • [0163]
    During a TERA layer etching process, a TRF signal can be provided to the upper electrode 725 using the first RF source 770. For example, the first RF source 770 can operate in a frequency range from approximately 0.1 MHz. to approximately 200 MHz. Alternatively, the first RF source 770 can operate in a frequency range from approximately 1 MHz. to approximately 100 MHz., or the first RF source 770 can operate in a frequency range from approximately 20 MHz. to approximately 100 MHz. The first RF source 770 can operate in a power range from approximately 10 watts to approximately 10000 watts, or alternatively, the first RF source 770 can operate in a power range from approximately 10 watts to approximately 5000 watts
  • [0164]
    Also, when etching a TERA layer, a BRF signal can be provided to the lower electrode 768 using the second RF source 775. For example, the second RF source 775 can operate in a frequency range from approximately 0.1 MHz. to approximately 200 MHz. Alternatively, the second RF source 775 can operate in a frequency range from approximately 0.2 MHz. to approximately 30 MHz, or the second RF source can operate in a frequency range from approximately 0.3 MHz. to approximately 15 MHz. The second RF source 775 can operate in a power range from approximately 0.0 watts to approximately 1000 watts, or alternatively, the second RF source 775 can operate in a power range from approximately 0.0 watts to approximately 500 watts. In an alternate embodiment, a BRF signal is not required.
  • [0165]
    In addition, a process gas can be provided to the processing chamber 710 using the shower plate 758. For example, the process gas can comprise an oxygen-containing gas and an inert gas. For example, the oxygen-containing gas can comprise O2, CO, NO, N2O, or CO2, or a combination of two or more thereof, and the flow rate can range from approximately 0 sccm to approximately 10000 sccm. The inert gas can comprise argon, helium, or nitrogen, or a combination of two or more thereof, and the flow rate for the inert gas can range from approximately 0 sccm to approximately 10000 sccm.
  • [0166]
    Furthermore, the chamber pressure and substrate temperature can be controlled during the etching of the TERA layer. For example, the chamber pressure can range from approximately 0.1 mTorr to approximately 100.0 mTorr, and the substrate temperature can range from approximately 0° C. to approximately 500° C.
  • [0167]
    During the oxidation of the features of a TERA layer, the substrate can be placed on the substrate holder 730 in a processing chamber 710. For example, the processing chamber 710 can be chosen based on the gap size between the upper electrode surface 725 and a surface of the substrate holder 730. The gap can range from approximately 10 mm to approximately 200 mm, or alternatively, the gap can range from approximately 150 mm to approximately 190 mm. In alternate embodiments, the gap size can be selected from a wide variety of predetermined values.
  • [0168]
    During the oxidation of the features of a TERA layer, a TRF signal can be provided to the upper electrode 725 using the first RF source 770. For example, the first RF source 770 can operate in a frequency range from approximately 0.1 MHz. to approximately 200 MHz. Alternatively, the first RF source 770 can operate in a frequency range from approximately 1 MHz. to approximately 100 MHz. or the first RF source 770 can operate in a frequency range from approximately 20 MHz. to approximately 100 MHz. The first RF source 770 can operate in a power range from approximately 10 watts to approximately 10000 watts, or alternatively, the first RF source 770 can operate in a power range from approximately 10 watts to approximately 5000 watts
  • [0169]
    Also, when oxidizing the features of a TERA layer, a BRF signal can be provided to the lower electrode 768 using the second RF source 775. For example, the second RF source 775 can operate in a frequency range from approximately 0.1 MHz. to approximately 200 MHz. Alternatively, the second RF source 775 can operate in a frequency range from approximately 0.2 MHz. to approximately 30 MHz. or the second RF source can operate in a frequency range from approximately 0.3 MHz. to approximately 15 MHz. The second RF source 775 can operate in a power range from approximately 0.0 watts to approximately 1000 watts, or alternatively, the second RF source 775 can operate in a power range from approximately 0.0 watts to approximately 500 watts. In an alternate embodiment, a BRF signal is not required.
  • [0170]
    In addition, when oxidizing the features of a TERA layer, a process gas can be provided to the processing chamber 710 using the shower plate 758. For example, the process gas can comprise an oxygen-containing gas and/or an inert gas. For example, the oxygen containing gas can comprise O2, CO, NO, N2O, or CO2, or a combination of two or more thereof, and the flow rate can range from approximately 0.0 sccm to approximately 10000 sccm. The inert gas can comprise argon, helium, or nitrogen, or a combination of two or more thereof, and the flow rate for the inert gas can range from approximately 0 sccm to approximately 10000 sccm. Furthermore, the chamber pressure and substrate temperature can be controlled when oxidizing the features of a TERA layer. For example, the chamber pressure can range from approximately 0.1 mTorr to approximately 100.0 Torr, and the substrate temperature can range from approximately 0° C. to approximately 500° C.
  • [0171]
    Although only certain embodiments of this invention have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention.
  • [0172]
    Thus, the description is not intended to limit the invention and the configuration, operation, and behavior of the present invention has been described with the understanding that modifications and variations of the embodiments are possible, given the level of detail present herein. Accordingly, the preceding detailed description is not meant or intended to, in any way, limit the invention—rather the scope of the invention is defined by the appended claims. Moreover, where list are provided herein, those lists are intended to be exemplary only. Being open-ended, the list is not meant to limit the scope of the invention solely to the specific embodiments enumerated. To the contrary, as should be appreciated by those skilled in the art, further components, stages, arrangements, etc. may be easily added or substituted without departing from the intended scope of the invention.

Claims (10)

  1. 1. A system for processing a Tunable Etch Rate ARC (TERA) layer on a substrate, comprising:
    a processing subsystem for depositing the TERA layer on the substrate using a plasma enhanced chemical vapor deposition (PECVD) system;
    a processing subsystem for creating features in the TERA layer using an etching system; and
    a processing subsystem for reducing the size of the features in the TERA layer.
  2. 2. The system of claim 1, further comprising:
    a substrate holder in a processing chamber in the PECVD system; and
    means for providing a process gas to the processing chamber, wherein the process gas comprises an inert gas and a silicon-containing precursor, or a carbon-containing precursor, or a combination thereof.
  3. 3. The system of claim 2, further comprising:
    an upper electrode coupled to the processing chamber; and
    a translation device coupled to the substrate holder for establishing a gap between an upper electrode surface and a surface of the substrate holder.
  4. 4. The system of claim 3, wherein the gap ranges from approximately 10 mm to approximately 200 mm.
  5. 5. The system of claim 2, further comprising:
    a first RF source coupled to the upper electrode, wherein the first RF source operates in a frequency range from approximately 0.1 MHz. to approximately 200 MHz. and operates in a power range from approximately 10 watts to approximately 10000 watts.
  6. 6. The system of claim 5, further comprising:
    a second RF source coupled to the substrate holder, wherein the second RF source operates in a frequency range from approximately 0.1 MHz. to approximately 200 MHz. and operates in a power range from approximately 10 watts to approximately 10000 watts.
  7. 7. The system of claim 2, further comprising:
    an RF source coupled to the substrate holder, wherein the RF source operates in a frequency range from approximately 0.1 MHz. to approximately 200 MHz. and operates in a power range from approximately 10 watts to approximately 10000 watts.
  8. 8. The system of claim 2, wherein the silicon-containing precursor comprises monosilane (SiH4), tetraethylorthosilicate (TEOS), monomethylsilane (1 MS), dimethylsilane (2MS), trimethylsilane (3MS), tetramethylsilane (4MS), octamethylcyclotetrasiloxane (OMCTS), dimethyldimethoxysilane (DMDMOS), or tetramethylcyclotetrasilane (TMCTS), or a combination of two or more thereof.
  9. 9. The system of claim 2, wherein the carbon-containing precursor comprises CH4, C2H4, C2H2, C6H6, or C6H5OH, or a combination of two or more thereof.
  10. 10. The system of claim 2, wherein the first process gas includes an inert gas comprising argon, helium, or and nitrogen, or a combination of two or more thereof.
US11486105 2004-07-06 2006-07-14 Processing system and method for chemically treating a tera layer Abandoned US20060254716A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10883784 US7097779B2 (en) 2004-07-06 2004-07-06 Processing system and method for chemically treating a TERA layer
US11486105 US20060254716A1 (en) 2004-07-06 2006-07-14 Processing system and method for chemically treating a tera layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11486105 US20060254716A1 (en) 2004-07-06 2006-07-14 Processing system and method for chemically treating a tera layer

Publications (1)

Publication Number Publication Date
US20060254716A1 true true US20060254716A1 (en) 2006-11-16

Family

ID=34969066

Family Applications (2)

Application Number Title Priority Date Filing Date
US10883784 Active 2024-09-01 US7097779B2 (en) 2004-07-06 2004-07-06 Processing system and method for chemically treating a TERA layer
US11486105 Abandoned US20060254716A1 (en) 2004-07-06 2006-07-14 Processing system and method for chemically treating a tera layer

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US10883784 Active 2024-09-01 US7097779B2 (en) 2004-07-06 2004-07-06 Processing system and method for chemically treating a TERA layer

Country Status (5)

Country Link
US (2) US7097779B2 (en)
JP (1) JP4842263B2 (en)
KR (1) KR20070032938A (en)
CN (1) CN1973358B (en)
WO (1) WO2006014193A1 (en)

Cited By (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060134919A1 (en) * 2003-03-17 2006-06-22 Tokyo Electron Limited Processing system and method for treating a substrate
US20080139003A1 (en) * 2006-10-26 2008-06-12 Shahid Pirzada Barrier coating deposition for thin film devices using plasma enhanced chemical vapor deposition process
US20090004363A1 (en) * 2004-09-14 2009-01-01 Keshner Marvin S Plasma enhanced chemichal vapor deposition apparatus and method
US7806126B1 (en) * 2002-09-30 2010-10-05 Lam Research Corporation Substrate proximity drying using in-situ local heating of substrate and substrate carrier point of contact, and methods, apparatus, and systems for implementing the same
US20120267048A1 (en) * 2011-04-25 2012-10-25 Tokyo Electron Limited Plasma processing apparatus
US20130276700A1 (en) * 2009-08-28 2013-10-24 Mitsubishi Materials Corporation Apparatus for producing polycrystalline silicon
US9343272B1 (en) 2015-01-08 2016-05-17 Applied Materials, Inc. Self-aligned process
US9349605B1 (en) 2015-08-07 2016-05-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US9355856B2 (en) 2014-09-12 2016-05-31 Applied Materials, Inc. V trench dry etch
US9355863B2 (en) 2012-12-18 2016-05-31 Applied Materials, Inc. Non-local plasma oxide etch
US9355862B2 (en) 2014-09-24 2016-05-31 Applied Materials, Inc. Fluorine-based hardmask removal
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US9368364B2 (en) * 2014-09-24 2016-06-14 Applied Materials, Inc. Silicon etch process with tunable selectivity to SiO2 and other materials
US9373517B2 (en) 2012-08-02 2016-06-21 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US9373522B1 (en) 2015-01-22 2016-06-21 Applied Mateials, Inc. Titanium nitride removal
US9378969B2 (en) 2014-06-19 2016-06-28 Applied Materials, Inc. Low temperature gas-phase carbon removal
US9378978B2 (en) 2014-07-31 2016-06-28 Applied Materials, Inc. Integrated oxide recess and floating gate fin trimming
US9384997B2 (en) 2012-11-20 2016-07-05 Applied Materials, Inc. Dry-etch selectivity
US9385028B2 (en) 2014-02-03 2016-07-05 Applied Materials, Inc. Air gap process
US9390937B2 (en) 2012-09-20 2016-07-12 Applied Materials, Inc. Silicon-carbon-nitride selective etch
US9396989B2 (en) 2014-01-27 2016-07-19 Applied Materials, Inc. Air gaps between copper lines
US9406523B2 (en) 2014-06-19 2016-08-02 Applied Materials, Inc. Highly selective doped oxide removal method
US9412608B2 (en) 2012-11-30 2016-08-09 Applied Materials, Inc. Dry-etch for selective tungsten removal
US9418858B2 (en) 2011-10-07 2016-08-16 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
US9425058B2 (en) 2014-07-24 2016-08-23 Applied Materials, Inc. Simplified litho-etch-litho-etch process
US9437451B2 (en) 2012-09-18 2016-09-06 Applied Materials, Inc. Radical-component oxide etch
US9449846B2 (en) 2015-01-28 2016-09-20 Applied Materials, Inc. Vertical gate separation
US9449845B2 (en) 2012-12-21 2016-09-20 Applied Materials, Inc. Selective titanium nitride etching
US9472412B2 (en) 2013-12-02 2016-10-18 Applied Materials, Inc. Procedure for etch rate consistency
US9472417B2 (en) 2013-11-12 2016-10-18 Applied Materials, Inc. Plasma-free metal etch
US9478432B2 (en) 2014-09-25 2016-10-25 Applied Materials, Inc. Silicon oxide selective removal
US9493879B2 (en) 2013-07-12 2016-11-15 Applied Materials, Inc. Selective sputtering for pattern transfer
US9496167B2 (en) 2014-07-31 2016-11-15 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9499898B2 (en) 2014-03-03 2016-11-22 Applied Materials, Inc. Layered thin film heater and method of fabrication
US9502258B2 (en) 2014-12-23 2016-11-22 Applied Materials, Inc. Anisotropic gap etch
US9553102B2 (en) 2014-08-19 2017-01-24 Applied Materials, Inc. Tungsten separation
US9564296B2 (en) 2014-03-20 2017-02-07 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9576809B2 (en) 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US9607856B2 (en) 2013-03-05 2017-03-28 Applied Materials, Inc. Selective titanium nitride removal
US9659792B2 (en) 2013-03-15 2017-05-23 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9659753B2 (en) 2014-08-07 2017-05-23 Applied Materials, Inc. Grooved insulator to reduce leakage current
US9691645B2 (en) 2015-08-06 2017-06-27 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US9721789B1 (en) 2016-10-04 2017-08-01 Applied Materials, Inc. Saving ion-damaged spacers
US9728437B2 (en) 2015-02-03 2017-08-08 Applied Materials, Inc. High temperature chuck for plasma processing systems
US9741593B2 (en) 2015-08-06 2017-08-22 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US9754800B2 (en) 2010-05-27 2017-09-05 Applied Materials, Inc. Selective etch for silicon films
US9768034B1 (en) 2016-11-11 2017-09-19 Applied Materials, Inc. Removal methods for high aspect ratio structures
US9773648B2 (en) 2013-08-30 2017-09-26 Applied Materials, Inc. Dual discharge modes operation for remote plasma
US9842744B2 (en) 2011-03-14 2017-12-12 Applied Materials, Inc. Methods for etch of SiN films
US9865484B1 (en) 2016-06-29 2018-01-09 Applied Materials, Inc. Selective etch using material modification and RF pulsing
US9881805B2 (en) 2015-03-02 2018-01-30 Applied Materials, Inc. Silicon selective removal
US9887096B2 (en) 2012-09-17 2018-02-06 Applied Materials, Inc. Differential silicon oxide etch
US9885117B2 (en) 2014-03-31 2018-02-06 Applied Materials, Inc. Conditioned semiconductor system parts
US9934942B1 (en) 2016-10-04 2018-04-03 Applied Materials, Inc. Chamber with flow-through source
US9947549B1 (en) 2016-10-10 2018-04-17 Applied Materials, Inc. Cobalt-containing material removal
US9966240B2 (en) 2014-10-14 2018-05-08 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US9978564B2 (en) 2012-09-21 2018-05-22 Applied Materials, Inc. Chemical control features in wafer process equipment

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4860219B2 (en) * 2005-02-14 2012-01-25 東京エレクトロン株式会社 The substrate processing method, an electronic device manufacturing method and a program for
US7323401B2 (en) * 2005-08-08 2008-01-29 Applied Materials, Inc. Semiconductor substrate process using a low temperature deposited carbon-containing hard mask
JP2007059705A (en) * 2005-08-25 2007-03-08 Seiko Epson Corp Capacitor and its manufacturing method, method for manufacturing ferroelectric memory device and actuator, and liquid injection head
JP4854317B2 (en) 2006-01-31 2012-01-18 東京エレクトロン株式会社 The substrate processing method
US7662718B2 (en) * 2006-03-09 2010-02-16 Micron Technology, Inc. Trim process for critical dimension control for integrated circuits
US7795148B2 (en) * 2006-03-28 2010-09-14 Tokyo Electron Limited Method for removing damaged dielectric material
JP5015534B2 (en) * 2006-09-22 2012-08-29 カシオ計算機株式会社 Method of forming the insulating film
US20080078743A1 (en) * 2006-09-28 2008-04-03 Munoz Andres F Elevated temperature chemical oxide removal module and process
JP2008181996A (en) * 2007-01-24 2008-08-07 Tokyo Electron Ltd Method of manufacturing semiconductor device, apparatus of manufacturing semiconductor device, control program, and computer storage medium
JP4949091B2 (en) * 2007-03-16 2012-06-06 東京エレクトロン株式会社 Substrate processing apparatus, a substrate processing method and a recording medium
US8980706B2 (en) * 2008-09-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Double treatment on hard mask for gate N/P patterning
CN102301458B (en) * 2009-01-31 2016-01-20 应用材料公司 A method and apparatus for etching
KR20120103719A (en) * 2009-12-22 2012-09-19 어플라이드 머티어리얼스, 인코포레이티드 Pecvd multi-step processing with continuous plasma
KR101341024B1 (en) * 2010-06-11 2013-12-13 엘지디스플레이 주식회사 Method of fabricating thin film pattern and flat display having the thin film pattern
WO2013183437A1 (en) * 2012-06-08 2013-12-12 東京エレクトロン株式会社 Gas treatment method
WO2015079632A1 (en) * 2013-11-28 2015-06-04 株式会社Joled Atomic layer deposition device
CN105826197A (en) * 2015-01-08 2016-08-03 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacturing method thereof, and electronic device
US9805747B2 (en) * 2015-08-17 2017-10-31 Western Digital Technologies, Inc. Method for making a perpendicular magnetic recording write head with write pole having thin side gaps and thicker leading gap

Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4872947A (en) * 1986-12-19 1989-10-10 Applied Materials, Inc. CVD of silicon oxide using TEOS decomposition and in-situ planarization process
US5240556A (en) * 1991-06-05 1993-08-31 Tokyo Electron Limited Surface-heating apparatus and surface-treating method
US5639345A (en) * 1996-01-11 1997-06-17 Taiwan Semiconductor Manufacturing Company Ltd. Two step etch back process having a convex and concave etch profile for improved etch uniformity across a substrate
US5656123A (en) * 1995-06-07 1997-08-12 Varian Associates, Inc. Dual-frequency capacitively-coupled plasma reactor for materials processing
US5858819A (en) * 1994-06-15 1999-01-12 Seiko Epson Corporation Fabrication method for a thin film semiconductor device, the thin film semiconductor device itself, liquid crystal display, and electronic device
US6013574A (en) * 1996-01-30 2000-01-11 Advanced Micro Devices, Inc. Method of forming low resistance contact structures in vias arranged between two levels of interconnect lines
US6070550A (en) * 1996-09-12 2000-06-06 Applied Materials, Inc. Apparatus for the stabilization of halogen-doped films through the use of multiple sealing layers
US6124154A (en) * 1996-10-22 2000-09-26 Seiko Epson Corporation Fabrication process for thin film transistors in a display or electronic device
US6316167B1 (en) * 2000-01-10 2001-11-13 International Business Machines Corporation Tunabale vapor deposited materials as antireflective coatings, hardmasks and as combined antireflective coating/hardmasks and methods of fabrication thereof and application thereof
US6391690B2 (en) * 1995-12-14 2002-05-21 Seiko Epson Corporation Thin film semiconductor device and method for producing the same
US6444137B1 (en) * 1990-07-31 2002-09-03 Applied Materials, Inc. Method for processing substrates using gaseous silicon scavenger
US20020173085A1 (en) * 2001-05-18 2002-11-21 Semiconductor Energy Laboratory Co., Ltd. & Sharp Kabushiki Kaisha Method of manufacturing a semiconductor device and semiconductor manufacturing apparatus
US6554906B1 (en) * 2000-01-20 2003-04-29 Sumitomo Electric Industries, Ltd. Wafer holder for semiconductor manufacturing apparatus and semiconductor manufacturing apparatus using the same
US6573030B1 (en) * 2000-02-17 2003-06-03 Applied Materials, Inc. Method for depositing an amorphous carbon layer
US20040038537A1 (en) * 2002-08-20 2004-02-26 Wei Liu Method of preventing or suppressing sidewall buckling of mask structures used to etch feature sizes smaller than 50nm
US20040087092A1 (en) * 2002-10-31 2004-05-06 Taiwan Semiconductor Manufacturing Company Novel approach to improve line end shortening
US6750127B1 (en) * 2003-02-14 2004-06-15 Advanced Micro Devices, Inc. Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance
US20050106888A1 (en) * 2003-11-14 2005-05-19 Taiwan Semiconductor Manufacturing Co. Method of in-situ damage removal - post O2 dry process

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07283216A (en) 1994-04-12 1995-10-27 Sony Corp Al metal wiring structure and its patterning method
US20020086547A1 (en) 2000-02-17 2002-07-04 Applied Materials, Inc. Etch pattern definition using a CVD organic layer as an anti-reflection coating and hardmask
JP3419745B2 (en) * 2000-02-28 2003-06-23 キヤノン販売株式会社 Semiconductor device and manufacturing method thereof
WO2003007357A1 (en) 2001-07-10 2003-01-23 Tokyo Electron Limited Dry etching method
US6541351B1 (en) * 2001-11-20 2003-04-01 International Business Machines Corporation Method for limiting divot formation in post shallow trench isolation processes
JP2003179064A (en) * 2001-12-10 2003-06-27 Sony Corp Method of forming wiring pattern
DE10223954A1 (en) 2002-05-29 2003-12-11 Infineon Technologies Ag Plasma enhanced chemical vapor deposition process for depositing silicon nitride or silicon oxynitride, A method for producing a layer arrangement and layer arrangement

Patent Citations (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4872947A (en) * 1986-12-19 1989-10-10 Applied Materials, Inc. CVD of silicon oxide using TEOS decomposition and in-situ planarization process
US6444137B1 (en) * 1990-07-31 2002-09-03 Applied Materials, Inc. Method for processing substrates using gaseous silicon scavenger
US5240556A (en) * 1991-06-05 1993-08-31 Tokyo Electron Limited Surface-heating apparatus and surface-treating method
US5858819A (en) * 1994-06-15 1999-01-12 Seiko Epson Corporation Fabrication method for a thin film semiconductor device, the thin film semiconductor device itself, liquid crystal display, and electronic device
US5656123A (en) * 1995-06-07 1997-08-12 Varian Associates, Inc. Dual-frequency capacitively-coupled plasma reactor for materials processing
US6391690B2 (en) * 1995-12-14 2002-05-21 Seiko Epson Corporation Thin film semiconductor device and method for producing the same
US5639345A (en) * 1996-01-11 1997-06-17 Taiwan Semiconductor Manufacturing Company Ltd. Two step etch back process having a convex and concave etch profile for improved etch uniformity across a substrate
US6013574A (en) * 1996-01-30 2000-01-11 Advanced Micro Devices, Inc. Method of forming low resistance contact structures in vias arranged between two levels of interconnect lines
US6070550A (en) * 1996-09-12 2000-06-06 Applied Materials, Inc. Apparatus for the stabilization of halogen-doped films through the use of multiple sealing layers
US6124154A (en) * 1996-10-22 2000-09-26 Seiko Epson Corporation Fabrication process for thin film transistors in a display or electronic device
US6316167B1 (en) * 2000-01-10 2001-11-13 International Business Machines Corporation Tunabale vapor deposited materials as antireflective coatings, hardmasks and as combined antireflective coating/hardmasks and methods of fabrication thereof and application thereof
US6554906B1 (en) * 2000-01-20 2003-04-29 Sumitomo Electric Industries, Ltd. Wafer holder for semiconductor manufacturing apparatus and semiconductor manufacturing apparatus using the same
US6573030B1 (en) * 2000-02-17 2003-06-03 Applied Materials, Inc. Method for depositing an amorphous carbon layer
US20020173085A1 (en) * 2001-05-18 2002-11-21 Semiconductor Energy Laboratory Co., Ltd. & Sharp Kabushiki Kaisha Method of manufacturing a semiconductor device and semiconductor manufacturing apparatus
US20040038537A1 (en) * 2002-08-20 2004-02-26 Wei Liu Method of preventing or suppressing sidewall buckling of mask structures used to etch feature sizes smaller than 50nm
US20040087092A1 (en) * 2002-10-31 2004-05-06 Taiwan Semiconductor Manufacturing Company Novel approach to improve line end shortening
US6750127B1 (en) * 2003-02-14 2004-06-15 Advanced Micro Devices, Inc. Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance
US20050106888A1 (en) * 2003-11-14 2005-05-19 Taiwan Semiconductor Manufacturing Co. Method of in-situ damage removal - post O2 dry process

Cited By (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7806126B1 (en) * 2002-09-30 2010-10-05 Lam Research Corporation Substrate proximity drying using in-situ local heating of substrate and substrate carrier point of contact, and methods, apparatus, and systems for implementing the same
US20060134919A1 (en) * 2003-03-17 2006-06-22 Tokyo Electron Limited Processing system and method for treating a substrate
US7462564B2 (en) * 2003-03-17 2008-12-09 Tokyo Electron Limited Processing system and method for treating a substrate
US20090004363A1 (en) * 2004-09-14 2009-01-01 Keshner Marvin S Plasma enhanced chemichal vapor deposition apparatus and method
US20080139003A1 (en) * 2006-10-26 2008-06-12 Shahid Pirzada Barrier coating deposition for thin film devices using plasma enhanced chemical vapor deposition process
WO2009082517A1 (en) * 2007-12-20 2009-07-02 Optisolar, Inc. Plasma enhanced chemical vapor deposition of barrier coatings
US9169560B2 (en) * 2009-08-28 2015-10-27 Mitsubishi Materials Corporation Apparatus for producing polycrystalline silicon
US20130276700A1 (en) * 2009-08-28 2013-10-24 Mitsubishi Materials Corporation Apparatus for producing polycrystalline silicon
US9754800B2 (en) 2010-05-27 2017-09-05 Applied Materials, Inc. Selective etch for silicon films
US9842744B2 (en) 2011-03-14 2017-12-12 Applied Materials, Inc. Methods for etch of SiN films
US20120267048A1 (en) * 2011-04-25 2012-10-25 Tokyo Electron Limited Plasma processing apparatus
US9111726B2 (en) * 2011-04-25 2015-08-18 Tokyo Electron Limited Plasma processing apparatus
US9418858B2 (en) 2011-10-07 2016-08-16 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
US9373517B2 (en) 2012-08-02 2016-06-21 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US9887096B2 (en) 2012-09-17 2018-02-06 Applied Materials, Inc. Differential silicon oxide etch
US9437451B2 (en) 2012-09-18 2016-09-06 Applied Materials, Inc. Radical-component oxide etch
US9390937B2 (en) 2012-09-20 2016-07-12 Applied Materials, Inc. Silicon-carbon-nitride selective etch
US9978564B2 (en) 2012-09-21 2018-05-22 Applied Materials, Inc. Chemical control features in wafer process equipment
US9384997B2 (en) 2012-11-20 2016-07-05 Applied Materials, Inc. Dry-etch selectivity
US9412608B2 (en) 2012-11-30 2016-08-09 Applied Materials, Inc. Dry-etch for selective tungsten removal
US9355863B2 (en) 2012-12-18 2016-05-31 Applied Materials, Inc. Non-local plasma oxide etch
US9449845B2 (en) 2012-12-21 2016-09-20 Applied Materials, Inc. Selective titanium nitride etching
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US9607856B2 (en) 2013-03-05 2017-03-28 Applied Materials, Inc. Selective titanium nitride removal
US9704723B2 (en) 2013-03-15 2017-07-11 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9659792B2 (en) 2013-03-15 2017-05-23 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9493879B2 (en) 2013-07-12 2016-11-15 Applied Materials, Inc. Selective sputtering for pattern transfer
US9773648B2 (en) 2013-08-30 2017-09-26 Applied Materials, Inc. Dual discharge modes operation for remote plasma
US9576809B2 (en) 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US9520303B2 (en) 2013-11-12 2016-12-13 Applied Materials, Inc. Aluminum selective etch
US9472417B2 (en) 2013-11-12 2016-10-18 Applied Materials, Inc. Plasma-free metal etch
US9711366B2 (en) 2013-11-12 2017-07-18 Applied Materials, Inc. Selective etch for metal-containing materials
US9472412B2 (en) 2013-12-02 2016-10-18 Applied Materials, Inc. Procedure for etch rate consistency
US9396989B2 (en) 2014-01-27 2016-07-19 Applied Materials, Inc. Air gaps between copper lines
US9385028B2 (en) 2014-02-03 2016-07-05 Applied Materials, Inc. Air gap process
US9499898B2 (en) 2014-03-03 2016-11-22 Applied Materials, Inc. Layered thin film heater and method of fabrication
US9564296B2 (en) 2014-03-20 2017-02-07 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9837249B2 (en) 2014-03-20 2017-12-05 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9903020B2 (en) 2014-03-31 2018-02-27 Applied Materials, Inc. Generation of compact alumina passivation layers on aluminum plasma equipment components
US9885117B2 (en) 2014-03-31 2018-02-06 Applied Materials, Inc. Conditioned semiconductor system parts
US9406523B2 (en) 2014-06-19 2016-08-02 Applied Materials, Inc. Highly selective doped oxide removal method
US9378969B2 (en) 2014-06-19 2016-06-28 Applied Materials, Inc. Low temperature gas-phase carbon removal
US9425058B2 (en) 2014-07-24 2016-08-23 Applied Materials, Inc. Simplified litho-etch-litho-etch process
US9496167B2 (en) 2014-07-31 2016-11-15 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9378978B2 (en) 2014-07-31 2016-06-28 Applied Materials, Inc. Integrated oxide recess and floating gate fin trimming
US9773695B2 (en) 2014-07-31 2017-09-26 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9659753B2 (en) 2014-08-07 2017-05-23 Applied Materials, Inc. Grooved insulator to reduce leakage current
US9553102B2 (en) 2014-08-19 2017-01-24 Applied Materials, Inc. Tungsten separation
US9355856B2 (en) 2014-09-12 2016-05-31 Applied Materials, Inc. V trench dry etch
US9355862B2 (en) 2014-09-24 2016-05-31 Applied Materials, Inc. Fluorine-based hardmask removal
US9368364B2 (en) * 2014-09-24 2016-06-14 Applied Materials, Inc. Silicon etch process with tunable selectivity to SiO2 and other materials
US9478434B2 (en) 2014-09-24 2016-10-25 Applied Materials, Inc. Chlorine-based hardmask removal
US9613822B2 (en) 2014-09-25 2017-04-04 Applied Materials, Inc. Oxide etch selectivity enhancement
US9837284B2 (en) 2014-09-25 2017-12-05 Applied Materials, Inc. Oxide etch selectivity enhancement
US9478432B2 (en) 2014-09-25 2016-10-25 Applied Materials, Inc. Silicon oxide selective removal
US9966240B2 (en) 2014-10-14 2018-05-08 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US9502258B2 (en) 2014-12-23 2016-11-22 Applied Materials, Inc. Anisotropic gap etch
US9343272B1 (en) 2015-01-08 2016-05-17 Applied Materials, Inc. Self-aligned process
US9373522B1 (en) 2015-01-22 2016-06-21 Applied Mateials, Inc. Titanium nitride removal
US9449846B2 (en) 2015-01-28 2016-09-20 Applied Materials, Inc. Vertical gate separation
US9728437B2 (en) 2015-02-03 2017-08-08 Applied Materials, Inc. High temperature chuck for plasma processing systems
US9881805B2 (en) 2015-03-02 2018-01-30 Applied Materials, Inc. Silicon selective removal
US9691645B2 (en) 2015-08-06 2017-06-27 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US9741593B2 (en) 2015-08-06 2017-08-22 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US9349605B1 (en) 2015-08-07 2016-05-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US9865484B1 (en) 2016-06-29 2018-01-09 Applied Materials, Inc. Selective etch using material modification and RF pulsing
US9721789B1 (en) 2016-10-04 2017-08-01 Applied Materials, Inc. Saving ion-damaged spacers
US9934942B1 (en) 2016-10-04 2018-04-03 Applied Materials, Inc. Chamber with flow-through source
US9947549B1 (en) 2016-10-10 2018-04-17 Applied Materials, Inc. Cobalt-containing material removal
US9768034B1 (en) 2016-11-11 2017-09-19 Applied Materials, Inc. Removal methods for high aspect ratio structures

Also Published As

Publication number Publication date Type
JP2008506255A (en) 2008-02-28 application
US7097779B2 (en) 2006-08-29 grant
CN1973358B (en) 2010-05-12 grant
KR20070032938A (en) 2007-03-23 application
WO2006014193A1 (en) 2006-02-09 application
CN1973358A (en) 2007-05-30 application
JP4842263B2 (en) 2011-12-21 grant
US20060006136A1 (en) 2006-01-12 application

Similar Documents

Publication Publication Date Title
US7520957B2 (en) Lid assembly for front end of line fabrication
US20030045098A1 (en) Method and apparatus for processing a wafer
US20030091938A1 (en) Method of depositing an amorphous carbon layer
US5681780A (en) Manufacture of semiconductor device with ashing and etching
US6465366B1 (en) Dual frequency plasma enhanced chemical vapor deposition of silicon carbide layers
US6764958B1 (en) Method of depositing dielectric films
US20110151142A1 (en) Pecvd multi-step processing with continuous plasma
US6991739B2 (en) Method of photoresist removal in the presence of a dielectric layer having a low k-value
US20040053484A1 (en) Method of fabricating a gate structure of a field effect transistor using a hard mask
US20060032833A1 (en) Encapsulation of post-etch halogenic residue
US20060130971A1 (en) Apparatus for generating plasma by RF power
US6767834B2 (en) Method of manufacturing a contact of a semiconductor device using cluster apparatus having at least one plasma pretreatment module
US20040209468A1 (en) Method for fabricating a gate structure of a field effect transistor
US20050009358A1 (en) Method of fabricating a gate structure of a field effect transistor having a metal-containing gate electrode
US20080257494A1 (en) Substrate processing apparatus
US6767824B2 (en) Method of fabricating a gate structure of a field effect transistor using an alpha-carbon mask
US20050085090A1 (en) Method for controlling accuracy and repeatability of an etch process
US8980758B1 (en) Methods for etching an etching stop layer utilizing a cyclical etching process
US20090269934A1 (en) Plasma treatment method for preventing defects in doped silicon oxide surfaces during exposure to atmosphere
US20090277874A1 (en) Method and apparatus for removing polymer from a substrate
US20070042603A1 (en) Method for etching having a controlled distribution of process results
US20100130015A1 (en) Patterning method
US20130337655A1 (en) Abatement and strip process chamber in a dual loadlock configuration
US20060228889A1 (en) Methods of removing resist from substrates in resist stripping chambers
US20040185674A1 (en) Nitrogen-free hard mask over low K dielectric

Legal Events

Date Code Title Description
AS Assignment

Owner name: TOKYO ELECTRON LIMITED, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MOSDEN, AELAN;YAMASHITA, ASAO;REEL/FRAME:018063/0909

Effective date: 20040624