Connect public, paid and private patent data with Google Patents Public Datasets

Pixel with spatially varying metal route positions

Download PDF

Info

Publication number
US20060249653A1
US20060249653A1 US11123782 US12378205A US2006249653A1 US 20060249653 A1 US20060249653 A1 US 20060249653A1 US 11123782 US11123782 US 11123782 US 12378205 A US12378205 A US 12378205A US 2006249653 A1 US2006249653 A1 US 2006249653A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
pixel
metal
distance
optical
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US11123782
Other versions
US7214920B2 (en )
Inventor
William Gazeley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Aptina Imaging Corp
Original Assignee
Avago Technologies Sensor IP (Singapore) Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength, or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14603Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength, or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14643Photodiode arrays; MOS imagers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength, or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14636Interconnect structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength, or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14683Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689MOS based technologies

Abstract

An image sensor including an array of pixels having an optical center, the array including a first pixel substantially at a first distance from the optical center in a first direction and a second pixel substantially at the first distance from the optical center in a second direction which is opposite the first direction. The first pixel includes a first metal segment and a first interlayer connect element. The first metal segment is positioned in a second metal layer at a shift distance toward the optical center from a first position. The first interlayer connect element is coupled between the first metal segment and a first metal layer and is positioned at the shift distance toward the optical center from a second position, wherein the second position is coincident with the first position. The second pixel includes a second metal segment, a second interlayer connect element, and a span element. The second metal segment is positioned in the second metal layer at the shift distance toward the optical center from a third position. The second interlayer connect element is coupled between the first and second metal layers, the interlayer connect element positioned at a fourth position which is coincident with the third position. The span element coupled to and extending from the second metal segment in generally the second direction and coupled to the second interlayer connect element.

Description

    BACKGROUND
  • [0001]
    Solid-state image sensors (also known as “solid-state imagers,” “image sensors,” and “imagers”) have broad applications in many areas and in a number of fields. Solid-state image sensors convert a received image into a signal indicative of the received image. Examples of solid-state image sensors include charge coupled devices (“CCD”), photodiode arrays, and CMOS imaging devices (also known as “CMOS image sensors” or “CMOS imaging arrays”).
  • [0002]
    Solid-state image sensors are fabricated from semiconductor materials, such as silicon or gallium arsenide, and comprise imaging arrays of light detecting, i.e., photosensitive, elements (also known as “photodetectors” or “photoreceptors”) interconnected to generate analog signals representative of an image illuminating the device. A typical imaging array comprises a number of photodetectors arranged into rows and columns, each photodetector generating photo-charges. The photo-charges are the result of photons striking the surface of the semiconductor material of the photodetector, and generating free charge carriers (electron-hole pairs) in an amount linearly proportional to the incident photon radiation. The photo-charges from each pixel are converted to a “charge signal” which is an electrical potential representative of the energy level reflected from a respective portion of the object and received by the solid-state image sensor. The resulting signal or potential is read and processed by video/image processing circuitry to create a signal representation of the image.
  • [0003]
    In recent years, CMOS image sensors have become a practical implementation option for imagers and provide cost and power advantages over other technologies such as CCD or CID. A conventional CMOS image sensor is typically structured as an imaging array of pixels, each pixel including a photodetector and a transistor region, and as discussed above, each pixel converts the incoming light into an electronic signal.
  • [0004]
    One type of active pixel design for a CMOS image sensor, often referred to as a pinned-diode pixel, includes four wires (or “metal interconnect lines” or “metal interconnect segments”), a photodetector (i.e. a photodiode), and three transistors, namely a reset transistor, a source-follower transistor, and an access transistor (or “transfer gate”). The photodiode and transistors are located in active areas of a silicon substrate that forms a floor to the pixel. Two of the metal interconnect segments are disposed in a first metal layer (generally referred to as metal-1), which is positioned above a poly-silicon layer formed on the silicon substrate, and provide reset and access (“transfer”) signals to the pixel.
  • [0005]
    The two remaining metal interconnect segments disposed perpendicularly to the first two metal interconnect segments in a second metal layer (generally referred to as metal-2), which is positioned above a dielectric insulation layer over the first metal layer, and provide power and column selection to the pixel. Conductive contacts couple the metal-1 layer to the poly-silicon layer and to the active areas of the silicon substrate, and conductive vias couple the metal-2 layer to the metal-1 layer. The contacts and via enable the metal interconnect segments to be in electrical communication with one another and with the poly-silicon layer and silicon substrate of the pixel. In a typical three-transistor active pixel design for a CMOS image sensor, each pixel includes four wires (or “metal interconnect lines” or “metal interconnect segments”) and three transistors, namely, a reset transistor, a source-follower transistor, and a select transistor. Two metal interconnect segments are disposed horizontally to provide row selection for either resetting the pixel or reading the pixel. Two other metal interconnect segments are disposed vertically (or substantially perpendicular to the first two metal interconnect segments) to provide column selection for both reading and resetting the pixel.
  • [0006]
    In conventional CMOS image sensors, the arrangement of the pixel's structures, including the relative positioning of the photodetector, the transistor region, and the metal interconnect segments, as well other structural elements, has presented problems. A major problem which conventional CMOS image sensors exhibit is pixel light shadowing (also referred to as “geometric shadowing”). Pixel light shadowing is caused when the average ray or principal ray striking the pixel deviates significantly from normal (or perpendicular to the imaging array plane). Under these conditions, one or more of the pixel elements situated over the photodetector may block a significant amount of light from being directed at the photodetector. As a result, the brightness of the resulting image can be significantly reduced, resulting in poor image quality
  • SUMMARY
  • [0007]
    In one aspect, the present invention provides an image sensor including an array of pixels having an optical center, the array including a first pixel substantially at a first distance from the optical center in a first direction and a second pixel substantially at the first distance from the optical center in a second direction which is opposite the first direction. The first pixel includes a first metal segment and a first interlayer connect element. The first metal segment is positioned in a second metal layer at a shift distance toward the optical center from a first position. The first interlayer connect element is coupled between the first metal segment and a first metal layer and is positioned at the shift distance toward the optical center from a second position, wherein the second position is coincident with the first position. The second pixel includes a second metal segment, a second interlayer connect element, and a span element. The second metal segment is positioned in the second metal layer at the shift distance toward the optical center from a third position. The second interlayer connect element is coupled between the first and second metal layers, the interlayer connect element positioned at a fourth position which is coincident with the third position. The span element is coupled to and extends from the second metal segment in generally the second direction and is coupled to the second interlayer connect element.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0008]
    Embodiments of the invention are better understood with reference to the following drawings. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
  • [0009]
    FIG. 1 is a block diagram illustrating generally a CMOS imaging array.
  • [0010]
    FIG. 2 is a block and schematic diagram illustrating a pixel of the CMOS imaging array of FIG. 1.
  • [0011]
    FIG. 3 is an example layout of the pixel of FIG. 2 according to the present invention.
  • [0012]
    FIG. 4 is a cross-sectional view illustrating portions of the pixel of FIG. 3.
  • [0013]
    FIG. 5 is an example layout of the pixel of FIG. 2 having shifted metal route positions according to the present invention.
  • [0014]
    FIG. 6 is a cross-sectional view illustrating portions of the pixel of FIG. 5.
  • [0015]
    FIG. 7 is an example layout of the pixel of FIG. 2 having shifted metal route positions according to the present invention.
  • [0016]
    FIG. 8 is a cross-sectional view illustrating portions of the pixel of FIG. 7.
  • [0017]
    FIG. 9 is a flow diagram illustrating generally one embodiment of a process for shifting metal route positions according to the present invention.
  • DETAILED DESCRIPTION
  • [0018]
    In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following Detailed Description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
  • [0019]
    FIG. 1 is a block diagram illustrating generally a CMOS imaging array 30 including a plurality of pixels 32 arranged in a plurality of rows and columns, with each pixel 32 generating photo-charges from received light representative of an image. The photo-charges generated by pixels 32 are the result of photons striking the surface of a semiconductor material, or photodetector (e.g. photodiode and photogate), and generating free charge carriers (i.e. electron hole pairs) in an amount linearly proportional to the incident photon radiation. As will be described in greater detail below, each pixel 32 includes metallic interconnect segments and vias that can be shifted based on their position relative to an optical center of array 30, in accordance with the present invention, so as to increase the photon radiation incident upon the semiconductor material.
  • [0020]
    FIG. 2 is a schematic diagram illustrating one example configuration of a pixel 32, commonly referred to as a buried-gated photodiode type pixel. Pixel 32 includes a photodetector 40, an access transistor 42 (often referred to as a “transfer gate”), a reset transistor 44, and a source follower transistor 46. The gate of transfer gate 40 is coupled to an access or transfer (TX) line 48, the source is coupled to photodiode (PD) 42, and the drain is coupled to a floating diffusion region (FD) 50. The gate of reset transistor 44 is coupled to a reset (RST) line 52, the source is coupled to FD 50, and the drain is coupled to a voltage line (PVDD) 54. The gate of source-follower transistor 46 is coupled to the source of reset transistor 44, the source is coupled to a column or bit (BIT) line 56, and the drain is coupled to PVDD 54. Although only one pixel 32 is illustrated, TX, RST lines 48, 52 extend across all pixels of a given row of array 30, and PVDD and BIT lines 54, 56 extend across all pixels of a given column of array 30.
  • [0021]
    Pixel 32 operates in two modes, integration and readout, based on signals received via TX 48 and RST lines 48, 52. Initially, pixel 32 is in a reset state with transfer gate 48 and reset transistor 52 turned on. To begin integrating, reset transistor 52 and transfer gate 48 are turned off. During the integration period, PD 42 accumulates a photo-generated charge that is proportional to the photon radiation that propagates through portions of pixel 32 and is incident upon photodetector 42.
  • [0022]
    After pixel 32 has integrated for a desired time period, reset transistor 44 is turned on and the reset level of FD 50 is sampled at BIT line 56 via source-follower transistor 46. Subsequently, transfer gate 40 is turned on and the accumulated charge is transferred from PD 42 to FD 50. The charge transfer causes the potential of FD 50 to deviate from the reset value, which is approximately equal to the level of PVDD line 54 minus a threshold voltage, to a signal value which is depends on the accumulated charge. The signal value is then sampled, or read, at BIT line 56 via source-follower transistor 46. The difference between the sampled signal value and the sampled reset value constitutes an image signal for pixel 32 and is proportional to the intensity of the light incident upon PD 42.
  • [0023]
    Following readout of the row of pixels in which pixel 32 is located, FD 50 is returned to ground to turn off source-follower transistor 46. Because all source-follower transistors of the pixels of each column constitute a wired-or circuit, returning FD 50 to ground ensures that only one source-follower transistor at a time will be turned on in a given column. FD 50 is returned to ground by temporarily driving PVDD 54 to a low voltage level (typically ground) and then pulsing RST 52 high which, in-turn, sets the floating diffusion area of each pixel in a given row (such as FD 50) to the voltage level of PVDD 54 (which as described above, has previously been driven to ground).
  • [0024]
    FIG. 3 illustrates an example layout of pixel 32 as illustrated by FIG. 2 when located in a region 60 (see FIG. 2) which is proximate to an optical center of array 30. The elements of pixel 32 are disposed in various layers which overlay a silicon substrate which forms the “floor” of pixel 32. In the illustrated example, with reference to drawing key 70, pixel 32 includes a polysilicon layer (“poly”) 72 overlaying the silicon substrate, a first metal layer (“metal-1”) 74 positioned above poly 72, and a second metal layer (metal-2) 76 positioned above poly 72. Dielectric insulation layers (not illustrated) are positioned between poly 72 and metal-1 74, and between metal-1 74 and metal-2 76. Pixel 32 includes additional material layers which, for ease of illustration, are not described or discussed herein.
  • [0025]
    PD 42, FD 50, and active areas 78 of the transistors are disposed in active regions (i.e. doped regions) of the silicon substrate. Contacts, illustrated at 80 provide conductive pathways to couple metal-1 74 to active areas 78 of the transistors, and to couple metal-1 74 to poly 72. Vias, indicated at 82, provide conductive pathways to couple metal-2 76 to metal-1 74.
  • [0026]
    TX and RST lines 48, 52 are disposed in metal-1 74 and PVVD and BIT lines 54, 56 are disposed in metal-2 76 and respectively extend horizontally and vertically (with respect to FIG. 3) across pixel 32. A segment 90 of poly 74 is positioned over PD 40 and FD 50 to form the gate of transfer gate 40. TX line 54 is coupled to segment 90 of poly 72 via a contact 92. A segment 94 of poly 72 is positioned over active area 78 to form the gate of reset transistor 44, and extends and is coupled to RST line 52 by contact 96. A segment 98 of poly 72 is positioned over active area 78 to form the gate of source-follower transistor 46. A first end of a segment 100 of metal-1 74 is coupled by a contact 102 to the source of reset transistor 44 in active area 78, and a second end is coupled by a contact 104 to segment 98 of poly 72, thereby coupling the source of reset transistor 44 to the gate of source-follower transistor 46. The source of reset transistor 44 is coupled to FD 50 via active area 78.
  • [0027]
    PVDD line 54 is coupled by a via 106 to a first end of a segment 108 of metal-1 74 which, in-turn, is coupled at a second end to the drains of reset and source-follower transistors 44, 46 by a contact 110. BIT line 56 is coupled by a via 112 to a first end of a segment 114 of metal-1 74 which, in-turn, is coupled at a second end to the source of source-follower transistor 46 by a contact 116. The photodetector of an adjacent pixel is illustrated at 120.
  • [0028]
    It is noted that FIG. 3 is included for illustrative purposes only and is not drawn to scale. As such, element sizes, spacing between elements, and relative position of elements with respect to one another have been exaggerated for ease of illustration and are not intended to exactly represent actual pixel structures.
  • [0029]
    It should also be noted that vias (e.g. vias 106 and 112) and contacts (e.g. 96, 102, 104, etc.) can be generally described as interlayer connect elements. As the name suggests, such interlayer connect elements function as “conduits” to electrically couple non-contacting layers to one another. The terms “via” and “connect” are used only for illustrative purposes to differentiate between connections between the metal-1 and metal-2 layers and between the metal-1 and the silicon substrate and/or the polysilicon layer.
  • [0030]
    FIG. 4 is a cross-sectional view of pixel 32 as illustrated by FIG. 3. A surface plane of array 30 and a surface plane of the silicon substrate in which PD 42 and the active areas 78 of the transistors positioned are respectively illustrated at 126 and 128. An isolation area 129 separates pixel 32 from the adjacent pixel 122. For ease of illustration, not all components of pixel 32 from FIG. 3 are illustrated, nor are other pixel components such as, for example, micro-lenses, color filters, and various transparent dielectric layers. Again, as with FIG. 3, FIG. 4 is intended for illustrative purposes only.
  • [0031]
    As described above, pixel 32 of FIG. 3 and FIG. 4 is located in region 60 (see FIG. 1) proximate to an optical center 130 of array 30. Optical axis 130 corresponds to a reference line perpendicular to the surface plane 126 of and intersecting a center of array 30. As illustrated, PVDD line 54, via 106, and via 112 are respectively positioned at distances 140, 142 and 144 from an edge 138 of pixel 32, which is proximate to PD 42. BIT line 56 is positioned at a distance 148 from PVDD line 54.
  • [0032]
    Generally speaking, pixel 32 of FIG. 4 is configured in a conventional fashion wherein PVDD and BIT lines 54, 56 of metal-2 76, segments 108, 114 of metal-1 74, and vias 106, 112 are positioned over active transistor areas 78 and isolation area 129 so as to keep the area between PD 42 and surface plane 126 free of metal interconnects so that light to PD 42 is not “blocked” by such obstacles. In most conventional imaging arrays, the conventional pixel configuration of pixel 32 as illustrated by FIG. 3 and FIG. 4 is identical for all pixels of the array. In other words, each pixel of array 30 is identically arranged with a fixed pitch. Thus, distances 140, 142, and 144 from edge 138 to PVDD line 54, via 106, via 112, and between PVDD and BIT lines 54, 56 are the same for each pixel of the array.
  • [0033]
    When pixel 32 is proximate to optical axis 130, such as in region 60, a principal or average ray angle of a bundle of incident light rays 160 incident upon surface plane 126 of array 30 is substantially normal (i.e. perpendicular to) to surface plane 126. As such, the conventional configuration of pixel 34 as illustrated by FIG. 3 and FIG. 4 is effective at allowing incident light rays 160 to reach PD 42.
  • [0034]
    However, the principal ray angle of a bundle of incident rays incident upon surface plane 126 deviates from normal with the distance from optical axis 130. In general, the deviation of the principal ray angle from normal increases in a non-linear fashion with distance from optical axis 130, with a maximum deviation occurring proximate to the edges of array 30 (i.e. the greatest distance from optical axis 130). The deviation results primarily from what is commonly referred to as the “non-telecentricity” of the lens utilized by an imaging device (not shown) employing imaging array 30. This deviation results in the conventional pixel structure (primarily the metal-2 76 elements) of pixel 32 of FIG. 3 and FIG. 4 causing shadowing (or “geometric shadowing”) of the associated photodetector PD 42 or the photodetector of an adjacent pixel, with the shadowing effects worsening as the pixels become more removed from optical axis 130. The shadowing reduces the light intensity received by the pixels, especially those pixels proximate to the edges of imaging array 30, which already see a reduction in light intensity relative to those pixels proximate the optical axis 130 from what is commonly referred to as vignetting (caused by 1/Cosine characteristics of the lens).
  • [0035]
    For example, if pixel 32 having the conventional configuration of FIG. 4 is positioned at region 62 of array 30 in lieu of region 60 (see FIG. 1), the principal ray angle of incident light upon surface plane 126 would deviate significantly from normal as illustrated by the bundle of incident rays at 162. As a result, when positioned at region 62, BIT line 56 of metal-2 76 blocks incident light to photodetector 120 of adjacent pixel 122, consequently reducing the brightness of an image produced by adjacent pixel 122.
  • [0036]
    Similarly, if pixel 32 having the conventional configuration of FIG. 4 is positioned at region 64 of array 30, opposite optical axis 130 from region 62 (see FIG. 1), the principle ray angle of incident light upon surface plane would deviate significantly from normal (by a same magnitude but opposite angle from the deviation at region 62) as illustrated by the bundle of incident rays 164. As result, when positioned at region 64, PVDD line 54 of metal-2 76 blocks incident light to PD 42, consequently reducing the brightness of an image produced by pixel 32.
  • [0037]
    In accordance with the present invention, and as illustrated by FIG. 5 through FIG. 8 below, the metal-2 elements and corresponding vias of pixels 32 (i.e. PVDD and BIT lines 54, 56 and vias 110, 112 in the illustrated examples) are shifted toward optical axis 130 based on their distance from and position to (i.e. to the right or left relative to FIG. 1) optical axis 130. Shifting the metal-2 elements and their corresponding vias toward the optical center of imaging array 30 in accordance with the present invention reduces light shadowing associated with conventional pixel structures.
  • [0038]
    Metal-1 74 elements (e.g. segment 100) are positioned in closer proximity to surface 128 of the silicon substrate and further away from imaging plane 126 than metal-2 76 elements. As such, metal-1 74 elements generally have little impact on geometric shadowing effects. Geometric shadowing is generally caused by pixel components in layers above metal-1 74 and closer to image plane 126, such as the elements of metal-2 76 as described herein. However, in some pixel architectures, metal-1 74 elements may contribute to geometric shadowing effects. As such, although described herein with respect to metal-2 76 elements and associated interlayer connect elements, the teachings of the present invention (as will be described in greater detail below) can also be applied to metal-1 74 elements and associated interlayer connect elements. The teaching of the present invention can also be applied to elements in metal layers beyond metal-1 and metal-2 when a pixel architecture employs such additional metal layers.
  • [0039]
    FIGS. 5 and 6 illustrate an example layout of pixel 32 in accordance with the present invention when located in region 62 of imaging array 30. As illustrated, PVDD and BIT lines 54, 56 of metal-2 76 and the corresponding vias 110 and 112 are shifted toward edge 38 by a shift distance 200 relative to their corresponding positions when pixel 32 is located at position 60 (as illustrated by FIGS. 3 and 4). The magnitude of shift distance 200 is based on the distance of pixel 32 from the optical center 130 of imaging array 30. The direction of shift distance 200 depends on the relative position of pixel 32 to optical center 130. Since edge 138 of pixel 32 of FIGS. 5 and 6 faces toward of optical center 130, the direction of shift distance 200 is toward edge 138 (i.e. to the “left” in FIGS. 1, 5, and 6).
  • [0040]
    With further reference to FIG. 4, distances 240, 242, and 242 between PVDD line 54, and vias 106, 112 respectively to edge 138 are less than distances 140, 142, and 144 by an amount equal to shift distance 200. Since BIT line 56 is also shifted toward edge 138 by shift distance 200, the distance 256 between PVDD and BIT lines 54, 56 is equal to distance 156. As illustrated by FIGS. 5 and 6, the positions and dimensions of metal-1 74 segments 108 and 114 have been adjusted accordingly.
  • [0041]
    As illustrated by FIG. 6, with PVDD and BIT lines 54, 56 of metal-2 76 and corresponding vias 106, 112 shifted toward edge 138 by shift distance 200, the bundle of incident light rays 162 is no longer blocked and has an unobstructed path to PD 120 of adjacent pixel 122. Additionally, even though PVDD line 54 of metal-2 76 is positioned between PD 42 and surface plane 126, a bundle of light rays (not illustrated) incident upon pixel 32 has a principal ray angle similar to that of the bundle of lights rays 162 and, thus, will not be blocked by PVDD line 54.
  • [0042]
    FIGS. 6 and 7 illustrate an example layout of pixel 32 in accordance with the present invention when located at region 64 of imaging array 30. As illustrated, PVDD and BIT lines 54 and 56 of metal-2 76 are shifted away from edge 138 by a shift distance 300 relative to their corresponding positions when pixel 32 is located at region 60 (as illustrated by FIGS. 3 and 4). As when pixel 32 is located at region 62 (as illustrated by FIGS. 5 and 6), the magnitude and direction of shift distance 300 are based respectively on the distance pixel 32 is from and the relative position of pixel 32 to optical center 130 of imaging array 30. Since edge 138 of pixel 32 of FIGS. 7 and 8 faces away from optical center 130, the direction of shift distance 300 is away from edge 138 (i.e. to the “right” in FIGS. 1, 7, and 8). In the illustrated example, region 64 is at substantially an equal distance from optical center 130 of array 30 ad region 62.
  • [0043]
    However, unlike when pixel 32 is located at region 62 (as illustrated by FIGS. 5 and 6), only via 112 associated with BIT line 56 is shifted toward optical center 130 (i.e. to the right) by shift distance 300. Because the pixels are so densely packed within the silicon substrate, the locations of the photodetectors and active transistor areas (e.g. PD 42 and active areas 78), the transistors (e.g. reset transistor 44 and source-follower transistor 46) and associated contacts (e.g. contacts 102, 104, 110, and 116) are at substantially fixed positions. As such, metal-1 72 segment 100 coupling the source of reset transistor 44 to the gate of source-follower transistor 46 is at a substantially fixed location.
  • [0044]
    Since via 106 couples PVDD line 54 to the drains of reset and source-follower transistors 44, 46 by metal-1 72 segment 108, via 106 cannot be shifted along with PVDD line 54 by shift distance 300 because such a shift would require metal-1 72 segment 108 to be extended across metal-1 72 segment 100. As such, via 106 is at a substantially fixed position. Therefore, in order to maintain electrical connection between the shifted PVDD 54 and the drains of reset and source-follower transistors 44, 46, a metal-2 76 span element 360 is added to pixel 32 to couple PVDD 54 to via 112.
  • [0045]
    In one embodiment, span element 360 is contiguous with and extends from PVDD 54 to via 106 by a distance at least equal to shift distance 300. In one embodiment, span element 360 is contiguous with and extends from PVDD 54 to via 106 by a distance substantially equal to shift distance 300. Although illustrated as extending from PVDD 54 in a linear fashion, in other embodiments, span element may include bends and angles to avoid conflicts with other pixel elements (not illustrated) which may be positioned between PVDD 54 and via 106.
  • [0046]
    With further reference to FIG. 4, distances 340 and 344 between PVDD line and 54 and via 112 respectively to edge 138 are greater than distances 140 and 144 by an amount equal to shift distance 300. Since BIT line 56 is also shifted away from edge 138 by shift distance 300, the distance 356 between PVDD and BIT lines 54, 56 is equal to distance 156. As illustrated by FIGS. 7 and 8, metal-1 72 segment 114 has been extended by shift distance 300.
  • [0047]
    As illustrated by FIG. 8, with PVDD and BIT lines 54, 56 of metal-2 76 shifted away from edge 138 by shift distance 300, the bundle of incident light rays 164 is no longer blocked and has an unobstructed path to PD 42. Additionally, even though BIT line 56 of metal-2 76 is positioned between surface plane 126 and PD 120 of adjacent pixel 122, a bundle of light rays (not illustrated) incident upon pixel 32 has a principal ray angle similar to that of the bundle of light rays 164 and, thus, will not be blocked by BIT line 56.
  • [0048]
    As described above, the principal ray angle of light incident upon imaging array 30 varies non-linearly with distance from optical axis 130 across imaging array 30, with the greatest deviations occurring along the edges of imaging array 30. As such, the magnitude in the shift distance of metal-2 76 elements for each pixel 32 of array 30 is dependent on the distance of the pixel from optical axis 130. The magnitude of the shift distance is also dependent on the distance of metal-2 76 from surface plane 126. Thus, in general, the shift distances are greater in magnitude for pixels 32 situated further away from optical axis 130 than for pixels situated closer to optical axis 130. Also, due to the non-linear nature of the deviations from normal of the principal ray angle across array 30, the magnitudes of shift distances also increases non-linearly as the pixels become further removed from optical axis 130.
  • [0049]
    FIG. 9 is a flow diagram illustrating one example embodiment of a process 400 for determining shift distances for each pixel of an array of pixels to be fabricated, such as pixels 32 of array 30. Process 400 begins at 402. At 404, parameters/data associated with the imaging array to be fabricated are determined and include information such as the number “m” of columns (C) and the number “n” of rows (R) of the imaging array, a “conventional” or base configuration of a pixel of the array (e.g. pixel 32 of FIG. 3 and FIG. 4, and including dimensions describing the pixel structure), and data related to a lens configuration to be utilized with the array (including non-linear characteristics of the principal ray angles associated with the lens).
  • [0050]
    At 406, the values for column counter (C) and row counter (R) are each set to a value of “1”. At 408, based on the dimensions of the array entered at 404, an optical center of the array is determined. Based on the value of C and R, the distance of the present pixel(R, C) from the optical center is determined.
  • [0051]
    At 410, based on the distance from optical center as determined at 408 and the non-linear characteristics of the principal ray angle and dimensions of the base pixel structure from 404, a shift distance (SD) is determined for the metal-2 elements of the present pixel (R, C)
  • [0052]
    At 410, process 400 queries whether the SD is greater than or equal to zero. If the answer to the query is “no”, process 400 proceeds to 414. At 414 (with additional reference to FIGS. 1, 5, and 6), since SD is less than zero, the present pixel (R, C) is located to the “right” of the optical center and the metal-2 segments are being shifted to the “left”. As such, there are no fixed transistors or connecting elements (e.g. segment 100 of FIG. 3) preventing movement of vias associated with metal-2 segments, and the vias will be shifted by the same SD as the corresponding metal-2 segments. Process 400 then proceeds to 416.
  • [0053]
    If the answer to the query at 412 is “yes”, process 400 proceeds to 418. At 418 (with additional reference to FIGS. 1, 5, and 6), since SD is greater than zero, the present pixel (R, C) is located to the “left” of the optical center and the metal-2 segments are being shifted to the “right”. As such, there are fixed transistors and/or connecting elements (e.g. segment 100 of FIG. 7) which prevent movement of vias associated with metal-2 segments. As such, vias of present pixel (R, C) which are not obstructed will be shifted by the same SD as the corresponding metal-2 segments, and vias whose movement is obstructed will remain at their “base” position.
  • [0054]
    Process 400 then proceeds to 420, where span elements are added to the pixel structure of the present pixel (R, C) to couple the fixed vias to their corresponding shifted metal-2 segments. In one embodiment, a length of the span elements is substantially equal to SD of the present pixel (R, C). Process 400 then proceeds to 416.
  • [0055]
    At 416, process 400 queries whether row counter “R” is equal to the number “n” of rows in the array to be fabricated. If the answer to the query is “no”, shift distances have not been determined for all pixels of the current row “R”, and process 400 proceeds to 422. At 422, row counter “R” is incremented by a value of “1” and process 400 returns to 408 where the above described process is repeated for the next pixel of the present column “C.”
  • [0056]
    If the answer to the query at 416 is “yes”, shift distances have been determined for all pixels of the current column “C”, and process 400 proceeds to 424. At 424, process 400 queries whether column counter “C” is equal to the number “m” of columns in the array to be fabricated. If the answer to the query is “no”, shift distances have not been determined for all columns of pixels of the array to be fabricated, and process 400 proceeds to 426. At 426, column counter “C” is incremented by a value of “1” and process 400 returns to 408 to determine shift distances for all pixels of the next column of pixels. If the answer to the query at 424 is “yes”, shift distances have been determined for all pixels of the array to be fabricated and process 400 is complete, as indicated at 428.
  • [0057]
    The above described process can be performed using a computer program on a computer system. For example, the characteristics of a bundle of light rays (e.g. the principal ray angle) incident upon each pixel 32 of array 30 can be determined by modeling the associated lens system. The placement of metal-2 segments, the corresponding vias, and required span elements can then be determined algorithmically based on the characteristics of the corresponding bundle of light rays so as to optimize a pixel operating parameter (e.g. photo radiation incident upon the photodetector). While original software may be developed, one example of a commercially available product that can be employed to perform the above described process is SKILL SCRIPT® in CADENCE IC Design Tools®.
  • [0058]
    In summary, by shifting the metal interconnect segments and corresponding vias in accordance with the present invention, the present invention provides pixel structures that significantly reduce photodetector shadowing, thereby increasing the brightness of images produced by the pixel. Additionally, by determining and providing span elements in accordance with the present invention, metal interconnect segments associated with fixed circuit elements, such as vias, are shifted while maintaining in required electrical communication with pixel elements.
  • [0059]
    Additionally, although described herein primarily with regard to a CMOS buried-gated photodiode type pixel employing three transistors and having metal interconnect segments disposed in two metal layers, the teachings of the present invention can be adapted to apply to other types of CMOS pixel architectures employing varying numbers of transistors and interconnects and more than two metal layers, and to other types of pixels (e.g. CCD type pixels).
  • [0060]
    Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.

Claims (20)

1. An image sensor including an array of pixels having an optical center, the array comprising:
a first pixel substantially at a first distance from the optical center in a first direction including:
a first metal segment positioned in a second metal layer at a shift distance toward the optical center from a first position; and
a first interlayer connect element coupled between the first metal segment and a first metal layer, the interlayer connect element positioned at the shift distance toward the optical center from a second position, wherein the second position is coincident with the first position; and
a second pixel substantially at the first distance from the optical center in a second direction which is opposite the first direction including:
a second metal segment positioned in the second metal layer at the shift distance toward the optical center from a third position;
a second interlayer connect element coupled between the first and second metal layers, the interlayer connect element positioned at a fourth position which is coincident with the third position; and
a span element coupled to and extending from the second metal segment in generally the second direction and coupled to the second interlayer connect element.
2. The image sensor of claim 1, wherein a magnitude of the shift distance increases non-linearly across the image sensor with distance from the optical center.
3. The image sensor of claim 1, where a direction of the shift distance on an orientation the pixel relative to the optical center.
4. The image sensor of claim 1, wherein the shift distance is based on a principal ray angle of light incident upon the first and second pixels.
5. The image sensor of claim 1, wherein the span element is positioned in the second metal layer.
6. The image sensor of claim 1, wherein the span element extends in generally the second direction by at least the shift distance.
7. The image sensor of claim 1, wherein the span element is contiguous with and extends from the second metal segment.
8. The image sensor of claim 1, wherein the first and second metal segment each comprise a voltage bus.
9. The image sensor of claim 1, wherein the first and second metal segments comprise signal buses extending across the array.
10. The image sensor of claim 1, wherein the image sensor comprises a complimentary metal-oxide semiconductor imaging sensor.
11. The image sensor of claim 1, wherein each of the pixels of the array comprises a buried-gate photodiode type pixel.
12. The image sensor of claim 1, wherein the first metal layer is positioned between the second metal layer and a silicon substrate.
13. A method of configuring an image sensor including an array of pixels having an optical center and having a first pixel substantially at a first distance from the optical center and in a first direction, and second pixel substantially at the first distance from the optical center and in a second direction which is opposite the first direction, the method comprising:
positioning a first metal segment of the first pixel in a second metal layer and at a shift distance toward the optical center from the first position;
positioning a first interlayer connect element, which is coupled between the first metal segment and a first metal layer, at the shift distance toward the optical center from a second position, wherein the second position is substantially coincident with the first position;
positioning a second metal segment of the second pixel in the second metal layer and at the shift distance toward the optical center from a third position;
positioning a second interlayer connect element, which is coupled between the first and second metal layers, at a fourth position which is substantially coincident with the third position; and
positioning a span element in generally the second direction from the second metal segment to the second interlayer connect element to couple the second metal segment to the second interlayer connect element.
14. The method of claim 13, wherein positioning the span element includes providing an extending the span element in the second metal layer.
15. The method of claim 13, wherein positioning the span element includes extending the span element by at least the shift distance.
16. The method of claim 13, wherein the first, second, third, and fourth positions are positions of a base pixel configuration.
17. A method of configuring an image sensor including an array of pixels having an optical center, each pixel of the array including a metal segment disposed in a second metal layer and an interlayer connect element coupled between the metal segment and a first metal layer, the method comprising:
modeling a base pixel configuration for each pixel of the array, the base pixel configuration including:
the metal segment at a first position in the second metal layer; and
the first interlayer connect element at a second position which is coincident with the first position; and
for each pixel of the array:
determining a shift distance for the pixel based on a distance of the pixel from the optical center;
determining a direction of the pixel from the optical center;
shifting the metal segment from the first position toward the optical center by the shift distance;
shifting the interlayer connect element from the second position toward the optical center by the shift distance if the pixel is in a first direction from the optical center; and
maintaining the via at the second position and providing a span element to couple the metal segment at the shifted location to the interlayer connect element if the pixel is in a second direction from the optical center.
18. The method of claim 17, wherein determining the shift distance includes determining an angle of incidence of a principal ray angle of a bundle of light rays incident upon the pixel.
19. The method of claim 17, wherein providing the span element includes coupling the span element and extending the span element by at least the shift distance to the interlayer connect element.
20. The method of claim 17, wherein determining a direction of the pixel includes determining an orientation of the pixel relative to the optical center.
US11123782 2005-05-06 2005-05-06 Pixel with spatially varying metal route positions Active 2025-10-25 US7214920B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11123782 US7214920B2 (en) 2005-05-06 2005-05-06 Pixel with spatially varying metal route positions

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US11123782 US7214920B2 (en) 2005-05-06 2005-05-06 Pixel with spatially varying metal route positions
US11256743 US7432491B2 (en) 2005-05-06 2005-10-24 Pixel with spatially varying sensor positions
GB0609029A GB2425887B (en) 2005-05-06 2006-05-05 Image sensor and method of configuring an image sensor
JP2006129206A JP2006313915A (en) 2005-05-06 2006-05-08 Pixel comprising metal path arrangement with spatial change
US11678986 US7408140B2 (en) 2005-05-06 2007-05-14 Pixel with spatially varying metal route positions
US12202666 US7728271B2 (en) 2005-05-06 2008-09-02 Pixel with spatially varying sensor positions

Publications (2)

Publication Number Publication Date
US20060249653A1 true true US20060249653A1 (en) 2006-11-09
US7214920B2 US7214920B2 (en) 2007-05-08

Family

ID=36604098

Family Applications (2)

Application Number Title Priority Date Filing Date
US11123782 Active 2025-10-25 US7214920B2 (en) 2005-05-06 2005-05-06 Pixel with spatially varying metal route positions
US11678986 Active US7408140B2 (en) 2005-05-06 2007-05-14 Pixel with spatially varying metal route positions

Family Applications After (1)

Application Number Title Priority Date Filing Date
US11678986 Active US7408140B2 (en) 2005-05-06 2007-05-14 Pixel with spatially varying metal route positions

Country Status (3)

Country Link
US (2) US7214920B2 (en)
JP (1) JP2006313915A (en)
GB (1) GB2425887B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070252182A1 (en) * 2006-04-27 2007-11-01 Beck Jeffery S Buried-gated photodiode device and method for configuring and operating same
US20070273779A1 (en) * 2006-05-25 2007-11-29 Sony Corporation Solid-state imaging device, method of manufacturing the same and camera module
US20150036030A1 (en) * 2013-07-30 2015-02-05 Sony Corporation Imaging element and electronic apparatus

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7432491B2 (en) 2005-05-06 2008-10-07 Micron Technology, Inc. Pixel with spatially varying sensor positions
US7466002B2 (en) * 2006-06-19 2008-12-16 Mitutoyo Corporation Incident light angle detector for light sensitive integrated circuit
JP4956084B2 (en) * 2006-08-01 2012-06-20 キヤノン株式会社 The photoelectric conversion apparatus and an imaging system using the same
US7729530B2 (en) * 2007-03-03 2010-06-01 Sergey Antonov Method and apparatus for 3-D data input to a personal computer with a multimedia oriented operating system
US20070164196A1 (en) * 2007-03-09 2007-07-19 Tay Hiok N Image sensor with pixel wiring to reflect light
JP2008282961A (en) * 2007-05-10 2008-11-20 Matsushita Electric Ind Co Ltd Solid-state imaging device
US8085391B2 (en) * 2007-08-02 2011-12-27 Aptina Imaging Corporation Integrated optical characteristic measurements in a CMOS image sensor
US8130300B2 (en) 2007-12-20 2012-03-06 Aptina Imaging Corporation Imager method and apparatus having combined select signals
JP5491077B2 (en) 2009-06-08 2014-05-14 キヤノン株式会社 The method of manufacturing a semiconductor device, and semiconductor device
US8482090B2 (en) 2010-07-15 2013-07-09 Exelis, Inc. Charged particle collector for a CMOS imager
US9229581B2 (en) 2011-05-05 2016-01-05 Maxim Integrated Products, Inc. Method for detecting gestures using a multi-segment photodiode and one or fewer illumination sources
US20140035812A1 (en) * 2011-05-05 2014-02-06 Maxim Integrated Products, Inc. Gesture sensing device

Citations (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5504355A (en) * 1991-12-10 1996-04-02 Nec Corporation Solid state image sensor device having two layer wiring structure
US5576763A (en) * 1994-11-22 1996-11-19 Lucent Technologies Inc. Single-polysilicon CMOS active pixel
US5841126A (en) * 1994-01-28 1998-11-24 California Institute Of Technology CMOS active pixel sensor type imaging system on a chip
US5920345A (en) * 1997-06-02 1999-07-06 Sarnoff Corporation CMOS image sensor with improved fill factor
US5990850A (en) * 1995-03-17 1999-11-23 Massachusetts Institute Of Technology Metallodielectric photonic crystal
US6057586A (en) * 1997-09-26 2000-05-02 Intel Corporation Method and apparatus for employing a light shield to modulate pixel color responsivity
US6194770B1 (en) * 1998-03-16 2001-02-27 Photon Vision Systems Llc Photo receptor with reduced noise
US6225670B1 (en) * 1997-06-04 2001-05-01 Imec Detector for electromagnetic radiation, pixel structure with high sensitivity using such detector and method of manufacturing such detector
US6278169B1 (en) * 1998-05-07 2001-08-21 Analog Devices, Inc. Image sensor shielding
US6288434B1 (en) * 1999-05-14 2001-09-11 Tower Semiconductor, Ltd. Photodetecting integrated circuits with low cross talk
US6352869B1 (en) * 1997-08-15 2002-03-05 Eastman Kodak Company Active pixel image sensor with shared amplifier read-out
US6369417B1 (en) * 2000-08-18 2002-04-09 Hyundai Electronics Industries Co., Ltd. CMOS image sensor and method for fabricating the same
US6376868B1 (en) * 1999-06-15 2002-04-23 Micron Technology, Inc. Multi-layered gate for a CMOS imager
US6466266B1 (en) * 1998-07-28 2002-10-15 Eastman Kodak Company Active pixel sensor with shared row timing signals
US6555842B1 (en) * 1994-01-28 2003-04-29 California Institute Of Technology Active pixel sensor with intra-pixel charge transfer
US6570617B2 (en) * 1994-01-28 2003-05-27 California Institute Of Technology CMOS active pixel sensor type imaging system on a chip
US6777662B2 (en) * 2002-07-30 2004-08-17 Freescale Semiconductor, Inc. System, circuit and method providing a dynamic range pixel cell with blooming protection
US6815787B1 (en) * 2002-01-08 2004-11-09 Taiwan Semiconductor Manufacturing Company Grid metal design for large density CMOS image sensor
US6838715B1 (en) * 2002-04-30 2005-01-04 Ess Technology, Inc. CMOS image sensor arrangement with reduced pixel light shadowing
US6930299B2 (en) * 2002-08-29 2005-08-16 Fujitsu Limited Semiconductor device for reading signal from photodiode via transistors
US20060104564A1 (en) * 2004-11-15 2006-05-18 Catrysse Peter B Integrated waveguide and method for designing integrated waveguide
US7138618B2 (en) * 2003-02-19 2006-11-21 Sony Corporation Solid-state image pickup device and image pickup camera

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7248297B2 (en) 2001-11-30 2007-07-24 The Board Of Trustees Of The Leland Stanford Junior University Integrated color pixel (ICP)
US6861686B2 (en) 2003-01-16 2005-03-01 Samsung Electronics Co., Ltd. Structure of a CMOS image sensor and method for fabricating the same

Patent Citations (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5504355A (en) * 1991-12-10 1996-04-02 Nec Corporation Solid state image sensor device having two layer wiring structure
US6744068B2 (en) * 1994-01-28 2004-06-01 California Institute Of Technology Active pixel sensor with intra-pixel charge transfer
US6555842B1 (en) * 1994-01-28 2003-04-29 California Institute Of Technology Active pixel sensor with intra-pixel charge transfer
US5841126A (en) * 1994-01-28 1998-11-24 California Institute Of Technology CMOS active pixel sensor type imaging system on a chip
US6570617B2 (en) * 1994-01-28 2003-05-27 California Institute Of Technology CMOS active pixel sensor type imaging system on a chip
US5576763A (en) * 1994-11-22 1996-11-19 Lucent Technologies Inc. Single-polysilicon CMOS active pixel
US5990850A (en) * 1995-03-17 1999-11-23 Massachusetts Institute Of Technology Metallodielectric photonic crystal
US5920345A (en) * 1997-06-02 1999-07-06 Sarnoff Corporation CMOS image sensor with improved fill factor
US6225670B1 (en) * 1997-06-04 2001-05-01 Imec Detector for electromagnetic radiation, pixel structure with high sensitivity using such detector and method of manufacturing such detector
US6352869B1 (en) * 1997-08-15 2002-03-05 Eastman Kodak Company Active pixel image sensor with shared amplifier read-out
US6235549B1 (en) * 1997-09-26 2001-05-22 Intel Corporation Method and apparatus for employing a light shield to modulate pixel color responsivity
US6057586A (en) * 1997-09-26 2000-05-02 Intel Corporation Method and apparatus for employing a light shield to modulate pixel color responsivity
US6194770B1 (en) * 1998-03-16 2001-02-27 Photon Vision Systems Llc Photo receptor with reduced noise
US6278169B1 (en) * 1998-05-07 2001-08-21 Analog Devices, Inc. Image sensor shielding
US6466266B1 (en) * 1998-07-28 2002-10-15 Eastman Kodak Company Active pixel sensor with shared row timing signals
US6288434B1 (en) * 1999-05-14 2001-09-11 Tower Semiconductor, Ltd. Photodetecting integrated circuits with low cross talk
US6376868B1 (en) * 1999-06-15 2002-04-23 Micron Technology, Inc. Multi-layered gate for a CMOS imager
US6369417B1 (en) * 2000-08-18 2002-04-09 Hyundai Electronics Industries Co., Ltd. CMOS image sensor and method for fabricating the same
US6815787B1 (en) * 2002-01-08 2004-11-09 Taiwan Semiconductor Manufacturing Company Grid metal design for large density CMOS image sensor
US6838715B1 (en) * 2002-04-30 2005-01-04 Ess Technology, Inc. CMOS image sensor arrangement with reduced pixel light shadowing
US6777662B2 (en) * 2002-07-30 2004-08-17 Freescale Semiconductor, Inc. System, circuit and method providing a dynamic range pixel cell with blooming protection
US6930299B2 (en) * 2002-08-29 2005-08-16 Fujitsu Limited Semiconductor device for reading signal from photodiode via transistors
US7138618B2 (en) * 2003-02-19 2006-11-21 Sony Corporation Solid-state image pickup device and image pickup camera
US20060104564A1 (en) * 2004-11-15 2006-05-18 Catrysse Peter B Integrated waveguide and method for designing integrated waveguide

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070252182A1 (en) * 2006-04-27 2007-11-01 Beck Jeffery S Buried-gated photodiode device and method for configuring and operating same
US7608873B2 (en) * 2006-04-27 2009-10-27 Aptina Imaging Corporation Buried-gated photodiode device and method for configuring and operating same
US20070273779A1 (en) * 2006-05-25 2007-11-29 Sony Corporation Solid-state imaging device, method of manufacturing the same and camera module
US7940328B2 (en) * 2006-05-25 2011-05-10 Sony Corporation Solid state imaging device having wirings with lateral extensions
US20110285901A1 (en) * 2006-05-25 2011-11-24 Sony Corporation Solid state imaging device, method of manufacturing the same and camera module
US8866941B2 (en) * 2006-05-25 2014-10-21 Sony Corporation Solid state imaging device with wiring lines shifted for pupil correction and simplified wiring pattern and method of manufacturing the same
US20150036030A1 (en) * 2013-07-30 2015-02-05 Sony Corporation Imaging element and electronic apparatus
US9854189B2 (en) * 2013-07-30 2017-12-26 Sony Semiconductor Solutions Corporation Imaging element and electronic apparatus with improved wiring layer configuration

Also Published As

Publication number Publication date Type
US20070205356A1 (en) 2007-09-06 application
GB2425887B (en) 2010-10-13 grant
US7214920B2 (en) 2007-05-08 grant
GB0609029D0 (en) 2006-06-14 grant
JP2006313915A (en) 2006-11-16 application
GB2425887A (en) 2006-11-08 application
US7408140B2 (en) 2008-08-05 grant

Similar Documents

Publication Publication Date Title
US6654057B1 (en) Active pixel sensor with a diagonal active area
US20050205901A1 (en) Photoelectric conversion film-stacked type solid-state imaging device
US6633334B1 (en) Solid-state image pickup device with optimum layout of building components around a photoelectric conversion portion
US8541730B2 (en) Solid-state imaging device, imaging apparatus, and method for manufacturing solid-state imaging device
US6780666B1 (en) Imager photo diode capacitor structure with reduced process variation sensitivity
US20120188420A1 (en) Imaging systems with array cameras for depth sensing
US7701029B2 (en) Solid-state image pickup device
US20080088724A1 (en) Solid-state imaging device, imaging apparatus and camera
US6657665B1 (en) Active Pixel Sensor with wired floating diffusions and shared amplifier
US20060011813A1 (en) Image sensor having a passivation layer exposing at least a main pixel array region and methods of fabricating the same
US6838715B1 (en) CMOS image sensor arrangement with reduced pixel light shadowing
US20060132633A1 (en) CMOS image sensors having pixel arrays with uniform light sensitivity
US7294818B2 (en) Solid state image pickup device and image pickup system comprising it
US20070091190A1 (en) Solid-state imaging apparatus and camera
US20070023799A1 (en) Structure and method for building a light tunnel for use with imaging devices
US20080029787A1 (en) Photoelectric conversion apparatus and image pickup system using photoelectric conversion apparatus
US20070206241A1 (en) Fused multi-array color image sensor
US20070215912A1 (en) Solid-state imaging device and imaging apparatus
US7535073B2 (en) Solid-state imaging device, camera module and electronic equipment module
US20130049082A1 (en) Solid-state imaging device and electronic apparatus
US20030127647A1 (en) Image sensor with performance enhancing structures
US20060175538A1 (en) CMOS active pixel sensor and active pixel sensor array using fingered type source follower transistor
US20070069258A1 (en) Pixel having two semiconductor layers, image sensor including the pixel, and image processing system including the image sensor
US20070177044A1 (en) Solid-state image pickup device
US20070164332A1 (en) Shared-pixel-type image sensors for controlling capacitance of floating diffusion region

Legal Events

Date Code Title Description
AS Assignment

Owner name: AGILENT TECHNOLOGIES, INC., COLORADO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GAZELEY, WILLIAM G.;REEL/FRAME:017182/0979

Effective date: 20050503

AS Assignment

Owner name: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD., SINGAPORE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AGILENT TECHNOLOGIES, INC.;REEL/FRAME:017206/0666

Effective date: 20051201

Owner name: AVAGO TECHNOLOGIES GENERAL IP PTE. LTD.,SINGAPORE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AGILENT TECHNOLOGIES, INC.;REEL/FRAME:017206/0666

Effective date: 20051201

AS Assignment

Owner name: CITICORP NORTH AMERICA, INC., DELAWARE

Free format text: SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:017207/0882

Effective date: 20051201

Owner name: CITICORP NORTH AMERICA, INC.,DELAWARE

Free format text: SECURITY AGREEMENT;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:017207/0882

Effective date: 20051201

AS Assignment

Owner name: AVAGO TECHNOLOGIES SENSOR IP PTE. LTD., SINGAPORE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AVAGO TECHNOLOGIES IMAGING IP (SINGAPORE) PTE. LTD.;REEL/FRAME:017675/0691

Effective date: 20060430

Owner name: AVAGO TECHNOLOGIES IMAGING IP (SINGAPORE) PTE. LTD

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.;REEL/FRAME:017675/0738

Effective date: 20060127

Owner name: AVAGO TECHNOLOGIES SENSOR IP PTE. LTD.,SINGAPORE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AVAGO TECHNOLOGIES IMAGING IP (SINGAPORE) PTE. LTD.;REEL/FRAME:017675/0691

Effective date: 20060430

AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AVAGO TECHNOLOGIES IMAGING HOLDING CORPORATION;REEL/FRAME:018757/0159

Effective date: 20061206

Owner name: MICRON TECHNOLOGY, INC.,IDAHO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AVAGO TECHNOLOGIES IMAGING HOLDING CORPORATION;REEL/FRAME:018757/0159

Effective date: 20061206

XAS Not any more in us assignment database

Free format text: CORRECTED COVER SHEET TO ADD PORTION OF THE PAGE THAT WAS PREVIOUSLY OMITTED FROM THE NOTICE AT REEL/FRAME 018757/0183 (ASSIGNMENT OF ASSIGNOR S INTEREST);ASSIGNOR:AVAGO TECHNOLOGIES IMAGING HOLDING CORPORATION;REEL/FRAME:019028/0237

AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AVAGO TECHNOLOGIES IMAGING HOLDING CORPORATION;REEL/FRAME:019407/0441

Effective date: 20061206

Owner name: MICRON TECHNOLOGY, INC.,IDAHO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AVAGO TECHNOLOGIES IMAGING HOLDING CORPORATION;REEL/FRAME:019407/0441

Effective date: 20061206

AS Assignment

Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CITICORP NORTH AMERICA, INC. C/O CT CORPORATION;REEL/FRAME:021590/0866

Effective date: 20061201

AS Assignment

Owner name: AVAGO TECHNOLOGIES IMAGING HOLDING CORPORATION, MA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AVAGO TECHNOLOGIES SENSOR IP PTE. LTD.;REEL/FRAME:021603/0690

Effective date: 20061122

Owner name: AVAGO TECHNOLOGIES IMAGING HOLDING CORPORATION,MAL

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:AVAGO TECHNOLOGIES SENSOR IP PTE. LTD.;REEL/FRAME:021603/0690

Effective date: 20061122

AS Assignment

Owner name: APTINA IMAGING CORPORATION,CAYMAN ISLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:024160/0051

Effective date: 20081003

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 017206 FRAME: 0666.ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT;ASSIGNOR:AGILENT TECHNOLOGIES, INC.;REEL/FRAME:038632/0662

Effective date: 20051201