US20060220087A1 - Method of forming a contact structure including a vertical barrier structure and two barrier layers - Google Patents

Method of forming a contact structure including a vertical barrier structure and two barrier layers Download PDF

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Publication number
US20060220087A1
US20060220087A1 US11421406 US42140606A US2006220087A1 US 20060220087 A1 US20060220087 A1 US 20060220087A1 US 11421406 US11421406 US 11421406 US 42140606 A US42140606 A US 42140606A US 2006220087 A1 US2006220087 A1 US 2006220087A1
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Prior art keywords
layer
structure
contact
barrier
polysilicon
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US11421406
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Fred Fishburn
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Micron Technology Inc
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Micron Technology Inc
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/7687Thin films associated with contacts of capacitors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/1085Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto
    • H01L27/10852Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor extending over the access transistor
    • H01L27/10855Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor extending over the access transistor with at least one step of making a connection between transistor and capacitor, e.g. plug
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

This invention relates to contact structures for use in integrated circuits and methods of fabricating contact structures. In one embodiment, a contact structure includes a conductive layer, one or more barrier layers formed above the conductive layer, and a barrier structure encircling the polysilicon layer and the one or more barrier layers. In an alternate embodiment, a contact structure is fabricated by forming a polysilicon layer on a substrate, forming a tungsten nitride layer above the polysilicon layer, and etching the polysilicon layer and the tungsten nitride layer to a level below the surface of a substrate structure. A silicon nitride layer is formed above the tungsten nitride layer, and a ruthenium silicide layer is formed above the silicon nitride layer. The ruthenium silicide layer is then polished.

Description

  • [0001]
    This application is a Divisional of U.S. application Ser. No. 10/753,041, filed Jan. 7, 2004, which is a Divisional of U.S. application Ser. No. 09/653,640, filed Aug. 31, 2000, now U.S. Pat. No. 6,787,833, both of which are incorporated herein by reference.
  • FIELD
  • [0002]
    This invention relates to contact structures, and more particularly to contact structures used in the fabrication of integrated circuits.
  • BACKGROUND
  • [0003]
    An integrated circuit, such as a dynamic random access memory (DRAM) includes passive devices, such as capacitors, and active devices, such as metal-oxide semiconductor field-effect transistors (MOSFETS), fabricated on a single substrate. In fabricating an integrated circuit to perform a particular function, the passive and active devices are coupled together. For example, a capacitor electrode is electrically coupled to a MOSFET drain or source to form a dynamic random access memory (DRAM) cell for storing information.
  • [0004]
    One method of coupling a capacitor electrode to a MOSFET drain or source includes the operation of directly coupling the capacitor electrode to the drain or source by fabricating the capacitor electrode at the drain or source. Unfortunately, several problems arise when a non-silicon electrode is directly coupled to a MOSFET drain or source. First, the electrode can experience oxidation, which interferes with the electrode conductivity and may cause unpredictable memory cell operation. Electrode oxidation is most likely to occur during capacitor formation processes performed in an O2 atmosphere. Second, atomic migration to and from a substrate, such as silicon substrate, may occur between the substrate in which the MOSFET source and drain are formed and other integrated circuit elements, such as the dielectric layer of a capacitor. Atomic migration alters the electrical properties of the integrated circuit elements and may cause unpredictable memory cell operation.
  • [0005]
    One solution to these problems is to form a contact structure having a barrier layer located between the electrode and the source or drain for blocking oxygen migration and atomic migration to and from the substrate. Unfortunately, a single barrier layer that effectively blocks both oxygen migration and atomic migration from the substrate may react with the conductive layer fabricated at the source or drain and cause unpredictable circuit operation.
  • [0006]
    For these and other reasons, there is a need for the present invention.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0007]
    FIGS. 1, 1A are illustrations of a cross-sectional view of embodiments of a contact structure
  • [0008]
    FIG. 2 is an illustration of a cross-sectional view of one embodiment of an integrated circuit structure suitable for use as a foundation for a contact structure.
  • [0009]
    FIG. 3 is an illustration of a cross-sectional view of one embodiment of a partially formed contact structure.
  • [0010]
    FIG. 4 is an illustration of a cross-sectional view of one embodiment of the partially formed contact structure of FIG. 3 after etching.
  • [0011]
    FIG. 5 is an illustration of a cross-sectional view of one embodiment of the partially formed contact structure of FIG. 4 after the formation of a barrier structure and a second barrier layer.
  • [0012]
    FIG. 6 is an illustration of a cross-sectional view of one embodiment of the contact structure of FIG. 5 after cleaning and polishing.
  • [0013]
    FIG. 7 is an illustration of a cross-sectional view of an alternate embodiment of a contact structure.
  • [0014]
    FIG. 8 is an illustration of a cross-sectional view of one embodiment of a partially formed contact structure.
  • [0015]
    FIG. 9 is an illustration of a cross-sectional view of one embodiment of the partially formed contact structure of FIG. 8 after chemical mechanical polishing (CMP).
  • [0016]
    FIG. 10 is an illustration of a cross-sectional view of one embodiment of the partially formed contact of FIG. 9 after etching.
  • [0017]
    FIG. 11 is an illustration of a cross-sectional view of one embodiment of the partially formed contact of FIG. 10 after depositing an oxide layer.
  • [0018]
    FIG. 12 is an illustration of a cross-sectional view of one embodiment of the partially formed contact structure of FIG. 11 after etching the oxide layer.
  • [0019]
    FIG. 13 a block diagram of a computer system suitable for use in connection with the present invention.
  • DETAILED DESCRIPTION
  • [0020]
    In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present inventions. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.
  • [0021]
    A contact structure is described that includes one or more layers and other structures for blocking atomic migration in an integrated circuit, which improves the reliability of the circuit.
  • [0022]
    The present invention provides, in one embodiment, a contact including a polysilicon layer formed on a substrate, one or more barrier layers formed above the polysilicon layer, and a barrier structure encircling the polysilicon layer and the one or more barrier layers. The polysilicon layer provides a conductive material for coupling to an active or a passive device in an integrated circuit. At least one of the one or more barrier layers restricts the migration of atoms to and from the substrate, and at least one of the one or more barrier layers restricts the migration of oxygen atoms. Restricting the migration of substrate atoms, prevents the electrical properties of the integrated circuit devices from being inadvertently altered during circuit fabrication. Restricting the migration of oxygen atoms, deters oxidation at electrode surfaces, such as capacitor electrode surfaces. Since the barrier layers of the contact are also electrically conductive, the contact is suitable for use in interconnecting integrated circuit devices.
  • [0023]
    In an alternate embodiment, the present invention provides a method of fabricating a contact. The method includes forming a polysilicon layer and a tungsten nitride layer above a base integrated circuit structure. The polysilicon layer is formed at an electrical connection site of an integrated circuit device. The polysilicon layer and the tungsten nitride layer are etched to a level below the surface of the base integrated circuit structure. The polysilicon layer encircling the contact is etched much deeper, and a silicon nitride layer is formed to encircle the tungsten nitride layer. A ruthenium silicide layer is formed above the tungsten nitride layer as an oxygen barrier. The silicon nitride layer prevents the polysilicon layer from reacting with the ruthenium silicide layer. After polishing and cleaning, the ruthenium silicide layer is ready for coupling to an integrated circuit device.
  • [0024]
    FIG. 1 is an illustration of one embodiment of contact structure 100 coupling device 103 to device 105 in integrated circuit 107. Contact structure 100 provides a conductive path for transmitting an electrical signal between devices 103 and 105. Contact structure 100, in one embodiment, includes polysilicon layer 109, barrier layers 111 and 113, and barrier structure 115. Devices 103 and 105, which are coupled together by contact structure 100, are not limited to a particular type of device. Devices 103 and 105 may be any type of active or passive device capable of being fabricated using integrated circuit technologies, such as metal-oxide semiconductor (MOS) or bipolar technologies. In the example embodiment shown in FIG. 1, device 103 is a capacitor and device 105 is a metal-oxide semiconductor field effect transistor (MOSFET). In the example embodiment shown in FIG. 1A, device 103 is a capacitor and device 105A is a bipolar transistor (BJT). However, contact structure 100 is not limited to use in connection with a particular type of integrated circuit 107. Contact structure 100 is suitable for use in connection with linear integrated circuits, such as operational amplifiers, digital integrated circuits, such as boolean logic circuits and storage circuits, and memory circuits, such as dynamic random access memory (DRAM) circuits, static random access memory (SRAM) circuits, erasable programmable read only memory (EPROM) circuits, electrically erasable programmable read only memory (EEPROM) circuits, and flash memory circuits.
  • [0025]
    A structure described herein encircles a second structure or layer when the structure partially or completely surrounds any portion of the second structure or layer. For example, in FIG. 1 barrier structure 115 encircles polysilicon layer 109 and barrier layers 111 and 113.
  • [0026]
    FIGS. 2-7 illustrate a series of cross-sectional views of integrated circuit 107 during the fabrication of contact structure 100. FIG. 2 illustrates one embodiment of base structure 201 suitable for use as a foundation for the fabrication of contact structure 100. Base structure 201 includes substrate 117, circuit structures 203 and 204 including polysilicon layer 205 and silicon nitride layer 207, and borophosphosilicate glass (BPSG) layer 209. BPSG layer 209 is etched to form plug volume 211.
  • [0027]
    Substrate 117 is preferably fabricated from a material, such as a semiconductor, that is suitable for use as a substrate in connection with the fabrication of integrated circuits. Substrate 117 includes doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures having an exposed surface with which to form the contact structures of the present invention. Substrate 117 refers to semiconductor structures during processing, and may include other layers that have been fabricated thereon. In one embodiment, substrate 117 is fabricated from silicon. Alternatively, substrate 117 is fabricated from germanium, gallium-arsenide, silicon-on-insulator, silicon-on-sapphire, or any other crystalline or amorphous material suitable for use as a substrate in the manufacture of integrated circuits. Substrate 117 is not limited to a particular material, and the material chosen for the fabrication of substrate 117 is not critical to the practice of the present invention.
  • [0028]
    FIG. 3 is an illustration of a cross-sectional view of one embodiment of a partially formed contact structure 100 including polysilicon layer 109 and barrier layer 111. Polysilicon layer 109 is deposited above base structure 201 to a thickness of between about 450 angstroms and 550 angstroms. The thickness of polysilicon layer 109 is not critical to the performance of the present invention, and the thickness of polysilicon layer 109 may be varied to meet the design rules of a particular integrated circuit fabrication process. After polysilicon layer 109 is deposited, barrier layer 111 is deposited above polysilicon layer 109. Barrier layer 111 prevents the diffusion of substrate atoms beyond barrier layer 111 and provides a conductive path between device 103 and device 105, as shown in FIG. 1. In one embodiment, barrier layer 111 is fabricated from tungsten nitride and has a thickness of between about 900 angstroms and 1100 angstroms. A thickness of less than about 900 angstroms does not sufficiently block the etch during the removal of the encircling polysilicon. A thickness of more than about 1100 angstroms causes contact structure 100 to have very little space remaining for the ruthenium silicide. During the formation of barrier layer 111, voids may form in the layer. Although it is preferable to avoid the formation of voids in barrier layer 111, the operation of contact structure 100 is not significantly degraded by the formation of voids.
  • [0029]
    FIG. 4 is an illustration of a cross-sectional view of one embodiment of the partially formed contact structure, which is shown in FIG. 3, after etching. Barrier layer 111 and polysilicon layer 109 are etched to a level below the surface of the BPSG layer 209. Polysilicon layer 109 is preferably etched long enough to recess the outer perimeter of the plug volume 211 down to circuit structures 203 and 204.
  • [0030]
    FIG. 5 is an illustration of one embodiment of the partially formed contact structure shown in FIG. 4 after the formation of barrier structure 115 and barrier layer 113. Barrier structure 115 prevents polysilicon layer 109 from interacting with barrier layer 113. In one embodiment, barrier structure 115 is fabricated by forming a layer of silicon nitride above substrate 117 and etching the silicon nitride to a level below the surface of BPSG layer 209. Barrier structure 115 has a thickness that is about equal to the thickness of polysilicon layer 109. After barrier structure 115 is fabricated, barrier layer 113 is fabricated above barrier layer 111 and barrier structure 115. Barrier layer 113 prevents oxygen from diffusing into substrate 117 and provides a conductive path between device 103 and device 105, as shown in FIG. 1. In one embodiment, barrier layer 113 is fabricated by forming a layer of platinum-iridium (PtIr) above barrier layer 111 and barrier structure 115. In an alternate embodiment, barrier layer 113 is fabricated by forming a layer of platinum-rhodium (PtRh) above barrier layer 111 and barrier structure 115.
  • [0031]
    FIG. 6 is an illustration of one embodiment of the contact structure shown in FIG. 5 after cleaning and polishing. A chemical-mechanical polishing (CMP) process and a post CMP process is applied contact structure 100 and to the surface of substrate 117. The post CMP process is either a wet or sputter etch for removing CMP residue and smeared barrier material. After the post CMP process, device 103, as shown in FIG. 1, may be fabricated above contact structure 100. In one embodiment, device 103 is a capacitor having a pair or electrodes 119 and 121 and a dielectric 123 for storing charged sensed by device 105.
  • [0032]
    Referring again to FIG. 1, in operation, contact structure 100 provides a conductive path for the exchange of electronic signals between devices 103 and 105. For example, in a DRAM cell in which device 103 is a capacitor and device 105 is a MOSFET, contact structure 100 provides a path so that the MOSFET is capable of sensing charge stored on the capacitor. Contact structure 100 also provides a barrier layer 111 for blocking the migration of substrate atoms into the upper layers of integrated circuit 107. In addition, contact structure 100 provides barrier layer 113 for blocking the migration of oxygen atoms into substrate 117.
  • [0033]
    FIG. 7 is an illustration of a cross-sectional view of an alternate embodiment of a contact structure. Contact structure 700 couples device 103 to device 105 in integrated circuit 707. Contact structure 700 provides a conductive path for transmitting an electrical signal between devices 103 and 105. Contact structure 700, in one embodiment, includes polysilicon layer 709, barrier layers 711 and 713, and barrier structure 715. Devices 103 and 105, which are coupled together by contact structure 700, are not limited to a particular type of device. Devices 103 and 105 may be any type of active or passive device capable of being fabricated using integrated circuit technologies, such as metal-oxide semiconductor (MOS) or bipolar technologies. In the example embodiment shown in FIG. 7, device 103 is a capacitor and device 105 is a metal-oxide semiconductor field effect transistor (MOSFET). However, contact structure 700 is not limited to use in connection with a particular type of integrated circuit 707. Contact structure 700 is suitable for use in connection with linear integrated circuits, such as operational amplifiers, digital integrated circuits, such as boolean logic circuits and storage circuits, and memory circuits, such as dynamic random access memory (DRAM) circuits, static random access memory (SRAM) circuits, electrically programmable memory (EPROM) circuits, and electrically erasable programmable memory (EEPROM) circuits.
  • [0034]
    FIG. 8 is an illustration of a cross-sectional view of one embodiment of a partially formed contact structure of FIG. 7 after the fabrication of one or more layers. The embodiment illustrated in FIG. 8 includes base structure 201 including substrate 117, circuit structures 203 and 204, which include polysilicon layer 205 and silicon nitride layer 207, and borophosphosilicate glass (BPSG) layer 209, which are described above in connection with contact structure 100. Also, as described above in connection with contact structure 100, BPSG layer 209 is etched to form plug volume 211. After the formation of plug volume 211, polysilicon layer 803, tungsten nitride layer 805, and RuSix layer 807 are formed above substrate 117. In one embodiment, the thickness of polysilicon layer 803 is about 500 angstroms, the thickness of tungsten nitride layer 805 is about 500 angstroms, and the thickness of RuSix layer 807 is about 2000 angstroms.
  • [0035]
    FIG. 9 is an illustration of a cross-sectional view of one embodiment of the partially formed contact structure of FIG. 8 after chemical mechanical polishing (CMP). In performing the CMP it is not necessary to completely remove polysilicon layer 803 from the surface of the BPSG layer 209. The CMP is followed by a dry etch to remove polysilicon layer 803 and tungsten nitride layer 805.
  • [0036]
    FIG. 10 is an illustration of a cross-sectional view of one embodiment of the partially formed contact of FIG. 9 after etching. A dry etch removes polysilicon layer 803 from the surface of BPSG 209, and etches polysilicon layer 803 and tungsten nitride layer 805 to a level below the surface of the BPSG layer 209. A dry etch of polysilicon layer 803 removes the polysilicon layer to a level near the surface of circuit structure 203. The dry etch also etches tungsten nitride layer 805 to a level below the surface of BPSG layer 209. Preferably, polysilicon layer 803 is etched to a level below the level of tungsten nitride layer 805.
  • [0037]
    FIG. 11 is an illustration of a cross-sectional view of one embodiment of the partially formed contact of FIG. 10 after forming oxide layer 1101. After contact structure 700 is etched as shown in FIG. 10, oxide layer 1101 is formed above contact structure 700 and at least partially fills the gap formed between tungsten nitride layer 805 and BPSG layer 209. Since oxide layer 1101 is intended to isolate polysilicon layer 803 from RuSix layer 807, oxide layer 1101 need not fill the gap down to the level of polysilicon layer 803.
  • [0038]
    FIG. 12 is an illustration of a cross-sectional view of one embodiment of contact structure 700 of FIG. 11 after etching oxide layer 1101. Oxide layer 1001 is etched to expose RuSix layer 807. After exposing RuSix layer 807, contact structure 700 is capable of coupling device 103 to device 105, as illustrated in FIG. 7.
  • [0039]
    FIG. 13 a block diagram of a computer system suitable for use in connection with the present invention. System 1300 comprises processor 1305 and memory device 1310, which includes contact structures of one or more of the types described above in conjunction with FIGS. 1-12. Memory device 1310 comprises memory array 1315, address circuitry 1320, and read circuitry 1330, and is coupled to processor 1305 by address bus 1335, data bus 1340, and control bus 1345. Processor 1305, through address bus 1335, data bus 1340, and control bus 1345 communicates with memory device 1310. In a read operation initiated by processor 1305, address information, data information, and control information are provided to memory device 1310 through busses 1335, 1340, and 1345. This information is decoded by addressing circuitry 1320, including a row decoder and a column decoder, and read circuitry 1330. Successful completion of the read operation results in information from memory array 1315 being communicated to processor 1305 over data bus 1340.
  • [0040]
    Contact structures and methods of fabricating contact structures have been described. The contact structures include one or more barrier layers and a barrier structure. One of the barrier layers is capable of blocking the migration of substrate atoms. Another of the barrier layers is capable blocking the migration of oxygen atoms. The barrier structure prevents at least two layers in the contact structure from reacting with each other. The methods of fabricating the contact structure include processes for forming the layers of the contact structure, etching the layers of the contact structure, forming the barrier structure, and polishing the contact structure.
  • [0041]
    Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.

Claims (44)

  1. 1. A memory cell comprising:
    a capacitor;
    a transistor;
    a contact structure coupling the capacitor to the transistor; and
    an insulating structure encircling the contact structure.
  2. 2. The memory cell of claim 1, wherein the transistor is a metal-oxide semiconductor field-effect transistor.
  3. 3. The memory cell of claim 1, wherein the contact structure includes one or more layers.
  4. 4. A memory cell comprising:
    a capacitor;
    a metal-oxide semiconductor field effect transistor (MOSFET);
    a contact structure coupling the capacitor to the MOSFET; and
    an insulating structure encircling the contact structure.
  5. 5. The memory cell of claim 4, wherein the MOSFET has a source and the contact structure couples the capacitor to the source.
  6. 6. The memory cell of claim 5, wherein the contact structure includes at least two barrier layers.
  7. 7. The memory cell of claim 4, wherein the contact structure includes a polysilicon layer, a tungsten nitride layer, and a platinum-iridium layer.
  8. 8. The memory cell of claim 7, wherein the insulating structure is fabricated from a tungsten nitride.
  9. 9. The memory cell of claim 7, wherein the contact structure separates the platinum-iridium layer from the polysilicon layer.
  10. 10. The memory cell of claim 7, wherein the insulating layer is capable of preventing the polysilicon layer from reacting with the contact structure.
  11. 11. The memory cell of claim 7, wherein platinum-ruthenium layer is separated from the polysilicon layer by the insulating structure.
  12. 12. The memory cell of claim 4, wherein the insulating structure is located between the contact structure and a borophosphosilicate glass layer.
  13. 13. A memory cell comprising:
    a capacitor;
    a transistor;
    a contact structure including a polysilicon layer, a tungsten nitride layer, and a ruthenium silicide layer, the contact structure coupling the capacitor to the transistor; and
    an insulating structure encircling the contact structure.
  14. 14. The memory cell of claim 13, wherein the transistor is a bipolar transistor.
  15. 15. The memory cell of claim 13, wherein the insulating layer is separated from the polysilicon layer by an air gap.
  16. 16. The memory cell of claim 13, wherein the transistor is a metal-oxide semiconductor field effect transistor (MOSFET).
  17. 17. A system comprising:
    a processor; and
    one or more memory cells coupled to the processor, wherein at least one of the memory cells includes a contact having an insulating structure to prevent a conductive layer from interacting with a barrier layer.
  18. 18. The system of claim 17, wherein the processor is a microprocessor.
  19. 19. The system of claim 17, wherein at least one of the memory cells is a dynamic random access memory (DRAM) cell.
  20. 20. The system of claim 19, wherein the processor is a reduced instruction set (RISC) processor.
  21. 21. The system of claim 17, wherein the barrier layer is to prevent migration of oxygen atoms into a substrate.
  22. 22. A system comprising:
    a processor; and
    one or more dynamic random access memory (DRAM) cells coupled to the processor, wherein at least one of the DRAM cells includes a contact structure including a barrier structure fabricated from silicon nitride.
  23. 23. The system of claim 22, wherein the barrier structure encircles the contact structure.
  24. 24. The system of claim 22, wherein the contact structure includes one or more barrier layers.
  25. 25. A system comprising:
    a processor; and
    one or more memory cells, wherein at least one of the memory cells includes a contact structure having an insulating structure encircling the contact structure.
  26. 26. The system of claim 25, wherein the contact structure includes a polysilicon layer and two barrier layers.
  27. 27. The system of claim 25, wherein the contact structure includes a barrier layer capable of blocking migration of silicon atoms and a barrier layer capable of blocking migration of oxygen atoms.
  28. 28. A method comprising:
    forming an active device on a substrate;
    forming a passive device on the substrate; and
    forming a contact structure including a barrier structure for coupling the passive device to the active device.
  29. 29. The method of claim 28, wherein forming the active device further includes forming the active device below a conductive layer.
  30. 30. The method of claim 29 further comprising, forming a first barrier layer above the conductive layer.
  31. 31. The method of claim 30 further comprising, forming a second barrier layer above the first barrier layer.
  32. 32. The method of claim 28, wherein forming the active device further includes forming the active device as a metal-oxide semiconductor field-effect transistor (MOSFET).
  33. 33. A method comprising:
    forming a conductive layer on a base structure having a surface;
    forming a first barrier layer above the conductive layer;
    etching the conductive layer and the first barrier layer to a level below the surface;
    forming a barrier structure that encircles the conductive layer and the first barrier layer;
    forming a second barrier layer above the first barrier layer; and
    polishing the second barrier layer and the surface.
  34. 34. The method of claim 33, further comprising:
    forming an active device below the conductive layer.
  35. 35. The method of claim 34, further comprising:
    forming a passive device above the second barrier layer.
  36. 36. A method comprising:
    forming a polysilicon layer on a base structure having a surface;
    forming a tungsten nitride layer above the conductive layer;
    etching the polysilicon layer and the tungsten nitride layer to a level below the surface;
    forming a silicon nitride structure that encircles the polysilicon layer and the tungsten nitride layer;
    forming a ruthenium silicide layer above the first barrier layer; and
    polishing the ruthenium silicide layer and the surface.
  37. 37. The method of claim 36, further comprising:
    forming a MOSFET below the conductive layer.
  38. 38. The method of claim 37, further comprising:
    forming a capacitor above the second barrier layer.
  39. 39. A method comprising:
    forming a conductive layer on a base structure having a surface;
    forming a first barrier layer above the conductive layer;
    forming a second barrier layer above the first barrier layer;
    etching the first barrier layer and the second barrier layer;
    etching the conductive layer and the first barrier layer to a level below the surface;
    forming an oxide layer above the second barrier layer; and
    removing the oxide layer from above the second barrier layer.
  40. 40. The method of claim 39, further comprising:
    forming a transistor below the conductive layer.
  41. 41. The method of claim 40, further comprising:
    forming a passive device above the second barrier layer.
  42. 42. A method of forming a contact, the method comprising:
    forming a structure having a plug volume above a substrate;
    forming a polysilicon layer in the plug volume;
    forming one or more barrier layers above the polysilicon layer;
    etching an outer perimeter to recess the outer perimeter of the plug volume down to a tungsten nitride layer;
    forming a barrier structure in the outer perimeter;
    etching the barrier structure to leave a sidewall above the tungsten nitride, but still expose the top surface;
    depositing the oxygen barrier layer to fill the rest of the plug; and
    polishing to isolate individual plug features.
  43. 43. The method of claim 42 further comprising, forming the polysilicon layer as a conductive layer
  44. 44. The method of claim 43 further comprising, forming the barrier structure to encircle the conductive layer.
US11421406 2000-08-31 2006-05-31 Method of forming a contact structure including a vertical barrier structure and two barrier layers Abandoned US20060220087A1 (en)

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US6787833B1 (en) 2004-09-07 grant
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US20040140494A1 (en) 2004-07-22 application
US7569453B2 (en) 2009-08-04 grant

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