US20060214196A1 - Semiconductor devices having a hybrid channel layer, current aperture transistors and methods of fabricating same - Google Patents
Semiconductor devices having a hybrid channel layer, current aperture transistors and methods of fabricating same Download PDFInfo
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- US20060214196A1 US20060214196A1 US11/436,745 US43674506A US2006214196A1 US 20060214196 A1 US20060214196 A1 US 20060214196A1 US 43674506 A US43674506 A US 43674506A US 2006214196 A1 US2006214196 A1 US 2006214196A1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- H01L29/2003—Nitride compounds
Definitions
- the present invention relates to semiconductor devices and, more particularly, to current aperture transistors.
- a performance characteristic of importance may be the breakdown characteristics of the device.
- the maximum reverse bias blocking voltage sustainable by the device may limit the potential applications for the device.
- the structure of the device may result in a breakdown voltage that is less than the breakdown voltage of the device.
- U-metal oxide semiconductor field effect transistor U-metal oxide semiconductor field effect transistor
- field crowding may result at a corner of the gate trench such that breakdown occurs in the region of the field crowding rather than in the bulk material.
- U-metal oxide semiconductor field effect transistor U-metal oxide semiconductor field effect transistor
- FIG. 1 illustrates a conventional current aperture transistor 10 .
- the current aperture transistor 10 includes a silicon doped GaN drain layer 12 with spaced apart regions of insulating GaN 14 that form the current aperture region 30 .
- the current aperture region 30 is part of a regrown unintentionally doped GaN layer 16 that has an AlGaN layer 18 formed thereon so that a two-dimensional electron gas (2DEG) forms at the interface between the unintentionally doped GaN layer 16 and the AlGaN layer 18 .
- a gate contact 24 and a source contact 22 are provided on the AlGaN layer 18 and a drain contact 26 is provided on the silicon doped GaN layer 12 .
- Some embodiments of the present invention provide transistors and/or methods of fabrication of transistors that include a source contact, drain contact and gate contact.
- a channel region is provided between the source and drain contacts and at least a portion of the channel regions includes a hybrid layer of semiconductor material.
- the transistor is a current aperture transistor.
- the hybrid layer of semiconductor material includes a Group III-nitride semiconductor material.
- the hybrid layer of semiconductor material may also include a region of p-type or insulating semiconductor material and a region of n-type semiconductor material. A portion of the channel region through the current aperture may include a vertical portion and a horizontal portion.
- the hybrid layer may include a pendeo-epitaxial layer having a higher doping level in the laterally grown portions of the pendeo-epitaxial layer.
- the hybrid layer may include a epitaxial laterally overgrown layer having a higher doping level in the laterally grown portions of the epitaxial laterally overgrown layer.
- the transistor includes a first n-type nitride-based layer on a substrate.
- the first n-type nitride-based layer has a first surface opposite the substrate and an aperture having sidewalls.
- a nitride-based layer is provided on the first n-type nitride-based layer and extends onto the sidewalls of the aperture.
- a portion of the nitride-based layer on the sidewalls of the aperture is n-type and a portion of the nitride-based layer on the first surface of the second n-type nitride-based layer is p-type and/or insulating.
- An unintentionally doped nitride-based layer is provided on the nitride based layer and extends to substantially fill the aperture.
- the unintentionally doped nitride-based layer has portions of n-type nitride-based semiconductor material on the n-type portions of the nitride-based layer.
- First and second layers of nitride-based semiconductor material are provided on the unintentionally doped nitride-based layer and are configured to provide a two-dimensional electron gas (2DEG) in a region of an interface between the first and second semiconductor material layers.
- the source contact and the gate contact are provided on the second layer of nitride-based semiconductor material and the drain contact is electrically connected to the first n-type nitride-based layer.
- a second n-type nitride-based layer is provided between the first n-type nitride-based layer and the substrate.
- the substrate has a trench formed therein and the first n-type nitride-based layer, the nitride based layer and the unintentionally doped nitride-based layer are cantilevered over the trench.
- a mask region is provided on the substrate or the second n-type nitride-based layer if present and a portion of the first n-type nitride-based layer, the nitride based layer and the unintentionally doped nitride-based layer extend onto the mask region.
- Additional embodiments of the present invention include a third n-type nitride-based layer between the second nitride-based layer and the substrate.
- the substrate may be a silicon carbide substrate and the drain contact may be provided on the substrate opposite the first n-type nitride-based layer.
- An insulating layer may also be provided between the gate contact and the second layer.
- the first n-type nitride-based layer includes a GaN based layer
- the second n-type nitride-based layer includes a GaN based layer
- the nitride-based layer on the second n-type nitride-based layer includes a GaN based layer
- the unintentionally doped nitride-based layer includes a GaN based layer
- the first layer includes an unintentionally doped GaN based layer
- the second layer includes an AlGaN and/or INAlN based layer.
- the substrate may also be a GaN substrate.
- transistors and/or methods of fabricating transistors that include a substrate having a trench therein and a first pendeo-epitaxial layer of semiconductor material of the first conductivity type is provided on the substrate is provided.
- the first pendeo-epitaxial layer has spaced apart cantilevered portions that extend over the trench.
- a second pendeo-epitaxial layer of semiconductor material of a second conductivity type and/or insulating is provided on the first pendeo-epitaxial layer of semiconductor material and includes spaced apart portions that extend from end surfaces of the cantilevered portions of the first pendeo-epitaxial layer that are the first conductivity type.
- a third pendeo-epitaxial layer of unintentionally doped semiconductor material is provided on the second pendeo-epitaxial layer and includes portions that extend from the spaced apart portions and coalesce and are the first conductivity type.
- a channel layer of semiconductor material is provided on the third pendeo-epitaxial layer and a barrier layer is provided on the channel layer.
- a source contact and a gate contact are provided on the barrier layer.
- a drain contact is electrically connected to the first layer of conformal semiconductor material.
- a first layer of conformal semiconductor material of a first conductivity type is provided on the substrate and the trench.
- the first pendeo-epitaxial layer may be provided on the first layer.
- the first conductivity type is n-type and the second conductivity type is p-type.
- the semiconductor material may include a nitride-based semiconductor material.
- the substrate may be a GaN substrate.
- the substrate may also be silicon carbide.
- the silicon carbide substrate may be the first conductivity type and the drain contact may be provided on the silicon carbide substrate.
- the nitride-based semiconductor material may include a GaN based semiconductor material.
- transistors and methods of fabricating transistors that include a mask region on a substrate are provided.
- a first epitaxial laterally overgrown layer of semiconductor material of the first conductivity type is provided on the substrate and at least a portion of the mask region.
- a second epitaxial laterally overgrown layer of semiconductor material of a second conductivity type and/or insulating is provided on the first epitaxial laterally overgrown layer of semiconductor material and at least a portion of the mask region and includes spaced apart portions that extend from end surfaces of the portions of the first epitaxial laterally overgrown layer on the mask region that are the first conductivity type.
- a third epitaxial laterally overgrown layer of unintentionally doped semiconductor material is provided on the second epitaxial laterally overgrown layer and includes portions that extend from the spaced apart portions and coalesce and are the first conductivity type.
- a channel layer of semiconductor material is provided on the third epitaxial laterally overgrown layer.
- a barrier layer is provided on the channel layer.
- a source contact and a gate contact are provided on the barrier layer.
- a drain contact is electrically connected to the first layer of semiconductor material.
- a first layer of semiconductor material of a first conductivity type is provided between the substrate and the first epitaxial laterally overgrown layer.
- the mask region may be provided on the first layer.
- the first conductivity type is n-type and the second conductivity type is p-type.
- the semiconductor material may be a nitride-based semiconductor material.
- the substrate may be silicon carbide and/or GaN.
- the silicon carbide substrate may be the first conductivity type and the drain contact may be provided on the silicon carbide substrate.
- the nitride-based semiconductor material may be a GaN based semiconductor material.
- Still further embodiments of the present invention provided current aperture transistors and methods of fabricating current aperture transistors that include a first layer of semiconductor material of a second conductivity type or insulating on a substrate.
- a channel layer of semiconductor material is provided on the second layer.
- a barrier layer is provided on the channel layer.
- a trench extends through the barrier layer, the channel layer and the first layer. The trench includes semiconductor material of the first conductivity type therein.
- a gate contact and a source contact are provided on the barrier layer. The source contact is on the barrier layer and opposite the trench from the gate contact.
- a drain contact is electrically connected to the first layer.
- a second layer of semiconductor material of a first conductivity type is provided between the substrate and the first layer of semiconductor material.
- the trench may extend through the first layer to and/or into the second layer.
- the first conductivity type is n-type and the second conductivity type is p-type.
- the semiconductor material may be a nitride-based semiconductor material.
- the substrate may be GaN.
- the substrate may also be silicon carbide.
- the silicon carbide substrate may be the first conductivity type and the drain contact may be provided on the silicon carbide substrate opposite the first layer of semiconductor material.
- the nitride-based semiconductor material may be a GaN based semiconductor material.
- An insulating layer may be provided between the gate contact and the barrier layer. Contact regions of semiconductor material of the first conductivity type may be provided between the source contact and the barrier layer.
- the trench may extend into the first layer.
- a third layer of semiconductor material of the first conductivity type may be disposed between the substrate and the first layer of semiconductor material.
- FIG. 1 is a schematic drawing of a conventional current aperture transistor.
- FIG. 2 is a schematic drawing of current aperture transistors according to some embodiments of the present invention.
- FIGS. 3A-3E are schematic drawings illustrating fabrication of current aperture transistors as illustrated in FIG. 2 .
- FIG. 4 is a schematic drawing of current aperture transistors according to further embodiments of the present invention.
- FIGS. 5A-5E are schematic drawings illustrating fabrication of current aperture transistors as illustrated in FIG. 4 .
- FIG. 6 is a schematic drawing illustrating a current aperture transistor according to further embodiments of the present invention.
- first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
- relative terms such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in the Figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower”, can therefore, encompass both an orientation of “lower” and “upper,” depending of the particular orientation of the figure.
- Embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a grown or deposited region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of concentrations at its edges with another region rather than a binary change from a first region to a second region of different composition. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present invention.
- Some embodiments of the present invention provide vertical transistors that have a current aperture that is at least partially horizontal and methods of forming such transistors.
- the current aperture is laterally grown, for example, through lateral pendeo-epitaxial growth and/or through epitaxial lateral overgrowth (ELO).
- ELO epitaxial lateral overgrowth
- the use of lateral growth allows for the formation of a layer of semiconductor material having differing regions of conductivity types and/or differing conductivities as a result of the preferential incorporation of dopants in the laterally grown regions of the device.
- Hybrid layer Such a single layer having differing lateral regions that are formed as part of a single growth or deposition process are referred to herein as a “hybrid layer.”
- Hybrid layers may be distinguished from layers that have a substantially uniform conductivity type and/or conductivity in a lateral direction or layers that are formed of a substantially uniform conductivity type and/or conductivity that are subsequently processed by, for example, ion implantation and/or diffusion to alter the characteristics of a portion of the layer.
- Some embodiments of the present invention provide a transistor having at least a portion of the channel of the transistor provided by a hybrid layer.
- Embodiments of the present invention may be suited for use in nitride-based vertical current aperture transistors, such as Group III-nitride based devices.
- Group III nitride refers to those semiconducting compounds formed between nitrogen and the elements in Group III of the periodic table, usually aluminum (Al), gallium (Ga), and/or indium (In).
- Al aluminum
- Ga gallium
- In indium
- the term also refers to ternary and quaternary compounds such as AlGaN and AlInGaN.
- the Group III elements can combine with nitrogen to form binary (e.g., GaN), ternary (e.g., AlGaN, AlInN), and quaternary (e.g., AlInGaN) compounds. These compounds all have empirical formulas in which one mole of nitrogen is combined with a total of one mole of the Group III elements. Accordingly, formulas such as Al x Ga 1-x N where 0 ⁇ x ⁇ 1 are often used to describe them.
- FIG. 2 is a schematic cross sectional illustration of a current aperture transistor according to some embodiments of the present invention.
- a substrate 110 such as a silicon carbide substrate, has a trench 150 formed therein.
- the trench may be from about 1 ⁇ m to about 20 ⁇ m deep and from about 0.5 ⁇ m to about 10 ⁇ m wide.
- the substrate 110 may be an n-type semiconductor material.
- the substrate 110 may be doped to provide a carrier concentration of from about 10 17 to about 10 20 cm ⁇ 3 .
- the substrate 110 may be an insulating or semi-insulating substrate. In such a case, a contact may be provided to the n+ layer 112 , for example, in a trench or at a peripheral edge of the device as illustrated in FIG. 1 .
- a first layer 112 of n-type semiconductor material such as a nitride-based semiconductor material, is provided on a surface of the substrate 110 and, in some embodiments, in the trench 150 .
- the first layer 112 may, for example, be AlGaN and may be doped with, for example, Si, Ge and/or O to provide an n+ layer of AlGaN.
- the first layer 112 has a thickness of from about 0 (i.e. is an optional layer) to about 1 ⁇ m.
- the first layer 112 may also be doped to provide a carrier concentration of from about 10 17 to about 10 20 cm ⁇ 3 .
- the substrate 110 is a GaN based substrate, such as a GaN substrate
- the first layer 112 may be omitted.
- a second layer 114 of n-type semiconductor material is provided on the first layer 112 (or the substrate if the first layer is omitted) and is cantilevered over the trench 150 .
- the second layer 114 may, for example, be an n+ GaN layer and may be formed as discussed below, by pendeo-epitaxial growth.
- the second layer 114 is provided on a first surface of the first layer 112 that is opposite the substrate 110 and does not extend completely across the trench 150 but includes spaced apart regions that have opposing sidewalls.
- the second layer 114 has a thickness of from about 0.1 ⁇ m to about 5 ⁇ m.
- the second layer 114 also may be doped with an n-type dopant, such as Si, Ge and/or O, to provide a carrier concentration of from about 10 17 to about 10 20 cm ⁇ 3 .
- a third layer 116 of p-type and/or insulating semiconductor material is provided on the second layer 114 and has portions 117 of n-type semiconductor material that extend from the sidewalls of the second layer 114 .
- the third layer 116 may be provided as a hybrid layer.
- the third layer 116 does not extend completely across the trench 150 but includes spaced apart regions that have opposing sidewalls.
- the third layer 116 may be p-type or insulating GaN formed as discussed below, by pendeo-epitaxial growth in the presence of an n-type dopant, such as Si, Ge and/or O, such that the portions 117 that are laterally grown are n-type GaN.
- the insulating and/or p-type regions of third layer 116 may substantially block current flow by, for example, having a Fermi level positioned at greater than about 0.5 eV from the conduction band.
- the portions 117 of the third layer 116 may be doped to provide a carrier concentration of, for example, from about 10 14 to about 10 19 cm ⁇ 3 .
- the third layer 116 may have a thickness of from about 0.1 ⁇ m to about 10 ⁇ m.
- a fourth layer 118 of unintentionally doped semiconductor material is provided on the third layer 116 .
- the unintentionally doped semiconductor material may be lightly doped.
- the fourth layer 118 has portions 119 of n-type semiconductor material that extend from the sidewalls of the third layer 116 .
- the fourth layer 118 may be provided as a hybrid layer.
- the fourth layer 118 extends completely across the trench 150 and may coalesce where the portions 119 extending from the sidewalls of the third layer 116 meet.
- a hole or opening 152 may be provided by the trench beneath the fourth layer 118 .
- the fourth layer 118 may be primarily unintentionally doped GaN formed as discussed below, by pendeo-epitaxial growth in the presence of an n-type dopant, such as Si, Ge and/or O such that the portions 119 that are laterally grown are n-type GaN.
- the n-type dopants may be affirmatively supplied and/or may be unintentional, for example, the n-type may be provided as a by-product of a prior processing step and/or contamination.
- the unintentionally doped regions of the fourth layer 118 may be lightly n-type or have a low net concentration of acceptors or deep levels.
- the portions 119 of the fourth layer 118 may be doped to provide a carrier concentration of, for example, from about 10 15 to about 10 20 cm ⁇ 3 .
- the fourth layer 118 may have a thickness of from about 0.1 ⁇ m to about 10 ⁇ m.
- a channel layer 120 and a barrier layer 122 may be provided on the fourth layer 118 .
- the channel layer 120 and the barrier layer 122 are configured so as to form a 2DEG near the interface between the channel layer 120 and the barrier layer 122 .
- the channel layer 120 and/or the barrier layer 122 may be provided by a single or multiple layers.
- the channel layer 120 is an unintentionally doped GaN layer.
- the barrier layer 122 may be an AlGaN and/or AlN layer.
- the channel layer 120 is GaN having a thickness of from about 5 m to about 5000 nm and the barrier layer 122 is AlGaN having a concentration of aluminum of from about 5% to about 100% and having a thickness of from about 1 nm to about 100 nm.
- a gate contact 130 is provided on the barrier layer 122 and, in some embodiments, may be provided on an oxide (not shown) on the barrier layer 122 . In some embodiments of the present invention, at least a portion of the gate contact 130 overlaps with the trench 150 . In some embodiments of the present invention, the gate contact 130 is confined to a region above the trench 150 . In still further embodiments, the gate contact 130 may be provided without overlap of the trench 150 .
- the gate contact 130 may be formed of, for example, Ni/Au.
- a dielectric layer such as a silicon nitride or silicon oxide layer is provided on the barrier layer 122 .
- the gate contact 130 may be formed in a recess in the dielectric layer or, in some embodiments, may be formed on the dielectric layer.
- a source contact 132 is also provided on the barrier layer 122 .
- the source contact 132 may be provided on a recess into the barrier layer 122 and/or on a contact region so as to reduce resistance between the source contact 132 and the channel layer 120 .
- the source contact 132 may be formed of, for example, Ti/Al/Ni/Au.
- a drain contact 134 is provided on the substrate 110 opposite the first layer 112 .
- a backside implant or epitaxial layer (not shown) may be provided so as to reduce resistance between the drain contact 134 and the substrate 110 .
- the backside implant or epitaxial layer may, for example, be an n+ region formed in or on the substrate 110 on which the drain contact 134 is provided.
- the substrate 110 may be thinned prior to formation of the drain contact 134 .
- the drain contact may be formed of, for example, nickel if a silicon carbide substrate is used.
- the drain contact 134 may, optionally, be formed on the first layer 112 , similar to the configuration illustrated in FIG. 1 .
- an insulating substrate or a semi-insulating substrate such as semi-insulating silicon carbide or sapphire, may be utilized for the substrate 110 .
- electrons from the source contact 132 may flow along the 2DEG formed near the interface of the barrier layer 122 and the channel layer 120 and then vertically into the n-type portions 119 of the fourth layer 118 and then laterally across the n-type portion 117 of the third layer 116 to the n+ layer 114 , vertically to the n+ layer 112 and to the drain contact 134 through the substrate 110 .
- a current aperture may be provided by the p or i regions of the third layer 116 with a current path provided by the n-type regions incorporated in the laterally grown portions of the third layer 116 and the fourth layer 118 .
- the hole 152 may also define the current aperture.
- a portion of the channel region of the device may be provided by a hybrid layer.
- the channel region through the current aperture may include a vertical portion through the fourth layer 118 and a horizontal portion through the third layer 116 .
- the Schottky gate contact 130 (or MOS gate if an insulating layer provided on the barrier layer 122 ) may modulate the charge in the 2DEG to control the flow of current through the aperture.
- a substrate 110 is provided on which nitride based devices may be formed.
- the substrate 110 may be an n-type silicon carbide (SiC) substrate that may be, for example, 4H polytype of silicon carbide.
- SiC silicon carbide
- Other silicon carbide candidate polytypes include the 3C, 6H, and 15R polytypes.
- Appropriate SiC substrates are manufactured by, for example, Cree, Inc., of Durham, N.C., the assignee of the present invention, and methods for producing are described, for example, in U.S. Pat. Nos. Re.
- Optional buffer, nucleation and/or transition layers may be provided on the substrate 110 .
- silicon carbide may be a preferred substrate material
- embodiments of the present invention may utilize any suitable substrate, such as sapphire, aluminum nitride, aluminum gallium nitride, gallium nitride, silicon, GaAs, LGO, ZnO, LAO, InP and the like.
- an appropriate buffer layer also may be formed.
- a second contact may be formed in a recess that extends to a drain layer opposite the current aperture from the gate.
- a trench 150 is formed in the substrate 110 , for example, by masking and etching the substrate 110 .
- a dry etch, wet etch or other etch technique known to those of skill in the art may be utilized.
- the particular etch technique may depend on the substrate material.
- a reactive ion etch may be utilized for a silicon carbide substrate.
- Other techniques for patterning the substrate to form a trench may also be utilized.
- the trench could be provided by a saw cut or laser removal of material.
- the first layer 112 is blanket formed on the substrate 110 including in the trench 150 .
- the first layer 112 is formed conformally so as to maintain the opening 152 formed by the trench 150 .
- the first layer 112 may be formed, for example, by plasma enhanced chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), low pressure chemical vapor deposition (LPCVD) or other technique known to those of skill in the art.
- PECVD plasma enhanced chemical vapor deposition
- MOCVD metal organic chemical vapor deposition
- MBE molecular beam epitaxy
- LPCVD low pressure chemical vapor deposition
- the particular deposition technique may depend on the composition of the first layer 112 and whether or not buffer layers such as those described above are utilized.
- the first layer 112 may be omitted.
- the substrate 110 is a GaN substrate
- the first layer 112 may be omitted and the trench may be formed in the GaN substrate.
- FIG. 3B illustrates formation of the second layer 114 .
- the second layer 114 is formed by pendeo-epitaxial growth so as to be cantilevered over the opening 152 of the trench 150 and the first layer 112 .
- Techniques for pendeo-epitaxial growth and/or epitaxial lateral overgrowth are known to those of skill in the art and need not be described further herein. However, examples of pendeo-epitaxial growth and/or epitaxial lateral overgrowth are described, for example, in U.S. Pat. Nos.
- the particular conditions for formation of the second layer 114 may depend on the composition of the second layer 114 .
- the growth may be oriented along different facets of the crystal structure so as to provide a higher degree of impurity incoroporation. Such an orientation may be provided, for example, by the orientation of the trench 150 and/or the mask 425 described below and/or the growth conditions such as temperature, ratio of source materials (e.g. ratio of Group III to Group V sources) and/or growth pressure.
- the second layer 114 may be grown in the presence of an n-type dopant, for example, for a GaN second layer 114 , Si, Ge and/or O may be incorporated in the second layer 114 so as to provide an n+ second layer 114 .
- the laterally grown portion may be more susceptible to incorporation of the dopant and, therefore, the laterally grown portions (illustrated by the dotted line in FIG. 2 ) may have a higher dopant concentration than the vertically grown portions of the second layer 114 .
- the second layer 114 is illustrated as an n+ layer, the dopant concentration and, accordingly, the carrier concentration, may differ in different regions of the second layer 114 .
- FIG. 3C illustrates the formation of the third layer 116 .
- the third layer 116 is also cantilevered over the opening 152 of the trench 150 .
- the third layer 116 may be formed by pendeo-epitaxial growth as described above.
- the third layer 116 is formed as insulating or p-type semiconductor material and may be formed in the presence of a small amount of n-type dopant, such as Si, by for example, including SiH 4 in the reaction chamber when the third layer 116 is grown.
- a p-type dopant such as Mg, Zn or Be, may be provided during formation of the third layer 116 .
- An insulating GaN layer may be formed in the absence of a dopant other than that discussed herein with regard to the n-type laterally grown region of the third layer 116 and/or in the presence of a compensating dopant, such as Fe.
- the quantity of n-type dopant provided may depend on the composition of the third layer 116 . However, the quantity should be sufficiently small so that the vertically grown portions of the third layer 116 are provided as p-type or insulating despite the presence of the n-type dopant (e.g.
- the p-type dopant or compensating dopant swamps the n-type dopant absent the preferential incorporation of n-type dopant provided by lateral growth) but sufficiently large so that the preferential incorporation of the n-type dopant in the laterally grown portions of the third layer 116 provide n-type regions.
- FIG. 3D illustrates formation of the fourth layer 118 .
- the fourth layer is formed by pendeo-epitaxial growth as discussed above and may be grown to cover the opening 152 of the trench 150 . Portions of the fourth layer 118 may be laterally grown to coalesce over the trench 150 .
- the fourth layer 118 is formed as an unintentionally doped layer and may be formed in the presence of a small amount of n-type dopant, such as Si, by for example, including SiH 4 in the reaction chamber when the fourth layer 118 is grown.
- the quantity of n-type dopant provided may depend on the composition of the fourth layer 118 .
- the quantity should be sufficiently small so that the vertically grown portions of the fourth layer 118 incorporate only an insubstantial amount of the n-type dopant and, thus, may be considered unintentionally doped.
- the quantity of n-type dopant should, however, be sufficiently large so that the preferential incorporation of the n-type dopant in the laterally grown portions of the fourth layer 118 provides n-type regions.
- FIG. 3E illustrates formation of the channel layer 120 and the barrier layer 122 .
- Such layers may be formed by conventional fabrication techniques based on the composition of the respective layers.
- a drain contact 134 , a source contact 132 and a gate contact 130 may be formed on the barrier layer utilizing conventional techniques as illustrated in FIG. 2 .
- the gate contact may be formed on a dielectric layer (not shown) on the barrier layer 122 .
- FIG. 4 illustrates a transistor according to further embodiments of the present invention.
- a first layer 412 of n-type semiconductor material is provided on a substrate 410 , such as an n-type semiconductor material substrate.
- the substrate 410 may be a silicon carbide substrate as described above with reference to the substrate 110 .
- the substrate 410 may be doped to provide a carrier concentration of from about 10 17 to about 10 20 cm ⁇ 3 .
- the substrate 410 may be an insulating or semi-insulating substrate.
- a contact may be provided to the n+ layer 414 , for example, in a trench or at a peripheral edge of the device as illustrated in FIG. 1 .
- a first layer 412 of n-type semiconductor material such as a nitride-based semiconductor material, is provided on a surface of the substrate 410 .
- the first layer 412 may, for example, may be AlGaN and may be doped with, for example, Si to provide an n-type layer of AlGaN.
- the first layer 412 has a thickness of from about 0 (i.e. is optional) to about 1 ⁇ m.
- the first layer 412 may also be doped to provide a carrier concentration of from about 10 17 to about 10 20 cm ⁇ 3 .
- a second layer 414 of n-type semiconductor material is provided on the first layer 412 .
- the second layer 414 may, for example, be an n+ GaN layer.
- the second layer 414 is provided on a first surface of the first layer 412 that is opposite the substrate 410 .
- the second layer 414 has a thickness of from about 0.1 ⁇ m to about 10 ⁇ m.
- the second layer 414 also may be doped to provide a carrier concentration of from about 10 17 to about 10 20 cm ⁇ 3 .
- Mask regions 425 are formed on the second layer 414 .
- the mask regions correspond to a region of the current aperture and, in some embodiments, may be provided sufficiently thin such that during the growth of the subsequent layers, the center is etched away leaving an interior opening.
- the mask regions 425 may suppress vertical growth from the second layer 414 .
- the mask regions 425 may be, for example, an oxide such as silicon dioxide.
- the first layer 412 and/or second layer 414 may be omitted.
- the substrate 410 is a GaN substrate
- the first layer 412 and/or the second layer 414 may be omitted and the mask 425 may be provided on the substrate 410 .
- a third layer 416 of n+ semiconductor material is provided on the second layer 414 and laterally overgrows at least a portion of the mask regions 425 .
- the third layer 416 does not completely cover the mask regions 425 and has spaced apart sidewalls.
- the third layer 416 may be n-type GaN formed as discussed above using epitaxial lateral overgrowth.
- the third layer 416 may be doped to provide a carrier concentration of, for example, from about 10 17 to about 10 20 cm ⁇ 3 .
- the third layer 416 may have a thickness of from about 0.1 ⁇ m to about 10 ⁇ m.
- a fourth layer 418 of p-type or insulating semiconductor material is provided on the third layer 416 and at least a portion of the mask regions 425 and has portions 419 of n-type semiconductor material that extend from the sidewalls of the third layer 416 .
- the fourth layer 418 may be provided as a hybrid layer.
- the fourth layer 418 does not extend completely across the mask regions 425 but includes spaced apart regions that have opposing sidewalls.
- the fourth layer 418 may be p-type or insulating GaN formed as discussed above, by epitaxial lateral overgrowth in the presence of an n-type dopant, such as Si, Ge or O, such that the portions 419 that are laterally grown are n-type GaN.
- the insulating and/or p-type regions of fourth layer 418 may substantially block current flow by, for example, having a Fermi level positioned at greater than about 0.5 eV from the conduction band.
- the portions 419 of the fourth layer 418 may be doped to provide a carrier concentration of, for example, from about 10 14 to about 10 19 cm ⁇ 3 .
- the fourth layer 418 may have a thickness of from about 0.1 ⁇ m to about 10 ⁇ m.
- a fifth layer 420 of unintentionally doped semiconductor material is provided on the fourth layer 418 .
- the fifth layer 420 has portions 421 of n-type semiconductor material that extend from the sidewalls of the fourth layer 418 .
- the fifth layer 420 may be provided as a hybrid layer.
- the fifth layer 420 extends completely between the sidewalls of the fourth layer 418 and may coalesce where portions extending from the sidewalls of the fourth layer 418 meet.
- the fifth layer 420 may be primarily unintentionally doped GaN formed as discussed elsewhere herein, by epitaxial lateral overgrowth in the presence of an n-type dopant, such as Si such that the portions 421 that are laterally grown are n-type GaN.
- the unintentionally doped regions of the fifth layer 420 may be lightly n-type or have a low net concentration of acceptors or deep levels.
- the portions 421 of the fifth layer 420 may be doped to provide a carrier concentration of, for example, from about 10 15 to about 10 20 cm ⁇ 3 .
- the fifth layer 420 may have a thickness of from about 0.1 ⁇ m to about 10 ⁇ m.
- a channel layer 422 and a barrier layer 424 may be provided on the fifth layer 420 .
- the channel layer 422 and the barrier layer 424 are configured so as to form a 2DEG near the interface between the channel layer 422 and the barrier layer 424 .
- the channel layer 422 and/or the barrier layer 424 may be provided by a single or multiple layers.
- the channel layer 422 is an unintentionally doped GaN layer.
- the barrier layer 424 may be an AlGaN and/or AlN layer.
- the channel layer 422 is GaN having a thickness of from about 5 mm to about 5000 nm and the barrier layer 424 is AlGaN having a concentration of aluminum of from about 5% to about 100% and having a thickness of from about 1 to about 10 nm.
- a gate contact 130 is provided on the barrier layer 424 and, in some embodiments, may be provided on an oxide (not shown) on the barrier layer 424 . In some embodiments of the present invention, at least a portion of the gate contact 130 overlaps with the region above the mask regions 425 . In some embodiments of the present invention, the gate contact 130 is confined to a region above the mask 425 and circumscribed by the mask 425 . In still further embodiments, the gate contact 130 may be provided without overlap of the mask 425 .
- the gate contact 130 may be formed of, for example, Ni/Au.
- a dielectric layer such as a silicon nitride or silicon oxide layer is provided on the barrier layer 424 .
- the gate contact 130 may be formed in a recess in the dielectric layer or, in some embodiments, may be formed on the dielectric layer.
- a source contact 132 is also provided on the barrier layer 424 .
- the source contact 132 may be provided on a recess in to the barrier layer 424 and/or on a contact region so as to reduce resistance between the source contact 132 and the channel layer 120 .
- the source contact 132 may be formed of, for example, Ti/Al/Ni/Au.
- a drain contact 134 is provided on the substrate 410 opposite the first layer 412 .
- a backside implant or epitaxial layer (not shown) may be provided so as to reduce resistance between the drain contact 134 and the substrate 410 .
- the backside implant or epitaxial layer may, for example, be an n+ region formed in or on the substrate 410 on which the drain contact 134 is provided.
- the substrate 410 may be thinned prior to formation of the drain contact 134 .
- the drain contact may be formed of, for example, nickel, if a silicon carbide substrate is used.
- the drain contact 134 may, optionally, be formed on the first layer 412 , similar to the configuration illustrated in FIG. 1 .
- an insulating substrate or a semi-insulating substrate such as semi-insulating silicon carbide or sapphire, may be utilized for the substrate 410 .
- electrons from the source contact 432 may flow along the 2DEG formed near the interface of the barrier layer 424 and the channel layer 422 and then vertically into the n-type portions 421 of the fifth layer 420 and then laterally across the n-type portion 419 of the fourth layer 418 to the n+ layer 416 , vertically to the n+ layer 414 and the first layer 412 and to the drain contact 134 through the substrate 410 .
- a current aperture may be provided by the p or i regions of the fourth layer 418 with a current path provided by the n-type regions incorporated in the laterally grown portions of the fourth layer 418 and the fifth layer 410 .
- the current aperture may also be defined by the mask 425 .
- a portion of the channel region of the device may be provided by a hybrid layer.
- the channel region through the current aperture may include a vertical portion through the fifth layer 420 and a horizontal portion through the fourth layer 418 .
- Current may also flow through the opening in the mask 425 is such opening is provided.
- the Schottky gate contact 130 (or MOS gate if an insulating layer provided on the barrier layer 424 ) may modulate the charge in the 2DEG to control the flow of current through the aperture.
- FIGS. 5A-5E Fabrication of embodiments of the present invention as illustrated in FIG. 4 is schematically illustrated in FIGS. 5A-5E .
- a substrate 410 is provided on which nitride based devices may be formed. Fabrication of the substrate 410 may be provided as discussed above with reference to the substrate 110 .
- the first layer 412 and the second layer 414 are sequentially formed on the substrate 410 .
- the first layer 412 and/or second layer 414 may be formed, for example, by plasma enhanced chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), low pressure chemical vapor deposition (LPCVD) or other technique known to those of skill in the art.
- PECVD plasma enhanced chemical vapor deposition
- MOCVD metal organic chemical vapor deposition
- MBE molecular beam epitaxy
- LPCVD low pressure chemical vapor deposition
- the particular deposition technique may depend on the composition of the first layer 412 and/or the second layer 414 .
- FIG. 5A further illustrates formation of the mask region 425 .
- the mask region 425 may, for example, be fabricated by depositing an oxide layer onto the second layer 414 and then selectively etching the deposited oxide layer, for example, using a subsequent etch mask, to provide the mask region 425 .
- a mask could be formed on the second layer 414 and the oxide layer selectively deposited in openings in the mask.
- Variable thickness of the mask regions 425 may result from etching of the mask during subsequent growth operations as a result of the high growth temperatures.
- the mask has a thickness such that an opening at the interior of the mask results from this etching. In other embodiments of the present invention, the thickness is such that a portion of the mask remains and no opening is formed.
- FIG. 5B illustrates formation of the third layer 416 .
- the third layer 416 is formed by epitaxial lateral overgrowth so as to extend partly over the mask region 425 and on the second layer 414 . Techniques for epitaxial lateral overgrowth are known to those of skill in the art and are described above. The particular conditions for formation of the third layer 416 may depend on the composition of the third layer 416 .
- the mask region 425 may be partially etched by the high temperature growth of the third layer 416 .
- the mask region 425 may have a tapered structure as the portions of the mask region 425 where no growth has occurred will be exposed and, therefore, etched for a longer period of time. Accordingly, in some embodiments of the present invention, the growth of the third layer 416 is carried out at a temperature sufficient to etch the mask region 425 .
- the third layer 416 may be grown in the presence of an n-type dopant, for example, for a GaN third layer 416 , Si, Ge or O may be incorporated in the third layer 416 so as to provide an n+ third layer 416 .
- the laterally grown portion may be more susceptible to incorporation of dopant and, therefore, the laterally grown portions (illustrated by the dotted line in FIG. 4 ) may have a higher dopant concentration than the vertically grown portions of the third layer 416 .
- the third layer 416 is illustrated as an n+ layer, the dopant and accordingly the carrier concentration, may differ in different regions of the second layer 416 .
- FIG. 5C illustrates the formation of the fourth layer 418 .
- the fourth layer 418 also extends over a portion of the mask region 425 .
- the fourth layer 418 may be formed by epitaxial lateral overgrowth as described above.
- the fourth layer 418 is formed as insulating or p-type semiconductor material and may be formed in the presence of a small amount of n-type dopant, such as Si, by for example, including SiH 4 in the reaction chamber when the fourth layer 418 is grown.
- a p-type dopant such as Mg, Zn or Be, may be provided during formation of the fourth layer 418 .
- An insulating GaN layer may be formed in the absence of a dopant other than that discussed herein with regard to the n-type laterally grown region of the fourth layer 418 and/or in the presence of a compensating dopant, such as Fe.
- the quantity of n-type dopant provided may depend on the composition of the fourth layer 418 . However, the quantity should be sufficiently small so that the vertically grown portions of the fourth layer 418 are provided as p-type or insulating despite the presence of the n-type dopant (e.g.
- the p-type dopant or compensating dopant swamps the n-type dopant absent the preferential incorporation of n-type dopant provided by lateral growth) but sufficiently large so that the preferential incorporation of the n-type dopant in the laterally grown portions 419 of the fourth layer 418 results in n-type regions.
- the mask region 425 may be further etched by the high temperature growth of the fourth layer 418 .
- the mask region 425 may have a tapered structure as the portions of the mask region 425 where no growth has occurred will be exposed and, therefore, etched for a longer period of time. Accordingly, in some embodiments of the present invention, the growth of the fourth layer 418 is carried out at a temperature sufficient to etch the mask region 425 .
- FIG. 5D illustrates formation of the fifth layer 420 .
- the fifth layer 420 is formed by epitaxial lateral overgrowth as discussed above and may be grown to cover the mask region 425 and the region between the mask regions 425 . Portions of the fifth layer 420 may be laterally grown to coalesce.
- the fifth layer 420 is formed as an unintentionally doped layer and may be formed in the presence of a small amount of n-type dopant, such as Si, by for example, including SiH 4 in the reaction chamber when the fifth layer 420 is grown.
- the quantity of n-type dopant provided may depend on the composition of the fifth layer 420 .
- the quantity should be sufficiently small so that the vertically grown portions of the fifth layer 420 incorporate only an insubstantial amount of the n-type dopant and, thus, may be considered unintentionally doped.
- the quantity of n-type dopant should, however, be sufficiently large so that the preferential incorporation of the n-type dopant in the laterally grown portions 421 of the fifth layer 420 results in n-type regions.
- the mask region 425 may be partially etched by the high temperature growth of the fifth layer 420 .
- the mask region 425 may be completely etched through in an interior portion.
- the mask region 425 may have a tapered structure as the portions of the mask region 425 where no growth has occurred will be exposed and, therefore, etched for a longer period of time. Accordingly, in some embodiments of the present invention, the growth of the fifth layer 420 is carried out at a temperature sufficient to etch the mask region 425 .
- FIG. 5E illustrates formation of the channel layer 422 and the barrier layer 424 .
- Such layers may be formed by conventional fabrication techniques based on the composition of the respective layers.
- a drain contact 134 , a source contact 132 and a gate contact 130 may be formed utilizing conventional techniques as illustrated in FIG. 4 .
- the gate contact may be formed on a dielectric layer (not shown) on the barrier layer 424 .
- an anneal or multiple anneals may be carried out to activate dopants and/or anneal contacts.
- Such annealing techniques are known to those of skill in the art and, therefore, need not be described further herein.
- FIG. 6 illustrates a transistor according to further embodiments of the present invention.
- the layer structure of the transistor may be formed and a trench subsequently formed through the layer structure and filled with n-type semiconductor material to provide the current aperture.
- a first layer 612 of n-type semiconductor material is provided on a substrate 610 , such as an n-type semiconductor material substrate.
- the substrate 610 may be a silicon carbide substrate as described above with reference to the substrate 110 .
- the substrate 610 may be doped to provide a carrier concentration of from about 10 17 to about 10 20 cm ⁇ 3 .
- the substrate 610 may be an insulating or semi-insulating substrate.
- a contact may be provided to the n+ layer 614 , for example, in a trench or at a peripheral edge of the device as illustrated in FIG. 1 .
- the first layer 612 may be omitted or provided as a buffer layer.
- a first layer 612 of n-type semiconductor material such as a nitride-based semiconductor material, is provided on a surface of the substrate 610 .
- the first layer 612 may, for example, may be AlGaN and may be doped with, for example, Si to provide an n-type layer of AlGaN.
- the first layer 612 has a thickness of from about 0 (i.e. the first layer is optional) to about 1 ⁇ m.
- the first layer 612 may also be doped to provide a carrier concentration of from about 10 17 to about 10 20 cm ⁇ 3 .
- a second layer 614 of n-type semiconductor material is provided on the first layer 612 .
- the second layer 614 may, for example, be an n+ GaN layer.
- the second layer 614 is provided on a first surface of the first layer 612 that is opposite the substrate 610 .
- the second layer 614 has a thickness of from about 0.1 ⁇ m to about 10 ⁇ m.
- the second layer 614 also may be doped to provide a carrier concentration of from about 10 17 to about 10 20 cm ⁇ 3 .
- a third layer 616 of p-type or insulating semiconductor material is provided on the second layer 614 .
- the third layer 616 may be p-type or insulating GaN formed as discussed above.
- the insulating and/or p-type regions of third layer 616 may substantially block current flow by, for example, having a Fermi level positioned at greater than about 0.5 eV from the conduction band.
- the third layer 616 may have a thickness of from about 0.1 ⁇ m to about 10 ⁇ m.
- a channel layer 618 and a barrier layer 620 may be provided on the third layer 616 .
- the channel layer 618 and the barrier layer 620 are configured so as to form a 2DEG near the interface between the channel layer 618 and the barrier layer 620 .
- the channel layer 618 and/or the barrier layer 620 may be provided by a single or multiple layers.
- the channel layer 618 is an unintentionally doped GaN layer.
- the barrier layer 620 may be an AlGaN and/or AlN layer.
- the channel layer 618 is GaN having a thickness of from about 5 nm to about 5 ⁇ m and the barrier layer 620 is AlGaN having a concentration of aluminum of from about 5% to about 100% and having a thickness of from about 1 nm to about 100 nm.
- a dielectric layer 626 such as a silicon nitride or silicon oxide layer is provided on the barrier layer 620 .
- a trench 622 is formed through the dielectric layer 626 , the barrier layer 620 , the channel layer 618 and the third layer 616 and extends to, and in some embodiments, into the second layer 614 .
- a region of n-type semiconductor material 624 such as a nitride-based semiconductor material, such as GaN, is provided in the trench 622 .
- the first layer 612 and/or second layer 614 may be omitted.
- the substrate 610 is a GaN substrate
- the first layer 612 and/or the second layer 614 may be omitted and the trench 622 may be provided to extend to and/or into the substrate 610 .
- a gate contact 630 is provided on the dielectric layer 626 and, in some embodiments, may be provided directly on the barrier layer 620 .
- the gate contact may be adjacent and spaced apart from the trench 622 .
- the gate contact 630 may be formed of, for example, Ni/Au.
- Source contact regions 628 may be provided of n-type semiconductor material, such as a nitride-based semiconductor material including, for example, GaN.
- the source contact regions 628 extend through the dielectric layer 626 to the barrier layer 620 .
- a source contact 632 is also provided on the barrier layer 620 .
- the source contact 632 may be provided on a recess in the barrier layer 620 .
- the source contact 632 may be formed of, for example, Ti/Al/Ni/Au.
- a drain contact 634 is provided on the substrate 610 opposite the first layer 612 .
- a backside implant (not shown) may be provided so as to reduce resistance between the drain contact 634 and the substrate 610 .
- the backside implant may, for example, be an n+ region formed in the substrate 610 on which the drain contact 634 is provided.
- the substrate 610 may be thinned prior to formation of the drain contact 634 .
- the drain contact may be formed of, for example, nickel, for a silicon carbide substrate.
- the drain contact 634 may, optionally, be formed on the first layer 612 or the second layer 614 , similar to the configuration illustrated in FIG. 1 .
- an insulating substrate or a semi-insulating substrate such as semi-insulating silicon carbide or sapphire, may be utilized for the substrate 610 .
- electrons from the source contact 632 may flow from the n-type contact regions 628 along the 2DEG formed near the interface of the barrier layer 620 and the channel layer 618 and then into the n-type region 624 to the n+ layer 614 and the first layer 612 and to the drain contact 634 through the substrate 610 .
- the gate contact 630 (or Schottky gate if an insulating layer is not provided on the barrier layer 620 ) may modulate the charge in the 2DEG to control the flow of current through the aperture.
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Abstract
Transistors and/or methods of fabricating transistors that include a source contact, drain contact and gate contact are provided. In some embodiments, a channel region is provided between the source and drain contacts and at least a portion of the channel regions includes a hybrid layer comprising semiconductor material. In particular embodiments of the present invention, the transistor is a current aperture transistor. The channel region may include pendeo-epitaxial layers or epitaxial laterally overgrown layers. Transistors and methods of fabricating current aperture transistors that include a trench that extends through the channel and barrier layers and includes semiconductor material therein are also provided.
Description
- The present application is a divisional of and claims priority from co-pending U.S. application Ser. No. 10/849,589, filed May 20, 2004, entitled “SEMICONDUCTOR DEVICES HAVING A HYBRID CHANNEL LAYER, CURRENT APERTURE TRANSISTORS AND METHODS OF FABRICATING SAME,” which is assigned to the assignee of the present application, the disclosure of which is hereby incorporated herein by reference as if set forth fully.
- The present invention relates to semiconductor devices and, more particularly, to current aperture transistors.
- In high voltage/high power electronic devices, a performance characteristic of importance may be the breakdown characteristics of the device. For example, the maximum reverse bias blocking voltage sustainable by the device may limit the potential applications for the device. In conventional transistors, the structure of the device may result in a breakdown voltage that is less than the breakdown voltage of the device. For example, in a conventional U-metal oxide semiconductor field effect transistor (UMOSFET), field crowding may result at a corner of the gate trench such that breakdown occurs in the region of the field crowding rather than in the bulk material. Various structures have been proposed in different types of transistors to provide breakdown voltages of the transistors that approach the bulk breakdown voltage of the materials used in the transistors.
- Current aperture transistors have been proposed as a potential approach to achieve near bulk breakdown limits in nitride-based devices.
FIG. 1 illustrates a conventionalcurrent aperture transistor 10. As seen inFIG. 1 , thecurrent aperture transistor 10 includes a silicon dopedGaN drain layer 12 with spaced apart regions of insulatingGaN 14 that form thecurrent aperture region 30. Thecurrent aperture region 30 is part of a regrown unintentionally dopedGaN layer 16 that has an AlGaNlayer 18 formed thereon so that a two-dimensional electron gas (2DEG) forms at the interface between the unintentionally dopedGaN layer 16 and theAlGaN layer 18. Agate contact 24 and asource contact 22 are provided on the AlGaNlayer 18 and adrain contact 26 is provided on the silicon dopedGaN layer 12. - In operation, electrons from the source contact 22 flow along the 2DEG and through the
current aperture 30 to thedrain contact 26. The Schottkygate contact 24 modulates the charge in the 2DEG to control the flow of current through the aperture. Because the pinched off region is located beneath the gate, substantial charge does not accumulate at the gate edge. Thus, the high field region may be buried in the bulk material. Further details on current aperture transistors may be found in Ben-Yaacov et al., “AlGaN/GaN current aperture vertical electron transistors with regrown channels”, Journal of Applied Physics, Vol. 95, No. 4, 15 Feb. 2004, pp. 2073-78. - Some embodiments of the present invention provide transistors and/or methods of fabrication of transistors that include a source contact, drain contact and gate contact. A channel region is provided between the source and drain contacts and at least a portion of the channel regions includes a hybrid layer of semiconductor material. In particular embodiments of the present invention, the transistor is a current aperture transistor.
- In further embodiments of the present invention, the hybrid layer of semiconductor material includes a Group III-nitride semiconductor material. The hybrid layer of semiconductor material may also include a region of p-type or insulating semiconductor material and a region of n-type semiconductor material. A portion of the channel region through the current aperture may include a vertical portion and a horizontal portion. The hybrid layer may include a pendeo-epitaxial layer having a higher doping level in the laterally grown portions of the pendeo-epitaxial layer. The hybrid layer may include a epitaxial laterally overgrown layer having a higher doping level in the laterally grown portions of the epitaxial laterally overgrown layer.
- In additional embodiments of the present invention, the transistor includes a first n-type nitride-based layer on a substrate. The first n-type nitride-based layer has a first surface opposite the substrate and an aperture having sidewalls. A nitride-based layer is provided on the first n-type nitride-based layer and extends onto the sidewalls of the aperture. A portion of the nitride-based layer on the sidewalls of the aperture is n-type and a portion of the nitride-based layer on the first surface of the second n-type nitride-based layer is p-type and/or insulating. An unintentionally doped nitride-based layer is provided on the nitride based layer and extends to substantially fill the aperture. The unintentionally doped nitride-based layer has portions of n-type nitride-based semiconductor material on the n-type portions of the nitride-based layer. First and second layers of nitride-based semiconductor material are provided on the unintentionally doped nitride-based layer and are configured to provide a two-dimensional electron gas (2DEG) in a region of an interface between the first and second semiconductor material layers. The source contact and the gate contact are provided on the second layer of nitride-based semiconductor material and the drain contact is electrically connected to the first n-type nitride-based layer.
- In additional embodiments of the present invention, a second n-type nitride-based layer is provided between the first n-type nitride-based layer and the substrate.
- In still further embodiments of the present invention, the substrate has a trench formed therein and the first n-type nitride-based layer, the nitride based layer and the unintentionally doped nitride-based layer are cantilevered over the trench.
- In other embodiments of the present invention, a mask region is provided on the substrate or the second n-type nitride-based layer if present and a portion of the first n-type nitride-based layer, the nitride based layer and the unintentionally doped nitride-based layer extend onto the mask region.
- Additional embodiments of the present invention include a third n-type nitride-based layer between the second nitride-based layer and the substrate. The substrate may be a silicon carbide substrate and the drain contact may be provided on the substrate opposite the first n-type nitride-based layer. An insulating layer may also be provided between the gate contact and the second layer.
- In some embodiments of the present invention, the first n-type nitride-based layer includes a GaN based layer, the second n-type nitride-based layer includes a GaN based layer, the nitride-based layer on the second n-type nitride-based layer includes a GaN based layer, the unintentionally doped nitride-based layer includes a GaN based layer, the first layer includes an unintentionally doped GaN based layer and the second layer includes an AlGaN and/or INAlN based layer. The substrate may also be a GaN substrate.
- In still further embodiments of the present invention, transistors and/or methods of fabricating transistors that include a substrate having a trench therein and a first pendeo-epitaxial layer of semiconductor material of the first conductivity type is provided on the substrate is provided. The first pendeo-epitaxial layer has spaced apart cantilevered portions that extend over the trench. A second pendeo-epitaxial layer of semiconductor material of a second conductivity type and/or insulating is provided on the first pendeo-epitaxial layer of semiconductor material and includes spaced apart portions that extend from end surfaces of the cantilevered portions of the first pendeo-epitaxial layer that are the first conductivity type. A third pendeo-epitaxial layer of unintentionally doped semiconductor material is provided on the second pendeo-epitaxial layer and includes portions that extend from the spaced apart portions and coalesce and are the first conductivity type. A channel layer of semiconductor material is provided on the third pendeo-epitaxial layer and a barrier layer is provided on the channel layer. A source contact and a gate contact are provided on the barrier layer. A drain contact is electrically connected to the first layer of conformal semiconductor material.
- In additional embodiments of the present invention, a first layer of conformal semiconductor material of a first conductivity type is provided on the substrate and the trench. The first pendeo-epitaxial layer may be provided on the first layer.
- In further embodiments of the present invention, the first conductivity type is n-type and the second conductivity type is p-type. The semiconductor material may include a nitride-based semiconductor material. The substrate may be a GaN substrate. The substrate may also be silicon carbide. The silicon carbide substrate may be the first conductivity type and the drain contact may be provided on the silicon carbide substrate. The nitride-based semiconductor material may include a GaN based semiconductor material.
- In yet further embodiments of the present invention, transistors and methods of fabricating transistors that include a mask region on a substrate are provided. A first epitaxial laterally overgrown layer of semiconductor material of the first conductivity type is provided on the substrate and at least a portion of the mask region. A second epitaxial laterally overgrown layer of semiconductor material of a second conductivity type and/or insulating is provided on the first epitaxial laterally overgrown layer of semiconductor material and at least a portion of the mask region and includes spaced apart portions that extend from end surfaces of the portions of the first epitaxial laterally overgrown layer on the mask region that are the first conductivity type. A third epitaxial laterally overgrown layer of unintentionally doped semiconductor material is provided on the second epitaxial laterally overgrown layer and includes portions that extend from the spaced apart portions and coalesce and are the first conductivity type. A channel layer of semiconductor material is provided on the third epitaxial laterally overgrown layer. A barrier layer is provided on the channel layer. A source contact and a gate contact are provided on the barrier layer. A drain contact is electrically connected to the first layer of semiconductor material.
- In further embodiments of the present invention, a first layer of semiconductor material of a first conductivity type is provided between the substrate and the first epitaxial laterally overgrown layer. The mask region may be provided on the first layer.
- In additional embodiments of the present invention, the first conductivity type is n-type and the second conductivity type is p-type. The semiconductor material may be a nitride-based semiconductor material. The substrate may be silicon carbide and/or GaN. The silicon carbide substrate may be the first conductivity type and the drain contact may be provided on the silicon carbide substrate. The nitride-based semiconductor material may be a GaN based semiconductor material.
- Still further embodiments of the present invention provided current aperture transistors and methods of fabricating current aperture transistors that include a first layer of semiconductor material of a second conductivity type or insulating on a substrate. A channel layer of semiconductor material is provided on the second layer. A barrier layer is provided on the channel layer. A trench extends through the barrier layer, the channel layer and the first layer. The trench includes semiconductor material of the first conductivity type therein. A gate contact and a source contact are provided on the barrier layer. The source contact is on the barrier layer and opposite the trench from the gate contact. A drain contact is electrically connected to the first layer.
- In additional embodiments of the present invention, a second layer of semiconductor material of a first conductivity type is provided between the substrate and the first layer of semiconductor material. In such embodiments, the trench may extend through the first layer to and/or into the second layer.
- In some embodiments of the present invention, the first conductivity type is n-type and the second conductivity type is p-type. The semiconductor material may be a nitride-based semiconductor material. The substrate may be GaN. The substrate may also be silicon carbide. The silicon carbide substrate may be the first conductivity type and the drain contact may be provided on the silicon carbide substrate opposite the first layer of semiconductor material. The nitride-based semiconductor material may be a GaN based semiconductor material. An insulating layer may be provided between the gate contact and the barrier layer. Contact regions of semiconductor material of the first conductivity type may be provided between the source contact and the barrier layer. The trench may extend into the first layer. A third layer of semiconductor material of the first conductivity type may be disposed between the substrate and the first layer of semiconductor material.
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FIG. 1 is a schematic drawing of a conventional current aperture transistor. -
FIG. 2 is a schematic drawing of current aperture transistors according to some embodiments of the present invention. -
FIGS. 3A-3E are schematic drawings illustrating fabrication of current aperture transistors as illustrated inFIG. 2 . -
FIG. 4 is a schematic drawing of current aperture transistors according to further embodiments of the present invention. -
FIGS. 5A-5E are schematic drawings illustrating fabrication of current aperture transistors as illustrated inFIG. 4 . -
FIG. 6 is a schematic drawing illustrating a current aperture transistor according to further embodiments of the present invention. - The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. It will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
- It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
- Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in the Figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The exemplary term “lower”, can therefore, encompass both an orientation of “lower” and “upper,” depending of the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The exemplary terms “below” or “beneath” can, therefore, encompass both an orientation of above and below.
- Embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments of the present invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a grown or deposited region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of concentrations at its edges with another region rather than a binary change from a first region to a second region of different composition. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present invention.
- Some embodiments of the present invention provide vertical transistors that have a current aperture that is at least partially horizontal and methods of forming such transistors. In some embodiments of the present invention, the current aperture is laterally grown, for example, through lateral pendeo-epitaxial growth and/or through epitaxial lateral overgrowth (ELO). In some embodiments of the present invention, the use of lateral growth allows for the formation of a layer of semiconductor material having differing regions of conductivity types and/or differing conductivities as a result of the preferential incorporation of dopants in the laterally grown regions of the device. Such a single layer having differing lateral regions that are formed as part of a single growth or deposition process are referred to herein as a “hybrid layer.” Hybrid layers may be distinguished from layers that have a substantially uniform conductivity type and/or conductivity in a lateral direction or layers that are formed of a substantially uniform conductivity type and/or conductivity that are subsequently processed by, for example, ion implantation and/or diffusion to alter the characteristics of a portion of the layer. Some embodiments of the present invention provide a transistor having at least a portion of the channel of the transistor provided by a hybrid layer.
- Embodiments of the present invention may be suited for use in nitride-based vertical current aperture transistors, such as Group III-nitride based devices. As used herein, the term “Group III nitride” refers to those semiconducting compounds formed between nitrogen and the elements in Group III of the periodic table, usually aluminum (Al), gallium (Ga), and/or indium (In). The term also refers to ternary and quaternary compounds such as AlGaN and AlInGaN. As is well understood by those in this art, the Group III elements can combine with nitrogen to form binary (e.g., GaN), ternary (e.g., AlGaN, AlInN), and quaternary (e.g., AlInGaN) compounds. These compounds all have empirical formulas in which one mole of nitrogen is combined with a total of one mole of the Group III elements. Accordingly, formulas such as AlxGa1-xN where 0≦x≦1 are often used to describe them.
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FIG. 2 is a schematic cross sectional illustration of a current aperture transistor according to some embodiments of the present invention. As illustrated inFIG. 2 , asubstrate 110, such as a silicon carbide substrate, has atrench 150 formed therein. In some embodiments of the present invention, the trench may be from about 1 μm to about 20 μm deep and from about 0.5 μm to about 10 μm wide. As discussed below, thesubstrate 110 may be an n-type semiconductor material. Thesubstrate 110 may be doped to provide a carrier concentration of from about 1017 to about 1020 cm−3. Alternatively, thesubstrate 110 may be an insulating or semi-insulating substrate. In such a case, a contact may be provided to then+ layer 112, for example, in a trench or at a peripheral edge of the device as illustrated inFIG. 1 . - As is further illustrated in
FIG. 2 , afirst layer 112 of n-type semiconductor material, such as a nitride-based semiconductor material, is provided on a surface of thesubstrate 110 and, in some embodiments, in thetrench 150. Thefirst layer 112 may, for example, be AlGaN and may be doped with, for example, Si, Ge and/or O to provide an n+ layer of AlGaN. In some embodiments of the present invention, thefirst layer 112 has a thickness of from about 0 (i.e. is an optional layer) to about 1 μm. Thefirst layer 112 may also be doped to provide a carrier concentration of from about 1017 to about 1020 cm−3. In some embodiments of the present invention where thesubstrate 110 is a GaN based substrate, such as a GaN substrate, thefirst layer 112 may be omitted. - A
second layer 114 of n-type semiconductor material is provided on the first layer 112 (or the substrate if the first layer is omitted) and is cantilevered over thetrench 150. Thesecond layer 114 may, for example, be an n+ GaN layer and may be formed as discussed below, by pendeo-epitaxial growth. Thesecond layer 114 is provided on a first surface of thefirst layer 112 that is opposite thesubstrate 110 and does not extend completely across thetrench 150 but includes spaced apart regions that have opposing sidewalls. In some embodiments of the present invention, thesecond layer 114 has a thickness of from about 0.1 μm to about 5 μm. Thesecond layer 114 also may be doped with an n-type dopant, such as Si, Ge and/or O, to provide a carrier concentration of from about 1017 to about 1020 cm−3. - A
third layer 116 of p-type and/or insulating semiconductor material is provided on thesecond layer 114 and hasportions 117 of n-type semiconductor material that extend from the sidewalls of thesecond layer 114. Thus, thethird layer 116 may be provided as a hybrid layer. Thethird layer 116 does not extend completely across thetrench 150 but includes spaced apart regions that have opposing sidewalls. In some embodiments of the present invention, thethird layer 116 may be p-type or insulating GaN formed as discussed below, by pendeo-epitaxial growth in the presence of an n-type dopant, such as Si, Ge and/or O, such that theportions 117 that are laterally grown are n-type GaN. The insulating and/or p-type regions ofthird layer 116 may substantially block current flow by, for example, having a Fermi level positioned at greater than about 0.5 eV from the conduction band. Theportions 117 of thethird layer 116 may be doped to provide a carrier concentration of, for example, from about 1014 to about 1019 cm−3. Thethird layer 116 may have a thickness of from about 0.1 μm to about 10 μm. - As is further illustrated in
FIG. 2 , afourth layer 118 of unintentionally doped semiconductor material is provided on thethird layer 116. As discussed below, the unintentionally doped semiconductor material may be lightly doped. Thefourth layer 118 hasportions 119 of n-type semiconductor material that extend from the sidewalls of thethird layer 116. Thus, thefourth layer 118 may be provided as a hybrid layer. In some embodiments, thefourth layer 118 extends completely across thetrench 150 and may coalesce where theportions 119 extending from the sidewalls of thethird layer 116 meet. Thus, a hole oropening 152 may be provided by the trench beneath thefourth layer 118. In some embodiments of the present invention, thefourth layer 118 may be primarily unintentionally doped GaN formed as discussed below, by pendeo-epitaxial growth in the presence of an n-type dopant, such as Si, Ge and/or O such that theportions 119 that are laterally grown are n-type GaN. The n-type dopants may be affirmatively supplied and/or may be unintentional, for example, the n-type may be provided as a by-product of a prior processing step and/or contamination. The unintentionally doped regions of thefourth layer 118 may be lightly n-type or have a low net concentration of acceptors or deep levels. Theportions 119 of thefourth layer 118 may be doped to provide a carrier concentration of, for example, from about 1015 to about 1020 cm−3. Thefourth layer 118 may have a thickness of from about 0.1 μm to about 10 μm. - A
channel layer 120 and abarrier layer 122 may be provided on thefourth layer 118. Thechannel layer 120 and thebarrier layer 122 are configured so as to form a 2DEG near the interface between thechannel layer 120 and thebarrier layer 122. Thechannel layer 120 and/or thebarrier layer 122 may be provided by a single or multiple layers. In some embodiments of the present invention, thechannel layer 120 is an unintentionally doped GaN layer. Thebarrier layer 122 may be an AlGaN and/or AlN layer. In some embodiments of the present invention, thechannel layer 120 is GaN having a thickness of from about 5 m to about 5000 nm and thebarrier layer 122 is AlGaN having a concentration of aluminum of from about 5% to about 100% and having a thickness of from about 1 nm to about 100 nm. - A
gate contact 130 is provided on thebarrier layer 122 and, in some embodiments, may be provided on an oxide (not shown) on thebarrier layer 122. In some embodiments of the present invention, at least a portion of thegate contact 130 overlaps with thetrench 150. In some embodiments of the present invention, thegate contact 130 is confined to a region above thetrench 150. In still further embodiments, thegate contact 130 may be provided without overlap of thetrench 150. Thegate contact 130 may be formed of, for example, Ni/Au. - Optionally, a dielectric layer, such as a silicon nitride or silicon oxide layer is provided on the
barrier layer 122. In such embodiments, thegate contact 130 may be formed in a recess in the dielectric layer or, in some embodiments, may be formed on the dielectric layer. - A
source contact 132 is also provided on thebarrier layer 122. Optionally, thesource contact 132 may be provided on a recess into thebarrier layer 122 and/or on a contact region so as to reduce resistance between thesource contact 132 and thechannel layer 120. Thesource contact 132 may be formed of, for example, Ti/Al/Ni/Au. - A
drain contact 134 is provided on thesubstrate 110 opposite thefirst layer 112. Optionally, a backside implant or epitaxial layer (not shown) may be provided so as to reduce resistance between thedrain contact 134 and thesubstrate 110. The backside implant or epitaxial layer may, for example, be an n+ region formed in or on thesubstrate 110 on which thedrain contact 134 is provided. Furthermore, thesubstrate 110 may be thinned prior to formation of thedrain contact 134. The drain contact may be formed of, for example, nickel if a silicon carbide substrate is used. As discussed above, thedrain contact 134 may, optionally, be formed on thefirst layer 112, similar to the configuration illustrated inFIG. 1 . In such embodiments of the present invention, an insulating substrate or a semi-insulating substrate, such as semi-insulating silicon carbide or sapphire, may be utilized for thesubstrate 110. - Without wishing to be bound by any theory of operation, electrons from the
source contact 132 may flow along the 2DEG formed near the interface of thebarrier layer 122 and thechannel layer 120 and then vertically into the n-type portions 119 of thefourth layer 118 and then laterally across the n-type portion 117 of thethird layer 116 to then+ layer 114, vertically to then+ layer 112 and to thedrain contact 134 through thesubstrate 110. Thus, a current aperture may be provided by the p or i regions of thethird layer 116 with a current path provided by the n-type regions incorporated in the laterally grown portions of thethird layer 116 and thefourth layer 118. Thehole 152 may also define the current aperture. Accordingly, a portion of the channel region of the device may be provided by a hybrid layer. Furthermore, the channel region through the current aperture may include a vertical portion through thefourth layer 118 and a horizontal portion through thethird layer 116. The Schottky gate contact 130 (or MOS gate if an insulating layer provided on the barrier layer 122) may modulate the charge in the 2DEG to control the flow of current through the aperture. - Fabrication of embodiments of the present invention as illustrated in
FIG. 2 is schematically illustrated inFIGS. 3A-3E . As seen inFIG. 3A , asubstrate 110 is provided on which nitride based devices may be formed. In particular embodiments of the present invention, thesubstrate 110 may be an n-type silicon carbide (SiC) substrate that may be, for example, 4H polytype of silicon carbide. Other silicon carbide candidate polytypes include the 3C, 6H, and 15R polytypes. Appropriate SiC substrates are manufactured by, for example, Cree, Inc., of Durham, N.C., the assignee of the present invention, and methods for producing are described, for example, in U.S. Pat. Nos. Re. 34,861; 4,946,547; 5,200,022; and 6,218,680, the contents of which are incorporated herein by reference in their entirety. Similarly, techniques for epitaxial growth of Group III nitrides have been described in, for example, U.S. Pat. Nos. 5,210,051; 5,393,993; 5,523,589; and 5,292,501, the contents of which are also incorporated herein by reference in their entirety. - Optional buffer, nucleation and/or transition layers (not shown) may be provided on the
substrate 110. - Although silicon carbide may be a preferred substrate material, embodiments of the present invention may utilize any suitable substrate, such as sapphire, aluminum nitride, aluminum gallium nitride, gallium nitride, silicon, GaAs, LGO, ZnO, LAO, InP and the like. In some embodiments, an appropriate buffer layer also may be formed. In devices having an insulating or semi-insulating substrate, a second contact may be formed in a recess that extends to a drain layer opposite the current aperture from the gate.
- As is further illustrated in
FIG. 3A , atrench 150 is formed in thesubstrate 110, for example, by masking and etching thesubstrate 110. A dry etch, wet etch or other etch technique known to those of skill in the art may be utilized. The particular etch technique may depend on the substrate material. For example, in some embodiments of the present invention, a reactive ion etch may be utilized for a silicon carbide substrate. Other techniques for patterning the substrate to form a trench may also be utilized. For example, the trench could be provided by a saw cut or laser removal of material. - The
first layer 112 is blanket formed on thesubstrate 110 including in thetrench 150. Thefirst layer 112 is formed conformally so as to maintain theopening 152 formed by thetrench 150. Thefirst layer 112 may be formed, for example, by plasma enhanced chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), low pressure chemical vapor deposition (LPCVD) or other technique known to those of skill in the art. The particular deposition technique may depend on the composition of thefirst layer 112 and whether or not buffer layers such as those described above are utilized. - In some embodiments of the present invention, the
first layer 112 may be omitted. For example, if thesubstrate 110 is a GaN substrate, thefirst layer 112 may be omitted and the trench may be formed in the GaN substrate. -
FIG. 3B illustrates formation of thesecond layer 114. Thesecond layer 114 is formed by pendeo-epitaxial growth so as to be cantilevered over the opening 152 of thetrench 150 and thefirst layer 112. Techniques for pendeo-epitaxial growth and/or epitaxial lateral overgrowth are known to those of skill in the art and need not be described further herein. However, examples of pendeo-epitaxial growth and/or epitaxial lateral overgrowth are described, for example, in U.S. Pat. Nos. 6,582,906, 6,706,114, 6,686,261, 6,621,148, 6,608,327, 6,602,764, 6,602,763, 6,586,778, 6,582,986, 6,570,192, 6,545,300, 6,521,514, 6,489,221, 6,486,042, 6,462,355, 6,380,108, 6,376,339, 6,261,929, 6,255,198, 6,177,688 and 6,051,849, the disclosures of which are incorporated herein by reference as if set forth fully herein. The particular conditions for formation of thesecond layer 114 may depend on the composition of thesecond layer 114. Furthermore, the growth may be oriented along different facets of the crystal structure so as to provide a higher degree of impurity incoroporation. Such an orientation may be provided, for example, by the orientation of thetrench 150 and/or themask 425 described below and/or the growth conditions such as temperature, ratio of source materials (e.g. ratio of Group III to Group V sources) and/or growth pressure. - The
second layer 114 may be grown in the presence of an n-type dopant, for example, for a GaNsecond layer 114, Si, Ge and/or O may be incorporated in thesecond layer 114 so as to provide an n+second layer 114. During lateral growth of thesecond layer 114, the laterally grown portion may be more susceptible to incorporation of the dopant and, therefore, the laterally grown portions (illustrated by the dotted line inFIG. 2 ) may have a higher dopant concentration than the vertically grown portions of thesecond layer 114. Thus, while thesecond layer 114 is illustrated as an n+ layer, the dopant concentration and, accordingly, the carrier concentration, may differ in different regions of thesecond layer 114. -
FIG. 3C illustrates the formation of thethird layer 116. Thethird layer 116 is also cantilevered over the opening 152 of thetrench 150. Thethird layer 116 may be formed by pendeo-epitaxial growth as described above. Thethird layer 116 is formed as insulating or p-type semiconductor material and may be formed in the presence of a small amount of n-type dopant, such as Si, by for example, including SiH4 in the reaction chamber when thethird layer 116 is grown. For a GaN based layer, a p-type dopant, such as Mg, Zn or Be, may may be provided during formation of thethird layer 116. An insulating GaN layer may be formed in the absence of a dopant other than that discussed herein with regard to the n-type laterally grown region of thethird layer 116 and/or in the presence of a compensating dopant, such as Fe. The quantity of n-type dopant provided may depend on the composition of thethird layer 116. However, the quantity should be sufficiently small so that the vertically grown portions of thethird layer 116 are provided as p-type or insulating despite the presence of the n-type dopant (e.g. the p-type dopant or compensating dopant swamps the n-type dopant absent the preferential incorporation of n-type dopant provided by lateral growth) but sufficiently large so that the preferential incorporation of the n-type dopant in the laterally grown portions of thethird layer 116 provide n-type regions. -
FIG. 3D illustrates formation of thefourth layer 118. The fourth layer is formed by pendeo-epitaxial growth as discussed above and may be grown to cover theopening 152 of thetrench 150. Portions of thefourth layer 118 may be laterally grown to coalesce over thetrench 150. Thefourth layer 118 is formed as an unintentionally doped layer and may be formed in the presence of a small amount of n-type dopant, such as Si, by for example, including SiH4 in the reaction chamber when thefourth layer 118 is grown. The quantity of n-type dopant provided may depend on the composition of thefourth layer 118. However, the quantity should be sufficiently small so that the vertically grown portions of thefourth layer 118 incorporate only an insubstantial amount of the n-type dopant and, thus, may be considered unintentionally doped. The quantity of n-type dopant should, however, be sufficiently large so that the preferential incorporation of the n-type dopant in the laterally grown portions of thefourth layer 118 provides n-type regions. -
FIG. 3E illustrates formation of thechannel layer 120 and thebarrier layer 122. Such layers may be formed by conventional fabrication techniques based on the composition of the respective layers. Adrain contact 134, asource contact 132 and agate contact 130 may be formed on the barrier layer utilizing conventional techniques as illustrated inFIG. 2 . In some embodiments of the present invention, the gate contact may be formed on a dielectric layer (not shown) on thebarrier layer 122. -
FIG. 4 illustrates a transistor according to further embodiments of the present invention. As seen inFIG. 4 , afirst layer 412 of n-type semiconductor material is provided on asubstrate 410, such as an n-type semiconductor material substrate. Thesubstrate 410 may be a silicon carbide substrate as described above with reference to thesubstrate 110. Thesubstrate 410 may be doped to provide a carrier concentration of from about 1017 to about 1020 cm−3. Alternatively, thesubstrate 410 may be an insulating or semi-insulating substrate. In such a case, a contact may be provided to then+ layer 414, for example, in a trench or at a peripheral edge of the device as illustrated inFIG. 1 . - As is further illustrated in
FIG. 4 , afirst layer 412 of n-type semiconductor material, such as a nitride-based semiconductor material, is provided on a surface of thesubstrate 410. Thefirst layer 412 may, for example, may be AlGaN and may be doped with, for example, Si to provide an n-type layer of AlGaN. In some embodiments of the present invention, thefirst layer 412 has a thickness of from about 0 (i.e. is optional) to about 1 μm. Thefirst layer 412 may also be doped to provide a carrier concentration of from about 1017 to about 1020 cm−3. - A
second layer 414 of n-type semiconductor material is provided on thefirst layer 412. Thesecond layer 414 may, for example, be an n+ GaN layer. Thesecond layer 414 is provided on a first surface of thefirst layer 412 that is opposite thesubstrate 410. In some embodiments of the present invention, thesecond layer 414 has a thickness of from about 0.1 μm to about 10 μm. Thesecond layer 414 also may be doped to provide a carrier concentration of from about 1017 to about 1020 cm−3. -
Mask regions 425 are formed on thesecond layer 414. The mask regions correspond to a region of the current aperture and, in some embodiments, may be provided sufficiently thin such that during the growth of the subsequent layers, the center is etched away leaving an interior opening. Themask regions 425 may suppress vertical growth from thesecond layer 414. Themask regions 425 may be, for example, an oxide such as silicon dioxide. - In some embodiments of the present invention, the
first layer 412 and/orsecond layer 414 may be omitted. For example, if thesubstrate 410 is a GaN substrate, thefirst layer 412 and/or thesecond layer 414 may be omitted and themask 425 may be provided on thesubstrate 410. Athird layer 416 of n+ semiconductor material is provided on thesecond layer 414 and laterally overgrows at least a portion of themask regions 425. Thethird layer 416 does not completely cover themask regions 425 and has spaced apart sidewalls. In some embodiments of the present invention, thethird layer 416 may be n-type GaN formed as discussed above using epitaxial lateral overgrowth. Thethird layer 416 may be doped to provide a carrier concentration of, for example, from about 1017 to about 1020 cm−3. Thethird layer 416 may have a thickness of from about 0.1 μm to about 10 μm. - A
fourth layer 418 of p-type or insulating semiconductor material is provided on thethird layer 416 and at least a portion of themask regions 425 and hasportions 419 of n-type semiconductor material that extend from the sidewalls of thethird layer 416. Thus, thefourth layer 418 may be provided as a hybrid layer. Thefourth layer 418 does not extend completely across themask regions 425 but includes spaced apart regions that have opposing sidewalls. In some embodiments of the present invention, thefourth layer 418 may be p-type or insulating GaN formed as discussed above, by epitaxial lateral overgrowth in the presence of an n-type dopant, such as Si, Ge or O, such that theportions 419 that are laterally grown are n-type GaN. The insulating and/or p-type regions offourth layer 418 may substantially block current flow by, for example, having a Fermi level positioned at greater than about 0.5 eV from the conduction band. Theportions 419 of thefourth layer 418 may be doped to provide a carrier concentration of, for example, from about 1014 to about 1019 cm−3. Thefourth layer 418 may have a thickness of from about 0.1 μm to about 10 μm. - As is further illustrated in
FIG. 4 , afifth layer 420 of unintentionally doped semiconductor material is provided on thefourth layer 418. Thefifth layer 420 hasportions 421 of n-type semiconductor material that extend from the sidewalls of thefourth layer 418. Thus, thefifth layer 420 may be provided as a hybrid layer. In some embodiments, thefifth layer 420 extends completely between the sidewalls of thefourth layer 418 and may coalesce where portions extending from the sidewalls of thefourth layer 418 meet. In some embodiments of the present invention, thefifth layer 420 may be primarily unintentionally doped GaN formed as discussed elsewhere herein, by epitaxial lateral overgrowth in the presence of an n-type dopant, such as Si such that theportions 421 that are laterally grown are n-type GaN. The unintentionally doped regions of thefifth layer 420 may be lightly n-type or have a low net concentration of acceptors or deep levels. Theportions 421 of thefifth layer 420 may be doped to provide a carrier concentration of, for example, from about 1015 to about 1020 cm−3. Thefifth layer 420 may have a thickness of from about 0.1 μm to about 10 μm. - A
channel layer 422 and abarrier layer 424 may be provided on thefifth layer 420. Thechannel layer 422 and thebarrier layer 424 are configured so as to form a 2DEG near the interface between thechannel layer 422 and thebarrier layer 424. Thechannel layer 422 and/or thebarrier layer 424 may be provided by a single or multiple layers. In some embodiments of the present invention, thechannel layer 422 is an unintentionally doped GaN layer. Thebarrier layer 424 may be an AlGaN and/or AlN layer. In some embodiments of the present invention, thechannel layer 422 is GaN having a thickness of from about 5 mm to about 5000 nm and thebarrier layer 424 is AlGaN having a concentration of aluminum of from about 5% to about 100% and having a thickness of from about 1 to about 10 nm. - A
gate contact 130 is provided on thebarrier layer 424 and, in some embodiments, may be provided on an oxide (not shown) on thebarrier layer 424. In some embodiments of the present invention, at least a portion of thegate contact 130 overlaps with the region above themask regions 425. In some embodiments of the present invention, thegate contact 130 is confined to a region above themask 425 and circumscribed by themask 425. In still further embodiments, thegate contact 130 may be provided without overlap of themask 425. Thegate contact 130 may be formed of, for example, Ni/Au. - Optionally, a dielectric layer, such as a silicon nitride or silicon oxide layer is provided on the
barrier layer 424. In such embodiments, thegate contact 130 may be formed in a recess in the dielectric layer or, in some embodiments, may be formed on the dielectric layer. - A
source contact 132 is also provided on thebarrier layer 424. Optionally, thesource contact 132 may be provided on a recess in to thebarrier layer 424 and/or on a contact region so as to reduce resistance between thesource contact 132 and thechannel layer 120. Thesource contact 132 may be formed of, for example, Ti/Al/Ni/Au. - A
drain contact 134 is provided on thesubstrate 410 opposite thefirst layer 412. Optionally, a backside implant or epitaxial layer (not shown) may be provided so as to reduce resistance between thedrain contact 134 and thesubstrate 410. The backside implant or epitaxial layer may, for example, be an n+ region formed in or on thesubstrate 410 on which thedrain contact 134 is provided. Furthermore, thesubstrate 410 may be thinned prior to formation of thedrain contact 134. The drain contact may be formed of, for example, nickel, if a silicon carbide substrate is used. As discussed above, thedrain contact 134 may, optionally, be formed on thefirst layer 412, similar to the configuration illustrated inFIG. 1 . In such embodiments of the present invention, an insulating substrate or a semi-insulating substrate, such as semi-insulating silicon carbide or sapphire, may be utilized for thesubstrate 410. - Without wishing to be bound by any theory of operation, electrons from the source contact 432 may flow along the 2DEG formed near the interface of the
barrier layer 424 and thechannel layer 422 and then vertically into the n-type portions 421 of thefifth layer 420 and then laterally across the n-type portion 419 of thefourth layer 418 to then+ layer 416, vertically to then+ layer 414 and thefirst layer 412 and to thedrain contact 134 through thesubstrate 410. Thus, a current aperture may be provided by the p or i regions of thefourth layer 418 with a current path provided by the n-type regions incorporated in the laterally grown portions of thefourth layer 418 and thefifth layer 410. The current aperture may also be defined by themask 425. - Accordingly, a portion of the channel region of the device may be provided by a hybrid layer. Furthermore, the channel region through the current aperture may include a vertical portion through the
fifth layer 420 and a horizontal portion through thefourth layer 418. Current may also flow through the opening in themask 425 is such opening is provided. The Schottky gate contact 130 (or MOS gate if an insulating layer provided on the barrier layer 424) may modulate the charge in the 2DEG to control the flow of current through the aperture. - Fabrication of embodiments of the present invention as illustrated in
FIG. 4 is schematically illustrated inFIGS. 5A-5E . As seen inFIG. 5A , asubstrate 410 is provided on which nitride based devices may be formed. Fabrication of thesubstrate 410 may be provided as discussed above with reference to thesubstrate 110. - The
first layer 412 and thesecond layer 414 are sequentially formed on thesubstrate 410. Thefirst layer 412 and/orsecond layer 414 may be formed, for example, by plasma enhanced chemical vapor deposition (PECVD), metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), low pressure chemical vapor deposition (LPCVD) or other technique known to those of skill in the art. The particular deposition technique may depend on the composition of thefirst layer 412 and/or thesecond layer 414. -
FIG. 5A further illustrates formation of themask region 425. Themask region 425 may, for example, be fabricated by depositing an oxide layer onto thesecond layer 414 and then selectively etching the deposited oxide layer, for example, using a subsequent etch mask, to provide themask region 425. Alternatively or additionally, a mask could be formed on thesecond layer 414 and the oxide layer selectively deposited in openings in the mask. Variable thickness of themask regions 425 may result from etching of the mask during subsequent growth operations as a result of the high growth temperatures. In some embodiments of the present invention, the mask has a thickness such that an opening at the interior of the mask results from this etching. In other embodiments of the present invention, the thickness is such that a portion of the mask remains and no opening is formed. -
FIG. 5B illustrates formation of thethird layer 416. Thethird layer 416 is formed by epitaxial lateral overgrowth so as to extend partly over themask region 425 and on thesecond layer 414. Techniques for epitaxial lateral overgrowth are known to those of skill in the art and are described above. The particular conditions for formation of thethird layer 416 may depend on the composition of thethird layer 416. As is further seen inFIG. 5B , themask region 425 may be partially etched by the high temperature growth of thethird layer 416. Thus, themask region 425 may have a tapered structure as the portions of themask region 425 where no growth has occurred will be exposed and, therefore, etched for a longer period of time. Accordingly, in some embodiments of the present invention, the growth of thethird layer 416 is carried out at a temperature sufficient to etch themask region 425. - The
third layer 416 may be grown in the presence of an n-type dopant, for example, for a GaNthird layer 416, Si, Ge or O may be incorporated in thethird layer 416 so as to provide an n+third layer 416. During lateral growth of thethird layer 416, the laterally grown portion may be more susceptible to incorporation of dopant and, therefore, the laterally grown portions (illustrated by the dotted line inFIG. 4 ) may have a higher dopant concentration than the vertically grown portions of thethird layer 416. Thus, while thethird layer 416 is illustrated as an n+ layer, the dopant and accordingly the carrier concentration, may differ in different regions of thesecond layer 416. -
FIG. 5C illustrates the formation of thefourth layer 418. Thefourth layer 418 also extends over a portion of themask region 425. Thefourth layer 418 may be formed by epitaxial lateral overgrowth as described above. Thefourth layer 418 is formed as insulating or p-type semiconductor material and may be formed in the presence of a small amount of n-type dopant, such as Si, by for example, including SiH4 in the reaction chamber when thefourth layer 418 is grown. For a GaN based layer, a p-type dopant, such as Mg, Zn or Be, may be provided during formation of thefourth layer 418. An insulating GaN layer may be formed in the absence of a dopant other than that discussed herein with regard to the n-type laterally grown region of thefourth layer 418 and/or in the presence of a compensating dopant, such as Fe. The quantity of n-type dopant provided may depend on the composition of thefourth layer 418. However, the quantity should be sufficiently small so that the vertically grown portions of thefourth layer 418 are provided as p-type or insulating despite the presence of the n-type dopant (e.g. the p-type dopant or compensating dopant swamps the n-type dopant absent the preferential incorporation of n-type dopant provided by lateral growth) but sufficiently large so that the preferential incorporation of the n-type dopant in the laterally grownportions 419 of thefourth layer 418 results in n-type regions. - As is further seen in
FIG. 5C , themask region 425 may be further etched by the high temperature growth of thefourth layer 418. Thus, themask region 425 may have a tapered structure as the portions of themask region 425 where no growth has occurred will be exposed and, therefore, etched for a longer period of time. Accordingly, in some embodiments of the present invention, the growth of thefourth layer 418 is carried out at a temperature sufficient to etch themask region 425. -
FIG. 5D illustrates formation of thefifth layer 420. Thefifth layer 420 is formed by epitaxial lateral overgrowth as discussed above and may be grown to cover themask region 425 and the region between themask regions 425. Portions of thefifth layer 420 may be laterally grown to coalesce. Thefifth layer 420 is formed as an unintentionally doped layer and may be formed in the presence of a small amount of n-type dopant, such as Si, by for example, including SiH4 in the reaction chamber when thefifth layer 420 is grown. The quantity of n-type dopant provided may depend on the composition of thefifth layer 420. However, the quantity should be sufficiently small so that the vertically grown portions of thefifth layer 420 incorporate only an insubstantial amount of the n-type dopant and, thus, may be considered unintentionally doped. The quantity of n-type dopant should, however, be sufficiently large so that the preferential incorporation of the n-type dopant in the laterally grownportions 421 of thefifth layer 420 results in n-type regions. - As is further seen in
FIG. 5D , themask region 425 may be partially etched by the high temperature growth of thefifth layer 420. In some embodiments, themask region 425 may be completely etched through in an interior portion. Thus, themask region 425 may have a tapered structure as the portions of themask region 425 where no growth has occurred will be exposed and, therefore, etched for a longer period of time. Accordingly, in some embodiments of the present invention, the growth of thefifth layer 420 is carried out at a temperature sufficient to etch themask region 425. -
FIG. 5E illustrates formation of thechannel layer 422 and thebarrier layer 424. Such layers may be formed by conventional fabrication techniques based on the composition of the respective layers. Adrain contact 134, asource contact 132 and agate contact 130 may be formed utilizing conventional techniques as illustrated inFIG. 4 . In some embodiments of the present invention, the gate contact may be formed on a dielectric layer (not shown) on thebarrier layer 424. - Depending on the particular composition of the layers/regions and/or contacts illustrated in FIGS. 2, 3A-3E, 4 and/or 5A-5E, an anneal or multiple anneals may be carried out to activate dopants and/or anneal contacts. Such annealing techniques are known to those of skill in the art and, therefore, need not be described further herein.
-
FIG. 6 illustrates a transistor according to further embodiments of the present invention. InFIG. 6 , the layer structure of the transistor may be formed and a trench subsequently formed through the layer structure and filled with n-type semiconductor material to provide the current aperture. As seen inFIG. 6 , afirst layer 612 of n-type semiconductor material is provided on asubstrate 610, such as an n-type semiconductor material substrate. Thesubstrate 610 may be a silicon carbide substrate as described above with reference to thesubstrate 110. Thesubstrate 610 may be doped to provide a carrier concentration of from about 1017 to about 1020 cm−3. Alternatively, thesubstrate 610 may be an insulating or semi-insulating substrate. In such a case, a contact may be provided to then+ layer 614, for example, in a trench or at a peripheral edge of the device as illustrated inFIG. 1 . In such embodiments, thefirst layer 612 may be omitted or provided as a buffer layer. - As is further illustrated in
FIG. 6 , afirst layer 612 of n-type semiconductor material, such as a nitride-based semiconductor material, is provided on a surface of thesubstrate 610. Thefirst layer 612 may, for example, may be AlGaN and may be doped with, for example, Si to provide an n-type layer of AlGaN. In some embodiments of the present invention, thefirst layer 612 has a thickness of from about 0 (i.e. the first layer is optional) to about 1 μm. Thefirst layer 612 may also be doped to provide a carrier concentration of from about 1017 to about 1020 cm−3. - A
second layer 614 of n-type semiconductor material is provided on thefirst layer 612. Thesecond layer 614 may, for example, be an n+ GaN layer. Thesecond layer 614 is provided on a first surface of thefirst layer 612 that is opposite thesubstrate 610. In some embodiments of the present invention, thesecond layer 614 has a thickness of from about 0.1 μm to about 10 μm. Thesecond layer 614 also may be doped to provide a carrier concentration of from about 1017 to about 1020 cm−3. - A
third layer 616 of p-type or insulating semiconductor material is provided on thesecond layer 614. In some embodiments of the present invention, thethird layer 616 may be p-type or insulating GaN formed as discussed above. The insulating and/or p-type regions ofthird layer 616 may substantially block current flow by, for example, having a Fermi level positioned at greater than about 0.5 eV from the conduction band. Thethird layer 616 may have a thickness of from about 0.1 μm to about 10 μm. - A
channel layer 618 and abarrier layer 620 may be provided on thethird layer 616. Thechannel layer 618 and thebarrier layer 620 are configured so as to form a 2DEG near the interface between thechannel layer 618 and thebarrier layer 620. Thechannel layer 618 and/or thebarrier layer 620 may be provided by a single or multiple layers. In some embodiments of the present invention, thechannel layer 618 is an unintentionally doped GaN layer. Thebarrier layer 620 may be an AlGaN and/or AlN layer. In some embodiments of the present invention, thechannel layer 618 is GaN having a thickness of from about 5 nm to about 5 μm and thebarrier layer 620 is AlGaN having a concentration of aluminum of from about 5% to about 100% and having a thickness of from about 1 nm to about 100 nm. - Optionally, a
dielectric layer 626, such as a silicon nitride or silicon oxide layer is provided on thebarrier layer 620. Atrench 622 is formed through thedielectric layer 626, thebarrier layer 620, thechannel layer 618 and thethird layer 616 and extends to, and in some embodiments, into thesecond layer 614. A region of n-type semiconductor material 624, such as a nitride-based semiconductor material, such as GaN, is provided in thetrench 622. - In some embodiments of the present invention, the
first layer 612 and/orsecond layer 614 may be omitted. For example, if thesubstrate 610 is a GaN substrate, thefirst layer 612 and/or thesecond layer 614 may be omitted and thetrench 622 may be provided to extend to and/or into thesubstrate 610. - A
gate contact 630 is provided on thedielectric layer 626 and, in some embodiments, may be provided directly on thebarrier layer 620. The gate contact may be adjacent and spaced apart from thetrench 622. Thegate contact 630 may be formed of, for example, Ni/Au. -
Source contact regions 628 may be provided of n-type semiconductor material, such as a nitride-based semiconductor material including, for example, GaN. Thesource contact regions 628 extend through thedielectric layer 626 to thebarrier layer 620. Asource contact 632 is also provided on thebarrier layer 620. Optionally, thesource contact 632 may be provided on a recess in thebarrier layer 620. Thesource contact 632 may be formed of, for example, Ti/Al/Ni/Au. - A
drain contact 634 is provided on thesubstrate 610 opposite thefirst layer 612. Optionally, a backside implant (not shown) may be provided so as to reduce resistance between thedrain contact 634 and thesubstrate 610. The backside implant may, for example, be an n+ region formed in thesubstrate 610 on which thedrain contact 634 is provided. Furthermore, thesubstrate 610 may be thinned prior to formation of thedrain contact 634. The drain contact may be formed of, for example, nickel, for a silicon carbide substrate. As discussed above, thedrain contact 634 may, optionally, be formed on thefirst layer 612 or thesecond layer 614, similar to the configuration illustrated inFIG. 1 . In such embodiments of the present invention, an insulating substrate or a semi-insulating substrate, such as semi-insulating silicon carbide or sapphire, may be utilized for thesubstrate 610. - Without wishing to be bound by any theory of operation, electrons from the
source contact 632 may flow from the n-type contact regions 628 along the 2DEG formed near the interface of thebarrier layer 620 and thechannel layer 618 and then into the n-type region 624 to then+ layer 614 and thefirst layer 612 and to thedrain contact 634 through thesubstrate 610. The gate contact 630 (or Schottky gate if an insulating layer is not provided on the barrier layer 620) may modulate the charge in the 2DEG to control the flow of current through the aperture. - In the drawings and specification, there have been disclosed typical embodiments of the invention, and, although specific terms have been employed, they have been used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
Claims (40)
1. A transistor comprising:
a mask region on a substrate;
a first epitaxial laterally overgrown layer comprising semiconductor material of a first conductivity type on the substrate and at least a portion of the mask region;
a second epitaxial laterally overgrown layer comprising semiconductor material of a second conductivity type and/or insulating on the first epitaxial laterally overgrown layer comprising semiconductor material and at least a portion of the mask region and that includes spaced apart portions that extend from end surfaces of the portions of the first epitaxial laterally overgrown layer on the mask region that are the first conductivity type;
a third epitaxial laterally overgrown layer comprising unintentionally doped semiconductor material on the second epitaxial laterally overgrown layer and that includes portions that extend from the spaced apart portions and coalesce and are the first conductivity type;
a channel layer comprising semiconductor material on the third epitaxial laterally overgrown layer;
a barrier layer on the channel layer;
a source contact on the barrier layer;
a gate contact on the barrier layer; and
a drain contact electrically connected to the first layer comprising semiconductor material.
2. The transistor of claim 1 , further comprising a first layer comprising semiconductor material comprising the first conductivity type on the substrate and wherein the mask region is on the first layer and the first epitaxial laterally overgrown layer is provided on the first layer.
3. The transistor of claim 1 , wherein the first conductivity type is n-type and the second conductivity type is p-type.
4. The transistor of claim 1 , wherein the semiconductor material comprises a nitride-based semiconductor material.
5. The transistor of claim 4 , wherein the substrate comprises gallium nitride.
6. The transistor of claim 4 , wherein the substrate comprises silicon carbide.
7. The transistor of claim 6 , wherein the silicon carbide substrate is the first conductivity type and wherein the drain contact is provided on the silicon carbide substrate.
8. The transistor of claim 4 , wherein the nitride-based semiconductor material comprises a GaN based semiconductor material.
9. A current aperture transistor comprising:
a first layer comprising semiconductor material of a second conductivity type or insulating on a substrate;
a channel layer comprising semiconductor material on the second layer;
a barrier layer on the channel layer;
a trench extending through the barrier layer, the channel layer and the first layer, the trench including semiconductor material of a first conductivity type therein;
a gate contact on the barrier layer;
a source contact on the barrier layer and opposite the trench from the gate contact; and
a drain contact electrically connected to the first layer.
10. The transistor of claim 9 , further comprising a second layer comprising semiconductor material of the first conductivity type on the substrate between the substrate and the first layer; and wherein the trench extends to the second layer.
11. The transistor of claim 9 , wherein the first conductivity type is n-type and the second conductivity type is p-type.
12. The transistor of claim 9 , wherein the semiconductor material comprises a nitride-based semiconductor material.
13. The transistor of claim 12 , wherein the substrate comprises gallium nitride.
14. The transistor of claim 12 , wherein the substrate comprises silicon carbide.
15. The transistor of claim 14 , wherein the silicon carbide substrate is the first conductivity type and wherein the drain contact is provided on the silicon carbide substrate.
16. The transistor of claim 9 , wherein the nitride-based semiconductor material comprises a GaN based semiconductor material.
17. The transistor of claim 9 , further comprising an insulating layer between the gate contact and the barrier layer.
18. The transistor of claim 9 , further comprising contact regions of semiconductor material of the first conductivity type between the source contact and the barrier layer.
19. The transistor of claim 10 , wherein the trench extends into the first layer.
20. The transistor of claim 10 , further comprising a third layer comprising semiconductor material of the first conductivity type disposed between the substrate and the second layer comprising semiconductor material.
21. A method of fabricating a transistor comprising:
forming a mask region on a substrate;
forming a first epitaxial laterally overgrown layer comprising semiconductor material of a first conductivity type by epitaxial lateral overgrowth on the first layer comprising semiconductor material and at least a portion of the mask region;
forming a second epitaxial laterally overgrown layer comprising semiconductor material of a second conductivity type and/or insulating by epitaxial lateral overgrowth on the first epitaxial laterally overgrown layer comprising semiconductor material and at least a portion of the mask region and that includes spaced apart portions that extend from end surfaces of the portions of the first epitaxial laterally overgrown layer on the mask region that are the first conductivity type;
forming a third epitaxial laterally overgrown layer comprising unintentionally doped semiconductor material by epitaxial lateral overgrowth on the second epitaxial laterally overgrown layer and that includes portions that extend from the spaced apart portions and coalesce and are the first conductivity type;
forming a channel layer comprising semiconductor material on the third epitaxial laterally overgrown layer;
forming a barrier layer on the channel layer;
forming a source contact on the barrier layer;
forming a gate contact on the barrier layer; and
forming a drain contact electrically connected to the first layer comprising semiconductor material.
22. The method of claim 21 , further comprising forming a first layer comprising semiconductor material of a first conductivity type on the substrate, wherein forming a mask region comprises forming a mask region on the first layer and wherein forming a first epitaxial laterally overgrown layer comprises forming a first epitaxial laterally overgrown layer on the first layer.
23. The method of claim 21 , wherein the first conductivity type is n-type and the second conductivity type is p-type.
24. The method of claim 21 , wherein the semiconductor material comprises a nitride-based semiconductor material.
25. The method of claim 24 , wherein the substrate comprises gallium nitride.
26. The method of claim 24 , wherein the substrate comprises silicon carbide.
27. The method of claim 26 , wherein the silicon carbide substrate is the first conductivity type and wherein forming the drain contact comprises forming the drain contact on the silicon carbide substrate.
28. The method of claim 24 , wherein the nitride-based semiconductor material comprises a GaN based semiconductor material.
29. A method of fabricating a current aperture transistor comprising:
forming a first layer comprising semiconductor material of a second conductivity type or insulating on a substrate;
forming a channel layer comprising semiconductor material on the second layer;
forming a barrier layer on the channel layer;
forming a trench extending through the barrier layer, the channel layer and the first layer,
forming a region of semiconductor material of the first conductivity type in the trench;
forming a gate contact on the barrier layer;
forming a source contact on the barrier layer and opposite the trench from the gate contact; and
forming a drain contact electrically connected to the first layer.
30. The method of claim 29 , further comprising forming a second layer comprising semiconductor material of a first conductivity type on a substrate, wherein forming a first layer comprises forming a first layer on the second layer and wherein forming a trench comprises forming a trench extending through the barrier layer, the channel layer and the first layer and to the second layer.
31. The method of claim 29 , wherein the first conductivity type is n-type and the second conductivity type is p-type.
32. The method of claim 29 , wherein the semiconductor material comprises a nitride-based semiconductor material.
33. The method of claim 32 , wherein the substrate comprises gallium nitride.
34. The method of claim 32 , wherein the substrate comprises silicon carbide.
35. The method of claim 34 , wherein the silicon carbide substrate is the first conductivity type and wherein forming the drain contact comprises forming the drain contact on the silicon carbide substrate.
36. The method of claim 32 , wherein the nitride-based semiconductor material comprises a GaN based semiconductor material.
37. The method of claim 29 , further comprising forming an insulating layer between the gate contact and the barrier layer.
38. The method of claim 29 , further comprising forming contact regions of semiconductor material of the first conductivity type between the source contact and the barrier layer.
39. The method of claim 30 , wherein the trench extends into the second layer.
40. The method of claim 30 , further comprising forming a third layer comprising semiconductor material of the first conductivity type disposed between the substrate and the second layer comprising semiconductor material.
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8603871B2 (en) | 2007-02-27 | 2013-12-10 | Fujitsu Limited | Compound semiconductor device and its manufacture method |
US20160359030A1 (en) * | 2008-04-23 | 2016-12-08 | Transphorm Inc. | Enhancement Mode III-N HEMTs |
US9711404B2 (en) * | 2015-03-16 | 2017-07-18 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
Families Citing this family (69)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7612390B2 (en) * | 2004-02-05 | 2009-11-03 | Cree, Inc. | Heterojunction transistors including energy barriers |
US20060017064A1 (en) * | 2004-07-26 | 2006-01-26 | Saxler Adam W | Nitride-based transistors having laterally grown active region and methods of fabricating same |
JP2006114886A (en) * | 2004-09-14 | 2006-04-27 | Showa Denko Kk | N-type group iii nitride semiconductor lamination structure |
US7456443B2 (en) * | 2004-11-23 | 2008-11-25 | Cree, Inc. | Transistors having buried n-type and p-type regions beneath the source region |
US7709859B2 (en) | 2004-11-23 | 2010-05-04 | Cree, Inc. | Cap layers including aluminum nitride for nitride-based transistors |
JP5087818B2 (en) * | 2005-03-25 | 2012-12-05 | 日亜化学工業株式会社 | Field effect transistor |
US9153645B2 (en) | 2005-05-17 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
US8324660B2 (en) | 2005-05-17 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
US7326971B2 (en) * | 2005-06-08 | 2008-02-05 | Cree, Inc. | Gallium nitride based high-electron mobility devices |
US7485512B2 (en) * | 2005-06-08 | 2009-02-03 | Cree, Inc. | Method of manufacturing an adaptive AIGaN buffer layer |
US7364988B2 (en) * | 2005-06-08 | 2008-04-29 | Cree, Inc. | Method of manufacturing gallium nitride based high-electron mobility devices |
US9331192B2 (en) * | 2005-06-29 | 2016-05-03 | Cree, Inc. | Low dislocation density group III nitride layers on silicon carbide substrates and methods of making the same |
US20070018198A1 (en) * | 2005-07-20 | 2007-01-25 | Brandes George R | High electron mobility electronic device structures comprising native substrates and methods for making the same |
US20070054467A1 (en) * | 2005-09-07 | 2007-03-08 | Amberwave Systems Corporation | Methods for integrating lattice-mismatched semiconductor structure on insulators |
US7777250B2 (en) | 2006-03-24 | 2010-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures and related methods for device fabrication |
US7388236B2 (en) * | 2006-03-29 | 2008-06-17 | Cree, Inc. | High efficiency and/or high power density wide bandgap transistors |
KR100735496B1 (en) * | 2006-05-10 | 2007-07-04 | 삼성전기주식회사 | Method for forming the vertically structured gan type light emitting diode device |
US9040398B2 (en) * | 2006-05-16 | 2015-05-26 | Cree, Inc. | Method of fabricating seminconductor devices including self aligned refractory contacts |
JP2008053448A (en) * | 2006-08-24 | 2008-03-06 | Rohm Co Ltd | Mis-type field effect transistor and manufacturing method thereof |
EP2062290B1 (en) | 2006-09-07 | 2019-08-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Defect reduction using aspect ratio trapping |
US7875958B2 (en) | 2006-09-27 | 2011-01-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures |
WO2008039495A1 (en) | 2006-09-27 | 2008-04-03 | Amberwave Systems Corporation | Tri-gate field-effect transistors formed by aspect ratio trapping |
US20080187018A1 (en) | 2006-10-19 | 2008-08-07 | Amberwave Systems Corporation | Distributed feedback lasers formed via aspect ratio trapping |
US8823057B2 (en) | 2006-11-06 | 2014-09-02 | Cree, Inc. | Semiconductor devices including implanted regions for providing low-resistance contact to buried layers and related devices |
US7692263B2 (en) | 2006-11-21 | 2010-04-06 | Cree, Inc. | High voltage GaN transistors |
US8878245B2 (en) * | 2006-11-30 | 2014-11-04 | Cree, Inc. | Transistors and method for making ohmic contact to transistors |
US7821032B2 (en) * | 2007-01-26 | 2010-10-26 | International Rectifier Corporation | III-nitride power semiconductor device |
US7825328B2 (en) | 2007-04-09 | 2010-11-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nitride-based multi-junction solar cell modules and methods for making the same |
US9508890B2 (en) | 2007-04-09 | 2016-11-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Photovoltaics on silicon |
US8304805B2 (en) | 2009-01-09 | 2012-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor diodes fabricated by aspect ratio trapping with coalesced films |
US8237151B2 (en) | 2009-01-09 | 2012-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Diode-based devices and methods for making the same |
US9484499B2 (en) * | 2007-04-20 | 2016-11-01 | Cree, Inc. | Transparent ohmic contacts on light emitting diodes with carrier substrates |
US8329541B2 (en) | 2007-06-15 | 2012-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | InP-based transistor fabrication |
WO2009007943A1 (en) * | 2007-07-09 | 2009-01-15 | Freescale Semiconductor, Inc. | Hetero-structure field effect transistor, integrated circuit including a hetero-structure field effect transistor and method for manufacturing a hetero-structure field effect transistor |
JP5208463B2 (en) * | 2007-08-09 | 2013-06-12 | ローム株式会社 | Nitride semiconductor device and method for manufacturing nitride semiconductor device |
US8344242B2 (en) | 2007-09-07 | 2013-01-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-junction solar cells |
US8368100B2 (en) | 2007-11-14 | 2013-02-05 | Cree, Inc. | Semiconductor light emitting diodes having reflective structures and methods of fabricating same |
US8183667B2 (en) | 2008-06-03 | 2012-05-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Epitaxial growth of crystalline material |
US8274097B2 (en) | 2008-07-01 | 2012-09-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduction of edge effects from aspect ratio trapping |
US8981427B2 (en) | 2008-07-15 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Polishing of small composite semiconductor materials |
WO2010016212A1 (en) * | 2008-08-06 | 2010-02-11 | 日本電気株式会社 | Field effect transistor manufacturing method |
WO2010016213A1 (en) * | 2008-08-06 | 2010-02-11 | 日本電気株式会社 | Field effect transistor |
EP2528087B1 (en) | 2008-09-19 | 2016-06-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation of devices by epitaxial layer overgrowth |
US20100072515A1 (en) | 2008-09-19 | 2010-03-25 | Amberwave Systems Corporation | Fabrication and structures of crystalline material |
US8253211B2 (en) | 2008-09-24 | 2012-08-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor sensor structures with reduced dislocation defect densities |
CN102197468B (en) * | 2008-10-29 | 2014-04-02 | 富士通株式会社 | Compound semiconductor device and method for manufacturing the same |
JP2010123899A (en) * | 2008-11-21 | 2010-06-03 | Panasonic Corp | Field-effect transistor |
JP5564791B2 (en) * | 2008-12-26 | 2014-08-06 | 富士通株式会社 | Compound semiconductor device and manufacturing method thereof |
WO2010114956A1 (en) | 2009-04-02 | 2010-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices formed from a non-polar plane of a crystalline material and method of making the same |
US8741715B2 (en) * | 2009-04-29 | 2014-06-03 | Cree, Inc. | Gate electrodes for millimeter-wave operation and methods of fabrication |
JP5568891B2 (en) * | 2009-06-03 | 2014-08-13 | 日本電気株式会社 | Heterojunction field effect transistor and manufacturing method thereof |
US20100314695A1 (en) * | 2009-06-10 | 2010-12-16 | International Rectifier Corporation | Self-aligned vertical group III-V transistor and method for fabricated same |
US9312343B2 (en) * | 2009-10-13 | 2016-04-12 | Cree, Inc. | Transistors with semiconductor interconnection layers and semiconductor channel layers of different semiconductor materials |
KR101774933B1 (en) * | 2010-03-02 | 2017-09-06 | 삼성전자 주식회사 | High Electron Mobility Transistor representing dual depletion and method of manufacturing the same |
CN102820369B (en) * | 2012-08-30 | 2014-10-29 | 中山大学 | Three-family nitride-based phototransistor and manufacturing method thereof |
JP6143598B2 (en) * | 2013-08-01 | 2017-06-07 | 株式会社東芝 | Semiconductor device |
JP2015056556A (en) * | 2013-09-12 | 2015-03-23 | 株式会社東芝 | Semiconductor device |
KR102021887B1 (en) * | 2013-12-09 | 2019-09-17 | 삼성전자주식회사 | Semiconductor device |
US9450079B2 (en) | 2014-04-09 | 2016-09-20 | International Business Machines Corporation | FinFET having highly doped source and drain regions |
WO2015176002A1 (en) * | 2014-05-15 | 2015-11-19 | The Regents Of The University Of California | Doping in iii-nitride devices |
USD826871S1 (en) | 2014-12-11 | 2018-08-28 | Cree, Inc. | Light emitting diode device |
CN104701359B (en) * | 2015-03-10 | 2018-02-02 | 苏州能屋电子科技有限公司 | Vertical stratification AlGaN/GaN HEMT devices and preparation method thereof |
CN104659082B (en) * | 2015-03-12 | 2018-02-02 | 苏州能屋电子科技有限公司 | Vertical stratification AlGaN/GaN HEMT devices and preparation method thereof |
US9998109B1 (en) * | 2017-05-15 | 2018-06-12 | Cree, Inc. | Power module with improved reliability |
JP7013710B2 (en) * | 2017-08-07 | 2022-02-01 | 住友電気工業株式会社 | Manufacturing method of nitride semiconductor transistor |
CN110875372B (en) * | 2018-09-03 | 2023-11-07 | 苏州捷芯威半导体有限公司 | Field effect transistor and manufacturing method thereof |
CN111682067B (en) * | 2020-06-23 | 2023-04-25 | 东南大学 | High electron mobility transistor with lateral depletion region |
US20230078017A1 (en) * | 2021-09-16 | 2023-03-16 | Wolfspeed, Inc. | Semiconductor device incorporating a substrate recess |
WO2024000431A1 (en) * | 2022-06-30 | 2024-01-04 | 广东致能科技有限公司 | Semiconductor device and manufacturing method therefor |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4916498A (en) * | 1985-09-15 | 1990-04-10 | Trw Inc. | High electron mobility power transistor |
US5831295A (en) * | 1995-12-01 | 1998-11-03 | Motorola, Inc. | Current confinement via defect generator and hetero-interface interaction |
US20030089930A1 (en) * | 2001-11-09 | 2003-05-15 | Zhao Jian Hui | Double-gated vertical junction field effect power transistor |
Family Cites Families (81)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2465317A2 (en) * | 1979-03-28 | 1981-03-20 | Thomson Csf | FIELD EFFECT TRANSISTOR WITH HIGH BREAKAGE FREQUENCY |
DE3072175D1 (en) * | 1979-12-28 | 1990-04-26 | Fujitsu Ltd | SEMICONDUCTOR DEVICES WITH HETEROUITION. |
JPH088350B2 (en) * | 1985-04-08 | 1996-01-29 | 日本電気株式会社 | Semiconductor device |
US4755867A (en) * | 1986-08-15 | 1988-07-05 | American Telephone And Telegraph Company, At&T Bell Laboratories | Vertical Enhancement-mode Group III-V compound MISFETs |
US4788156A (en) * | 1986-09-24 | 1988-11-29 | Microwave Technology, Inc. | Subchannel doping to reduce short-gate effects in field effect transistors |
US4866005A (en) * | 1987-10-26 | 1989-09-12 | North Carolina State University | Sublimation of silicon carbide to produce large, device quality single crystals of silicon carbide |
US5411914A (en) | 1988-02-19 | 1995-05-02 | Massachusetts Institute Of Technology | III-V based integrated circuits having low temperature growth buffer or passivation layers |
EP0334006A1 (en) | 1988-02-22 | 1989-09-27 | Siemens Aktiengesellschaft | Stacked channel heterojunction fet |
US5416354A (en) * | 1989-01-06 | 1995-05-16 | Unitrode Corporation | Inverted epitaxial process semiconductor devices |
US4946547A (en) * | 1989-10-13 | 1990-08-07 | Cree Research, Inc. | Method of preparing silicon carbide surfaces for crystal growth |
US5053348A (en) * | 1989-12-01 | 1991-10-01 | Hughes Aircraft Company | Fabrication of self-aligned, t-gate hemt |
US5210051A (en) * | 1990-03-27 | 1993-05-11 | Cree Research, Inc. | High efficiency light emitting diodes from bipolar gallium nitride |
US5172197A (en) * | 1990-04-11 | 1992-12-15 | Hughes Aircraft Company | Hemt structure with passivated donor layer |
US5292501A (en) * | 1990-06-25 | 1994-03-08 | Degenhardt Charles R | Use of a carboxy-substituted polymer to inhibit plaque formation without tooth staining |
US5200022A (en) * | 1990-10-03 | 1993-04-06 | Cree Research, Inc. | Method of improving mechanically prepared substrate surfaces of alpha silicon carbide for deposition of beta silicon carbide thereon and resulting product |
US5192987A (en) * | 1991-05-17 | 1993-03-09 | Apa Optics, Inc. | High electron mobility transistor with GaN/Alx Ga1-x N heterojunctions |
JP3352712B2 (en) * | 1991-12-18 | 2002-12-03 | 浩 天野 | Gallium nitride based semiconductor device and method of manufacturing the same |
DE69202554T2 (en) * | 1991-12-25 | 1995-10-19 | Nippon Electric Co | Tunnel transistor and its manufacturing process. |
JPH05275463A (en) | 1992-03-30 | 1993-10-22 | Matsushita Electric Ind Co Ltd | Semiconductor device |
JPH05326561A (en) * | 1992-05-22 | 1993-12-10 | Nec Corp | Manufacture of field effect transistor |
JPH06267991A (en) * | 1993-03-12 | 1994-09-22 | Hitachi Ltd | Semiconductor device and its manufacture |
US5393993A (en) * | 1993-12-13 | 1995-02-28 | Cree Research, Inc. | Buffer structure between silicon carbide and gallium nitride and resulting semiconductor devices |
US5686737A (en) * | 1994-09-16 | 1997-11-11 | Cree Research, Inc. | Self-aligned field-effect transistor for high frequency applications |
US5523589A (en) * | 1994-09-20 | 1996-06-04 | Cree Research, Inc. | Vertical geometry light emitting diode with group III nitride active layer and extended lifetime |
US5592501A (en) * | 1994-09-20 | 1997-01-07 | Cree Research, Inc. | Low-strain laser structures with group III nitride active layers |
JP3157690B2 (en) | 1995-01-19 | 2001-04-16 | 沖電気工業株式会社 | Method for manufacturing pn junction element |
US5534462A (en) | 1995-02-24 | 1996-07-09 | Motorola, Inc. | Method for forming a plug and semiconductor device having the same |
US5670798A (en) * | 1995-03-29 | 1997-09-23 | North Carolina State University | Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact non-nitride buffer layer and methods of fabricating same |
SE9501311D0 (en) | 1995-04-10 | 1995-04-10 | Abb Research Ltd | Method of producing a semiconductor device having a semiconductor layer of SiC |
US6002148A (en) * | 1995-06-30 | 1999-12-14 | Motorola, Inc. | Silicon carbide transistor and method |
KR100195269B1 (en) * | 1995-12-22 | 1999-06-15 | 윤종용 | Manufacture method of liquid crystal display device |
US5915164A (en) * | 1995-12-28 | 1999-06-22 | U.S. Philips Corporation | Methods of making high voltage GaN-A1N based semiconductor devices |
DE19600116C2 (en) * | 1996-01-03 | 2001-03-15 | Siemens Ag | Double heterostructure HEMT |
JPH1050982A (en) | 1996-07-31 | 1998-02-20 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device |
US6936839B2 (en) * | 1996-10-16 | 2005-08-30 | The University Of Connecticut | Monolithic integrated circuit including a waveguide and quantum well inversion channel devices and a method of fabricating same |
US6677619B1 (en) | 1997-01-09 | 2004-01-13 | Nichia Chemical Industries, Ltd. | Nitride semiconductor device |
US6448648B1 (en) * | 1997-03-27 | 2002-09-10 | The United States Of America As Represented By The Secretary Of The Navy | Metalization of electronic semiconductor devices |
JPH10335637A (en) * | 1997-05-30 | 1998-12-18 | Sony Corp | Hetero-junction field effect transistor |
US6201262B1 (en) * | 1997-10-07 | 2001-03-13 | Cree, Inc. | Group III nitride photonic devices on silicon carbide substrates with conductive buffer interlay structure |
JP3372470B2 (en) * | 1998-01-20 | 2003-02-04 | シャープ株式会社 | Nitride III-V compound semiconductor device |
US6608327B1 (en) * | 1998-02-27 | 2003-08-19 | North Carolina State University | Gallium nitride semiconductor structure including laterally offset patterned layers |
US6051849A (en) * | 1998-02-27 | 2000-04-18 | North Carolina State University | Gallium nitride semiconductor structures including a lateral gallium nitride layer that extends from an underlying gallium nitride layer |
US6150680A (en) * | 1998-03-05 | 2000-11-21 | Welch Allyn, Inc. | Field effect semiconductor device having dipole barrier |
JPH11261053A (en) | 1998-03-09 | 1999-09-24 | Furukawa Electric Co Ltd:The | High electron mobility transistor |
US6086673A (en) * | 1998-04-02 | 2000-07-11 | Massachusetts Institute Of Technology | Process for producing high-quality III-V nitride substrates |
US6500257B1 (en) * | 1998-04-17 | 2002-12-31 | Agilent Technologies, Inc. | Epitaxial material grown laterally within a trench and method for producing same |
US6316793B1 (en) * | 1998-06-12 | 2001-11-13 | Cree, Inc. | Nitride based transistors on semi-insulating silicon carbide substrates |
US6177688B1 (en) * | 1998-11-24 | 2001-01-23 | North Carolina State University | Pendeoepitaxial gallium nitride semiconductor layers on silcon carbide substrates |
US6255198B1 (en) * | 1998-11-24 | 2001-07-03 | North Carolina State University | Methods of fabricating gallium nitride microelectronic layers on silicon layers and gallium nitride microelectronic structures formed thereby |
JP3209270B2 (en) * | 1999-01-29 | 2001-09-17 | 日本電気株式会社 | Heterojunction field effect transistor |
US6582906B1 (en) * | 1999-04-05 | 2003-06-24 | Affymetrix, Inc. | Proportional amplification of nucleic acids |
US6518637B1 (en) * | 1999-04-08 | 2003-02-11 | Wayne State University | Cubic (zinc-blende) aluminum nitride |
US6218680B1 (en) * | 1999-05-18 | 2001-04-17 | Cree, Inc. | Semi-insulating silicon carbide without vanadium domination |
US6685194B2 (en) | 1999-05-19 | 2004-02-03 | Lannie Dietle | Hydrodynamic rotary seal with varying slope |
US6812053B1 (en) * | 1999-10-14 | 2004-11-02 | Cree, Inc. | Single step pendeo- and lateral epitaxial overgrowth of Group III-nitride epitaxial layers with Group III-nitride buffer layer and resulting structures |
US6521514B1 (en) * | 1999-11-17 | 2003-02-18 | North Carolina State University | Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on sapphire substrates |
JP4592938B2 (en) | 1999-12-08 | 2010-12-08 | パナソニック株式会社 | Semiconductor device |
US6639255B2 (en) * | 1999-12-08 | 2003-10-28 | Matsushita Electric Industrial Co., Ltd. | GaN-based HFET having a surface-leakage reducing cap layer |
US6380108B1 (en) * | 1999-12-21 | 2002-04-30 | North Carolina State University | Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on weak posts, and gallium nitride semiconductor structures fabricated thereby |
JP3393602B2 (en) * | 2000-01-13 | 2003-04-07 | 松下電器産業株式会社 | Semiconductor device |
US6586781B2 (en) | 2000-02-04 | 2003-07-01 | Cree Lighting Company | Group III nitride based FETs and HEMTs with reduced trapping and method for producing the same |
US6403451B1 (en) * | 2000-02-09 | 2002-06-11 | Noerh Carolina State University | Methods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride posts |
JP4667556B2 (en) * | 2000-02-18 | 2011-04-13 | 古河電気工業株式会社 | Vertical GaN-based field effect transistor, bipolar transistor and vertical GaN-based field effect transistor manufacturing method |
US6261929B1 (en) * | 2000-02-24 | 2001-07-17 | North Carolina State University | Methods of forming a plurality of semiconductor layers using spaced trench arrays |
US6475889B1 (en) * | 2000-04-11 | 2002-11-05 | Cree, Inc. | Method of forming vias in silicon carbide and resulting devices and circuits |
JP4022708B2 (en) | 2000-06-29 | 2007-12-19 | 日本電気株式会社 | Semiconductor device |
US6515316B1 (en) * | 2000-07-14 | 2003-02-04 | Trw Inc. | Partially relaxed channel HEMT device |
US6548333B2 (en) * | 2000-12-01 | 2003-04-15 | Cree, Inc. | Aluminum gallium nitride/gallium nitride high electron mobility transistors having a gate contact on a gallium nitride based cap segment |
JP3428962B2 (en) * | 2000-12-19 | 2003-07-22 | 古河電気工業株式会社 | GaN based high mobility transistor |
US6593193B2 (en) | 2001-02-27 | 2003-07-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
US6849882B2 (en) * | 2001-05-11 | 2005-02-01 | Cree Inc. | Group-III nitride based high electron mobility transistor (HEMT) with barrier/spacer layer |
US6706114B2 (en) * | 2001-05-21 | 2004-03-16 | Cree, Inc. | Methods of fabricating silicon carbide crystals |
US6646293B2 (en) | 2001-07-18 | 2003-11-11 | Motorola, Inc. | Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates |
CA2454269C (en) * | 2001-07-24 | 2015-07-07 | Primit Parikh | Insulating gate algan/gan hemt |
US7030428B2 (en) * | 2001-12-03 | 2006-04-18 | Cree, Inc. | Strain balanced nitride heterojunction transistors |
JP3986887B2 (en) | 2002-05-17 | 2007-10-03 | 松下電器産業株式会社 | Semiconductor device |
US6982204B2 (en) | 2002-07-16 | 2006-01-03 | Cree, Inc. | Nitride-based transistors and methods of fabrication thereof using non-etched contact recesses |
US6884704B2 (en) * | 2002-08-05 | 2005-04-26 | Hrl Laboratories, Llc | Ohmic metal contact and channel protection in GaN devices using an encapsulation layer |
US20040021152A1 (en) * | 2002-08-05 | 2004-02-05 | Chanh Nguyen | Ga/A1GaN Heterostructure Field Effect Transistor with dielectric recessed gate |
JP4746825B2 (en) | 2003-05-15 | 2011-08-10 | 富士通株式会社 | Compound semiconductor device |
US6909125B2 (en) * | 2003-07-08 | 2005-06-21 | Texas Instruments Incorporated | Implant-controlled-channel vertical JFET |
-
2004
- 2004-05-20 US US10/849,589 patent/US7084441B2/en not_active Expired - Lifetime
-
2006
- 2006-05-18 US US11/436,745 patent/US20060214196A1/en not_active Abandoned
-
2007
- 2007-10-12 US US11/871,790 patent/US7479669B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4916498A (en) * | 1985-09-15 | 1990-04-10 | Trw Inc. | High electron mobility power transistor |
US5831295A (en) * | 1995-12-01 | 1998-11-03 | Motorola, Inc. | Current confinement via defect generator and hetero-interface interaction |
US20030089930A1 (en) * | 2001-11-09 | 2003-05-15 | Zhao Jian Hui | Double-gated vertical junction field effect power transistor |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8603871B2 (en) | 2007-02-27 | 2013-12-10 | Fujitsu Limited | Compound semiconductor device and its manufacture method |
US20160359030A1 (en) * | 2008-04-23 | 2016-12-08 | Transphorm Inc. | Enhancement Mode III-N HEMTs |
US9941399B2 (en) * | 2008-04-23 | 2018-04-10 | Transphorm Inc. | Enhancement mode III-N HEMTs |
US9711404B2 (en) * | 2015-03-16 | 2017-07-18 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
US20080029789A1 (en) | 2008-02-07 |
US7084441B2 (en) | 2006-08-01 |
US7479669B2 (en) | 2009-01-20 |
US20050258450A1 (en) | 2005-11-24 |
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