US20060208322A1 - Method and apparatus for removing adjacent conductive and non-conductive materials of a microelectronic substrate - Google Patents

Method and apparatus for removing adjacent conductive and non-conductive materials of a microelectronic substrate Download PDF

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Publication number
US20060208322A1
US20060208322A1 US11413286 US41328606A US2006208322A1 US 20060208322 A1 US20060208322 A1 US 20060208322A1 US 11413286 US11413286 US 11413286 US 41328606 A US41328606 A US 41328606A US 2006208322 A1 US2006208322 A1 US 2006208322A1
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material
substrate
conductive
microelectronic
polishing
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US11413286
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Whonchee Lee
Scott Meikle
Guy Blalock
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Micron Technology Inc
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Micron Technology Inc
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • H01L21/31053Planarisation of the insulating layers involving a dielectric removal step
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • H01L21/3212Planarisation by chemical mechanical polishing [CMP]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • H01L21/3212Planarisation by chemical mechanical polishing [CMP]
    • H01L21/32125Planarisation by chemical mechanical polishing [CMP] by simultaneously passing an electrical current, i.e. electrochemical mechanical polishing, e.g. ECMP
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/65Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/91Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers

Abstract

A microelectronic substrate and method for removing adjacent conductive and nonconductive materials from a microelectronic substrate. In one embodiment, the microelectronic substrate includes a substrate material (such as borophosphosilicate glass) having an aperture with a conductive material (such as platinum) disposed in the aperture and a fill material (such as phosphosilicate glass) in the aperture adjacent to the conductive material. The fill material can have a hardness of about 0.04 GPa or higher, and a microelectronics structure, such as an electrode, can be disposed in the aperture, for example, after removing the fill material from the aperture. Portions of the conductive and fill material external to the aperture can be removed by chemically-mechanically polishing the fill material, recessing the fill material inwardly from the conductive material, and electrochemically-mechanically polishing the conductive material. The hard fill material can resist penetration by conductive particles, and recessing the fill material can provide for more complete removal of the conductive material external to the aperture.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • [0001]
    This application is related to the following pending U.S. patent applications, all of which are incorporated herein by reference: Ser. No. 09/651,779 (Attorney Docket 10829.8515US), filed Aug. 30, 2000; Ser. No. 09/888,084 (Attorney Docket 10829.8515US01), filed Jun. 21, 2001; Ser. No. 09/887,767 (Attorney Docket 10829.8515US02), filed Jun. 21, 2001; and Ser. No. 09/888,002 (Attorney Docket 10829.8515US03), filed Jun. 21, 2001. This application is also related to the following U.S. patent applications, filed simultaneously herewith and incorporated herein by reference: Ser. No. 10/______ (Attorney Docket 10829.8515US06); Ser. No. 10/______ (Attorney Docket 10829.8515US07); Ser. No. 10/______ (Attorney Docket 10829.8515US08) and Ser. No. 10/______ (Attorney Docket 10829.8672US).
  • TECHNICAL FIELD
  • [0002]
    The present invention relates generally to methods and apparatuses for removing adjacent conductive and nonconductive materials of a microelectronic substrate
  • BACKGROUND
  • [0003]
    Microelectronic substrates and substrate assemblies typically include a semiconductor material having features, such as memory cells, that are linked with conductive lines. The conductive lines can be formed by first forming trenches or other recesses in the semiconductor material and then overlaying a conductive material (such as a metal) in the trenches. The conductive material is then selectively removed to leave conductive lines extending from one feature in the semiconductor material to another.
  • [0004]
    One technique for forming microelectronic features, such as capacitors, is to dispose the features in isolated containers within the microelectronic substrate. One typical process includes forming an aperture in a substrate material (such as borophosphosilicate glass or BPSG), coating the microelectronic substrate (including the walls of the aperture) first with a barrier layer and then with a conductive layer, and then overfilling the aperture with a generally nonconductive material, such as a photoresist material. The excess photoresist material, conductive layer material, and barrier layer material located external to the aperture are then removed using chemical-mechanical planarization or polishing (CMP). The capacitor is then disposed within the photoresist material in the aperture and coupled to other features of the microelectronic substrate with an overlying network of vias and lines.
  • [0005]
    One drawback with the foregoing container technique for forming capacitors is that during the CMP process, small particles of the conductive material removed from the conductive layer can become embedded in the photoresist material within the aperture. The embedded conductive material can cause short circuits and/or other defects in the capacitor that is subsequently formed in the aperture, causing the capacitor to fail.
  • SUMMARY
  • [0006]
    The present invention is directed toward methods and apparatuses for removing adjacent conductive and nonconductive materials of a microelectronic substrate. A method in accordance with one aspect of the invention includes forming an aperture in a microelectronic substrate material, disposing a conductive material in the aperture proximate to a wall of the aperture, and disposing a fill material in the aperture proximate to the conductive material. In one aspect of this embodiment, the fill material has a hardness of about 0.04 GPa or higher, and in another aspect of the invention, the fill material has a hardness of about 6.5 GPa or higher. For example, the fill material can include a phosphosilicate glass or a spin-on glass. A microelectronic feature, such as an electrode, can then be disposed in the aperture.
  • [0007]
    A method in accordance with another aspect of the invention includes providing a microelectronic substrate having a substrate material defining a substrate material plane, a conductive material proximate to the substrate material, and a generally nonconductive material proximate to the conductive material. The conductive material is accordingly positioned between the substrate material and the generally nonconductive material. A portion of the generally nonconductive material includes a first external portion projecting beyond the substrate material plane, and a portion of the conductive material includes a second external portion projecting beyond the substrate material plane. At least part of the first external portion extending beyond the second external portion is removed, and the fill material is recessed inwardly toward the substrate material plane. At least part of the second external portion is also removed. For example, the first external portion can be removed via chemical-mechanical polishing, and the second external portion can be removed via electrochemical-mechanical polishing. In a further aspect of the invention, the first external portion can be recessed until it extends outwardly from the substrate material plane by distance from about 200 Å to about 500 Å.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0008]
    FIGS. 1A-1F schematically illustrate a process for forming features in a microelectronic substrate in accordance with an embodiment of the invention.
  • [0009]
    FIG. 2 is a partially schematic illustration of an apparatus for carrying out processes in accordance with embodiments of the invention.
  • [0010]
    FIG. 3 is a partially schematic, isometric view of a portion of the apparatus shown in FIG. 2 in accordance with an embodiment of the invention.
  • [0011]
    FIG. 4 is a partially schematic, side elevation view of an apparatus for processing a microelectronic substrate in accordance with another embodiment of the invention.
  • [0012]
    FIG. 5 schematically illustrates a waveform for electrolytically processing a microelectronic substrate in accordance with another embodiment of the invention.
  • DETAILED DESCRIPTION
  • [0013]
    The present disclosure describes methods and apparatuses for processing microelectronic substrates. Many specific details of certain embodiments of the invention are set forth in the following description and in FIGS. 1A-5 to provide a thorough understanding of these embodiments. One skilled in the art, however, will understand that the present invention may have additional embodiments and that the invention may be practiced without several of the details described below.
  • [0014]
    FIG. 1A is a partially schematic illustration of a microelectronic substrate 110 positioned for processing in accordance with an embodiment of the invention. In one aspect of this embodiment, the microelectronic substrate 110 includes a substrate material 111, such as borophosphosilicate glass (BPSG), and in other embodiments, the microelectronic substrate 110 can include other substrate materials 111, such as undoped silicon dioxide. In any of these embodiments, one or more apertures 112 (two of which are shown in FIG. 1A) can be formed in a substrate material plane 113 of the substrate material 111, using conventional techniques such as patterned etching. In one embodiment, the apertures 112 have a relatively high aspect ratio (i.e., depth-to-width ratio). For example, in one particular embodiment, the apertures 112 can have an aspect ratio of about 4:1 or more, and in other embodiments, the apertures 112 can have other aspect ratios. In any of these embodiments, an underlayer 114 (such as tantalum or tantalum oxide) can be disposed on the substrate material plane 113 and adjacent to the walls of the apertures 112. The underlayer 114 can be disposed on the microelectronic substrate 110 using conventional techniques, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). In one aspect of this embodiment, the underlayer 114 can form a barrier layer and in other embodiments, the underlayer 114 can perform other functions, such as promoting adhesion of subsequently deposited materials onto the walls of the apertures 112.
  • [0015]
    A layer of conductive material 115 is then disposed on the underlayer 114. In one embodiment, the conductive material 115 can include platinum or platinum alloys, and in other embodiments, the conductive material 115 can include other electrically conductive constituents, such as rhodium, ruthenium, copper or alloys of these materials. Platinum may be particularly suitable for apertures 112 having high aspect ratios, such as aspect ratios of approximately 4:1 or more.
  • [0016]
    A fill material 117 is then disposed on the conductive material 115. The fill material 117 includes subplane portions 118 (positioned beneath the substrate material plane 113 in the apertures 112) and a first external portion 119 that extends outwardly away from the substrate material plane 113, external to the apertures 112. The first external portion 119 is disposed on a second external portion 120 defined by the part of the conductive material 115 located external to the apertures 112 and beyond the substrate material plane 113.
  • [0017]
    In one embodiment, the fill material 117 can include a relatively hard, generally nonconductive substance, such as phosphosilicate glass (PSG). In a specific aspect of this embodiment, the fill material 117 can include PSG having 6% phosphorous. In other embodiments, the fill material 117 can include other relatively hard PSG or non-PSG materials, such as spin-on glass (SOG). In any of these embodiments, the fill material 117 has a hardness greater than that of a typical photoresist material. Accordingly, in one particular embodiment, the fill material 117 can have a hardness of about 0.04 GPa or higher. In one aspect of this embodiment, the hardness is calculated by driving an indenter with a known geometry into the material and measuring the normal applied force as a function of displacement. In other embodiments, the hardness is calculated in accordance with other methods. In a particular embodiment in which the fill material 117 includes 6% phosphorous PSG, the fill material 117 can have a hardness of about 6.5 GPa or higher. In any of these embodiments, the relatively hard composition of the fill material 117 can resist penetration from particles of the conductive material 115, as described in greater detail below.
  • [0018]
    The first external portion 119 of the fill material 117 can be removed (as shown in FIG. 1B) so that the remaining fill material 117 is flush with the conductive material 115. In one aspect of this embodiment, conventional CMP techniques and slurries are used to remove the first projection 119. Apparatuses for removing the first projection 119 are described in greater detail below with reference to FIGS. 2-5.
  • [0019]
    As shown in FIG. 1C, a portion of the remaining fill material 117 can be recessed relative to the adjacent conductive material 115 prior to removing the adjacent conductive material 115. For example, when the conductive material 115 projects away from the substrate material plane 113 by a distance D1, the remaining fill material 117 can project by distance D2 (less than D1) from the substrate material plane 113. In one particular embodiment, where D1 is approximately 1,000 Å, D2 can be from about 200 Å to about 500 Å. In other embodiments, the relative values of D1 and D 2 can be different, so long as D2 is less than D1. For example, the recess distance (e.g., D1 minus D2) can be from about 50% to about 80% of D1. In any of these embodiments, selective etch techniques can be used to selectively recess the fill material 117 relative to the adjacent second external portion 120 of the conductive material 115. The second external portion 120 is then removed, as described below.
  • [0020]
    FIG. 1D is a schematic illustration of the microelectronic substrate 110 after the second external portion 120 (FIG. 1C) of the conductive material 115 has been removed. The second external portion 120 can be removed using electrochemical-mechanical polishing (ECMP) techniques and an apparatus generally similar to that described in greater detail below with reference to FIGS. 2-5. In one aspect of this embodiment, the removal of the conductive material 115 is halted upon exposing the underlayer 114. In a further aspect of this embodiment, the conductive material 115 is removed more rapidly than is the fill material 117, so that projections 122 of the fill material 117 extend outwardly from the substrate material plane 113 at the end of this phase of processing. For example, during ECMP processing, the conductive material 115 is removed electrolytically, as well as by chemical and/or mechanical action, whereas the generally nonconductive fill material 117 is removed without electrolytic action. As will be described in greater detail below with reference to FIG. 1E, the projections 122 of the fill material 117 are removed in a subsequent step.
  • [0021]
    One aspect of an embodiment of the process described above with reference to FIGS. 1C and 1D is that the fill material 117 is recessed relative to the adjacent conductive material 115 by a selected distance prior to removing the adjacent conductive material 115. One advantage of this process is that recessing the fill material 117 can reduce the likelihood for forming residual deposits of conductive material 115 around the apertures 112. For example, if the fill material 117 is flush with the second projection 120 (as indicated by distance D0 in FIG. 1C) when the conductive material 115 is removed, the resulting large mass of fill material 117 extending away from the substrate material plane 113 can “shield” the adjacent conductive material 115 and reduce the effectiveness of the ECMP process for removing the conductive material 115. Accordingly, the process can leave residual deposits 115 a of the conductive material 115 around the apertures 112, as shown in dashed lines in FIG. 1D. These deposits, if not removed, can cause short-circuits with adjacent structures, and/or can adversely affect subsequent processing steps. Conversely, if the fill material 117 is recessed substantially lower than the distance D2, the fill material 117 may not adequately support the conducive material 115 within the apertures 112 during the ECMP and CMP processes, causing the conductive material 115 to shear out of the apertures 112 during processing.
  • [0022]
    The projections 122 of the fill material 117, along with the portions of the underlayer 114 and the conductive material 115 extending out of the apertures 112, are then removed to form the containers 130, as shown in FIG. 1E. Accordingly, each container 130 includes a volume of fill material 117 surrounded by a layer of conductive material 115, which is in turn surrounded by the underlayer 114. At this point, each container 130 is electrically isolated and shielded from the surrounding structures in the microelectronic substrate 110.
  • [0023]
    As shown in FIG. 1F, further features (such as electrodes) can next be disposed in the containers 130 to form structures 121 such as capacitors. The features can be disposed in the containers 130 using conventional techniques (such as selective etching and deposition) and are electrically coupled to each other and/or to external contacts with a network of vias and/or lines, also formed with conventional techniques, such as damascene techniques. For example, in one embodiment, the remaining fill material 117 within the apertures 112 is removed. A film 118, formed from a material such as tantalum pentoxide, is then disposed in the apertures 112, and a conductive electrode 119 is disposed adjacent to the film 118 to form the capacitor. In other embodiments, the foregoing techniques can be used to form other features in the microelectronic substrate 110, such as trenches and/or conductive lines. In any of these embodiments, portions of the microelectronic substrate 110 can then be diced from the larger wafer of which they are a part for encapsulation and incorporation in electronic devices.
  • [0024]
    FIGS. 2-5 schematically illustrate apparatuses for processing the microelectronic substrate 110 in a manner generally similar to that described above with reference to FIGS. 1A-1F. For example, FIG. 2 schematically illustrates an apparatus 260 chemically-mechanically and/or electrochemically-mechanically polishing the microelectronic substrate 110 in accordance with an embodiment of the invention. In one aspect of this embodiment, the apparatus 260 has a support table 280 with a top-panel 281 at a workstation where an operative portion “W” of a polishing pad 283 is positioned. The top-panel 281 is generally a rigid plate to provide a flat, solid surface to which a particular section of the polishing pad 283 may be secured during polishing.
  • [0025]
    The apparatus 260 can also have a plurality of rollers to guide, position and hold the polishing pad 283 over the top-panel 281. The rollers can include a supply roller 287, first and second idler rollers 284 a and 284 b, first and second guide rollers 285 a and 285 b, and a take-up roller 286. The supply roller 287 carries an unused or preoperative portion of the polishing pad 283, and the take-up roller 286 carries a used or postoperative portion of the polishing pad 283. Additionally, the first idler roller 284 a and the first guide roller 285 a can stretch the polishing pad 283 over the top-panel 281 to hold the polishing pad 283 stationary during operation. A motor (not shown) drives at least one of the supply roller 287 and the take-up roller 286 to sequentially advance the polishing pad 283 across the top-panel 281. Accordingly, clean preoperative sections of the polishing pad 283 may be quickly substituted for used sections to provide a consistent surface for polishing and/or cleaning the microelectronic substrate 110.
  • [0026]
    The apparatus 260 can also have a carrier assembly 290 that controls and protects the microelectronic substrate 110 during polishing. The carrier assembly 290 can include a substrate holder 292 to pick up, hold and release the substrate 110 at appropriate stages of the polishing process. The carrier assembly 290 can also have a support gantry 294 carrying a drive assembly 295 that can translate along the gantry 294. The drive assembly 295 can have an actuator 296, a drive shaft 297 coupled to the actuator 296, and an arm 298 projecting from the drive shaft 297. The arm 298 carries the substrate holder 292 via a terminal shaft 299 such that the drive assembly 295 orbits the substrate holder 292 about an axis E-E (as indicated by arrow “R1”). The terminal shaft 299 may also rotate the substrate holder 292 about its central axis F-F (as indicated by arrow “R2”).
  • [0027]
    The polishing pad 283 and a polishing liquid 289 define a polishing medium 282 that mechanically and/or chemically-mechanically removes material from the surface of the microelectronic substrate 110. The polishing pad 283 used in the apparatus 260 can be a fixed-abrasive polishing pad in which abrasive particles are fixedly bonded to a suspension medium. Accordingly, the polishing solution 289 can be a “clean solution” without abrasive particles because the abrasive particles are fixedly distributed across a polishing surface 288 of the polishing pad 283. In other applications, the polishing pad 283 may be a nonabrasive pad without abrasive particles, and the polishing solution 289 can be a slurry with abrasive particles and chemicals to remove material from the microelectronic substrate 110. To polish the microelectronic substrate 110 with the apparatus 260, the carrier assembly 290 presses the microelectronic substrate 110 against the polishing surface 288 of the polishing pad 283 in the presence of the polishing solution 289. The drive assembly 295 then orbits the substrate holder 292 about the axis E-E and optionally rotates the substrate holder 292 about the axis F-F to translate the substrate 110 across the polishing surface 288. As a result, the abrasive particles and/or the chemicals in the polishing medium 282 remove material from the surface of the microelectronic substrate 110 in a chemical and/or chemical-mechanical polishing process.
  • [0028]
    In a further aspect of this embodiment, the polishing solution 289 can include an electrolyte for ECMP processing. In another embodiment, the apparatus 260 can include an electrolyte supply vessel 230 that delivers an electrolyte separately to the polishing surface 288 of the polishing pad 283 with a conduit 237, as described in greater detail below with reference to FIG. 3. In either embodiment, the apparatus 260 can further include a current supply 221 coupled to electrodes positioned proximate to the polishing pad 283. Accordingly, the apparatus 260 can electrolytically remove material from the microelectronic substrate 110.
  • [0029]
    FIG. 3 is a partially exploded, partially schematic isometric view of a portion of the apparatus 260 described above with reference to FIG. 2. In one aspect of the embodiment shown in FIG. 3, the top-panel 281 houses a plurality of electrode pairs 370, each of which includes a first electrode 340 a and a second electrode 340 b. The first electrodes 340 a are coupled to a first lead 348 a and the second electrodes 340 b are coupled to a second lead 348 b. The first and second leads 348 a and 348 b are coupled to the current supply 241 (FIG. 2). In one aspect of this embodiment, the first electrodes 340 a can be separated from the second electrodes 340 b by an electrode dielectric layer 349 a that includes Teflon™ or another suitable dielectric material. The electrode dielectric layer 349 a can accordingly control the volume and dielectric constant of the region between the first and second electrodes 340 a and 340 b to control the electrical coupling between the electrodes.
  • [0030]
    The electrodes 340 a and 340 b can be electrically coupled to the microelectronic substrate 110 (FIG. 2) by the polishing pad 283. In one aspect of this embodiment, the polishing pad 283 is saturated with an electrolyte 331 supplied by the supply conduits 337 through apertures 338 in the top-panel 281 just beneath the polishing pad 283. Accordingly, the electrodes 320 a and 320 b are selected to be compatible with the electrolyte 331. In an another arrangement, the electrolyte 331 can be supplied to the polishing pad 283 from above (for example, by disposing the electrolyte 331 in the polishing liquid 289, rather than by directing the electrolyte upwardly through the polishing pad 283). Accordingly, the apparatus 260 can include a pad dielectric layer 349 b (FIG. 2) positioned between the polishing pad 283 and the electrodes 340 a and 340 b. When the pad dielectric layer 349 b is in place, the electrodes 340 a and 340 b are isolated from physical contact with the electrolyte 331 and can accordingly be selected from materials that are not necessarily compatible with the electrolyte 331.
  • [0031]
    FIG. 4 is an isometric view of a portion of an apparatus 460 having electrodes 440 (shown as a first electrode 440 a and a second electrode 440 b), and a polishing medium 482 arranged in accordance with another embodiment of the invention. In one aspect of this embodiment, the polishing medium 482 includes polishing pad portions 483 that project beyond the electrodes 440 a and 440 b. Each polishing pad portion 483 can include a polishing surface 488 and a plurality of flow passages 484 coupled to a fluid source (not shown in FIG. 4) with a conduit 437. Each flow passage 484 can have an aperture 485 proximate to the polishing surface 488 to provide an electrolyte 431 proximate to an interface between the microelectronic substrate 110 and the polishing surface 488. In one aspect of this embodiment, the pad portions 483 can include recesses 487 surrounding each aperture 485. Accordingly, the electrolyte 431 can proceed outwardly from the flow passages 484 while the microelectronic substrate 110 is positioned directly overhead and remains spaced apart from the electrodes 420.
  • [0032]
    Any of the foregoing apparatuses described above with reference to FIGS. 2-4 can be used to chemically-mechanically process the microelectronic substrate 110, and/or electrochemically-mechanically process the microelectronic substrate 110. When the apparatuses are used to electrochemically-mechanically process the microelectronic substrate 110, they can provide a varying electrical current that passes from the electrodes, through the conductive material of the microelectronic substrate 110, via the electrolytic fluid without contacting the electrodes with the microelectronic substrate 110. For example, as shown in FIG. 5, the apparatus can generate a high-frequency wave 504 and can superimpose a low-frequency wave 502 on the high-frequency wave 504. In one aspect of this embodiment, the high-frequency wave 504 can include a series of positive or negative voltage spikes contained within a square wave envelope defined by the low-frequency wave 502. Each spike of the high-frequency wave 504 can have a relatively steep rise-time slope to transfer charge through the dielectric material to the electrolyte and a more gradual fall-time slope. The fall-time slope can define a straight line, as indicated by high-frequency wave 504, or a curved line, as indicated by high-frequency wave 504 a. In other embodiments, the high-frequency wave 504 and the low-frequency wave 502 can have other shapes depending, for example, on the particular characteristics of the dielectric material and the electrolyte, the characteristics of the microelectronic substrate 110, and/or the target rate at which conductive material is to be removed from the microelectronic substrate 110.
  • [0033]
    From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the spirit and scope of the invention. For example, many of the structures and processes described above in the content of microelectronic containers can also be applied to other microelectronic features. Accordingly, the invention is not limited except as by the appended claims.

Claims (12)

  1. 1. A microelectronic substrate, comprising:
    a substrate material having an aperture;
    a conductive material positioned on the aperture proximate to a wall of the aperture; and
    a fill material removably disposed in the aperture proximate to the conductive material, the fill material having a hardness of about 0.04 GPa or higher.
  2. 2. The microelectronic substrate of claim 1 wherein the fill material has a hardness of about 6.5 GPa or higher.
  3. 3. The microelectronic substrate of claim 1 wherein the substrate material includes borophosphosilicate glass, the aperture has an aspect ratio of about 10:1 or greater, the conductive material includes platinum, and the fill material includes phosphosilicate glass.
  4. 4. The microelectronic substrate of claim 1 wherein the substrate material includes borophosphosilicate glass.
  5. 5. The microelectronic substrate of claim 1 wherein the conductive material includes platinum, and wherein the conductive material includes at least one of platinum, rhodium and ruthenium.
  6. 6. The microelectronic substrate of claim 1 wherein the fill material includes phosphosilicate glass.
  7. 7. The microelectronic substrate of claim 1 wherein the fill material includes phosphosilicate glass with about 6% phosphorous.
  8. 8. The microelectronic substrate of claim 1 wherein the substrate material includes at least one of borophosposilicate glass and undoped silicon dioxide, and wherein the conductive material includes at least one of platinum, rhodium and ruthenium.
  9. 9. A microelectronic substrate, comprising:
    a borophosphosilicate glass substrate material having an aperture, the aperture having an aspect ratio of about 4:1 or more;
    an underlayer that includes tantalum and is disposed in the aperture;
    a platinum lining disposed in the aperture proximate to the barrier layer; and
    a phosphosilicate glass fill material disposed in the aperture adjacent to the platinum lining.
  10. 10. The microelectronic substrate of claim 9 wherein the phosphosilicate glass fill material includes about 6% phosphorous.
  11. 11. The microelectronic substrate of claim 9 wherein the phosphosilicate glass fill material has a hardness of about 6.5 GPa or higher.
  12. 12-53. (canceled)
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US8048756B2 (en) 2011-11-01 grant
US20100176083A1 (en) 2010-07-15 application
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US20060199351A1 (en) 2006-09-07 application
US7078308B2 (en) 2006-07-18 grant

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