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Nitride semiconductor LED improved in lighting efficiency and fabrication method thereof

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US20060208264A1
US20060208264A1 US11439127 US43912706A US2006208264A1 US 20060208264 A1 US20060208264 A1 US 20060208264A1 US 11439127 US11439127 US 11439127 US 43912706 A US43912706 A US 43912706A US 2006208264 A1 US2006208264 A1 US 2006208264A1
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layer
semiconductor
doped
nitride
formed
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US11439127
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Yung Ryu
Kee Yang
Bang Oh
Jin Park
Young Kim
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Ryu Yung H
Yang Kee J
Oh Bang W
Park Jin S
Kim Young H
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds

Abstract

A nitride semiconductor LED improved in lighting efficiency and a fabrication method thereof, in which an n-doped semiconductor layer is formed on a substrate. An active layer is formed on the n-doped semiconductor layer to expose at least a partial area of the n-doped semiconductor layer. A p-doped semiconductor layer is formed on the active layer. A p+-doped semiconductor layer is formed on the p-doped semiconductor layer. An n+-doped semiconductor layer is formed in at least a partial upper region of the p+-doped semiconductor layer via n-dopant ion implantation. The n+-doped semiconductor layer cooperates with an underlying partial region of the p+-doped semiconductor layer to realize a reverse bias tunneling junction. Also, an upper n-doped semiconductor layer is formed on the n+-doped semiconductor layer to realize lateral current spreading. The invention can improve lighting efficiency by using the reverse bias tunneling junction and/or the lateral current spreading.

Description

    CLAIM OF PRIORITY
  • [0001]
    This application claims the benefit of Korean Patent Application No. 2004-18597 filed on Mar. 18, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.
  • BACKGROUND OF THE INVENTION
  • [0002]
    1. Field of the Invention
  • [0003]
    The present invention relates to a nitride semiconductor Light Emitting Diode (LED) improved in lighting efficiency and a fabrication method thereof. In particular, the present invention relates to a nitride semiconductor LED, which is improved in lighting efficiency by using a reverse bias tunneling junction and/or lateral current spreading, and a fabrication method thereof.
  • [0004]
    2. Description of the Related Art
  • [0005]
    In general, nitride semiconductors are used in LEDs for generating blue or green wavelength light. Such nitride semiconductors may be expressed by an equation of AlxInyGa(1-x-y)N, wherein 0≧x≧1, 0≧y≧1 and 0≧x+y≧1.
  • [0006]
    LEDs for generating green light are produced by using GaN semiconductors having a wide band gap of about 3.4 eV. A nitride semiconductor of for example GaN has a wide band gap, which acts as a problem in the formation of electrodes and ohmic contact structures. In more detail, there are problems in that contact resistance increased in a p-electrode region also raises the drive voltage while enhancing the heat generation of a diode. Although various schemes may be proposed as means for forming the ohmic contact structures, actually adoptable means are extremely restrictive because those regions forming ohmic contact structures also function as major light emitting surfaces, thereby bringing a critical requirement of allowing light from the active layer to pass through the major light transmitting surfaces.
  • [0007]
    As a conventional technique satisfying such requirements, there is proposed U.S. Pat. No. 5,563,422, which is entitled “Gallium Nitride-Based III-V Group Compound Semiconductor Device and Method of Producing the Same” and assigned to Nichia Chemical Industries, Ltd. This document proposes a transparent electrode layer using a Ni/Au double layer, and a structure of a nitride semiconductor LED disclosed in this document is shown in FIG. 1.
  • [0008]
    As shown in FIG. 1, a conventional nitride semiconductor LED 10 includes an n-doped GaN cladding layer 13, a GaN/InGaN active layer 15 of a Multiple Quantum Well (MQW) structure and a p-doped GaN cladding layer 17 formed in their order on a sapphire (AlO3) substrate 11, in which the p-doped GaN cladding layer 17 and the GaN/InGaN active layer 15 are removed in part to partially expose the top surface of the n-dope GaN cladding layer 13. The nitride semiconductor LED 10 also includes an n-electrode 19 a formed on the n-doped GaN cladding layer 13 and an ohmic contact structure. The ohmic contact structure is constituted of a transparent electrode 18 of Ni/Au formed on the p-doped GaN cladding layer 17 and a p-bonding electrode 19 b formed on the transparent electrode 18. The transparent electrode 18 is provided to improve contact resistance while ensuring transparency, and may be obtained via deposition of a Ni/Au double layer and subsequent heat treatment.
  • [0009]
    However, according to the afore-described technique, the transparent electrode attached on the p-doped semiconductor layer causes relatively poor ohmic contact properties thereby increasing drive voltage. It is also difficult to improve brightness since only relatively low transparency metals such as Ni/Au are attached on the p-doped semiconductor layer owing to weak bonding force of the p-doped semiconductor layer with respect to metal. Furthermore, the n-doped GaN cladding layer shows relatively bad overvoltage resistance when bonded with the n-electrode.
  • SUMMARY OF THE INVENTION
  • [0010]
    The present invention has been made to solve the foregoing problems of the prior art and it is therefore an object of the present invention to provide a nitride semiconductor LED which is improved in lighting efficiency by using a reverse bias tunneling junction and a fabrication method thereof.
  • [0011]
    It is another object of the present invention to provide a nitride semiconductor LED which is improved in lighting efficiency by using lateral current spreading and a fabrication method thereof.
  • [0012]
    According to an aspect of the invention for realizing the object, there is provided a fabrication method of nitride semiconductor Light Emitting Diodes (LEDs), the method comprising the following steps of:
  • [0013]
    (a) forming an n-doped semiconductor layer on a substrate;
  • [0014]
    (b) forming an active layer on the n-doped semiconductor layer;
  • [0015]
    (c) forming a p-doped semiconductor layer on the active layer;
  • [0016]
    (d) forming a p+-doped semiconductor layer on the p-doped semiconductor layer;
  • [0017]
    (e) implanting n-dopant ions into the p+-doped semiconductor layer to convert at least a portion of the p+-doped semiconductor layer into an n+-doped semiconductor layer so that the n+-doped semiconductor layer cooperates with a remaining region of the p+-doped semiconductor layer to form a reverse bias tunneling junction; and
  • [0018]
    (f) mesa-etching a resultant semiconductor structure to the extent of exposing a partial area of the n-doped semiconductor layer.
  • [0019]
    Preferably, the ion implantation step (e) may comprise: forming a SiO2 layer on the resultant semiconductor layer; etching the SiO2 layer to expose at least a portion of the p+-doped semiconductor layer; implanting n-dopant ions through the etched portion of the SiO2 layer; and removing the SiO2 layer via heat treatment.
  • [0020]
    Preferably, the ion implantation step (e) implants n-dopants in high and low energy levels into an upper region of the p+-doped semiconductor layer to form an n+-doped semiconductor layer on the remaining region of the p+-doped semiconductor layer and an upper n-doped semiconductor layer on the n+-doped semiconductor layer, thereby realizing lateral current spreading.
  • [0021]
    Preferably, the ion implantation step (e) may comprise: implanting n-dopant ions at a first energy level into an upper region of the n+-doped semiconductor layer to form an n+-doped semiconductor layer on the remaining region of the p+-doped semiconductor layer; and implanting n-dopant at a second energy level different from the first energy level into the upper region of the n+-doped semiconductor layer to form an upper n-doped semiconductor layer on the n+-doped semiconductor layer, thereby realizing lateral current spreading.
  • [0022]
    Also, the fabrication method of nitride semiconductor LEDs of the invention may further comprise the step of: (g) forming p- and n- electrodes on the upper n-doped semiconductor layer and the exposed partial area of the n-doped semiconductor layer, respectively, after the ion implantation step (e).
  • [0023]
    In addition, the fabrication method of nitride semiconductor LEDs may further comprise the step of: (h) forming a p-transparent electrode and an n-electrode on the n+-doped semiconductor layer and the exposed partial area of the n-doped semiconductor layer, respectively, after the etching step (f), wherein the transparent electrodes are made of at least one selected from a group consisting of Indium-Tin Oxide (ITO), Cadmium-Tin Oxide (CTO) and Titanium Tungsten Nitride (TiWN).
  • [0024]
    According to another aspect of the invention for realizing the object, there is provided a fabrication method of nitride semiconductor Light Emitting Diodes (LEDs), the method comprising the following steps of:
  • [0025]
    (a) forming an n-doped semiconductor layer on a substrate;
  • [0026]
    (b) forming an active layer on the n-doped semiconductor layer;
  • [0027]
    (c) forming a p-doped semiconductor layer on the active layer;
  • [0028]
    (d) forming p+-doped semiconductor layer on the p-doped semiconductor layer;
  • [0029]
    (e) forming an upper n-doped semiconductor layer on the p+-doped semiconductor layer;
  • [0030]
    (f) implanting n-dopant ions into the upper n-doped semiconductor layer to convert at least a partial region of the upper n-doped semiconductor layer into an n+-doped semiconductor layer so that the n+-doped semiconductor layer cooperates with a remaining region of the p+-doped semiconductor layer to form a reverse bias tunneling junction; and
  • [0031]
    (g) mesa-etching a resultant semiconductor structure to the extent of exposing a partial area of the n-doped semiconductor layer.
  • [0032]
    Preferably, the ion implantation step (f) may comprise: forming a SiO2 layer on the resultant semiconductor layer; etching the SiO2 layer to expose at least a portion of the p+-doped semiconductor layer; implanting n-dopant ions through the etched portion of the SiO2 layer; and removing the SiO2 layer via heat treatment.
  • [0033]
    Preferably, the ion implantation step (f) may comprise: implanting n+-dopants at a predetermined energy level into a lower region of the n-doped semiconductor layer to form an n+-doped semiconductor layer, whereby the n+-doped semiconductor layer cooperates with an upper remaining region of the n-doped semiconductor layer to realize lateral current spreading.
  • [0034]
    Also, the fabrication method of nitride semiconductor LEDs of the invention may further comprise the step of: (h) forming p- and n- electrodes on the upper n-doped semiconductor layer and the exposed partial area of the n-doped semiconductor layer, respectively, after the ion implantation step (f).
  • [0035]
    In addition, the fabrication method of nitride semiconductor LEDs of the invention may further comprise the step of: (i) forming a p-transparent electrode and an n-electrode on the n+-doped semiconductor layer and the exposed partial area of the n-doped semiconductor layer, respectively, after the etching step (g), wherein the transparent electrodes are made of at least one selected from a group consisting of Indium-Tin Oxide (ITO), Cadmium-Tin Oxide (CTO) and Titanium Tungsten Nitride (TiWN).
  • [0036]
    According to yet another aspect of the invention for realizing the object, there is provided a nitride semiconductor Light Emitting Diode (LED) comprising: an n-doped semiconductor layer formed on a substrate; an active layer formed on the n-doped semiconductor layer to expose at least a partial area of the n-doped semiconductor layer; a p-doped semiconductor layer formed on the active layer; a p+-doped semiconductor layer formed on the p-doped semiconductor layer; and an n+-doped semiconductor layer formed in at least a partial upper region of the p+-doped semiconductor layer via n-dopant ion implantation, the n+-doped semiconductor layer cooperating with an underlying partial region of the p+-doped semiconductor layer to realize a reverse bias tunneling junction.
  • [0037]
    Also, the nitride semiconductor LED of the invention may further comprise an upper n-doped semiconductor layer formed on the p+-doped semiconductor layer in order to realize lateral current spreading.
  • [0038]
    Preferably, the n+-doped semiconductor layer may be formed at an energy level different from that of the upper n-doped semiconductor layer.
  • [0039]
    Also, the nitride semiconductor LED of the invention may further comprise a p-electrode formed on the upper n-doped semiconductor layer and an n-electrode formed on the exposed partial area of the n-doped semiconductor layer.
  • [0040]
    In addition, the nitride semiconductor LED of the invention may further comprise a p-transparent electrode formed on the n+-doped semiconductor layer and an n- electrode formed on the exposed partial area of the n-doped semiconductor layer, wherein the transparent electrodes are made of at least one selected from a group consisting of Indium-Tin Oxide (ITO), Cadmium-Tin Oxide (CTO) and Titanium Tungsten Nitride (TiWN).
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0041]
    FIG. 1 is a sectional view illustrating a conventional nitride semiconductor LED structure;
  • [0042]
    FIGS. 2 to 4 are stepwise sectional views illustrating a fabrication method of a nitride semiconductor LED according to a first embodiment of the invention;
  • [0043]
    FIGS. 5 to 7 are stepwise sectional views illustrating a fabrication method of a nitride semiconductor LED according to a second embodiment of the invention;
  • [0044]
    FIGS. 8 to 10 are stepwise sectional views illustrating a fabrication method of a nitride semiconductor LED according to a third embodiment of the invention; and
  • [0045]
    FIGS. 11 to 13 are stepwise sectional views illustrating a fabrication method of a nitride semiconductor LED according to a fourth embodiment of the invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • [0046]
    The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
  • First Embodiment
  • [0047]
    FIGS. 2 to 4 are stepwise sectional views illustrating a fabrication method of a nitride semiconductor LED according to a first embodiment of the invention.
  • [0048]
    First, as shown in FIG. 2, a buffer layer 104, an undoped GaN layer 106, an n-doped semiconductor layer 108, an active layer 110, a p-doped semiconductor layer 112 and a high concentration p-doped or p+-doped semiconductor layer 114 are grown in their order on a sapphire substrate 102 to form a semiconductor structure, and an ion implantation process is performed to implant high concentration n-dopants or n+-dopants into the p+-doped semiconductor layer 114.
  • [0049]
    The ion implantation process may be carried out by forming a SiO2 buffer layer on the p+-doped semiconductor layer 114 and selectively etching the buffer layer to implant n+-dopants into a desired region. In this case, the ion implantation process forms the SiO2 buffer layer on the p+-doped semiconductor layer 114, i.e., the top of the semiconductor structure, etches the SiO2 buffer layer to expose a portion of the p+-doped semiconductor layer, implants n-dopant ions through the etched portion of the SiO2 buffer layer, and performs proper heat treatment such as Rapid Thermal Annealing (RTA) to activate the n-dopants and remove the SiO2 buffer layer.
  • [0050]
    Preferably, the n-dopants are ion-implanted at a concentration of about 1E15 to 1E16 atoms/cm2 under an acceleration voltage of about 100 eV to 50 keV. The n-dopants may be at least one selected from the group consisting of C, Si, Ge, Sn, Ni, P, As, Sb and so on. Subsequent heat treatment is preferably carried out in a temperature range from about 700 to 1300° C. under a nitrogen atmosphere for about 1 to 30 minutes.
  • [0051]
    Alternatively, high concentration n-dopants may be implanted into the p+-doped semiconductor layer 114 without the formation of the SiO2 buffer layer.
  • [0052]
    In response to the ion implantation process as above, a high concentration n-doped or n+-doped semiconductor layer 116 is formed in an upper region of the p+-doped semiconductor layer 114, but a lower region underlying the n+-doped semiconductor layer 116 remains as a p+-doped semiconductor layer 114 a as shown in FIG. 3. The above ion implantation process can precisely control the dose of dopant ions resultantly imparting desired characteristics to the n+-doped semiconductor layer 116. As the n+-doped semiconductor layer 116 is formed on the p+-doped semiconductor layer 114 a, a reverse bias tunneling junction is established between the semiconductor layers 116 and 114 a.
  • [0053]
    Then, a resultant semiconductor structure obtained as above is mesa-etched to the extent of exposing a partial area of the n-doped semiconductor layer 108, and a p-transparent electrode 120 and an n-electrode 122 are formed on the n+-doped semiconductor layer 116 and the exposed partial area of the n-doped semiconductor layer 108, respectively, to produce a nitride semiconductor 100 of the invention.
  • [0054]
    Also, because the reverse bias tunneling junction is formed between the n+-doped semiconductor layer 116 and the p+-doped semiconductor layer 114 a, an excellent ohmic contact is ensured between the uppermost n+-doped semiconductor layer 116 and the transparent metal electrode 120. Then, in place of a conventional Ni/Au metal layer, the p-transparent electrode 120 can be made of at least one selected from the group consisting of Indium-Tin Oxide (ITO), Cadmium-Tin Oxide (CTO) and Titanium Tungsten Nitride (TiWN) of excellent transparency. The transparent electrode of the invention can improve the brightness of the nitride semiconductor LED 100 since they have light transparency superior to that of the conventional transparent electrode of Ni/Au, in which for example ITO has a light transparency of about 90 to 98% but Ni/Au has a light transparency of about 65 to 80%.
  • [0055]
    This semiconductor structure as above can lower the drive voltage of the entire nitride semiconductor 100 based upon the excellent ohmic contact while improving the brightness owing to the transparent electrode of excellent transparency.
  • Second Embodiment
  • [0056]
    FIGS. 5 to 7 are stepwise sectional views illustrating a fabrication method of a nitride semiconductor LED according to second embodiment of the invention.
  • [0057]
    First, as shown in FIG. 5, a buffer layer 104, an undoped GaN layer 106, an n-doped semiconductor layer 108, an active layer 110, a p-doped semiconductor layer 112 and a high concentration p-doped or p+-doped semiconductor layer 114 are grown in their order on a sapphire substrate 102 to form a semiconductor structure, and anion implantation process is performed to implant low/high concentration n-dopants or n-/n+-dopants into the p+-doped semiconductor layer 114.
  • [0058]
    In this ion implantation process, an upper region of the p+-doped semiconductor layer 114 is converted into a high concentration n-doped or n+-doped semiconductor layer 116 and an upper n-doped semiconductor layer 118 but a lower region of the p+-doped semiconductor layer 114 underlying the n+-doped semiconductor layer 116 remains as a p+-doped semiconductor layer 114 a in order to form a semiconductor structure as shown in FIG. 6.
  • [0059]
    The ion implantation process may be carried out by forming a SiO2 buffer layer on the p+-doped semiconductor layer 114 and selectively etching the buffer layer to implant n-/n+-dopants into desired regions. In this case, the ion implantation process forms the SiO2 buffer layer on the p+-doped semiconductor layer 114, i.e., the top of the semiconductor structure, etches the SiO2 buffer layer to expose at least a portion of the p+-doped semiconductor layer, implants n-/n+-dopant ions through the etched portion of the SiO2 buffer layer, and performs RTA to activate the n-/n+-dopants and remove the SiO2 buffer layer.
  • [0060]
    The n-/n+-ion implantation process is performed at different energy levels. That is, the n+-doped semiconductor layer 116 is formed via high energy ion implantation, but the upper n-doped semiconductor layer 118 is formed via low energy ion implantation. In this case, the high energy ion implantation is performed in an energy level of 500 eV to 50 keV and preferably 1 to 10 keV. The low energy ion implantation is performed in. an energy level of 100 eV to 1 keV and preferably to 300 to 500 eV.
  • [0061]
    Alternatively, the n+-doped semiconductor layer 116 may be formed in a high energy level before the n-doped semiconductor layer 118 is formed in a low energy level, in which the energy levels are the same as above.
  • [0062]
    Further, the ion implantation process may have two steps of first implanting n-dopants at a high concentration in a high energy level and then implanting n-dopants at a low concentration in a low energy level. On the contrary, this process may implant n-dopants first at a low concentration and then at a high concentration.
  • [0063]
    Subsequent heat treatment is preferably carried out in a temperature range from about 700 to 1300° C. under a nitrogen atmosphere for about 1 to 30 minutes.
  • [0064]
    Alternatively, high concentration n-dopants may be implanted into the p+-doped semiconductor layer 114 without the formation of the SiO2 buffer layer. The same or different n+-/n-dopants may be used by selecting at least one from the group consisting of C, Si, Ge, Sn, Ni, P, As, Sb and so on.
  • [0065]
    Then, the semiconductor structure shown in FIG. 6 is mesa-etched to the extent of exposing a partial area of the n-doped semiconductor layer 108 as shown in FIG. 7, and p- and n-electrodes 130 and 132 are formed on the upper n-doped semiconductor layer 118 and the exposed partial area of the n-doped semiconductor layer 108, respectively, to produce a nitride semiconductor 100A of the invention.
  • [0066]
    In the nitride semiconductor 100A of this embodiment, the p+-doped semiconductor layer 114 a cooperates with the overlying n+-doped semiconductor layer 116 to establish a reverse bias tunneling junction as described above thereby to obtain an excellent ohmic contact while reducing drive voltage.
  • [0067]
    Furthermore, the n+-doped semiconductor layer 116 and the upper n-doped semiconductor layer 118 cooperate to obtain lateral current spreading so that the p- and n- electrodes 130 and 132 can be bonded to the uppermost layer of the semiconductor structure without the formation of conventional transparent electrodes. As a result, this semiconductor structure can improve brightness to a specific level equivalent to light quantity absorbed by the conventional transparent electrodes.
  • Third Embodiment
  • [0068]
    FIGS. 8 to 10 are stepwise sectional views illustrating a fabrication method of a nitride semiconductor LED according to a third embodiment of the invention.
  • [0069]
    First, as shown in FIG. 8, a buffer layer 204, an undoped GaN layer 206, an n-doped semiconductor layer 208, an active layer 210, a p-doped semiconductor layer 212, a high concentration p-doped or p+-doped semiconductor layer 214 and an upper n-doped semiconductor layer 216 are grown in their order on a sapphire substrate 202 to form a semiconductor structure. Then, n-dopants are implanted at a high concentration into the upper n-doped semiconductor layer 216 via ion implantation.
  • [0070]
    The ion implantation process converts the upper n-doped semiconductor layer 216 into a high concentration n-doped or n+-doped semiconductor layer 218 as shown in FIG. 9.
  • [0071]
    The ion implantation process first forms a SiO2 buffer layer on the upper n-doped semiconductor layer 216, and selectively etches the SiO2 buffer layer to implant n-dopants at a high concentration into a desired portion. In this case, the ion implantation process forms the SiO2 buffer layer on the upper n-doped semiconductor layer 216, i.e., the top of the semiconductor structure, etches the SiO2 buffer layer to expose a portion of the upper n-doped semiconductor layer 216, implants n-dopant ions through the etched portion of the SiO2 buffer layer, and performs proper heat treatment such as Rapid RTA to activate the n-dopants and remove the SiO2 buffer layer.
  • [0072]
    Preferably, the n-dopants are ion-implanted at a concentration of about 1E15 to 1E16 atoms/cm2 under an acceleration voltage of about 100 eV to 50 keV. The n-dopants may be at least one selected from the group consisting of C, Si, Ge, Sn, Ni, P, As, Sb and so on. Subsequent heat treatment is preferably carried out in a temperature range from about 700 to 1300° C. under a nitrogen atmosphere for about 1 to 30 minutes.
  • [0073]
    Alternatively, n-dopants may be implanted at a high concentration into the entire upper n-doped semiconductor layer 216 without the formation of the SiO2 buffer layer, in which the n-dopants may be at least one selected from the group consisting of C, Si, Ge, Sn, Ni, P, As, Sb and so on.
  • [0074]
    As the n+-doped semiconductor layer 218 is formed on the p+-doped semiconductor layer 214, a reverse bias tunneling junction is established between the semiconductor layers 218 and 214.
  • [0075]
    Then, a resultant semiconductor structure obtained as above is mesa-etched to the extent of exposing a partial area of the n-doped semiconductor layer 208, and a p-transparent electrode 220 and an n-electrode 222 are formed on the n+-doped semiconductor layer 218 and the exposed partial area of the n-doped semiconductor layer 208, respectively, to produce a nitride semiconductor 200 of the invention.
  • [0076]
    Also, because the reverse bias tunneling junction is formed between the n+-doped semiconductor layer 216 and the p+-doped semiconductor layer 214, an excellent ohmic contact is ensured between the uppermost n+-doped semiconductor layer 218 and the transparent metal electrode 220. Then, in place of a conventional Ni/Au metal layer, the p-transparent electrode 220 can be made of at least one selected from the group consisting of ITO, CTO and TiWN of excellent transparency. The transparent electrode of the invention can improve the brightness of the nitride semiconductor LED 200 since they have light transparency superior to that of the conventional transparent electrode of Ni/Au, in which for example ITO has a light transparency of about 90 to 98% but Ni/Au has a light transparency of about 65 to 80%.
  • [0077]
    This semiconductor structure as above can lower the drive voltage of the entire nitride semiconductor 200 based upon the excellent ohmic contact while improving the brightness owing to the transparent electrode 220 of excellent transparency.
  • Fourth Embodiment
  • [0078]
    FIGS. 11 to 13 are stepwise sectional views illustrating a fabrication method of a nitride semiconductor LED according to a fourth embodiment of the invention.
  • [0079]
    First, as shown in FIG. 11, a buffer layer 204, an undoped GaN layer 206, an n-doped semiconductor layer 208, an active layer 210, a p-doped semiconductor layer 212, a high concentration p-doped or p+-doped semiconductor layer 214 and an upper n-doped semiconductor layer 216 are grown in their order on a sapphire substrate 202 to form a semiconductor structure, and n-dopants are implanted at a high concentration into the upper n-doped semiconductor layer 216 via ion implantation.
  • [0080]
    The ion implantation process first forms a SiO2 buffer layer on the upper n-doped semiconductor layer 216, and selectively etches the SiO2 buffer layer to implant n-dopants at a high concentration into a desired portion (i.e., 218). In this case, the ion implantation process forms the SiO2 buffer layer on the upper n-doped semiconductor layer 216, i.e., the top of the semiconductor structure, etches the SiO2 buffer layer to expose a portion of the upper n-doped semiconductor layer 216, implants n-dopant ions at a high concentration through the etched portion of the SiO2 buffer layer, and performs proper heat treatment such as RTA to activate the n-dopants and remove the SiO2 buffer layer.
  • [0081]
    The ion implantation process is carried out at a high energy level in the range of about 100 eV to 50 keV to mainly implant n-dopants at a high concentration into a lower region of the n-doped semiconductor layer 216 so that the lower region of the n-doped semiconductor layer 216 is converted into an n+-doped semiconductor layer 218 but an upper region of the n-doped semiconductor layer 216 remains as an upper n-doped semiconductor layer 216 a. As a consequence, the ion implantation process forms a resultant semiconductor structure as shown in FIG. 12.
  • [0082]
    Preferably, the n-dopants are ion-implanted at a concentration of about 1E15 to 1E16 atoms/cm2 under an acceleration voltage of about 100 eV to 50 keV. The n-dopants may be at least one selected from the group consisting of C, Si, Ge, Sn, Ni, P, As, Sb and so on. Subsequent heat treatment is preferably carried out in a temperature range from about 700 to 1300° C. under a nitrogen atmosphere for about 1 to 30 minutes.
  • [0083]
    Alternatively, high concentration n-dopants or n+-dopants may be implanted into the upper n-doped semiconductor layer 216 without the formation of the SiO2 buffer layer.
  • [0084]
    The resultant semiconductor structure as shown in FIG. 12 is mesa-etched to the extent of exposing a partial area of the n-doped semiconductor layer 208, and p- and n-electrodes 230 and 232 are formed on the upper n-doped semiconductor layer 216 a and the exposed partial area of the n-doped semiconductor layer 208, respectively, to produce a nitride semiconductor 200A of the invention as shown in FIG. 13.
  • [0085]
    In the nitride semiconductor 200A of this embodiment, the p+-doped semiconductor layer 214 cooperates with the overlying n+-doped semiconductor layer 218 to establish a reverse bias tunneling junction as described above to enable an excellent ohmic contact while reducing drive voltage.
  • [0086]
    Furthermore, the n+-doped semiconductor layer 218 and the upper n-doped semiconductor layer 216 a cooperate to obtain lateral current spreading so that the p- and n- electrodes 230 and 232 can be bonded to the uppermost layer of the semiconductor structure without the formation of conventional transparent electrodes. As a result,- this semiconductor structure can improve brightness to a specific level equivalent to light quantity absorbed by the conventional transparent electrodes.
  • [0087]
    Although the sapphire substrate has been adopted by the foregoing embodiments of the invention, it is merely an example. The sapphire substrate may be replaced by one selected from the group consisting of a SiC substrate, an oxide substrate and a carbide substrate.
  • [0088]
    As set forth above, the present invention can realize the excellent ohmic contact from the reverse bias tunneling junction formed between the n+-doped semiconductor layer and the underlying p+-doped semiconductor layer, thereby improving brightness while reducing drive voltage.
  • [0089]
    Further, because the n+-doped semiconductor layer cooperates with the upper n-doped semiconductor layer to realize lateral current spreading, the electrodes can be directly connected to the n-doped semiconductor layers without the formation of transparent electrode thereby improving brightness further.
  • [0090]
    While the present invention has been shown and described in connection with the preferred embodiments, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (6)

1-12. (canceled)
13. A nitride semiconductor Light Emitting Diode (LED) comprising:
an n-doped semiconductor layer formed on a substrate;
an active layer formed on the n-doped semiconductor layer to expose at least a partial area of the n-doped semiconductor layer;
a p-doped semiconductor layer formed on the active layer;
a p+-doped semiconductor layer formed on the p-doped semiconductor layer; and
an n+-doped semiconductor layer formed in at least a partial upper region of the p+-doped semiconductor layer via n-dopant ion implantation, the n+-doped semiconductor layer cooperating with an underlying partial region of the p+-doped semiconductor layer to realize a reverse bias tunneling junction.
14. The nitride semiconductor LED according to claim 13, further comprising an upper n-doped semiconductor layer formed on the p+-doped semiconductor layer in order to realize lateral current spreading.
15. The nitride semiconductor LED according to claim 14, wherein the n+-doped semiconductor layer is formed at an energy level different from that of the upper n-doped semiconductor layer.
16. The nitride semiconductor LED according to claim 14, further comprising a p-electrode formed on the upper n-doped semiconductor layer and an n-electrode formed on the exposed partial area of the n-doped semiconductor layer.
17. The nitride semiconductor LED according to claim 13, further comprising a p-transparent electrode formed on the n+-doped semiconductor layer and an n-electrode formed on the exposed partial area of the n-doped semiconductor layer, wherein the transparent electrode is made of at least one selected from a group consisting of Indium-Tin Oxide (ITO), Cadmium-Tin Oxide (CTO) and Titanium Tungsten Nitride (TiWN).
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