New! View global litigation for patent families

US20060183271A1 - High density stepped, non-planar nitride read only memory - Google Patents

High density stepped, non-planar nitride read only memory Download PDF

Info

Publication number
US20060183271A1
US20060183271A1 US11399874 US39987406A US2006183271A1 US 20060183271 A1 US20060183271 A1 US 20060183271A1 US 11399874 US11399874 US 11399874 US 39987406 A US39987406 A US 39987406A US 2006183271 A1 US2006183271 A1 US 2006183271A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
memory
substrate
source
drain
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11399874
Inventor
Leonard Forbes
Kie Ahn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. MNOS, SNOS
    • G11C16/0475Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. MNOS, SNOS comprising plural independent storage sites which store independent data
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/112Read-only memory structures [ROM] and multistep manufacturing processes therefor
    • H01L27/115Electrically programmable read-only memories; Multistep manufacturing processes therefor
    • H01L27/11563Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM
    • H01L27/11568Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the memory core region

Abstract

A non-planar, stepped NROM array is comprised of cells formed in trenches and on pillars that are etched into a substrate. Each cell has a plurality of charge storage regions in its nitride layer and a pair of source/drain regions that are shared with adjacent cells in a column. The source/drain regions, formed in the pillar/trench sidewalls, couple the column cells serially into bitlines. The rows of the array are each coupled by a wordline. A second set of trenches separates the columns of cells.

Description

    RELATED APPLICATION
  • [0001]
    This application is a Divisional of U.S. application Ser. No. 10/899,906, titled “HIGH DENSITY STEPPED, NON-PLANAR NITRIDE READ ONLY MEMORY” filed Jul. 27, 2004, (pending) which is commonly assigned and incorporated herein by reference.
  • TECHNICAL FIELD OF THE INVENTION
  • [0002]
    The present invention relates generally to memory devices and in particular the present invention relates to an NROM device architecture.
  • BACKGROUND OF THE INVENTION
  • [0003]
    Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
  • [0004]
    Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
  • [0005]
    FIG. 1 shows a cross-section of a typical prior art NROM array. The array is comprised of a silicon substrate 100 with a gate oxide layer 101 formed over the substrate 100. A silicon nitride layer 102 is formed over the gate oxide 101. Each transistor 140-142 is comprised of two charge storage regions 110 and 111 in the nitride layer 102. An intergate insulator 107 is formed over the nitride layer 102 prior to forming the control gate/wordline 120-122 of each transistor 140-142 over the intergate insulator 107 and substantially between the source/drain regions 130-133.
  • [0006]
    The minimum feature size of the transistors 140-142 of FIG. 1 is described by F. The density is therefore one bit for each 4F2 units surface area. This is typically described as a density of 4F2/bit.
  • [0007]
    As computers become smaller and their performance increase, the computer components should also go through a corresponding size reduction and performance increase. To accomplish this, the transistors can be reduced in size. This has the effect of increased speed and memory density with decreased power requirements.
  • [0008]
    However, a problem with decreased flash memory size is that flash memory cell technologies have some scaling limitations due to the high voltage requirements for program and erase operations. As MOSFETs are scaled to deep sub-micron dimensions, it becomes more difficult to maintain an acceptable aspect ratio. Not only is the gate oxide thickness scaled to less than 10 nm as the channel length becomes sub-micron but the depletion region width and junction depth must be scaled to smaller dimensions.
  • [0009]
    For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device having increased memory density and performance.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0010]
    FIG. 1 shows a cross-sectional view of a typical prior art planar NAND NROM array.
  • [0011]
    FIG. 2 shows a cross-sectional view of one embodiment of a non-planar, stepped NROM array of the present invention.
  • [0012]
    FIG. 3 shows a cross-sectional view of fabrication steps for one embodiment of the present invention in accordance with the array of FIG. 2.
  • [0013]
    FIG. 4 shows a cross-sectional view of additional steps for one embodiment of the fabrication method of the present invention in accordance with the array of FIG. 2.
  • [0014]
    FIG. 5 shows a cross-sectional view of additional steps for one embodiment of the fabrication method of the present invention in accordance with the array of FIG. 2.
  • [0015]
    FIG. 6 shows a three dimensional, cross-sectional view of one embodiment of the array of FIG. 2.
  • [0016]
    FIG. 7 shows a block diagram of an electronic system that incorporates the non-planar, stepped NROM array of the present invention.
  • DETAILED DESCRIPTION
  • [0017]
    In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof. The terms wafer or substrate used in the following description include any base semiconductor structure. Both are to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure, and terms wafer or substrate include the underlying layers containing such regions/junctions.
  • [0018]
    FIG. 2 illustrates a cross-sectional view of one embodiment of a stepped, non-planar NROM flash memory array of the present invention. The memory cells are fabricated on a trenched substrate 200 with steps between the adjacent devices along the row of series connected transistors. The transistors are not vertical structures but are conventional devices with conduction in channels that are parallel to the substrate surface. These devices achieve a density of 1F2/bit with multiple level cell storage.
  • [0019]
    A portion of the array illustrated in FIG. 2 is comprised of a column of transistors of which two 210 and 211 are discussed. An upper plane transistor 211 is fabricated on a pillar on the substrate 200. A lower plane transistor 210 is fabricated in a trench of the substrate 200.
  • [0020]
    Source/drain regions 220-222 are doped into the pillar/trench sidewalls. These regions 220-222 couple adjacent transistors of each plane together into columns (i.e., bitlines) of a NAND architecture memory array. The upper plane transistor 211 uses source/drain regions 221 and 222 while the lower plane transistor 210 uses source/drain regions 220 and 221. These two transistors 210 and 211 are coupled by the shared source/drain region 221.
  • [0021]
    Channel regions exist at the top of each pillar and the bottom of each trench between the source/drain regions 220-222. During operation of the transistor 210 and 211, a channel forms between the source/drain regions 220 and 221 or 221 and 222 in the particular channel region of the operating transistor.
  • [0022]
    In one embodiment, the source/drain regions 220-222 are n+ regions that are doped into a p-type substrate. However, the source/drain regions and substrate of the present invention are not limited to any one conductivity type.
  • [0023]
    A first dielectric layer 201 is formed over the substrate 200 including both the pillars and the trenches and pillar/trench sidewalls. A silicon nitride layer 203 is formed over the oxide layer 201. This layer 203 comprises the charge storage regions near the source/drain regions 220-222 for each particular transistor. In the illustrated embodiment, each transistor 210 or 211 has two charge storage regions 230 and 231 or 233 and 234. Alternate embodiments may have different quantities of charge storage regions.
  • [0024]
    A second dielectric layer 205 is formed over the nitride layer 203. Polysilicon control gates/wordlines 240 and 241 are formed over the second dielectric layer 205 and substantially between each source/drain region 220-222 for either the pillar transistor 211 or the trench transistor 210.
  • [0025]
    In one embodiment, the two dielectric layers are comprised of an oxide such that an oxide-nitride-oxide (ONO) gate insulator is formed. Alternate embodiments may use other dielectric materials.
  • [0026]
    As shown later, with reference to FIG. 6, the wordlines couple each memory array row of transistors. In the embodiment of FIG. 2, one wordline 240 couples a row of the lower plane of transistors (i.e., the trenches). Another wordline 241 couples a row of the upper plane of transistors (i.e., the pillars).
  • [0027]
    The gate insulator and/or the intergate insulator between the nitride layer and the polysilicon wordlines can be high-k dielectrics (i.e., dielectric constant greater than that of SiO2), composite insulators, silicon oxide, or some other insulator. Silicon dioxide (SiO2) is an insulator with a relative dielectric constant of 3.9. A high-k gate insulator requires smaller write and erase voltages due to the reduced thickness layer between the control gate and the floating gate. These dielectric layers may be formed by atomic layer deposition (ALD), evaporation, or some other fabrication technique.
  • [0028]
    As is well known in the art, ALD is based on the sequential deposition of individual monolayers or fractions of a monolayer in a well-controlled manner. Gaseous precursors are introduced one at a time to the substrate surface and between the pulses the reactor is purged with an inert gas or evacuated.
  • [0029]
    In the first reaction step, the precursor is saturatively chemisorbed at the substrate surface and during subsequent purging the precursor is removed from the reactor. In the second step, another precursor is introduced on the substrate and the desired films growth reaction takes place. After that reaction, byproducts and the precursor excess are purged from the reactor. When the precursor chemistry is favorable, one ALD cycle can be performed in less than one second in a properly designed flow-type reactor. The most commonly used oxygen source materials for ALD are water, hydrogen peroxide, and ozone. Alcohols, oxygen and nitrous oxide can also been used.
  • [0030]
    ALD is well suited for deposition of high-k dielectrics such as AlOx, LaAlO3, HfAlO3, Pr2O3, Lanthanide-doped TiOx, HfSiON, Zr—Sn—Ti—O films using TiCl4 or TiI4, ZrON, HfO2/Hf, ZrAlxOy, CrTiO3, and ZrTiO4.
  • [0031]
    The dielectric layers of the present invention can also be formed by evaporation. Dielectric materials formed by evaporation can include: TiO2, HfO2, CrTiO3, ZrO2, Y2O3, Gd2O3, PrO2, ZrOxNy, Y—Si—O, and LaAlO3.
  • [0032]
    Very thin films of TiO2 can be fabricated with electron-gun evaporation from a high purity TiO2 slug (e.g., 99.9999%) in a vacuum evaporator in the presence of an ion beam. In one embodiment, an electron gun is centrally located toward the bottom of the chamber. A heat reflector and a heater surround the substrate holder. Under the substrate holder is an ozonizer ring with many small holes directed to the wafer for uniform distribution of ozone that is needed to compensate for the loss of oxygen in the evaporated TiO2 film. An ion gun with a fairly large diameter (3-4 in. in diameter) is located above the electron gun and argon gas is used to generate Ar ions to bombard the substrate surface uniformly during the film deposition to compact the growing TiO2 film.
  • [0033]
    A two-step process is used in fabricating a high purity HfO2 film. This method avoids the damage to the silicon surface by Ar ion bombardment, such as that encountered during Hf metal deposition using dc sputtering. A thin Hf film is deposited by simple thermal evaporation. In one embodiment, this is by electron-beam evaporation using a high purity Hf metal slug (e.g., 99.9999%) at a low substrate temperature (e.g., 150°-200° C.). Since there is no plasma and ion bombardment of the substrate (as in the case of sputtering), the original atomically smooth surface of the silicon substrate is maintained. The second step is oxidation to form the desired HfO2.
  • [0034]
    The first step in the deposition of CoTi alloy film is by thermal evaporation. The second step is the low temperature oxidation of the CoTi film at 400° C. Electron beam deposition of the CoTi layer minimizes the effect of contamination during deposition. The CoTi films prepared from an electron gun possess the highest purity because of the high-purity starting material. The purity of zone-refined starting metals can be as high as 99.999%. Higher purity can be obtained in deposited films because of further purification during evaporation.
  • [0035]
    A two-step process in fabricating a high-purity ZrO2 film avoids the damage to the silicon surface by Ar ion bombardment. A thin Zr film is deposited by simple thermal evaporation. In one embodiment, this is accomplished by electron beam evaporation using an ultra-high purity Zr metal slug (e.g., 99.9999%) at a low substrate temperature (e.g., 150°-200° C.). Since there is no plasma and ion bombardment of the substrate, the original atomically smooth surface of the silicon substrate is maintained. The second step is the oxidation to form the desired ZrO2.
  • [0036]
    The fabrication of Y2O3 and Gd2O3 films may be accomplished with a two-step process. In one embodiment, an electron gun provides evaporation of high purity (e.g., 99.9999%) Y or Gd metal followed by low-temperature oxidation technology by microwave excitation in a Kr/O2 mixed high-density plasma at 400° C. The method of the present invention avoids damage to the silicon surface by Ar ion bombardment such as that encountered during Y or Gd metal deposition sputtering. A thin film of Y or Gd is deposited by thermal evaporation. In one embodiment, an electron-beam evaporation technique is used with an ultra-high purity Y or Gd metal slug at a low substrate temperature (e.g., 150°-200° C.). Since there is no plasma or ion bombardment of the substrate, the original atomically smooth surface of the silicon substrate is maintained. The second step is the oxidation to form the desired Y2O3 or Gd2O3.
  • [0037]
    The desired high purity of a PrO2 film can be accomplished by depositing a thin film by simple thermal evaporation. In one embodiment, this is accomplished by an electron-beam evaporation technique using an ultra-high purity Pr metal slug at a low substrate temperature (e.g., 150°-200° C.). Since there is no plasma and ion bombardment of the substrate, the original atomically smooth surface of the silicon substrate is maintained. The second step includes the oxidation to form the desired PrO2.
  • [0038]
    The nitridation of the ZrO2 samples comes after the low-temperature oxygen radical generated in high-density Krypton plasma. The next step is the nitridation of the samples at temperatures >700° C. in a rapid thermal annealing setup. Typical heating time of several minutes may be necessary, depending on the sample geometry.
  • [0039]
    The formation of a Y—Si—O film may be accomplished in one step by co-evaporation of the metal (Y) and silicon dioxide (SiO2) without consuming the substrate Si. Under a suitable substrate and two-source arrangement, yttrium is evaporated from one source, and SiO2 is from another source. A small oxygen leak may help reduce the oxygen deficiency in the film. The evaporation pressure ratio rates can be adjusted easily to adjust the Y—Si—O ratio.
  • [0040]
    The prior art fabrication of lanthanum aluminate (LaAlO3) films has been achieved by evaporating single crystal pellets on Si substrates in a vacuum using an electron-beam gun. The evaporation technique of the present invention uses a less expensive form of dry pellets of Al2O3 and La2O3 using two electron guns with two rate monitors. Each of the two rate monitors is set to control the composition. The composition of the film, however, can be shifted toward the Al2O3 or La2O3 side depending upon the choice of dielectric constant. After deposition, the wafer is annealed ex situ in an electric furnace at 700° C. for ten minutes in N2 ambience. In an alternate embodiment, the wafer is annealed at 800°-900° C. in RTA for ten to fifteen seconds in N2 ambience.
  • [0041]
    The above described ALD and evaporation techniques are for purposes of illustration only. The embodiments of the present invention are not limited to any one dielectric material or dielectric fabrication technique.
  • [0042]
    FIG. 3 illustrates an embodiment for fabricating the non-planar NROM array of FIG. 2. The substrate 300 is etched to produce trenches 305 between the substrate pillars 308 and 309. A doped oxide is deposited over the trenches 305 and pillars 308 and 309. This oxide layer is directionally etched to leave the oxide only on the sidewalls 301-304 of the trenches.
  • [0043]
    During a subsequent anneal process, the sidewall oxide forms the source/drain regions 404-407 of the transistors as illustrated in FIG. 4. The sidewall oxide layers are then removed.
  • [0044]
    In one embodiment, conventional techniques are employed to provide an oxide layer 401, nitride layer 402, and an oxide intergate layer 403 (ONO) as is described, for example, in “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell”, by Boaz Eitan et al., IEEE Electron Device Letters, Vol. 21, No. 11, November 2000, pp. 543-545, IEEE Catalogue No. 0741-3106/00, or in “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device” by T. Y. Chan et al., IEEE Electron Device Letters, Vol. EDL-8, No. 3, March, 1987, pp. 93-95, IEEE Catalogue No. 0741-3106/87/0300-0093.
  • [0045]
    In one embodiment, the thin oxide, nitride, and oxide layers combine to form the ONO gate insulator layer, such as is employed in SONOS devices. In one embodiment, the gate insulator has a thickness of approximately 10 nanometers (nm).
  • [0046]
    In alternative embodiments, the gate insulator is selected from the group of silicon dioxide (SiO2) formed by wet oxidation, silicon oxynitride (SON), silicon rich oxide (SRO), and silicon rich aluminum oxide (Al2O3).
  • [0047]
    In still other embodiments, the gate insulator may be selected from the group of silicon rich aluminum oxide insulators, silicon rich oxides with inclusions of nanoparticles of silicon, silicon oxide insulators with inclusions of nanoparticles of silicon carbide, and silicon oxycarbide insulators. In still other embodiments, the gate insulator includes a composite layer selected from the group of an oxide-aluminum oxide (Al2O3)-oxide composite layer, an oxide-silicon oxycarbide-oxide composite layer, and an oxide-nitride-aluminum oxide composite layer.
  • [0048]
    The aluminum oxide top layer has a higher dielectric constant so that this layer can be thicker in order to preclude tunneling to and from the control gate to the nitride storage layer. Alternate embodiments use other high dielectric constant insulators as the top layer.
  • [0049]
    In still other embodiments, the gate insulator includes a composite layer, or a non-stoichiometric single layer of two or more materials selected from the group of silicon (Si), titanium (Ti), and tantalum (Ta).
  • [0050]
    FIG. 5 illustrates that a polysilicon wordline/control gate layer 501-503 is formed over the gate insulator. This process may be a directional, anisotropic deposition of polysilicon. Alternate embodiments may use other materials and/or processes for forming the wordlines/control gates.
  • [0051]
    As is illustrated in FIG. 6, the structures have been masked and a second set of trenches is etched perpendicular 601 to the original trenches. This separates the ONO structures of each cell, clears the sidewalls, and forms the pillars with source/drain regions along two of the sidewalls. In one embodiment, the second set of trenches is etched deeper into the substrate than the first set in order to affect a separation of the source/drain regions along the subsequent wordline/control gate.
  • [0052]
    FIG. 6 shows that each row of transistors in the upper plane is coupled together along the same wordline. Similarly, each row of the lower plane of transistors is coupled together along the same wordline.
  • [0053]
    SONOS devices are capable of storing more than one bit per gate. Typically, the hot carriers are injected into one side of the ONO layer, adjacent a source/drain region, to provide a high electrical field. By reversing the polarity of the potentials applied to the source/drain regions, charge may be injected into the other side of the ONO layer.
  • [0054]
    In operation, application of suitable electrical biases to the source/drain regions and the control gate cause hot majority charge carriers to be injected into the nitride layer and become trapped, providing a threshold voltage shift and thus providing multiple, alternative, measurable electrical states representing stored data. “Hot” charge carriers are not in thermal equilibrium with their environment. In other words, hot charge carriers represent a situation where a population of high kinetic energy charge carriers exist. Hot charge carriers may be electrons or holes.
  • [0055]
    The stepped, non-planar NROM flash memory devices of the present invention can be programmed with tunnel injection using positive gate voltages with respect to the substrate/p-well. In another embodiment, channel hot electron injection can be used in a programming operation. This is accomplished by applying a positive drain voltage (e.g., +6 to +9V) to a first source/drain region, a positive voltage to the control gate (e.g., +12V) and grounding the second source/drain region to create a hot electron injection into the gate insulator of the charge storage region.
  • [0056]
    An alternate embodiment programming operation uses substrate enhanced hot electron injection (SEHE). In this embodiment, a negative substrate bias is applied to the p-type substrate. This bias increases the surface lateral field near a source/drain region thus increasing the number of hot electrons. The benefit of such an embodiment is that a lower drain voltage is required during programming operations. In one embodiment, the negative substrate bias is in the range of 0V to −3V. Alternate embodiments may use other voltage ranges.
  • [0057]
    For an erase operation, one embodiment uses tunneling with conventional negative gate voltages with respect to the substrate/p-well. In another embodiment, the control gate is grounded, the drain connection is left floating and the source region has a positive voltage applied (e.g., +12V). Alternate embodiments for erase operations can use other methods such as substrate enhanced band-to-band tunneling induced hot hole injection (SEBBHH) that are well known in the art.
  • [0058]
    While above-described figures are to a NAND NROM flash memory device, the present invention is not limited to such a structure. For example, using a virtual ground array that is well known in the art, the stepped, non-planar NROM array can be fabricated in a NOR architecture. In the NOR configuration, the cells are arranged in a matrix. The gates of each floating gate memory cell of the array matrix are connected by rows to wordlines and their drains are connected to column bitlines. The source of each floating gate memory cell is typically connected to a common source line. Still other embodiments can use other architectures.
  • [0059]
    FIG. 7 illustrates a functional block diagram of a memory device 700 that can incorporate the flash memory cells of the present invention. The memory device 700 is coupled to a processor 710. The processor 710 may be a microprocessor or some other type of controlling circuitry. The memory device 700 and the processor 710 form part of an electronic system 720. The memory device 700 has been simplified to focus on features of the memory that are helpful in understanding the present invention.
  • [0060]
    The memory device includes an array of NROM, flash memory cells 730 that can be comprised of the stepped, non-planar NROM cells illustrated previously. The memory array 730 is arranged in banks of rows and columns. The control gates of each row of memory cells is coupled with a wordline while the drain and source connections of the memory cells are coupled to bitlines. As is well known in the art, the connections of the cells to the bitlines determines whether the array is a NAND architecture or a NOR architecture.
  • [0061]
    An address buffer circuit 740 is provided to latch address signals provided on address input connections A0-Ax 742. Address signals are received and decoded by a row decoder 744 and a column decoder 746 to access the memory array 730. It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends on the density and architecture of the memory array 730. That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts.
  • [0062]
    The memory device 700 reads data in the memory array 730 by sensing voltage or current changes in the memory array columns using sense/buffer circuitry 750. The sense/buffer circuitry, in one embodiment, is coupled to read and latch a row of data from the memory array 730. Data input and output buffer circuitry 760 is included for bi-directional data communication over a plurality of data connections 762 with the controller 710. Write circuitry 755 is provided to write data to the memory array.
  • [0063]
    Control circuitry 770 decodes signals provided on control connections 772 from the processor 710. These signals are used to control the operations on the memory array 730, including data read, data write (program), and erase operations. The control circuitry 770 may be a state machine, a sequencer, or some other type of controller.
  • [0064]
    The memory device illustrated in FIG. 7 has been simplified to facilitate a basic understanding of the features of the memory. A more detailed understanding of internal circuitry and functions of NROM memories are known to those skilled in the art.
  • CONCLUSION
  • [0065]
    In summary, the stepped, non-planar NROM flash memory cells of the present invention provide a high-density memory array with multiple level storage in a nitride layer. The density, in one embodiment, is 1F2/bit versus the typical 4F2/bit of the prior art conventional NAND flash memory structure. The memory cells of one array column (i.e., bitline) are divided up into an upper plane of cells and a lower plane of cells. In the NAND configuration, the cells are coupled in series through the source/drain regions. In the NOR configuration, the cells are arranged in a matrix.
  • [0066]
    Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof.

Claims (20)

  1. 1. A method for programming a non-planar, stepped NROM flash memory array comprising rows and columns of NROM cells, each row of NROM cells coupled on one of a first or a second plane and each column of NROM cells coupled on both the first and the second plane, each NROM cell having a pair of source/drain regions, a gate insulator comprising a plurality of charge storage regions, and a control gate, the method comprising:
    biasing the control gate with a first positive voltage;
    biasing a first source/drain region with a second positive voltage; and
    allowing a second source/drain region to float to create a hot electron injection into a first charge storage region.
  2. 2. The method of claim 1 wherein the second source/drain region is grounded.
  3. 3. The method of claim 1 and further including allowing the first source/drain region to float and biasing the second source/drain region with the second positive voltage to create the hot electron injection into a second charge storage region.
  4. 4. The method of claim 3 wherein the first source/drain region is grounded.
  5. 5. The method of claim 1 wherein the first positive voltage is +12V and the second positive voltage is in a range from +6V to +9V.
  6. 6. The method of claim 3 and further including biasing the substrate with a negative substrate.
  7. 7. The method of claim 6 wherein the negative substrate voltage creates substrate enhanced hot electron injection (SEHE).
  8. 8. The method of claim 6 wherein the negative substrate voltage is in a range of 0V to −3V.
  9. 9. The method of claim 6 wherein the second positive voltage is reduced in response to the substrate bias.
  10. 10. A method for erasing a non-planar, stepped NROM flash memory array comprising rows and columns of NROM cells, each row of NROM cells coupled on one of a first or a second plane and each column of NROM cells coupled on both the first and the second plane, each NROM cell having a pair of source/drain regions, a gate insulator comprising a plurality of charge storage regions, and a control gate, the method comprising:
    biasing the control gate;
    allowing a first source/drain region to float; and
    biasing a second source/drain region with a positive voltage to erase a first charge storage region.
  11. 11. The method of claim 10 and further including biasing the first source/drain region with the positive voltage and allowing the second source/drain region to float to erase a second charge storage region.
  12. 12. The method of claim 10 wherein biasing the control gate comprises grounding the control gate.
  13. 13. The method of claim 10 wherein the positive voltage is +12V.
  14. 14. The method of claim 10 wherein biasing the control gate comprises biasing the control gate with a voltage that is negative with respect to a substrate voltage.
  15. 15. The method of claim 10 and further including biasing the substrate such that substrate enhanced band-to-band tunneling induced hot hole injection is accomplished.
  16. 16. An electronic system comprising:
    a processor that generates memory control signals; and
    a non-planar, flash memory array coupled to the processor that operates in response to the memory control signals, the array comprising:
    a first plurality of memory cells in a first plane in a first column; and
    a second plurality of memory cells in a second plane in the first column, the second plurality of memory cells coupled to the first plurality of memory cells.
  17. 17. The system of claim 16 wherein the flash memory array is a NAND NROM flash device.
  18. 18. The system of claim 16 wherein the array is a virtual ground memory array.
  19. 19. The system of claim 16 wherein the flash memory array is a NOR NROM flash device.
  20. 20. The system of claim 16 wherein the plurality of memory cells are NROM cells comprising an oxide-nitride-oxide structure.
US11399874 2004-07-27 2006-04-07 High density stepped, non-planar nitride read only memory Abandoned US20060183271A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10899906 US7138681B2 (en) 2004-07-27 2004-07-27 High density stepped, non-planar nitride read only memory
US11399874 US20060183271A1 (en) 2004-07-27 2006-04-07 High density stepped, non-planar nitride read only memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11399874 US20060183271A1 (en) 2004-07-27 2006-04-07 High density stepped, non-planar nitride read only memory

Publications (1)

Publication Number Publication Date
US20060183271A1 true true US20060183271A1 (en) 2006-08-17

Family

ID=35731978

Family Applications (3)

Application Number Title Priority Date Filing Date
US10899906 Active 2024-10-28 US7138681B2 (en) 2004-07-27 2004-07-27 High density stepped, non-planar nitride read only memory
US11399761 Active 2025-07-06 US7427536B2 (en) 2004-07-27 2006-04-07 High density stepped, non-planar nitride read only memory
US11399874 Abandoned US20060183271A1 (en) 2004-07-27 2006-04-07 High density stepped, non-planar nitride read only memory

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US10899906 Active 2024-10-28 US7138681B2 (en) 2004-07-27 2004-07-27 High density stepped, non-planar nitride read only memory
US11399761 Active 2025-07-06 US7427536B2 (en) 2004-07-27 2006-04-07 High density stepped, non-planar nitride read only memory

Country Status (1)

Country Link
US (3) US7138681B2 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060180876A1 (en) * 2004-07-27 2006-08-17 Micron Technology, Inc. High density stepped, non-planar nitride read only memory
US20060245255A1 (en) * 2004-08-03 2006-11-02 Micron Technology, Inc. High density stepped, non-planar flash memory
US20080048248A1 (en) * 2006-08-22 2008-02-28 Nec Electronics Corporation Semiconductor memory device
US20080080249A1 (en) * 2006-10-03 2008-04-03 Powerchip Semiconductor Corp. Non-volatile memory, fabricating method and operating method thereof
US20080274625A1 (en) * 2002-12-04 2008-11-06 Micron Technology, Inc. METHODS OF FORMING ELECTRONIC DEVICES CONTAINING Zr-Sn-Ti-O FILMS
US7972974B2 (en) 2006-01-10 2011-07-05 Micron Technology, Inc. Gallium lanthanide oxide films
US8154066B2 (en) 2004-08-31 2012-04-10 Micron Technology, Inc. Titanium aluminum oxide films
US8445952B2 (en) 2002-12-04 2013-05-21 Micron Technology, Inc. Zr-Sn-Ti-O films
US20170084625A1 (en) * 2015-09-18 2017-03-23 Renesas Electronics Corporation Semiconductor device

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6852167B2 (en) * 2001-03-01 2005-02-08 Micron Technology, Inc. Methods, systems, and apparatus for uniform chemical-vapor depositions
US8026161B2 (en) * 2001-08-30 2011-09-27 Micron Technology, Inc. Highly reliable amorphous high-K gate oxide ZrO2
US6844203B2 (en) * 2001-08-30 2005-01-18 Micron Technology, Inc. Gate oxides, and methods of forming
US7160577B2 (en) 2002-05-02 2007-01-09 Micron Technology, Inc. Methods for atomic-layer deposition of aluminum oxides in integrated circuits
US7045430B2 (en) * 2002-05-02 2006-05-16 Micron Technology Inc. Atomic layer-deposited LaAlO3 films for gate dielectrics
US7205218B2 (en) * 2002-06-05 2007-04-17 Micron Technology, Inc. Method including forming gate dielectrics having multiple lanthanide oxide layers
US6790791B2 (en) * 2002-08-15 2004-09-14 Micron Technology, Inc. Lanthanide doped TiOx dielectric films
US7199023B2 (en) * 2002-08-28 2007-04-03 Micron Technology, Inc. Atomic layer deposited HfSiON dielectric films wherein each precursor is independendently pulsed
US7135369B2 (en) * 2003-03-31 2006-11-14 Micron Technology, Inc. Atomic layer deposited ZrAlxOy dielectric layers including Zr4AlO9
US7192824B2 (en) * 2003-06-24 2007-03-20 Micron Technology, Inc. Lanthanide oxide / hafnium oxide dielectric layers
US7202523B2 (en) 2003-11-17 2007-04-10 Micron Technology, Inc. NROM flash memory devices on ultrathin silicon
US7081421B2 (en) 2004-08-26 2006-07-25 Micron Technology, Inc. Lanthanide oxide dielectric layer
US7494939B2 (en) 2004-08-31 2009-02-24 Micron Technology, Inc. Methods for forming a lanthanum-metal oxide dielectric layer
US7462902B2 (en) * 2004-09-17 2008-12-09 Powerchip Semiconductor Corp. Nonvolatile memory
US7235501B2 (en) * 2004-12-13 2007-06-26 Micron Technology, Inc. Lanthanum hafnium oxide dielectrics
US7212440B2 (en) * 2004-12-30 2007-05-01 Sandisk Corporation On-chip data grouping and alignment
US7560395B2 (en) 2005-01-05 2009-07-14 Micron Technology, Inc. Atomic layer deposited hafnium tantalum oxide dielectrics
US7391078B2 (en) * 2005-01-31 2008-06-24 Powerchip Semiconductor Corp. Non-volatile memory and manufacturing and operating method thereof
US7374964B2 (en) * 2005-02-10 2008-05-20 Micron Technology, Inc. Atomic layer deposition of CeO2/Al2O3 films as gate dielectrics
US7687409B2 (en) 2005-03-29 2010-03-30 Micron Technology, Inc. Atomic layer deposited titanium silicon oxide films
US7365027B2 (en) 2005-03-29 2008-04-29 Micron Technology, Inc. ALD of amorphous lanthanide doped TiOx films
US7662729B2 (en) 2005-04-28 2010-02-16 Micron Technology, Inc. Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer
US7269067B2 (en) * 2005-07-06 2007-09-11 Spansion Llc Programming a memory device
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
US7709402B2 (en) 2006-02-16 2010-05-04 Micron Technology, Inc. Conductive layers for hafnium silicon oxynitride films
US20070247924A1 (en) * 2006-04-06 2007-10-25 Wei Zheng Methods for erasing memory devices and multi-level programming memory device
US7605030B2 (en) 2006-08-31 2009-10-20 Micron Technology, Inc. Hafnium tantalum oxynitride high-k dielectric and metal gates
US7760547B2 (en) * 2007-09-25 2010-07-20 Sandisk Corporation Offset non-volatile storage
JP5349903B2 (en) * 2008-02-28 2013-11-20 ルネサスエレクトロニクス株式会社 Method of manufacturing a semiconductor device
US8105884B2 (en) * 2008-10-06 2012-01-31 Samsung Electronics Co., Ltd. Cross point memory arrays, methods of manufacturing the same, masters for imprint processes, and methods of manufacturing masters
US8586962B2 (en) 2008-10-06 2013-11-19 Samsung Electronics Co., Ltd. Cross point memory arrays, methods of manufacturing the same, masters for imprint processes, and methods of manufacturing masters
US9449978B2 (en) * 2014-01-06 2016-09-20 Micron Technology, Inc. Semiconductor devices including a recessed access device and methods of forming same

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5045490A (en) * 1990-01-23 1991-09-03 Texas Instruments Incorporated Method of making a pleated floating gate trench EPROM
US5306941A (en) * 1991-10-09 1994-04-26 Ricoh Company, Ltd. Semiconductor memory device and production process thereof
US5511020A (en) * 1993-11-23 1996-04-23 Monolithic System Technology, Inc. Pseudo-nonvolatile memory incorporating data refresh operation
US5780890A (en) * 1994-12-26 1998-07-14 Nippon Steel Corporation Nonvolatile semiconductor memory device and a method of writing data in the same
US5825062A (en) * 1995-12-12 1998-10-20 Rohm Co., Ltd. Semiconductor device including a nonvolatile memory
US6077745A (en) * 1997-01-22 2000-06-20 International Business Machines Corporation Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array
US6583479B1 (en) * 2000-10-16 2003-06-24 Advanced Micro Devices, Inc. Sidewall NROM and method of manufacture thereof for non-volatile memory cells
US6627945B1 (en) * 2002-07-03 2003-09-30 Advanced Micro Devices, Inc. Memory device and method of making
US6670246B1 (en) * 2002-12-17 2003-12-30 Nanya Technology Corporation Method for forming a vertical nitride read-only memory
US20040066672A1 (en) * 2002-06-21 2004-04-08 Micron Technology, Inc. Vertical NROM having a storage density of 1 bit per IF2
US6720217B2 (en) * 2002-07-18 2004-04-13 Hynix Semiconductor Inc. Method of manufacturing flash memory device using trench device isolation process

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6555870B1 (en) * 1999-06-29 2003-04-29 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and method for producing same
JP3948292B2 (en) * 2002-02-01 2007-07-25 株式会社日立製作所 The semiconductor memory device and manufacturing method thereof
US7050330B2 (en) * 2003-12-16 2006-05-23 Micron Technology, Inc. Multi-state NROM device
US7202523B2 (en) * 2003-11-17 2007-04-10 Micron Technology, Inc. NROM flash memory devices on ultrathin silicon
US7241654B2 (en) * 2003-12-17 2007-07-10 Micron Technology, Inc. Vertical NROM NAND flash memory array
US7190616B2 (en) * 2004-07-19 2007-03-13 Micron Technology, Inc. In-service reconfigurable DRAM and flash memory device
US7138681B2 (en) * 2004-07-27 2006-11-21 Micron Technology, Inc. High density stepped, non-planar nitride read only memory
US20070029610A1 (en) * 2005-08-08 2007-02-08 Houng-Chi Wei Non-volatile memory and fabricating method thereof

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5045490A (en) * 1990-01-23 1991-09-03 Texas Instruments Incorporated Method of making a pleated floating gate trench EPROM
US5306941A (en) * 1991-10-09 1994-04-26 Ricoh Company, Ltd. Semiconductor memory device and production process thereof
US5511020A (en) * 1993-11-23 1996-04-23 Monolithic System Technology, Inc. Pseudo-nonvolatile memory incorporating data refresh operation
US5780890A (en) * 1994-12-26 1998-07-14 Nippon Steel Corporation Nonvolatile semiconductor memory device and a method of writing data in the same
US5825062A (en) * 1995-12-12 1998-10-20 Rohm Co., Ltd. Semiconductor device including a nonvolatile memory
US6077745A (en) * 1997-01-22 2000-06-20 International Business Machines Corporation Self-aligned diffused source vertical transistors with stack capacitors in a 4F-square memory cell array
US6583479B1 (en) * 2000-10-16 2003-06-24 Advanced Micro Devices, Inc. Sidewall NROM and method of manufacture thereof for non-volatile memory cells
US20040066672A1 (en) * 2002-06-21 2004-04-08 Micron Technology, Inc. Vertical NROM having a storage density of 1 bit per IF2
US6627945B1 (en) * 2002-07-03 2003-09-30 Advanced Micro Devices, Inc. Memory device and method of making
US6720217B2 (en) * 2002-07-18 2004-04-13 Hynix Semiconductor Inc. Method of manufacturing flash memory device using trench device isolation process
US6670246B1 (en) * 2002-12-17 2003-12-30 Nanya Technology Corporation Method for forming a vertical nitride read-only memory

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8445952B2 (en) 2002-12-04 2013-05-21 Micron Technology, Inc. Zr-Sn-Ti-O films
US7923381B2 (en) 2002-12-04 2011-04-12 Micron Technology, Inc. Methods of forming electronic devices containing Zr-Sn-Ti-O films
US20080274625A1 (en) * 2002-12-04 2008-11-06 Micron Technology, Inc. METHODS OF FORMING ELECTRONIC DEVICES CONTAINING Zr-Sn-Ti-O FILMS
US7427536B2 (en) * 2004-07-27 2008-09-23 Micron Technology, Inc. High density stepped, non-planar nitride read only memory
US20060180876A1 (en) * 2004-07-27 2006-08-17 Micron Technology, Inc. High density stepped, non-planar nitride read only memory
US8017988B2 (en) 2004-08-03 2011-09-13 Micron Technology, Inc. High density stepped, non-planar flash memory
US7544989B2 (en) * 2004-08-03 2009-06-09 Micron Technology, Inc. High density stepped, non-planar flash memory
US20090218611A1 (en) * 2004-08-03 2009-09-03 Micron Technology, Inc. High density stepped, non-planar flash memory
US20060245255A1 (en) * 2004-08-03 2006-11-02 Micron Technology, Inc. High density stepped, non-planar flash memory
US8541276B2 (en) 2004-08-31 2013-09-24 Micron Technology, Inc. Methods of forming an insulating metal oxide
US8154066B2 (en) 2004-08-31 2012-04-10 Micron Technology, Inc. Titanium aluminum oxide films
US9583334B2 (en) 2006-01-10 2017-02-28 Micron Technology, Inc. Gallium lanthanide oxide films
US9129961B2 (en) 2006-01-10 2015-09-08 Micron Technology, Inc. Gallium lathanide oxide films
US7972974B2 (en) 2006-01-10 2011-07-05 Micron Technology, Inc. Gallium lanthanide oxide films
JP2008053270A (en) * 2006-08-22 2008-03-06 Nec Electronics Corp Semiconductor memory device, and its manufacturing method
US7692237B2 (en) * 2006-08-22 2010-04-06 Nec Electronics Corporation Semiconductor memory device
US20080048248A1 (en) * 2006-08-22 2008-02-28 Nec Electronics Corporation Semiconductor memory device
US20080080249A1 (en) * 2006-10-03 2008-04-03 Powerchip Semiconductor Corp. Non-volatile memory, fabricating method and operating method thereof
US20170084625A1 (en) * 2015-09-18 2017-03-23 Renesas Electronics Corporation Semiconductor device
US9780109B2 (en) * 2015-09-18 2017-10-03 Renesas Electronics Corporation Semiconductor device

Also Published As

Publication number Publication date Type
US20060180876A1 (en) 2006-08-17 application
US20060023513A1 (en) 2006-02-02 application
US7427536B2 (en) 2008-09-23 grant
US7138681B2 (en) 2006-11-21 grant

Similar Documents

Publication Publication Date Title
US6489649B2 (en) Semiconductor device having nonvolatile memory and method of manufacturing thereof
US6348380B1 (en) Use of dilute steam ambient for improvement of flash devices
US6265268B1 (en) High temperature oxide deposition process for fabricating an ONO floating-gate electrode in a two bit EEPROM device
US7450423B2 (en) Methods of operating non-volatile memory cells having an oxide/nitride multilayer insulating structure
US7122415B2 (en) Atomic layer deposition of interpoly oxides in a non-volatile memory device
US7405968B2 (en) Non-volatile memory cell using high-K material and inter-gate programming
US6551948B2 (en) Flash memory device and a fabrication process thereof, method of forming a dielectric film
US5998264A (en) Method of forming high density flash memories with MIM structure
US7199023B2 (en) Atomic layer deposited HfSiON dielectric films wherein each precursor is independendently pulsed
US6458677B1 (en) Process for fabricating an ONO structure
US6406960B1 (en) Process for fabricating an ONO structure having a silicon-rich silicon nitride layer
US6686632B2 (en) Dual-bit multi-level ballistic MONOS memory
US7115469B1 (en) Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process
US6091101A (en) Multi-level flash memory using triple well
US6963103B2 (en) SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators
US6949481B1 (en) Process for fabrication of spacer layer with reduced hydrogen content in semiconductor device
US7227234B2 (en) Embedded non-volatile memory cell with charge-trapping sidewall spacers
US7135421B2 (en) Atomic layer-deposited hafnium aluminum oxide
US6319775B1 (en) Nitridation process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device
US20040070020A1 (en) Nonvolatile semiconductor memory device and method for operating the same
US20090039414A1 (en) Charge trapping memory cell with high speed erase
US20060131633A1 (en) Integrated two device non-volatile memory
US6803275B1 (en) ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices
US20060166443A1 (en) Multi-state NROM device
US20060110870A1 (en) Scalable integrated logic and non-volatile memory