US20060174081A1 - Memory interface and method of interfacing between functional entities - Google Patents

Memory interface and method of interfacing between functional entities Download PDF

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US20060174081A1
US20060174081A1 US11/331,643 US33164306A US2006174081A1 US 20060174081 A1 US20060174081 A1 US 20060174081A1 US 33164306 A US33164306 A US 33164306A US 2006174081 A1 US2006174081 A1 US 2006174081A1
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function
memory
processor core
interface
method
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David Latta
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David Latta
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1647Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4022Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units

Abstract

A data and signal interface for controlling the transfer of data and signals between a memory array and macro function such as that of a digital signal processor (DSP) core. In one embodiment, the interface comprises a plurality of memory ports which interface with X/Y memory banks, a plurality of function ports, each with a function controller, which interface with DSP functions, a crossbar connecting the memory and function ports, and an arbitration unit for arbitrating memory access by the function ports. The memory interface advantageously allows multiple simultaneous accesses of memory banks via a plurality of macro functions, each access under the control of a parent processor instruction. A standardized protocol used for memory read/write operations is also disclosed.

Description

    PRIORITY
  • This application is a divisional of U.S. patent application Serial No. 09/801,241 filed Mar. 7, 2001, entitled “Memory Interface And Method Of Interfacing Between Functional Entities”, which claims priority benefit to U.S. provisional patent application Serial No. 60/188,546 filed Mar. 10, 2000 and entitled “Memory Interface and Method of Interfacing Between Integrated Circuits.”
  • RELATED APPLICATIONS
  • This application is related to pending U.S. patent application Ser. No. 09/418,663 filed Oct. 14, 1999 entitled “Method and Apparatus for Managing the Configuration and Functionality of a Semi-Conductor Design”, now U.S. Pat. No. 6,862,563, which claims priority benefit of U.S. provisional patent application Serial No. 60/104,271 filed Oct. 14, 1998, of the same title.
  • COPYRIGHT
  • A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
  • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to the field of integrated circuit design, specifically to the integration of peripheral components and macro functions with a central processing unit (CPU) or user-customizable microprocessor.
  • 2. Description of Related Technology
  • As semiconductor processing capabilities increase the number of transistors that can be economically built on a single Integrated Circuit (IC), systems designers are made less effective by the difficulty encountered in combining large-scale macro blocks on a single IC. Such large-scale macro blocks (or “macro functions”) include, for example, those associated with third generation (“3G”) communications architectures, such as functions performing Viterbi butterfly decode, cyclic redundancy checks (CRC), convolutional encoding/decoding, permutation, and carrier modulation/demodulation. Some of the problems encountered by the designer are underscored by the need to integrate special purpose functions with an existing instruction set implemented by a given central processing unit (CPU). Often, a non-integrated design approach is employed, wherein the large-scale macro blocks or functions are treated as separate entities from the processor core, thereby requiring additional complexity, as well as specialized or unique interfaces between the core and its associated functions which are not standardized across the device. Specifically, with respect to memory interfaces, the use of control registers associated with the memory ports of the interface not only complicates the design, but also may under certain circumstances limit or restrict the functionality of the interface. For example, individual macro blocks associated with the design may be precluded from acting on data in separate memory banks simultaneously, thereby hindering the performance of the design as a whole by requiring that memory accesses be performed in “lock-step” fashion.
  • Prior art treatment of large-scale macro functions as separate entities within the design has further disabilities relating to memory. In particular, since the macro block is effectively a separate entity from the core, memory interfaces to existing core memory are often quite complex, thereby often necessitating the provision of separate memory dedicated to the macro function (or shared between multiple macro functions). The requirement for such additional memory adds cost and complexity to the device, as well as monopolizing already precious real estate on the die. This is especially true for so-called “system-on-a-chip” (SoC) designs, where available memory is often a limiting parameter. Additionally, such dedicated “off-core” memory is by definition not local to the core, and hence results in increased latency when such memory must be accessed by the core.
  • Furthermore, as more such large-scale macro function blocks are added to the design, the propensity for such increased complexity and non-standardization across the design increases accordingly.
  • Furthermore, conventional interface mechanisms are typically based on a common bus, and transfers between peripherals and the core(s) are arbitrated by one or more direct memory access (DMA) controllers. However, under such an approach, the timed transfer of data may not be deterministic, which is often a crucial requirement for DSP applications. Specifically, DSP systems often require not only that data are processed correctly mathematically, but that results are delivered at the right time. In this sense a “deterministic” transfer is one for which the timing is exactly known.
  • Based on the foregoing, there is a need for an improved apparatus and method for enabling macro functions and peripherals present on an integrated device to interface with the device processor core in a simple and standardized manner. Such improved interface would not only allow for standardized interface between macro-functions across the device, but also allow multiple macros to interface with individual (or a plurality of) memory banks simultaneously. Such improved apparatus and method would also ideally obviate separate or discrete local memory now used in support of macro (e.g., DSP core) functions, and facilitate deterministic transfer of data between functional entities in the design.
  • SUMMARY OF THE INVENTION
  • The present invention satisfies the aforementioned needs by an improved apparatus and method for interfacing between integrated circuit devices, such as between a digital processor and associated memory array.
  • In a first aspect of the invention, an improved interface apparatus useful for interfacing between an external device and one or more processor functions is disclosed. In one exemplary embodiment, the external device comprises a memory array, and the interface comprises a plurality of memory ports, a plurality of function ports with associated function controllers, a crossbar connecting the memory ports to the function ports, and an arbitration unit for arbitrating memory accesses and facilitating burst load/store operations. The interface apparatus enables a macro block to be integrated with the CPU, controlled with a custom processor instruction, and act directly on CPU local memory banks. Other macro blocks can also access data in other banks simultaneously. Under CPU control, blocks of data can be acted on by macro functions in a pipelined fashion. The local CPU memory banks therefore replace memory that might otherwise be duplicated in the macro block. Once acquired, data is local to the CPU which can also act on it without unnecessary additional latency.
  • In a second aspect of the invention, an improved data transfer protocol used in conjunction with the aforementioned interface is disclosed. In one embodiment, the protocol comprises a synchronous protocol using a plurality of registers disposed within the aforementioned functional control units of the function ports. Data exchange with the memory interface is synchronized with the clock of the processor core, and data is strobed in and out of the memory after memory access has been requested and granted. The grant of memory access requests is delayed if the requested memory bank is being accessed for a burst load/store operation, or by the processor core. The protocol of the invention supports, in conjunction with the memory interface, multiple simultaneous strobed accesses to different memory banks by different macro functions (function ports) associated with the interface.
  • In a third aspect of the invention, an improved data processing apparatus is disclosed. The device generally comprises a processor core, the aforementioned memory interface, at least one macro function, XY memory array, and I/O interface. In one exemplary embodiment, the processor core comprises an extensible RISC-based digital processor, and the macro function comprises a digital signal processor (DSP). The DSP may be a general purpose DSP, or alternatively any one of a number of algorithmically optimized designs which are adapted to perform certain data processing tasks. The RISC processor and DSP are tightly coupled such that the DSP and memory interface effectively become part of the RISC processor's instruction set, the macro function (DSP) being controlled by, for example, decoded instructions generated by the pipeline decode stage of the RISC processor. Furthermore, peripheral devices can have direct memory access (DMA) capability with respect to the XY memory array via the I/O interface. The components are also advantageously combined into a single-die integrated circuit device. In another embodiment, the device comprises a “3G” ASIC having a plurality of macro blocks including a signal receiver and demodulator, “turbo” or Viterbi decoder, block cyclic redundancy code (CRC) calculation macro, block permute macro, block convolution encoder macro, and modulator and transmitter, all of which are coupled to the core memory array via the memory interface.
  • In a fourth aspect of the invention, a method of interfacing between a memory and one or more processor functions is disclosed. In one exemplary embodiment, the method comprises specifying a number of function ports for an interface; specifying a number of memory ports for the interface; setting a number of control and other registers based on the function port configuration; specifying an interface protocol; initiating the function(s) associated with the function port(s); arbitrating one or more memory accesses; and performing read/write access to memory according to the selected protocol and control by the parent processor core.
  • In a fifth aspect of the invention, a method of testing a function associated with the previously described memory interface is disclosed. In one exemplary embodiment, the method comprises providing a memory interface having at least one memory port and associated memory array, at least one function port and associated function, and at least one control register used for controlling said function; providing a test sequence; providing an input test value in the memory array; initiating the function; generating results from the operation of the function on the input test value; and comparing the results returned by the function against a known value in order to test the operation of the function.
  • In a sixth aspect of the invention, an improved method of designing an integrated circuit device having an extensible processor core, secondary processor (e.g., DSP) or macro function, and memory interface is disclosed. In one embodiment, the method comprises providing an extensible core; providing at least one macro function; providing at least one memory interface; adding an HDL (hardware description language) “wrapper” around the DSP or macro function, the HDL wrapper adapted to (i) translate signals, (ii) buffer memory interfaces, and (iii) synchronize clock signals with the memory interface. In another embodiment, the method comprises providing an extensible core; providing at least one “soft” macro function; providing at least one memory interface as described previously herein; and adapting the “soft” macro function implementation to meet the specification associated with the memory interface.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a plot of data sample rate versus type of application, illustrating the relationship between various types of processor architectures and their possible applications.
  • FIG. 2 is a block diagram of one exemplary embodiment of the memory interface according to the present invention.
  • FIG. 2 a is a logical block diagram of one exemplary embodiment of logic adapted to provide decoded instruction and operand information from the parent processor's decode pipeline stage to the memory interface of the invention.
  • FIG. 3 is a block diagram illustrating a first application of the interface of FIG. 2, wherein the DSP core is “tightly” coupled to the parent processor core (e.g. ARC) and XY memory.
  • FIG. 4 is a block diagram illustrating a second application of the interface of FIG. 2, wherein the DSP core is served by a separate I/O interface, the DSP core being controlled by the processor core.
  • FIG. 5 is a block diagram illustrating a third application of the interface of FIG. 2, wherein the interface is used to interface directly between an I/O device and the XY memory.
  • FIG. 6 is block diagram of one embodiment of the interface of the invention, illustrating the various signals and registers associated therewith.
  • FIG. 6 a is a logical flow diagram illustrating one exemplary embodiment of the method for testing a macro function using the memory interface of the present invention.
  • FIG. 7 is a timing diagram illustrating one embodiment of the protocol used in conjunction with the interface of the present invention.
  • FIG. 8 is a block diagram of one exemplary embodiment of an integrated processor device including a processor core, DSP core, XY memory, and the memory interface of the present invention.
  • FIG. 9 is a block diagram of a second embodiment of an integrated processor device including the memory interface of the present invention and a plurality of macro function entities, the processor device and macro function entities being adapted for 3G communications.
  • FIG. 9 a is a logical block diagram illustrating the operation of one exemplary embodiment of the macro function “pipeline” using the memory interface of the present invention.
  • FIG. 10 is a logical flow diagram illustrating one embodiment of the method of interfacing a function with a memory array according to the invention.
  • FIG. 11 is a logical flow diagram illustrating one exemplary embodiment of the method of generating a design for an integrated circuit device having a parent processor, a memory interface, and at least one macro function associated therewith, wherein an HDL “wrapper” is used as the macro function interface.
  • FIG. 11 a is a logical flow diagram illustrating one embodiment of the method of adding an HDL wrapper according to FIG. 11.
  • FIG. 12 is a logical flow diagram illustrating a second embodiment of the method of generating a design for an integrated circuit device having a parent processor, a memory interface, and at least one macro function associated therewith, wherein a “soft” macro function is utilized and adapted to the requirements of the memory interface.
  • DETAILED DESCRIPTION
  • Reference is now made to the drawings wherein like numerals refer to like parts throughout.
  • As used herein, the term “processor” is meant to include any integrated circuit or other electronic device capable of performing an operation on at least one instruction word including, without limitation, extensible reduced instruction set core (RISC) processors such as the ARC™ user-configurable core manufactured by the Assignee hereof, central processing units (CPUs), and digital signal processors (DSPs). Furthermore, various functional aspects of the processor may be implemented solely as software or firmware associated with the processor.
  • As used herein, the term “parent” processor refers generally to the aforementioned ARC core (or similar), while the term “host” processor refers generally to an external processor which controls the operation of the ARC core and/or other functional aspects of the design.
  • Additionally, it will be recognized by those of ordinary skill in the art that the term “stage” as used herein refers to various successive stages within a pipelined processor; i.e., stage 1 refers to the first pipelined stage, stage 2 to the second pipelined stage, and so forth.
  • It is also noted that while portions of the following description are cast in terms of VHSIC hardware description language (VHDL), other hardware description languages such as Verilog® may be used to describe various embodiments of the invention with equal success. Furthermore, while an exemplary Synopsys® synthesis engine such as the Design Compiler 2000.05 (DC00) is used to synthesize the various embodiments set forth herein, other synthesis engines such as Buildgates® available from, inter alia, Cadence Design Systems, Inc., may be used. IEEE std. 1076.3-1997, IEEE Standard VHDL Synthesis Packages, describe an industry-accepted language for specifying a Hardware Definition Language-based design and the synthesis capabilities that may be expected to be available to one of ordinary skill in the art.
  • Overview
  • The memory interface of the present invention has been conceived to enable, inter alia, DSP macro functions and peripherals to interface with another processor core using a simple and standard methodology. Close integration with predefined VLSI functions increases the ability to satisfy demanding applications and meet emerging industry standards, such as those relating to so-called “3G” applications. For certain high-speed communications tasks, only custom DSP and input/output (I/O) functions can meet the processing demands. This concept is illustrated in FIG. 1.
  • The extensible nature of certain processor cores (e.g., the Applicant's “ARC” core) and associated XY memory allow DSP and I/O functions to be tightly coupled for such demanding applications. Using the apparatus and methodology of the present invention, the DSP core(s) effectively become part of the parent processor core instruction set, and I/O peripherals have direct memory access (DMA) to the processor core.
  • Furthermore, many algorithmically optimized DSP core designs exist. Combining dedicated hardware functional performance and software flexibility within the same IC advantageously provides the most cost effective and shortest time to market for new product development.
  • Description of Interface
  • Referring now to FIG. 2, one exemplary embodiment of the memory interface of the present invention is described. As shown in FIG. 2, the interface 200 comprises generally a plurality of memory ports 202, a plurality of function ports 204, a plurality of function controllers 206 associated with the aforementioned function ports 204, and an arbitration controller 208. The interface 200 is designed to interface between various “macro” functions 210 associated with a logic or processing device typically in the form of an integrated circuit (IC) such as a DSP, microprocessor, or ASIC (hereinafter generally referred to as “IC function”), and a memory array 212 having a plurality of individual memory banks 214. While an interface 200 having a plurality of ports 202, 204 is shown, it will be recognized that the interface device 200 of the present invention may be implemented with any lesser number of ports, such as one memory port 202 and one function port 204.
  • The number of function ports 204 (and hence macro functions 210) is determined by the algorithmic needs of a particular application, and the necessity for hardware acceleration in that application. The number of memory ports 202 (and hence memory banks 214) is determined by the virtual flow of data between macro function blocks, the latter equivalent to a macro function block processing pipeline under CPU control. If a macro block 210 is processing data from a peripheral device (such as shown in FIG. 6 herein) before storing to CPU local memory, then the number of memory banks 214 is determined by the buffering requirements associated with the macro block function, and the ability of the CPU to process data in software.
  • The memory ports 202 of the apparatus of FIG. 2 comprise interfaces with the banks 214 of the array 212. Advantageously, there are no control registers associated with the memory ports 202; rather, control is performed via the associated IC function 210. The interface 200 arbitrates access to each of the memory banks 214 using the arbitration controller 208. The memory ports of the illustrated embodiment comprise simple address, data, read, write, select, and control signals required by typical random access memory (RAM) design instantiations as are well known in the semiconductor arts, thereby making optimal use of existing technology.
  • One embodiment of the arbitration controller logic is described. The arbitration controller 208 comprises a multiplexer adapted to select between burst, direct memory interface (DMI) devices, debug (not shown) functions, and the processor. The construction and operation of multiplexer devices are generally well known in the semiconductor arts, and accordingly not described further herein. The multiplexer of the present invention, however, is controlled by logic which provides the following priority structure: (i) the burst address is selected with the highest priority; (ii) external device permission to access the memory of the bank is given next priority; (iii) the debug channel is selected when the parent processor core (e.g., ARC) is halted, and the host device attempts to access the XY memory; and (iv) the processor source and destination operand busses are otherwise selected if appropriate. It will be recognized that other priority structures may be implemented consistent with the invention, however.
  • The function ports 204 comprise the interface of the memory interface 200 with the IC functions 210. All data, control, and clock signals are routed through the function ports 204. A synchronous protocol, described in detail herein with respect to FIG. 7, is used in the present embodiment to facilitate read/write data transfer through the ports 204, although it can be appreciated that other protocols (synchronous or non-synchronous) may be substituted. It will be recognized that the illustrated arrangement shows a minimum interface requirement, and other more complex or functionally enhanced arrangements (or combinations thereof) can be substituted. For example a virtual component interface (VCI) of the type well known in the art could be used consistent with the invention.
  • The function controllers 206 comprises the control, status, and test registers (see Tables 4-6 below) associated with each of the IC functions 210. The function controllers also include an interface (as illustrated in the exemplary configuration of FIG. 2 a) to the core processor's stage two instruction decode and source operand value.
  • The interface 200 of the invention further utilizes a data transfer “fabric” which interconnects the memory ports 202 with the function ports 204, thereby facilitating data distribution within the interface. In the embodiment illustrated in FIG. 2, the fabric comprises a crossbar arrangement (represented by the series of arrows 216 of FIG. 2) for data communication between the ports 202, 204, although it will be appreciated that other techniques for (selectively) communicating data form one or more ports to one or more ports may be utilized. The construction and operation of crossbar switches is well known in the electronic arts, and accordingly is not described further herein.
  • Using the aforementioned crossbar arrangement, each IC function 210 is connected through the interface 200 to a bank 214 of the memory array 212, and multiple functions/banks may be connected simultaneously. In the illustrated embodiment, the memory array 212 comprises XY memory. Such memory may comprise, for example, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double-data rate (DDR) SDRAM, embedded/flash memory, or any other type of memory suitable for the desired application. Such memory devices are well known in the semiconductor arts, and accordingly will not be described further herein. The determination of which memory bank 214 in the array 212 is accessed is made either by (i) a control register in processor core auxiliary register space; or (ii) the instruction operand (e.g. “FFT 2” of the aforementioned ARC core). For example, in the case where the IC function comprises a DSP, the individual functions associated with the DSP can access any of the XY memory banks 214 in the array 212 for intermediate calculations and results. In one embodiment of the invention, the XY memory is implemented as two pages of memory, and adapted such that two operand sources may be provided simultaneously. Alternatively, provision may be made for selection between one of the two pages of memory at any one time if desired.
  • It is noted that different DSP cores (or other types of processor cores) will generally have varying interface, control and memory requirements. The interface 200 of the present invention advantageously provides the designer with the ability to integrate cores of various configurations directly with the parent processor core (e.g., extensible ARC processor) instruction and operand decode mechanism, auxiliary register, and on-core memory resources. The chip/system designer may choose to either to add an HDL “wrapper” around the DSP or core to translate signals, buffer memory interfaces, and synchronize clock signals, or alternatively modify the “soft” DSP core implementation to meet the specification associated with the memory interface 200, as described below with respect to FIGS. 11 a and 11 b.
  • Referring now to FIGS. 3-5, exemplary applications of the memory interface 200 of the present invention are described, illustrating how the interface 200 can be used to integrate devices such as DSP cores, ASICS, or other types of peripherals. As illustrated in FIG. 3, a DSP core 302 may be tightly coupled to an associated processor core (e.g., ARC) using the interface 200. As used herein, the term “tightly coupled” refers generally to the degree of interaction and coherence between the DSP core, interface, and parent processor. In the example of FIG. 3, the DSP core 302 can act on buffered data contained in the XY memory bank 212. The interface 200 of the present invention allows the DSP core 302 to be initiated by an instruction from the parent processor core (not shown), and uses the parent processor core extension registers for control. Specifically, auxiliary registers may be mapped to control the macro function block 210 and report status, and may be accessed through “LR” and “SR” instructions, as illustrated in the following example:  ld %r0, #CONTROL_WORD  sr %r0, [macro_control] ; load the control word into auxiliary reg.  ld %r0, #BANK  go_macro 0, %r0 ; source operand contains bank to act on : : Irq_macro_ready:  lr %r0, [macro_status] ; read status Copyright © 2001 ARC International plc. All rights reserved.
  • As illustrated in FIG. 4, some DSP core functions (such as calculations performed in support of the aforementioned high-speed 3G communications) may require data at a higher rate than can be provided by the parent processor core. In the example of FIG. 4, the DSP core 302 is served with data by a local peripheral device 404 (such as a data storage device), and delivers “processed” results (such as, for example, the output of a FFT algorithm, packing/unpacking data from a high data rate bit stream, or Viterbi decode metrics) directly into the XY memory 214 of the processor. The interface 200 further provides support for interrupts and flags to indicate, inter alia, block filled or empty status. As shown in FIG. 6, DSP function status signals may be connected to bits in registers mapped into the parent processor's auxiliary register space. Similarly, bits in that register may be used to enable the routing of interrupt signals from the DSP function to processor's interrupt controller.
  • As illustrated in the example of FIG. 5, the I/O peripheral device 404 may also interface directly with the memory interface 200. In this manner, unprocessed or “raw” data may be delivered directly to the various memory banks 214 within the memory array 212 as arbitrated by the interface 200. Hence, the memory interface advantageously allows the memory array to act as a multi-bank buffer for storage and subsequent read-out of such raw data.
  • In terms of operation, the functions of the DSP core 302 (or other IC function in communication with the interface 200) may, if desired, be initiated by the processor core (e.g. ARC™) pipeline stage 2 instruction decode, and also may optionally use the operand value. Other schemes of DSP core or peripheral initiation may also be used consistent with the invention. For example, it is also possible to initiate and control the DSP core or IC function using one or more control/status registers within the auxiliary space associated with the parent processor.
  • It is also noted that one or more XY memory banks 214 within the array 212 can advantageously be filled by a “burst” mode load while DSP functions execute on other memory banks. The memory interface 200 and the X/Y memory burst control unit (not shown) arbitrate between accesses. The burst control unit provides direct memory access (DMA) between the main memory and the XY memory system. Its functionality includes the ability to transfer blocks of data, and in one embodiment is integrated with the existing XY system. Note also that the arbitration unit of the present invention includes logic to arbitrate between the processor, an external DSP core (via DMI), host debug port (also not shown) and the parent processor, as previously described.
  • In one embodiment, the occupied memory resource is “locked out” by one access to another using a first-in-time method (i.e., whichever access is initiated first will lock the other access out until completed), as illustrated below:  ld %r0, #CONTROL_WORD  sr %r0, [macro_control] ; load the control word into auxiliary reg.  go_macro 0, %r0 ; source operand contains bank to act on : :  mov %r0, x0_u Copyright © 2001 ARC International plc. All rights reserved.

    In the foregoing example, the move (mov) instruction is attempting to transfer data from XY memory into a core register. Two arbitration solutions are possible: (i) either stall the move operation until the macro function completes, or (ii) with additional control logic, stall the macro function and allow processor access to a non-conflicting memory region.
  • It will be recognized, however, that other types of memory arbitration of the type well known in the art may be utilized to provide non-conflicting memory resource access, round-robin or prioritized arbitration with time division, queued or packetized transfer.
  • If either the aforementioned burst mode or DSP core function have control over X/Y memory, then “read or “write” operations by the parent processor core to that memory bank will be invalid, but this will not stall the processor core, as block transfers are, in the present embodiment, permitted to take multiple cycles. Hence, in this embodiment, the programmer has the responsibility of ensuring that such automated memory accesses, once initiated, have completed, although other mechanisms for ensuring memory access operation completion may conceivably be used. The following shows a polled solution to invalid parent processor XY access during burst mode:   sr [burst_control], ; DMA data into #INITIATE_BURST XY memory. : ; No access to same XY bank here : ; Wait:   lr %r0, [burst_status]   bne Wait ; Wait for DMA to complete   mov %r0, x0_u ; XY access allowed Copyright © 2001 ARC International plc. All rights reserved.

    Data Transfer Protocol
  • When the DSP core 302 or I/O device 404 (FIGS. 3-5) requests access to a memory bank 214 within the array 212, access is arbitrated by the interface 200, specifically the arbitration controller 208 (FIG. 2). The interface 200 of the invention provides data, address, XY page and read/write selection using a memory request/memory grant system which is synchronous with the system clock (CLK). FIG. 6 illustrates a simple interface configuration 600, based on a standard bus-request/bus-grant mechanism, having only one memory port 602 and one function port 604. The interface 600 is coupled via the function port 604 to a DSP function 610, which is coupled to an I/O peripheral 620. The X/Y memory banks 614 interface directly with the memory port 602 of the interface 600. The function controller 606 includes the data, control, and debug register set for the function port 604, and also interfaces with the stage 2 instruction decode (1-bit) and operand (32-bit) of the parent processor core.
  • The signal set associated with the exemplary interface 600 of FIG. 6 is now described with respect to Tables 1-3 below. Table 1 lists interface signals for the interface 600 and their associated functions. Table 2 lists memory request/grant signals. Table 3 lists register control signals and signals generated by the processor core (e.g. ARC™) used to initiate function execution and to provide immediate operands from pipeline stage 2, as previously described.
  • In the present invention, the control signals used to initiate the macro function are duplicated in one or more control registers. Specifically, in one embodiment, the signals are connected such that a “write” operation to the control register in auxiliary space is registered as a valid command as if correct in stage 2 of the processor pipeline. This ability, inter alia, facilitates the testing of the macro block through the host interface, as described below in greater detail. As auxiliary registers will be accessible from the host interface, this design feature advantageously ensures that the function can be tested. For example, a test sequence might write an input test vector into XY memory, initiate the macro function, and then compare returned results against a known vector. This process is depicted graphically in FIG. 6A. Such process may be applied to any number of different operations including, for example, decoding of convolution-encoded data by a Viterbi function (and “Turbo” decode), or correct calculation of a CRC for a block of data.
  • Additional auxiliary registers may be used for test purposes as well. For example, in Applicant's ARC core, four test registers are configured for each function port by default. Specifically, if a macro block is connected to a peripheral device, the four test registers can be used to simulate the action of that peripheral under software control. Comparison of transform results in memory to the known stimulus can therefore be achieved for validation of the correct functioning of the macro block 210, advantageously without having to generate real-world stimuli. Other uses of the test registers are possible depending on the testing/operational requirements. It will also be recognized, however, that such additional auxiliary registers are optional, and may be specified in any number desired by the programmer/designer as allowed by the hardware constraints.
  • In the present embodiment, a number of read/write registers associated with each function port are provided. A default value is normally set, but as with the auxiliary registers, this number may vary. These read/write registers are used for control and data requirements specific to the function associated with the function port, such as, for example, error reporting such as internal data saturation of a fast fixed-point FFT block, status of a connected peripheral, etc.
  • One or more control registers are also provided. A basic requirement of the control register in the present invention is that power control and external function reset capabilities are provided. This reset (or other control) forces the function to release the memory bank back to the parent processor core. Interrupt control is provided and enabled by the control register, but the IC function also reports internal function status to the processor core using flags.
  • Tables 4-6 list registers used within the exemplary interface 600 of FIG. 6. Table 4 lists control/status registers; in the illustrated embodiment, two control/status registers are provided which control read/write operations. Table 5 lists general purpose registers; four general purpose registers are provided within the interface 600 for passing control parameters and data to the IC function, and for implementing special features. For example, the control parameters passed to the IC function could comprise FFT size or window type, and the IC function could return a block exponent or cyclic redundancy code (CRC) via the general purpose registers. Another example is for a DES instruction having the key code and accumulators as extension registers. Many other uses are possible.
  • Table 6 lists test/debug registers within the interface 600; four registers are provided in the present embodiment for, inter alia, function specific testing and debug capability. For example, as previously described, if a macro block is connected to a peripheral device the test registers might be used to simulate the action of that peripheral under software control, with comparison of transform results in memory to the known stimulus without having to generate real-world stimuli. TABLE 1 Interface Signals Signal Description DMI_DATA Data read/write bus from custom function. 16/32-bit data. DMI_ADDR Address bus from custom function. Bus size depends on bank size. DMI_X/Y Signal from custom function selects X or Y bank for read or write. DMI_1632 Signal from custom function selects 16 or 32- bit addressing and data bus mode. DMI_R*/W Signal from custom function requests read or write. DMI_BNK Signal from custom function requests XY bank for transfer.
  • TABLE 2 Memory Request/Grant Signals Signal Description DMI_CLK System clock output from ARC Memory Interface. DMI_MR Memory request signal from custom function. DMI_MG Memory grant signal from ARC Memory Interface. DMI_DS Data strobe signal from custom function.
  • TABLE 3 Register Control Signals Signal Description DMI_CTRL Control signals output from ARC Memory Interface control/status register. DMI_STAT Status signals from custom function. DMI_IRQ Interrupt signals from custom function (enabled in control/status register. DMI_INS ARC state 2 instruction decode (via ARC Memory Interface) used to initiate function execution. DMI_OP ARC state 2 operand (via ARC Memory Interface) used for basic function parameters.
  • TABLE 4 Register Control Signals Signal Description DMI_CTRLx Write: IRQ enable, reset, power, run/stop, clear error, test mode, free bits . . . DMI_Opx Write: Set operand for function initiation via DMI_CTRLx. Read: An error code may be returned by a read.

    Notes:
  • 1. Default bit positions are defined in the implementation specification.
  • For example, the settings of Table 4a are representative bit positions: TABLE 4a Representative Bit Positions 8 7 6 5 4 3 2 1 0 RESET IRQ_ENABLE POWER RUN CLEAR TEST TEST TEST TEST ERROR MODE3 MODE2 MODE1 MODE0
  • 2. An “x', in the register name specifies the function to which the register applies. All registers of the illustrated embodiment are 32-bits. TABLE 5 General Purpose Registers Signal Description DMI_GPOx Function specific read/write register. DMI_GP1x Function specific read/write register. DMI_GP2x Function specific read/write register. DMI_GP3x Function specific read/write register.
  • TABLE 6 Test/debug Registers Signal Description DMI_DBGOx Function specific read/write test/debug register. DMI_DBGOx Function specific read/write test/debug register. DMI_DBGOx Function specific read/write test/debug register. DMI_DBGOx Function specific read/write test/debug register.

    It is noted that while the foregoing embodiment described a specific number of signals and registers associated with these signals, variations in the configuration of the interface, including the number and function of signals, and/or the number of registers, may be employed depending on the specific application and needs of the designer/programmer.
  • Referring now to FIG. 7, one embodiment of the interface protocol according to the invention is described. While the DSP function 610 may have its own clock, data exchange with the interface 600 is, in the present embodiment, synchronized with the clock of the processor core. Data is strobed in and out of the memory 612 after memory access has been requested and granted as previously described.
  • As illustrated in FIG. 7, the clock signal (DMI_CLK) 701 comprises a regular periodic clock signal of the type well known in the art. During a write cycle 702, the memory request and grant signals (DMI_MR, DMI_MG) 703, data strobe signal (DMI_DS) 704, data read/write signal from the IC function (DMI_R/*W) 706, and addressing/bus size select/X or Y memory bank select signals (DMI_ADDR, DMI_X/Y, and DMI_1632, respectively) 708, 710, 712 are set as indicated in FIG. 7 to perform a write operation from the data bus (DMI_Data) 714 to the selected address within the X or Y bank via the interface 600. Conversely, during the read cycle, the interface 600 sets the aforementioned signals 703, 704, 706, 08, 710, 712 as appropriate to load data from the selected memory bank 614 and transfer it to the IC function using the interface 600; i.e., via the memory port, fabric, and function port to the IC function.
  • FIG. 8 illustrates an exemplary pipelined processor (system) fabricated using a 1.0 micron process. As shown in FIG. 8, the processor 800 includes, inter alia, a processor core 802, on-chip read-only memory 804, XY random access memory 806, a DSP core 808, memory interface 200, ADC 812, DAC 814, custom analog and/or digital circuitry 816, and an external interface 818. The device is fabricated using the customized VHDL design methodology of Applicant's co-pending U.S. patent application Ser. No. 09/418,663 entitled “Method and Apparatus for Managing the Configuration and Functionality of a Semiconductor Design” filed Oct. 14, 1999, which is incorporated herein by reference in its entirety. The interface 200 of the present invention may advantageously be integrated directly into the configuration environment described therein, as discussed in greater detail below with respect to FIGS. 11-12. Many of the interface 200 configuration parameters, such as the number of memory ports, may be inherited directly from the XY memory configuration specified in this environment. The generated design is subsequently synthesized into a logic level representation, and then reduced to a physical device using compilation, layout and fabrication techniques well known in the semiconductor arts.
  • It will be appreciated by one skilled in the art that the processor of FIG. 8 may contain any commonly available peripheral such as serial communications devices, parallel ports, timers, counters, high current drivers, LCD drivers, memories and other similar devices. The present invention is not limited to the type, number or complexity of peripherals and other circuitry that may be combined using the method and apparatus. Rather, any limitations are imposed by the physical capacity of the extant semiconductor processes which improve over time. Therefore it is anticipated that the complexity and degree of integration possible employing the present invention will further increase as semiconductor processes improve. For example, the present invention is compatible with 0.35, 0.18, and 0.1 micron processes, and ultimately may be applied to processes of even smaller or other resolution. An exemplary process for fabrication of the device is the 0.1 micron “Blue Logic” Cu-11 process offered by International Business Machines Corporation, although others may be used.
  • FIG. 9 illustrates yet another embodiment of an integrated circuit 900 fabricated using the apparatus and methods of the present invention. Specifically, the IC comprises an application specific integrated circuit (ASIC) embodying a “3G” (i.e., third generation) communications application having a plurality of macro functional blocks 210. The macro functional blocks 210 of the memory interface 902 include a signal receiver and demodulation block 904, “turbo” or Viterbi decoder block 906, block CRC calculation macro block 908, block permute macro block 910, block convolution encoder macro block 912, and modulation and transmit block 914. The memory banks 920 act to form circular buffers of the type well known in the data processing arts. Data remains in the memory banks 920 and is acted on by the macro blocks 210 in sequence.
  • Furthermore, multiple macro blocks may be active as a “macro pipeline” controlled by the CPU as illustrated in FIG. 9 a. Specifically, the macro functions, under CPU control via customized instructions within the base or extension instruction sets of the parent processor, sequentially act on data transferred to or out of the memory array in lockstep or pipelined fashion via the memory interface of the invention. FIG. 9 a illustrates the pipelined flow of block data in a 4-memory bank, 4-function configuration of the present invention. Exemplary pseudo-code for this operation is as follows: for(;;) { function0(bank[(cycle+0)%BANKS]); /* Initiate functions */ function1(bank[(cycle+1)%BANKS]); function2(bank[(cycle+2)%BANKS]); function3(bank[(cycle+3)%BANKS]); while(all_functions_not_complete); /* Wait */ cycle++; } Copyright © 2001 ARC International plc. All rights reserved.
  • Referring now to FIG. 10, the method of interfacing a function with a memory array according to the invention is described. In the first step 1002 of the method 1000, a number of function ports and memory ports are specified or defined for the interface. As previously described, the interface may, in one example, inherit the number of memory ports from the parent processor core design (as specified by the user/design constraints).
  • Next, in step 1004, the number of control and other registers needed for the interface is set based on the function port configuration. In one exemplary embodiment, a library of macro blocks with compatible interfaces is instantiated in the design by the (e.g. the semiconductor synthesis and design software manufactured by the Assignee hereof, and described in detail in Assignee's co-pending U.S. patent application Ser. No. 09/418,663, previously incorporated herein). Under such approach, the aforementioned software has knowledge of the block's requirements, and can instantiate the interface block appropriately.
  • The interface protocol is then specified in step 1006. One exemplary synchronous protocol is described herein with reference to FIG. 7. In step 1008, the function(s) associated with the function port(s) is/are initiated. As previously described, the functions may be initiated by the processor core stage 2 pipeline decode, using one or more control/status registers in auxiliary memory space, or even other methods. In step 1010, memory accesses are arbitrated by the crossbar/arbitration unit, 216/208 (FIG. 2) based on the memory access request/grant scheme previously described, or other arbitration scheme. Lastly, in step 1012, the read/write access to memory are conducted according to the selected protocol and control by the parent via one or more extension registers.
  • Referring now to FIG. 11, an improved method of designing an integrated circuit device having an extensible processor core, secondary processor (e.g., DSP) or macro function, and memory interface is described. As shown in FIG. 11, one embodiment of the method 1100 generally comprises first providing an HDL representation of an extensible core cell, such as the ARC user-configurable core previously described herein (step 1102). Next, HDL representations of one or more macro functions (blocks) are provided per step 1104. Examples of macro functions include the Viterbi decode, convolutional encoding, or CRC block previously described. Next, in step 1106, HDL representations of one or more memory interfaces as described herein with respect to FIG. 3 are provided. An HDL “wrapper” (i.e., a complementary HDL description designed to adapt to, and interface with, the selected macro functions) is then generated and disposed “around” the aforementioned macro function (s) in step 1108. As used herein, the terms “wrapper” and “around” are not necessarily used in a physical or spatial context, but rather in a figurative sense in that the HDL wrapper functionally envelopes the macro function block(s) (e.g., DSP core) so as to provide proper communication between the existing function block and the memory interface of the invention. Specifically, such communication includes (i) translating signals transmitted to and from the memory interface, (ii) buffering memory operations, and (iii) synchronizing clock signals of the macro function with the memory interface. Note that in the embodiment of FIG. 11, the pre-defined functions and protocols associated with the macro function block(s) (e.g., DSP) are preserved; the HDL wrapper acts in effect as a translation and interface medium between the macro function and memory interface device, the latter ultimately coupled to the memory array.
  • FIG. 11 a illustrates one embodiment of the method of designing an integrated circuit adding the HDL wrapper according to step 1108 of the method 1100 of FIG. 11. In general, the system builds from the master database a hierarchical directory structure containing HDL files that fully describe the parent processor. The memory interface is included in the master database and, once the memory interface and other related parameters are selected by the user, are included in the directory structure.
  • The memory configuration (i.e., use of memory interface and number of memory ports and function ports) is first specified by the user (step 1120). The system builder script is then invoked (step 1122) to (i) create a working directory of the user files, and (ii) copy files, including VHDL for macro functions and memory interface as required from the master database. The selected files are also customized as required to configure the system as selected by the user. The structural VHDL is then generated per step 1124. A simulation makefile and a synthesis script are then generated (step 1126). The designer then simulates or synthesizes the design (including memory interface and macro functions) per steps 1128 and 1130, respectively.
  • FIG. 12 illustrates a second embodiment of the method of designing an integrated circuit according to the invention. The method 1200 generally comprises first providing an extensible core description as previously described (step 1202). Next, at least one “soft” macro function is provided per step 1204. As used herein, the term “soft” refers to a macro function which may be selectively configured by the designer. Such soft macro functions effectively have the HDL wrapper previously described with respect to step 1108 of FIGS. 11 and 11 a above incorporated directly into their design. The wrapper furthermore may be made configurable itself.
  • The memory interface description is next provided per step 1206. In step 1208, the parent processor parameters such as cache size, extension instructions, and type of build (e.g., system versus core only) is selected. The memory configuration (i.e., use of memory interface and number of memory ports and function ports) is also specified. The system builder script is then invoked (step 1210) to (i) create a working directory of the user files, and (ii) copy files, including VHDL for modules and extensions, as required from the master database. One of the copied files in the present example comprises the memory interface file, while another comprises that for the selected “soft” macro functions previously identified for the build by the user. The selected files are also customized to configure the system as selected by the user. The structural VHDL is then generated per step 1212. A simulation makefile and a synthesis script are then generated (step 1214). The designer then simulates or synthesizes the design (including extended core, memory interface, and user-configured macro functions) per steps 1216 and 1218, respectively. Note that in contrast to the method of FIG. 11, the method of FIG. 12 integrates the memory interface with the “soft” macro function(s) (and processor core) during design generation, thereby modifying the macro function configuration.
  • It will be recognized that while certain aspects of the invention are described in terms of a specific sequence of steps of a method, these descriptions are only illustrative of the broader methods of the invention, and may be modified as required by the particular application. Certain steps may be rendered unnecessary or optional under certain circumstances. Additionally, certain steps or functionality may be added to the disclosed embodiments, or the order of performance of two or more steps permuted. All such variations are considered to be encompassed within the invention disclosed and claimed herein.
  • While the above detailed description has shown, described, and pointed out novel features of the invention as applied to various embodiments, it will be understood that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made by those skilled in the art without departing from the invention. The foregoing description is of the best mode presently contemplated of carrying out the invention. This description is in no way meant to be limiting, but rather should be taken as illustrative of the general principles of the invention. The scope of the invention should be determined with reference to the claims appended hereto.

Claims (31)

1.-30. (canceled)
31. A method of designing a user-configured and extended processor apparatus having a processor interface device, secondary processing function, and memory associated therewith, the method comprising:
providing a user-configurable and extendable primary processor core having an instruction set;
extending said primary core with at least one secondary processor function extension;
configuring said apparatus with at least one input/output (I/O) related function;
wherein said secondary processing function and I/O extensions comprise a portion of said instruction set; and
wherein said secondary processing function and I/O extensions have direct memory access (DMA) to said primary processor core.
32. The method of claim 31, wherein said designing further comprises generating a description language model by:
receiving one or more inputs from a user for at least one customizable parameter of the primary processor core;
providing at least one prototype description of the primary processor core for which a model is being generated; and
generating through an automated process a description language model based on the least one customizable parameter and the at least one prototype description, said act of generating comprising modifying or substituting at least portions of said at least one prototype description.
33. The method of claim 32, further comprising generating test code associated with said customized description language using an automated process and based at least in part on the at least one customizable parameter.
34. The method of claim 32, wherein the description language model includes both functional and structural description language descriptions for at least the primary processor core.
35. The method of claim 32, wherein said instruction set comprises both base and extension instructions.
36. The method of claim 31, wherein said secondary processing function comprises a digital signal processing (DSP) function.
37. The method of claim 31, further comprising extending said primary processor core with at least one 3G-related extension selected from the group consisting of: (i) turbo coding or decoding, and (ii) convolutional coding or decoding.
38. A user-configured and extended processor apparatus having a processor interface device, secondary processing function, and memory associated therewith, the processor apparatus being designed according to the method comprising:
providing a user-configurable and extendable primary processor core having an instruction set;
extending said primary core with at least one secondary processor function extension;
configuring said apparatus with at least one input/output (I/O) related function;
wherein said secondary processing function and I/O extensions comprise a portion of said instruction set; and
wherein said secondary processing function and I/O extensions have direct memory access (DMA) to said primary processor core.
39. The processor apparatus of claim 38, wherein said designing further comprises generating a description language model by:
receiving one or more inputs from a user for at least one customizable parameter of the primary processor core;
providing at least one prototype description of the primary processor core for which a model is being generated; and
generating through an automated process a description language model based on the least one customizable parameter and the at least one prototype description, said act of generating comprising modifying or substituting at least portions of said at least one prototype description.
40. The processor apparatus of claim 39, further comprising generating test code associated with said customized description language using an automated process and based at least in part on the at least one customizable parameter.
41. The processor apparatus of claim 39, wherein the description language model includes both functional and structural description language descriptions for at least the primary processor core.
42. The processor apparatus of claim 39, wherein said instruction set comprises both base and extension instructions.
43. The processor apparatus of claim 38, wherein said secondary processing function comprises a digital signal processing (DSP) function.
44. The method of claim 38, further comprising extending said primary processor core with at least one 3G-related extension selected from the group consisting of: (i) turbo coding or decoding, and (ii) convolutional coding or decoding.
45. A method of designing a user-configurable and extendable processing apparatus, the method comprising:
providing a software representation of a user-configurable and extendable processor core having an instruction set;
providing a software representation of a memory array;
providing a software representation of at least one macro function optimized for specific processing tasks;
providing software representation of at least one interface between said array and said at least one macro function; and
generating a design of said processing apparatus based at least in part on said software descriptions of said processor core, at least one macro function, memory array and at least one interface;
wherein said at least one macro function comprises an extension of said processor core.
46. The method of claim 45, wherein said at least one macro function is substantially under control of said processor core via one or more customized instructions within a base or extension instruction sets of said processor core.
47. The method of claim 46, wherein said one or more customized instructions act on data transferred to or out of said memory array in a pipelined fashion via said interface.
48. The method of claim 45, wherein said method of designing further comprises generating a description language model by at least:
receiving one or more inputs from a user for at least one customizable parameter of the processor core;
providing at least one prototype description of the processor core for which a model is being generated; and
generating through an automated process a description language model based on the least one customizable parameter and the at least one prototype description, said act of generating comprising modifying or substituting at least portions of said at least one prototype description.
49. The method of claim 48, further comprising generating test code associated with said customized description language using an automated process and based at least in part on the at least one customizable parameter.
50. The method of claim 48, wherein the description language model includes both functional and structural description language descriptions for at least the processor core.
51. The method of claim 48, wherein said instruction set comprises both base and extension instructions.
52. The method of claim 45, wherein said at least one function comprises a digital signal processing (DSP) function.
53. A user-configurable and extendable processing apparatus designed by the method comprising:
providing a software representation of a user-configurable and extendable processor core having an instruction set;
providing a software representation of a memory array;
providing a software representation of at least one macro function optimized for specific processing tasks;
providing software representation of at least one interface between said array and said at least one macro function; and
generating a design of said processing apparatus based at least in part on said software descriptions of said processor core, at least one macro function, memory array and at least one interface;
wherein said at least one macro function comprises an extension of said processor core.
54. The apparatus of claim 53, wherein said at least one macro function is substantially under control of said processor core via one or more customized instructions within a base or extension instruction sets of said processor core.
55. The apparatus of claim 54, wherein said one or more customized instructions act on data transferred to or out of said memory array in a pipelined fashion via said interface.
56. The apparatus of claim 53, wherein said method of designing further comprises generating a description language model by at least:
receiving one or more inputs from a user for at least one customizable parameter of the processor core;
providing at least one prototype description of the processor core for which a model is being generated; and
generating through an automated process a description language model based on the least one customizable parameter and the at least one prototype description, said act of generating comprising modifying or substituting at least portions of said at least one prototype description.
57. The apparatus of claim 56, further comprising generating test code associated with said customized description language using an automated process and based at least in part on the at least one customizable parameter.
58. The apparatus of claim 56, wherein the description language model includes both functional and structural description language descriptions for at least the processor core.
59. The apparatus of claim 56, wherein said instruction set comprises both base and extension instructions.
60. The apparatus of claim 53, wherein said at least one function comprises a digital signal processing (DSP) function.
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060036988A1 (en) * 2001-06-12 2006-02-16 Altera Corporation Methods and apparatus for implementing parameterizable processors and peripherals
US20090055565A1 (en) * 2000-03-10 2009-02-26 David Latta Memory interface and method of interfacing between functional entities
US20090295821A1 (en) * 2008-05-30 2009-12-03 Advanced Micro Devices, Inc. Scalable and Unified Compute System
US20090300278A1 (en) * 2008-05-29 2009-12-03 Advanced Micro Devices, Inc. Embedded Programmable Component for Memory Device Training
WO2013025262A2 (en) * 2011-04-06 2013-02-21 Cypress Semiconductor Memory devices and methods for high random transaction rate
US20140136743A1 (en) * 2011-07-22 2014-05-15 Panasonic Corporation Data processing device and data processing method
WO2015108257A1 (en) * 2014-01-20 2015-07-23 Samsung Electronics Co., Ltd. Method and apparatus for processing data by using memory

Families Citing this family (66)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7043682B1 (en) * 2002-02-05 2006-05-09 Arc International Method and apparatus for implementing decode operations in a data processor
KR100450680B1 (en) * 2002-07-29 2004-10-01 삼성전자주식회사 Memory controller for increasing bus bandwidth, data transmitting method and computer system having the same
US7131097B1 (en) * 2002-09-24 2006-10-31 Altera Corporation Logic generation for multiple memory functions
US7305593B2 (en) * 2003-08-26 2007-12-04 Lsi Corporation Memory mapping for parallel turbo decoding
US7096322B1 (en) * 2003-10-10 2006-08-22 Unisys Corporation Instruction processor write buffer emulation using embedded emulation control instructions
JP4765260B2 (en) * 2004-03-31 2011-09-07 日本電気株式会社 Data processing device, processing method thereof, program, and mobile phone device
US7634621B1 (en) * 2004-07-13 2009-12-15 Nvidia Corporation Register file allocation
US7280428B2 (en) 2004-09-30 2007-10-09 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
US7373447B2 (en) * 2004-11-09 2008-05-13 Toshiba America Electronic Components, Inc. Multi-port processor architecture with bidirectional interfaces between busses
US8595459B2 (en) 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
US7747833B2 (en) 2005-09-30 2010-06-29 Mosaid Technologies Incorporated Independent link and bank selection
US20070076502A1 (en) 2005-09-30 2007-04-05 Pyeon Hong B Daisy chain cascading devices
WO2007036050A1 (en) 2005-09-30 2007-04-05 Mosaid Technologies Incorporated Memory with output control
TWI460736B (en) * 2005-09-30 2014-11-11 Conversant Intellectual Property Man Inc Independent link and bank selection
US7652922B2 (en) * 2005-09-30 2010-01-26 Mosaid Technologies Incorporated Multiple independent serial link memory
US8275949B2 (en) * 2005-12-13 2012-09-25 International Business Machines Corporation System support storage and computer system
KR100720525B1 (en) * 2005-12-28 2007-05-15 동부일렉트로닉스 주식회사 Integrated circuit including aes core and wrapper for validating of aes core
US8364861B2 (en) 2006-03-28 2013-01-29 Mosaid Technologies Incorporated Asynchronous ID generation
US8335868B2 (en) 2006-03-28 2012-12-18 Mosaid Technologies Incorporated Apparatus and method for establishing device identifiers for serially interconnected devices
US8069328B2 (en) 2006-03-28 2011-11-29 Mosaid Technologies Incorporated Daisy chain cascade configuration recognition technique
US7551492B2 (en) 2006-03-29 2009-06-23 Mosaid Technologies, Inc. Non-volatile semiconductor memory with page erase
ES2498096T3 (en) 2006-03-31 2014-09-24 Mosaid Technologies Incorporated Flash memory system control scheme
US20070260841A1 (en) 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
DE102006025133A1 (en) * 2006-05-30 2007-12-06 Infineon Technologies Ag Storage and storage communication system
US7522468B2 (en) * 2006-06-08 2009-04-21 Unity Semiconductor Corporation Serial memory interface
US7904639B2 (en) 2006-08-22 2011-03-08 Mosaid Technologies Incorporated Modular command structure for memory and memory system
US20080059687A1 (en) * 2006-08-31 2008-03-06 Peter Mayer System and method of connecting a processing unit with a memory unit
US8700818B2 (en) 2006-09-29 2014-04-15 Mosaid Technologies Incorporated Packet based ID generation for serially interconnected devices
US20090222251A1 (en) * 2006-10-31 2009-09-03 International Business Machines Corporation Structure For An Integrated Circuit That Employs Multiple Interfaces
US7817470B2 (en) 2006-11-27 2010-10-19 Mosaid Technologies Incorporated Non-volatile memory serial core architecture
US7818464B2 (en) 2006-12-06 2010-10-19 Mosaid Technologies Incorporated Apparatus and method for capturing serial input data
US8010709B2 (en) 2006-12-06 2011-08-30 Mosaid Technologies Incorporated Apparatus and method for producing device identifiers for serially interconnected devices of mixed type
US8331361B2 (en) 2006-12-06 2012-12-11 Mosaid Technologies Incorporated Apparatus and method for producing device identifiers for serially interconnected devices of mixed type
US7529149B2 (en) 2006-12-12 2009-05-05 Mosaid Technologies Incorporated Memory system and method with serial and parallel modes
US8984249B2 (en) 2006-12-20 2015-03-17 Novachips Canada Inc. ID generation apparatus and method for serially interconnected devices
US7971132B2 (en) * 2007-01-05 2011-06-28 Dialogic Corporation Universal multimedia engine and method for producing the same
US8010710B2 (en) 2007-02-13 2011-08-30 Mosaid Technologies Incorporated Apparatus and method for identifying device type of serially interconnected devices
EP2109862A4 (en) 2007-02-16 2010-08-04 Mosaid Technologies Inc Semiconductor device and method for reducing power consumption in a system having interconnected devices
US8122202B2 (en) 2007-02-16 2012-02-21 Peter Gillingham Reduced pin count interface
US8493808B2 (en) 2007-02-22 2013-07-23 Mosaid Technologies Incorporated Data flow control in multiple independent port
US8046527B2 (en) 2007-02-22 2011-10-25 Mosaid Technologies Incorporated Apparatus and method for using a page buffer of a memory device as a temporary cache
US8086785B2 (en) 2007-02-22 2011-12-27 Mosaid Technologies Incorporated System and method of page buffer operation for memory devices
US7796462B2 (en) 2007-02-22 2010-09-14 Mosaid Technologies Incorporated Data flow control in multiple independent port
JP2008299476A (en) * 2007-05-30 2008-12-11 Fujitsu Microelectronics Ltd Semiconductor integrated circuit
US7624244B2 (en) * 2007-06-22 2009-11-24 International Business Machines Corporation System for providing a slow command decode over an untrained high-speed interface
US7979616B2 (en) * 2007-06-22 2011-07-12 International Business Machines Corporation System and method for providing a configurable command sequence for a memory interface device
US7688652B2 (en) 2007-07-18 2010-03-30 Mosaid Technologies Incorporated Storage of data in memory via packet strobing
US9081901B2 (en) * 2007-10-31 2015-07-14 Raytheon Company Means of control for reconfigurable computers
US7983099B2 (en) 2007-12-20 2011-07-19 Mosaid Technologies Incorporated Dual function compatible non-volatile memory device
US7940572B2 (en) 2008-01-07 2011-05-10 Mosaid Technologies Incorporated NAND flash memory having multiple cell substrates
US8410911B2 (en) * 2008-04-16 2013-04-02 RFID Mexico, S.A. DE C.V. RFID network system
US8139390B2 (en) 2008-07-08 2012-03-20 Mosaid Technologies Incorporated Mixed data rates in memory devices and systems
IT1392495B1 (en) * 2008-12-29 2012-03-09 St Microelectronics Srl Method for designing an accelerator high performance type asic (integrated circuit for specific application - application-specific integrated circuit)
US8521980B2 (en) 2009-07-16 2013-08-27 Mosaid Technologies Incorporated Simultaneous read and write data transfer
US8121826B1 (en) * 2009-07-17 2012-02-21 Xilinx, Inc. Graphical user interface for system design
KR101076869B1 (en) * 2010-03-16 2011-10-25 광운대학교 산학협력단 Memory centric communication apparatus in coarse grained reconfigurable array
US20110276775A1 (en) * 2010-05-07 2011-11-10 Mosaid Technologies Incorporated Method and apparatus for concurrently reading a plurality of memory devices using a single buffer
US20120017116A1 (en) * 2010-07-16 2012-01-19 Kabushiki Kaisha Toshiba Memory control device, memory device, and memory control method
US9268719B2 (en) 2011-08-05 2016-02-23 Rambus Inc. Memory signal buffers and modules supporting variable access granularity
CN103827842B (en) * 2011-09-29 2017-07-07 英特尔公司 Message is write to controller storage space
US8825967B2 (en) 2011-12-08 2014-09-02 Conversant Intellectual Property Management Inc. Independent write and read control in serially-connected devices
CN104736625B (en) * 2012-10-26 2018-07-20 埃克森美孚化学专利公司 Blend polymer and by its product obtained
US9224454B2 (en) * 2013-10-25 2015-12-29 Cypress Semiconductor Corporation Multi-channel physical interfaces and methods for static random access memory devices
US9361973B2 (en) 2013-10-28 2016-06-07 Cypress Semiconductor Corporation Multi-channel, multi-bank memory with wide data input/output
DE102014206607B3 (en) * 2014-04-04 2015-10-01 Siemens Aktiengesellschaft Method for operating an automation device, processor for use in the method and process device according to the method and system
EP3035204B1 (en) 2014-12-19 2018-08-15 Intel Corporation Storage device and method for performing convolution operations

Citations (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4701860A (en) * 1985-03-07 1987-10-20 Harris Corporation Integrated circuit architecture formed of parametric macro-cells
US5333176A (en) * 1992-04-30 1994-07-26 Murata Machinery, Ltd. Cellular hand held portable speakerphone system having an interface adapter
US5680632A (en) * 1992-12-24 1997-10-21 Motorola, Inc. Method for providing an extensible register in the first and second data processing systems
US5768613A (en) * 1990-07-06 1998-06-16 Advanced Micro Devices, Inc. Computing apparatus configured for partitioned processing
US5848289A (en) * 1992-11-27 1998-12-08 Motorola, Inc. Extensible central processing unit
US5872993A (en) * 1997-12-01 1999-02-16 Advanced Micro Devices, Inc. Communications system with multiple, simultaneous accesses to a memory
US5978889A (en) * 1997-11-05 1999-11-02 Timeplex, Inc. Multiple device data transfer utilizing a multiport memory with opposite oriented memory page rotation for transmission and reception
US6226780B1 (en) * 1998-08-31 2001-05-01 Mentor Graphics Corporation Circuit design method and apparatus supporting a plurality of hardware design languages
US6330684B1 (en) * 1997-06-30 2001-12-11 Matsushita Electric Industrial Co., Ltd. Processor and processing method
US6446181B1 (en) * 2000-03-31 2002-09-03 Intel Corporation System having a configurable cache/SRAM memory
US6463514B1 (en) * 1998-02-18 2002-10-08 International Business Machines Corporation Method to arbitrate for a cache block
US6477683B1 (en) * 1999-02-05 2002-11-05 Tensilica, Inc. Automated processor generation system for designing a configurable processor and method for the same
US6477697B1 (en) * 1999-02-05 2002-11-05 Tensilica, Inc. Adding complex instruction extensions defined in a standardized language to a microprocessor design to produce a configurable definition of a target instruction set, and hdl description of circuitry necessary to implement the instruction set, and development and verification tools for the instruction set
US20030009612A1 (en) * 2000-03-10 2003-01-09 David Latta Memory interface and method of interfacing between functional entities
US6539522B1 (en) * 2000-01-31 2003-03-25 International Business Machines Corporation Method of developing re-usable software for efficient verification of system-on-chip integrated circuit designs
US6564042B1 (en) * 2000-03-03 2003-05-13 Qualcomm Incorporated Velocity-estimation-based gain tables
US6574787B1 (en) * 1999-08-16 2003-06-03 Sequence Design, Inc. Method and apparatus for logic synthesis (word oriented netlist)
US6628662B1 (en) * 1999-11-29 2003-09-30 International Business Machines Corporation Method and system for multilevel arbitration in a non-blocking crossbar switch
US6701515B1 (en) * 1999-05-27 2004-03-02 Tensilica, Inc. System and method for dynamically designing and evaluating configurable processor instructions
US6763327B1 (en) * 2000-02-17 2004-07-13 Tensilica, Inc. Abstraction of configurable processor functionality for operating systems portability
US6862563B1 (en) * 1998-10-14 2005-03-01 Arc International Method and apparatus for managing the configuration and functionality of a semiconductor design
US7036106B1 (en) * 2000-02-17 2006-04-25 Tensilica, Inc. Automated processor generation system for designing a configurable processor and method for the same
US20060236300A1 (en) * 2005-04-15 2006-10-19 Nec Laboratories America, Inc. Automatically boosting the software content of system LSI designs
US7139893B2 (en) * 2001-10-30 2006-11-21 Micron Technology, Inc. Transparent SDRAM in an embedded environment

Family Cites Families (120)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0157817B2 (en) 1982-06-29 1989-12-07 Hitachi Ltd
US4611278A (en) 1983-04-01 1986-09-09 Honeywell Information Systems Inc. Wraparound buffer for repetitive decimal numeric operations
US4755966A (en) 1985-06-28 1988-07-05 Hewlett-Packard Company Bidirectional branch prediction and optimization
US4896258A (en) 1985-07-04 1990-01-23 Hitachi, Ltd. Data processor provided with instructions which refer to both tagged and tagless data
US4763242A (en) 1985-10-23 1988-08-09 Hewlett-Packard Company Computer providing flexible processor extension, flexible instruction set extension, and implicit emulation for upward software compatibility
US4890218A (en) 1986-07-02 1989-12-26 Raytheon Company Variable length instruction decoding apparatus having cross coupled first and second microengines
US4992934A (en) 1986-12-15 1991-02-12 United Technologies Corporation Reduced instruction set computing apparatus and methods
US5535331A (en) 1987-09-04 1996-07-09 Texas Instruments Incorporated Processor condition sensing circuits, systems and methods
US5081575A (en) * 1987-11-06 1992-01-14 Oryx Corporation Highly parallel computer architecture employing crossbar switch with selectable pipeline delay
US5019967A (en) 1988-07-20 1991-05-28 Digital Equipment Corporation Pipeline bubble compression in a computer system
US4974155A (en) 1988-08-15 1990-11-27 Evans & Sutherland Computer Corp. Variable delay branch system
DE68927218D1 (en) 1988-10-18 1996-10-24 Hewlett Packard Co Method and apparatus for condition code in a central processor
US5226125A (en) * 1989-11-17 1993-07-06 Keith Balmer Switch matrix having integrated crosspoint logic and method of operation
US6070003A (en) * 1989-11-17 2000-05-30 Texas Instruments Incorporated System and method of memory access in apparatus having plural processors and plural memories
DE68928980T2 (en) * 1989-11-17 1999-08-19 Texas Instruments Inc Multiprocessor with crossbar switches between processors and memories
US5555384A (en) 1989-12-01 1996-09-10 Silicon Graphics, Inc. Rescheduling conflicting issued instructions by delaying one conflicting instruction into the same pipeline stage as a third non-conflicting instruction
US5210870A (en) 1990-03-27 1993-05-11 International Business Machines Database sort and merge apparatus with multiple memory arrays having alternating access
JP2834837B2 (en) 1990-03-30 1998-12-14 松下電工株式会社 Programmable controller
US5544067A (en) 1990-04-06 1996-08-06 Lsi Logic Corporation Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation
US5553002A (en) 1990-04-06 1996-09-03 Lsi Logic Corporation Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, using milestone matrix incorporated into user-interface
US5867399A (en) 1990-04-06 1999-02-02 Lsi Logic Corporation System and method for creating and validating structural description of electronic system from higher-level and behavior-oriented description
US5555201A (en) 1990-04-06 1996-09-10 Lsi Logic Corporation Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information
US5247637A (en) 1990-06-01 1993-09-21 Cray Research, Inc. Method and apparatus for sharing memory in a multiprocessor system
DE69130519T2 (en) 1990-06-29 1999-06-10 Digital Equipment Corp High-performance multi-processor with floating point and method for its operation
DE69130138T2 (en) 1990-06-29 1999-05-06 Digital Equipment Corp Branch prediction unit for high-performance processor
JP2508907B2 (en) 1990-09-18 1996-06-19 日本電気株式会社 Control method of delayed branch instruction
EP0479390B1 (en) 1990-10-05 1999-01-07 Philips Electronics N.V. Processing device including a memory circuit and a group of functional units
JPH04172533A (en) 1990-11-07 1992-06-19 Toshiba Corp Electronic computer
DE69227604T2 (en) 1991-03-11 1999-06-24 Silicon Graphics Inc Mountain Backward compatible computer architecture with extended word widths and address space
US5590294A (en) 1991-03-19 1996-12-31 Silicon Graphics, Inc. Method and apparatus for retarting pipeline processing
US5481707A (en) 1991-05-19 1996-01-02 Unisys Corporation Dedicated processor for task I/O and memory management
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
AT164463T (en) 1991-07-08 1998-04-15 Seiko Epson Corp Single-chip page printer-control circuit
US5450586A (en) 1991-08-14 1995-09-12 Hewlett-Packard Company System for analyzing and debugging embedded software through dynamic and interactive use of code markers
US5491640A (en) 1992-05-01 1996-02-13 Vlsi Technology, Inc. Method and apparatus for synthesizing datapaths for integrated circuit design and fabrication
DE69220369D1 (en) 1992-10-15 1997-07-17 Siemens Ag Examination of testability rules with a VHDL simulator
JPH06150023A (en) 1992-11-06 1994-05-31 Hitachi Ltd Microcomputer and system thereof
US5361373A (en) 1992-12-11 1994-11-01 Gilson Kent L Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfigurable instruction execution means and method therefor
US5404319A (en) 1993-02-11 1995-04-04 Analog, Inc. Translation of behavioral modeling properties into an analog hardware description language
JPH06314264A (en) * 1993-05-06 1994-11-08 Nec Corp Self-routing cross bar switch
DE69408769D1 (en) 1993-10-18 1998-04-09 Cyrix Corp Conveyor Control and register translation in microprocessor
US5509129A (en) 1993-11-30 1996-04-16 Guttag; Karl M. Long instruction word controlling plural independent processor operations
US5577204A (en) * 1993-12-15 1996-11-19 Convex Computer Corporation Parallel processing computer system interconnections utilizing unidirectional communication links with separate request and response lines for direct communication or using a crossbar switching device
US5724566A (en) 1994-01-11 1998-03-03 Texas Instruments Incorporated Pipelined data processing including interrupts
WO1995022102A1 (en) 1994-02-08 1995-08-17 Meridian Semiconductor, Inc. Method and apparatus for simultaneously executing instructions in a pipelined microprocessor
US5867400A (en) 1995-05-17 1999-02-02 International Business Machines Corporation Application specific processor and design method for same
US5493508A (en) 1994-06-01 1996-02-20 Lsi Logic Corporation Specification and design of complex digital systems
JP3452989B2 (en) 1994-09-26 2003-10-06 三菱電機株式会社 Central processing unit
US5636364A (en) 1994-12-01 1997-06-03 International Business Machines Corporation Method for enabling concurrent misses in a cache memory
US5537580A (en) 1994-12-21 1996-07-16 Vlsi Technology, Inc. Integrated circuit fabrication using state machine extraction from behavioral hardware description language
US5794062A (en) 1995-04-17 1998-08-11 Ricoh Company Ltd. System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
US5878240A (en) * 1995-05-11 1999-03-02 Lucent Technologies, Inc. System and method for providing high speed memory access in a multiprocessor, multimemory environment
US6026219A (en) 1995-05-12 2000-02-15 Synopsys, Inc. Behavioral synthesis links to logic synthesis
US5898595A (en) 1995-05-26 1999-04-27 Lsi Logic Corporation Automated generation of megacells in an integrated circuit design system
US5920711A (en) 1995-06-02 1999-07-06 Synopsys, Inc. System for frame-based protocol, graphical capture, synthesis, analysis, and simulation
JPH08339326A (en) * 1995-06-09 1996-12-24 Hitachi Chubu Software Ltd Multiprocessor device
US5841663A (en) 1995-09-14 1998-11-24 Vlsi Technology, Inc. Apparatus and method for synthesizing integrated circuits using parameterized HDL modules
SE505783C2 (en) 1995-10-03 1997-10-06 Ericsson Telefon Ab L M Method for making a digital signal processor
US5870588A (en) 1995-10-23 1999-02-09 Interuniversitair Micro-Elektronica Centrum(Imec Vzw) Design environment and a design method for hardware/software co-design
US6035123A (en) 1995-11-08 2000-03-07 Digital Equipment Corporation Determining hardware complexity of software operations
US5696956A (en) 1995-11-08 1997-12-09 Digital Equipment Corporation Dynamically programmable reduced instruction set computer with programmable processor loading on program number field and program number register contents
US5819064A (en) 1995-11-08 1998-10-06 President And Fellows Of Harvard College Hardware extraction technique for programmable reduced instruction set computers
US5778208A (en) 1995-12-18 1998-07-07 International Business Machines Corporation Flexible pipeline for interlock removal
GB2308470B (en) 1995-12-22 2000-02-16 Nokia Mobile Phones Ltd Program memory scheme for processors
US5703789A (en) 1995-12-29 1997-12-30 Synopsys, Inc. Test ready compiler for design for test synthesis
GB2309803B (en) 1996-02-01 2000-01-26 Advanced Risc Mach Ltd Processing cycle control in a data processing apparatus
US5819050A (en) 1996-02-29 1998-10-06 The Foxboro Company Automatically configurable multi-purpose distributed control processor card for an industrial control system
US5854929A (en) 1996-03-08 1998-12-29 Interuniversitair Micro-Elektronica Centrum (Imec Vzw) Method of generating code for programmable processors, code generator and application thereof
US5790824A (en) * 1996-03-18 1998-08-04 Advanced Micro Devices, Inc. Central processing unit including a DSP function preprocessor which scans instruction sequences for DSP functions
US5970510A (en) 1996-04-10 1999-10-19 Northrop Grumman Corporation Distributed memory addressing system
US6173434B1 (en) 1996-04-22 2001-01-09 Brigham Young University Dynamically-configurable digital processor using method for relocating logic array modules
US5752271A (en) 1996-04-29 1998-05-12 Sun Microsystems, Inc. Method and apparatus for using double precision addressable registers for single precision data
US5748875A (en) 1996-06-12 1998-05-05 Simpod, Inc. Digital logic simulation/emulation system
US5784603A (en) 1996-06-19 1998-07-21 Sun Microsystems, Inc. Fast handling of branch delay slots on mispredicted branches
US5812416A (en) 1996-07-18 1998-09-22 Lsi Logic Corporation Integrated circuit design decomposition
US5994892A (en) 1996-07-31 1999-11-30 Sacramento Municipal Utility District Integrated circuit design automatic utility meter: apparatus & method
US5838984A (en) 1996-08-19 1998-11-17 Samsung Electronics Co., Ltd. Single-instruction-multiple-data processing using multiple banks of vector registers
US5768445A (en) * 1996-09-13 1998-06-16 Silicon Graphics, Inc. Compression and decompression scheme performed on shared workstation memory by media coprocessor
US5963454A (en) 1996-09-25 1999-10-05 Vlsi Technology, Inc. Method and apparatus for efficiently implementing complex function blocks in integrated circuit designs
KR19980033054A (en) 1996-10-23 1998-07-25 윌리엄비.켐플러 Programmable memory access
US6311309B1 (en) 1996-10-28 2001-10-30 Altera Corporation Methods and apparatus for simulating a portion of a circuit design
US6006022A (en) 1996-11-15 1999-12-21 Microsystem Synthesis, Inc. Cross-linked development and deployment apparatus and method
US5854930A (en) 1996-12-30 1998-12-29 Mci Communications Corporations System, method, and computer program product for script processing
US5987574A (en) 1997-04-30 1999-11-16 Sony Corporation Bank arbitration for SDRAM memory control
US5960468A (en) 1997-04-30 1999-09-28 Sony Corporation Asynchronous memory interface for a video processor with a 2N sized buffer and N+1 bit wide gray coded counters
US6016543A (en) 1997-05-14 2000-01-18 Mitsubishi Denki Kabushiki Kaisha Microprocessor for controlling the conditional execution of instructions
US6182258B1 (en) 1997-06-03 2001-01-30 Verisity Ltd. Method and apparatus for test generation during circuit design
US5995736A (en) 1997-07-24 1999-11-30 Ati Technologies, Inc. Method and system for automatically modelling registers for integrated circuit design
US6195593B1 (en) 1997-09-03 2001-02-27 Seiko Epson Corporation Reusable modules for complex integrated circuit devices
US6226776B1 (en) 1997-09-16 2001-05-01 Synetry Corporation System for converting hardware designs in high-level programming language to hardware implementations
US6044453A (en) 1997-09-18 2000-03-28 Lg Semicon Co., Ltd. User programmable circuit and method for data processing apparatus using a self-timed asynchronous control structure
US6360350B1 (en) 1997-10-07 2002-03-19 International Business Corporation Method and system for performing circuit analysis on an integrated-circuit design having design data available in different forms
US5999734A (en) 1997-10-21 1999-12-07 Ftl Systems, Inc. Compiler-oriented apparatus for parallel compilation, simulation and execution of computer programs and hardware models
US6091431A (en) 1997-12-18 2000-07-18 Intel Corporation Method and apparatus for improving processor to graphics device local memory performance
US6256729B1 (en) 1998-01-09 2001-07-03 Sun Microsystems, Inc. Method and apparatus for resolving multiple branches
US6038646A (en) 1998-01-23 2000-03-14 Sun Microsystems, Inc. Method and apparatus for enforcing ordered execution of reads and writes across a memory interface
US6421818B1 (en) 1998-02-20 2002-07-16 Lsi Logic Corporation Efficient top-down characterization method
US6378123B1 (en) 1998-02-20 2002-04-23 Lsi Logic Corporation Method of handling macro components in circuit design synthesis
US6125429A (en) * 1998-03-12 2000-09-26 Compaq Computer Corporation Cache memory exchange optimized memory organization for a computer system
US6092167A (en) 1998-03-20 2000-07-18 Lsi Logic Corporation Robust interface for high speed memory access
US6240492B1 (en) 1998-05-22 2001-05-29 International Business Machines Corporation Memory interface for functional unit of integrated system allowing access to dedicated memory and shared memory, and speculative generation of lookahead fetch requests
US6110218A (en) 1998-06-01 2000-08-29 Advanced Micro Devices, Inc. Generation of multiple simultaneous random test cycles for hardware verification of multiple functions of a design under test
US6438678B1 (en) * 1998-06-15 2002-08-20 Cisco Technology, Inc. Apparatus and method for operating on data in a data communications system
US6356995B2 (en) * 1998-07-02 2002-03-12 Picoturbo, Inc. Microcode scalable processor
US6269467B1 (en) 1998-09-30 2001-07-31 Cadence Design Systems, Inc. Block based design methodology
CN100351782C (en) 1999-05-13 2007-11-28 Arc国际美国控股公司 Method and apparatus for jump delay slot control in pipelined processor
EP1190337A2 (en) 1999-05-13 2002-03-27 ARC International U.S. Holdings Inc. Method and apparatus for processor pipeline segmentation and re-assembly
US6671743B1 (en) 1998-11-13 2003-12-30 Creative Technology, Ltd. Method and system for exposing proprietary APIs in a privileged device driver to an application
EP1026595B1 (en) 1999-01-11 2008-07-23 Sgs-Thomson Microelectronics Ltd. Memory interface device and method for accessing memories
US8636648B2 (en) * 1999-03-01 2014-01-28 West View Research, Llc Endoscopic smart probe
US6295571B1 (en) * 1999-03-19 2001-09-25 Times N Systems, Inc. Shared memory apparatus and method for multiprocessor systems
US6560754B1 (en) 1999-05-13 2003-05-06 Arc International Plc Method and apparatus for jump control in a pipelined processor
US6338136B1 (en) 1999-05-18 2002-01-08 Ip-First, Llc Pairing of load-ALU-store with conditional branch
US6457173B1 (en) 1999-08-20 2002-09-24 Hewlett-Packard Company Automatic design of VLIW instruction formats
US6385757B1 (en) 1999-08-20 2002-05-07 Hewlett-Packard Company Auto design of VLIW processors
US6408428B1 (en) 1999-08-20 2002-06-18 Hewlett-Packard Company Automated design of processor systems using feedback from internal measurements of candidate systems
US6637018B1 (en) 1999-10-29 2003-10-21 Cadence Design Systems, Inc. Mixed signal synthesis behavioral models and use in circuit design optimization
US6618839B1 (en) * 1999-11-30 2003-09-09 Synplicity, Inc. Method and system for providing an electronic system design with enhanced debugging capabilities
US7010558B2 (en) 2001-04-19 2006-03-07 Arc International Data processor with enhanced instruction execution and method
US7181596B2 (en) 2002-02-12 2007-02-20 Ip-First, Llc Apparatus and method for extending a microprocessor instruction set

Patent Citations (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4701860A (en) * 1985-03-07 1987-10-20 Harris Corporation Integrated circuit architecture formed of parametric macro-cells
US5768613A (en) * 1990-07-06 1998-06-16 Advanced Micro Devices, Inc. Computing apparatus configured for partitioned processing
US5333176A (en) * 1992-04-30 1994-07-26 Murata Machinery, Ltd. Cellular hand held portable speakerphone system having an interface adapter
US5848289A (en) * 1992-11-27 1998-12-08 Motorola, Inc. Extensible central processing unit
US5680632A (en) * 1992-12-24 1997-10-21 Motorola, Inc. Method for providing an extensible register in the first and second data processing systems
US6330684B1 (en) * 1997-06-30 2001-12-11 Matsushita Electric Industrial Co., Ltd. Processor and processing method
US5978889A (en) * 1997-11-05 1999-11-02 Timeplex, Inc. Multiple device data transfer utilizing a multiport memory with opposite oriented memory page rotation for transmission and reception
US5872993A (en) * 1997-12-01 1999-02-16 Advanced Micro Devices, Inc. Communications system with multiple, simultaneous accesses to a memory
US6463514B1 (en) * 1998-02-18 2002-10-08 International Business Machines Corporation Method to arbitrate for a cache block
US6226780B1 (en) * 1998-08-31 2001-05-01 Mentor Graphics Corporation Circuit design method and apparatus supporting a plurality of hardware design languages
US6862563B1 (en) * 1998-10-14 2005-03-01 Arc International Method and apparatus for managing the configuration and functionality of a semiconductor design
US6477683B1 (en) * 1999-02-05 2002-11-05 Tensilica, Inc. Automated processor generation system for designing a configurable processor and method for the same
US6477697B1 (en) * 1999-02-05 2002-11-05 Tensilica, Inc. Adding complex instruction extensions defined in a standardized language to a microprocessor design to produce a configurable definition of a target instruction set, and hdl description of circuitry necessary to implement the instruction set, and development and verification tools for the instruction set
US6701515B1 (en) * 1999-05-27 2004-03-02 Tensilica, Inc. System and method for dynamically designing and evaluating configurable processor instructions
US6574787B1 (en) * 1999-08-16 2003-06-03 Sequence Design, Inc. Method and apparatus for logic synthesis (word oriented netlist)
US6628662B1 (en) * 1999-11-29 2003-09-30 International Business Machines Corporation Method and system for multilevel arbitration in a non-blocking crossbar switch
US6539522B1 (en) * 2000-01-31 2003-03-25 International Business Machines Corporation Method of developing re-usable software for efficient verification of system-on-chip integrated circuit designs
US6763327B1 (en) * 2000-02-17 2004-07-13 Tensilica, Inc. Abstraction of configurable processor functionality for operating systems portability
US7036106B1 (en) * 2000-02-17 2006-04-25 Tensilica, Inc. Automated processor generation system for designing a configurable processor and method for the same
US6564042B1 (en) * 2000-03-03 2003-05-13 Qualcomm Incorporated Velocity-estimation-based gain tables
US20030009612A1 (en) * 2000-03-10 2003-01-09 David Latta Memory interface and method of interfacing between functional entities
US6988154B2 (en) * 2000-03-10 2006-01-17 Arc International Memory interface and method of interfacing between functional entities
US6446181B1 (en) * 2000-03-31 2002-09-03 Intel Corporation System having a configurable cache/SRAM memory
US7139893B2 (en) * 2001-10-30 2006-11-21 Micron Technology, Inc. Transparent SDRAM in an embedded environment
US20060236300A1 (en) * 2005-04-15 2006-10-19 Nec Laboratories America, Inc. Automatically boosting the software content of system LSI designs

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9418042B2 (en) 2000-03-10 2016-08-16 Synopsys, Inc. Memory interface and method of interfacing between functional entities
US20090055565A1 (en) * 2000-03-10 2009-02-26 David Latta Memory interface and method of interfacing between functional entities
US8959269B2 (en) 2000-03-10 2015-02-17 Synopsys, Inc. Memory interface and method of interfacing between functional entities
US8688879B2 (en) 2000-03-10 2014-04-01 Synopsys, Inc. Memory interface and method of interfacing between functional entities
US20060190907A1 (en) * 2001-06-12 2006-08-24 Altera Corporation Methods and apparatus for implementing parameterizable processors and peripherals
US20080134127A1 (en) * 2001-06-12 2008-06-05 Altera Corporation Methods and apparatus for implementing parameterizable processors and peripherals
US8156455B2 (en) 2001-06-12 2012-04-10 Altera Corporaton Methods and apparatus for implementing parameterizable processors and peripherals
US8037434B2 (en) 2001-06-12 2011-10-11 Altera Corporation Methods and apparatus for implementing parameterizable processors and peripherals
US8132132B2 (en) * 2001-06-12 2012-03-06 Altera Corporation Methods and apparatus for implementing parameterizable processors and peripherals
US20060036988A1 (en) * 2001-06-12 2006-02-16 Altera Corporation Methods and apparatus for implementing parameterizable processors and peripherals
US20090300278A1 (en) * 2008-05-29 2009-12-03 Advanced Micro Devices, Inc. Embedded Programmable Component for Memory Device Training
US20090295821A1 (en) * 2008-05-30 2009-12-03 Advanced Micro Devices, Inc. Scalable and Unified Compute System
US20100146211A1 (en) * 2008-05-30 2010-06-10 Advanced Micro Devices, Inc. Shader Complex with Distributed Level One Cache System and Centralized Level Two Cache
US8558836B2 (en) 2008-05-30 2013-10-15 Advanced Micro Devices, Inc. Scalable and unified compute system
US8195882B2 (en) * 2008-05-30 2012-06-05 Advanced Micro Devices, Inc. Shader complex with distributed level one cache system and centralized level two cache
US8570790B2 (en) 2011-01-13 2013-10-29 Cypress Semiconductor Corporation Memory devices and methods for high random transaction rate
US8630111B2 (en) 2011-01-13 2014-01-14 Cypress Semiconductor Corporation Memory devices and methods for high random transaction rate
WO2013025262A3 (en) * 2011-04-06 2014-05-08 Cypress Semiconductor Memory devices and methods for high random transaction rate
CN103890740A (en) * 2011-04-06 2014-06-25 赛普拉斯半导体公司 Memory devices and methods for high random transaction rate
WO2013025262A2 (en) * 2011-04-06 2013-02-21 Cypress Semiconductor Memory devices and methods for high random transaction rate
US8924613B2 (en) * 2011-07-22 2014-12-30 Panasonic Corporation Data processing device and data processing method
US20140136743A1 (en) * 2011-07-22 2014-05-15 Panasonic Corporation Data processing device and data processing method
WO2015108257A1 (en) * 2014-01-20 2015-07-23 Samsung Electronics Co., Ltd. Method and apparatus for processing data by using memory

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US8959269B2 (en) 2015-02-17
US9418042B2 (en) 2016-08-16
US6988154B2 (en) 2006-01-17
US20150154143A1 (en) 2015-06-04
US20140281114A1 (en) 2014-09-18
WO2001069411A3 (en) 2003-04-17
AU4346301A (en) 2001-09-24
US20030009612A1 (en) 2003-01-09
US20090055565A1 (en) 2009-02-26

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