US20060131717A1 - Multi-chip package structure - Google Patents

Multi-chip package structure Download PDF

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Publication number
US20060131717A1
US20060131717A1 US11/353,532 US35353206A US2006131717A1 US 20060131717 A1 US20060131717 A1 US 20060131717A1 US 35353206 A US35353206 A US 35353206A US 2006131717 A1 US2006131717 A1 US 2006131717A1
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United States
Prior art keywords
chip
substrate
package
sub
top surface
Prior art date
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Abandoned
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US11/353,532
Inventor
Su Tao
Yu-Fang Tsai
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Publication date
Priority to TW092137630 priority Critical
Priority to TW92137630 priority
Priority to TW093119671A priority patent/TWI283467B/en
Priority to TW093119671 priority
Priority to US11/026,763 priority patent/US7129583B2/en
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Priority to US11/353,532 priority patent/US20060131717A1/en
Assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC. reassignment ADVANCED SEMICONDUCTOR ENGINEERING, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TSAI, YU-FANG, TAO, SU
Publication of US20060131717A1 publication Critical patent/US20060131717A1/en
Application status is Abandoned legal-status Critical

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    • HELECTRICITY
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    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L2924/151Die mounting substrate
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    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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Abstract

The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the sub-package and the top surface of the first substrate. The bottom surface of the sub-package is attached to the first chip. The sub-package comprises a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface, and is electrically connected to the first chip. The second chip is attached to the top surface of the second substrate to which the second chip is electrically connected. The second molding compound encapsulates the second chip and part of the top surface of the second substrate. Whereby, the relative large area caused by the parallel arrangement of a plurality of conventional package structures can be reduced, and there is no need to redesign signal-transmitting path.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a multi-chip package structure, particularly to a multi-chip package structure having a sub-package.
  • 2. Description of the Related Art
  • The requirement of high density, high performance and precise cost control of an electronic product speeds up the developments of System On a Chip (SOC) and System In a Package (SIP). The mostly used package technique is Multi-Chip Module (MCM), which integrates the chips having different functions, such as microprocessors, memories, logic elements, optical ICs and capacitors, and replaces the prior art of disposing individual packages on one circuit board.
  • FIGS. 1 and 2 show the perspective and cross-sectional views of a conventional Multi-Chip Module package structure, respectively. The conventional Multi-Chip Module package structure 10 comprises a first substrate 11, a first package structure 12, a second package structure 13 and a plurality of first solder balls 14.
  • The first substrate 11 has a top surface 111 and a bottom surface 112. The first solder balls 14 are formed on the bottom surface 112 of the first substrate 11. The first package structure 12 comprises a first chip 121, a plurality of first wires 122 and a first molding compound 123. The first chip 121 is adhered to the top surface 111 of the first substrate 11, and is electrically connected to the first substrate 11 by utilizing the first wires 122. The first molding compound 123 encapsulates the first chip 121, the first wires 122 and part of the top surface 111 of the first substrate 11.
  • The second package structure 13 comprises a second substrate 131, a second chip 132, a plurality of second wires 133, a second molding compound 134 and a plurality of second solder balls 135. The second substrate 131 has a top surface 1311 and a bottom surface 1312. The second chip 132 is adhered to the top surface 1311 of the second substrate 131, and is electrically connected to the second substrate 131 by utilizing the second wires 133. The second molding compound 134 encapsulates the second chip 132, the second wires 133 and part of the top surface 1311 of the second substrate 131. The second solder balls 135 are formed on the bottom surface 1312 of the second substrate 131. The second package structure 13 is attached to the top surface 111 of the first substrate 11 by surface mounting that utilizes the second solder balls 135 after the second package structure 13 itself has been packaged.
  • In the conventional Multi-Chip Module package structure 10, the first chip 121 is a microprocessor chip, and the second chip 132 is a memory chip. Because different memory chips have different sizes and different amounts of I/O pins, it is necessary to redesign signal-transmitting path when the microprocessor chip is integrated with different memory chips, which increases the manufacture cost and extends the research time. Additionally, in the conventional Multi-Chip Module package structure 10, the first package structure 12 and the second package structure 13 are disposed in parallel relationship, which occupies a relative large area.
  • Consequently, there is an existing need for a novel and improved multi-chip package structure to solve the above-mentioned problem.
  • SUMMARY OF THE INVENTION
  • One objective of the present invention is to provide a package structure having a sub-package therein. The package structure of the present invention is formed by stacking so as to avoid the shortcoming of large area caused by parallel arrangement of a plurality of conventional package structures.
  • Another objective of the present invention is to provide a package structure having a sub-package therein. The sub-package is a package that has been tested, and is integrated into the package structure of the present invention as a Known-Good Die (KGD). The manufacture cost of the package structure of the present invention is reduced because package test is cheaper and easier than Known-Good Die test.
  • Another objective of the present invention is to provide a package structure having a sub-package therein. The package structure of the present invention has at least two chips; therefore, there is no need to redesign the signal-transmitting path between the chips.
  • Yet another objective of the present invention is to provide a multi-chip package structure comprising a first substrate, a first chip, a sub-package and a first molding compound.
  • The first substrate has a top surface and a bottom surface. The first chip is attached to the top surface of the first substrate and is electrically connected to the first substrate.
  • The sub-package has a top surface and a bottom surface, wherein the bottom surface of the sub-package is attached to the first chip. The sub-package includes a second substrate, a second chip and a second molding compound. The second substrate has a top surface and a bottom surface and is electrically connected to the first chip. The second chip is attached to the bottom surface of the second substrate and is electrically connected to the second substrate. The second molding compound is used for encapsulating the second chip and part of the bottom surface of the second substrate.
  • The first molding compound is used for encapsulating the first chip, the sub-package and the top surface of the first substrate.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 shows a perspective view of a conventional Multi-Chip Module package structure;
  • FIG. 2 shows a cross-sectional view of a conventional Multi-Chip Module package structure;
  • FIG. 3 shows a cross sectional view of a multi-chip package structure according to the first embodiment of the present invention;
  • FIG. 4 shows a cross sectional view of a multi-chip package structure according to the second embodiment of the present invention;
  • FIG. 5 shows a cross sectional view of a multi-chip package structure according to the third embodiment of the present invention;
  • FIG. 6 shows a cross sectional view of a multi-chip package structure according to the fourth embodiment of the present invention;
  • FIG. 7 shows a cross sectional view of a multi-chip package structure according to the fifth embodiment of the present invention;
  • FIG. 8 shows a cross sectional view of a multi-chip package structure according to the sixth embodiment of the present invention;
  • FIG. 9 shows a cross sectional view of a second type of sub-package according to the present invention;
  • FIG. 10 shows a cross sectional view of a third type of sub-package according to the present invention;
  • FIG. 11 shows a cross sectional view of a multi-chip package structure according to the seventh embodiment of the present invention;
  • FIG. 12 shows a cross sectional view of a fifth type of sub-package according to the present invention;
  • FIG. 13 shows a cross sectional view of a sixth type of sub-package according to the present invention;
  • FIG. 14 shows a cross sectional view of a seventh type of sub-package according to the present invention;
  • FIG. 15 shows a cross sectional view of a multi-chip package structure according to the eighth embodiment of the present invention;
  • FIG. 16 shows a cross sectional view of a multi-chip package structure according to the ninth embodiment of the present invention; and
  • FIG. 17 shows a cross sectional view of a multi-chip package structure according to the tenth embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE INVENTION
  • FIG. 3 shows a cross sectional view of a multi-chip package structure according to the first embodiment of the present invention. The multi-chip package structure 20A of the embodiment comprises a first substrate 21, a first chip 22, a plurality of first wires 23, a sub-package 24, a plurality of third wires 25, a first molding compound 26 and a plurality of solder balls 27.
  • The first substrate 21 has a top surface 211 and a bottom surface 212. The first chip 22 is attached to the top surface 211 of the first substrate 21 and is electrically connected to the first substrate 21 by utilizing the first wires 23. It is to be noted that if the first chip 22 is attached to the first substrate 21 by flip-chip, there is no need to dispose the first wires 23.
  • The sub-package 24 has a top surface 241 and a bottom surface 242. The bottom surface 242 of the sub-package 24 is attached to the first chip 22 by utilizing adhesive glue. The sub-package 24 includes a second substrate 243, a second chip 244, a plurality of second wires 245 and a second molding compound 246.
  • The second substrate 243 has a top surface 2431 and a bottom surface 2432 and is electrically connected to the first chip 22 by utilizing the third wires 25 or electrically connected to the first substrate 21 by utilizing the third wires 25 (not shown). The second chip 244 is attached to the top surface 2431 of the second substrate 243 and is electrically connected to the second substrate 243 by utilizing the second wires 245. The second molding compound 246 is used for encapsulating the second chip 244 and part of the top surface 2431 of the second substrate 243. It is to be noted that the second molding compound 246 does not cover the entire top surface 2431 of the second substrate 243. There are a plurality of pads (not shown) disposed on the portion of the top surface 2431 of the second substrate 243 that is not covered by the second molding compound 246 so as to be electrically connected to the third wires 25.
  • The sub-package 24 is selected from a group consisting of Land Grid Array (LGA) package, Quad Flat Non-leaded (QFN) package, Small Outline Non-leaded (SON) package and Chip On Film package. In this embodiment, the sub-package 24 is a Land Grid Array package whose bottom surface 2432 has a plurality of landing pads for testing. Therefore, the sub-package 24 is adhered to the first chip 22 after being tested so as to raise the yield rate of the multi-chip package structure 20A.
  • The first molding compound 26 is used for encapsulating the first chip 22, the sub-package 24, the first wires 23, the third wires 25 and the top surface 211 of the first substrate 21. The solder balls 27 are formed on the bottom surface 212 of the first substrate 21 so as to be electrically connected to an outer circuit.
  • The first chip 22 and the second chip 244 may be optical chip, logic chip, microprocessor chip or memory chip. In this embodiment, the first chip 22 is a microprocessor chip, and the second chip 244 is a memory chip.
  • FIG. 4 shows a cross sectional view of a multi-chip package structure according to the second embodiment of the present invention. The multi-chip package structure 20B of the embodiment is substantially equal to that of the first embodiment, except that a heat spreader 28 is added to the embodiment. The heat spreader 28 comprises a heat spreader body 281 and a supporting portion 282, wherein the supporting portion 282 extends outwardly and downwardly from the heat spreader body 281 so as to support the heat spreader body 281. The top surface of the heat spreader body 281 is exposed to the air after being encapsulated so as to increase heat dissipation efficiency.
  • FIG. 5 shows a cross sectional view of a multi-chip package structure according to the third embodiment of the present invention. The multi-chip package structure 20C of the embodiment is substantially equal to that of the first embodiment, except that the first chip 22 and the sub-package 24 are transposed. That is, the first chip 22 is disposed on the top surface 241 of the sub-package 24, and the bottom surface 242 of the sub-package 24 is adhered to the top surface 211 of the first substrate 21. Additionally, in this embodiment, the third wires 25 electrically connect the top surface 2431 of the second substrate 243 and the top surface 211 of the first substrate 21. Alternatively, the third wires 25 may electrically connect the first chip 22 and the first substrate 21, or the third wires 25 may electrically connect the first chip 22 and the second substrate 243.
  • FIG. 6 shows a cross sectional view of a multi-chip package structure according to the fourth embodiment of the present invention. The multi-chip package structure 30A of the embodiment comprises a first substrate 31, a first chip 32, a plurality of first wires 33, a sub-package 34, a plurality of third wires 35, a first molding compound 36, a plurality of solder balls 37, a third chip 38 and a plurality of fourth wires 39.
  • The first substrate 31 has a top surface 311 and a bottom surface 312. The first chip 32 is attached to the top surface 311 of the first substrate 31 and is electrically connected to the first substrate 31 by utilizing the first wires 33. It is to be noted that if the first chip 32 is attached to the first substrate 31 by flip-chip, there is no need to dispose the first wires 33.
  • The sub-package 34 has a top surface 341 and a bottom surface 342. The bottom surface 342 of the sub-package 34 is attached to the first chip 32 by utilizing adhesive glue. The sub-package 34 includes a second substrate 343, a second chip 344, a plurality of second wires 345 and a second molding compound 346.
  • The second substrate 343 has a top surface 3431 and a bottom surface 3432 and is electrically connected to the first chip 32 by utilizing the third wires 35. The second chip 344 is attached to the top surface 3431 of the second substrate 343 and is electrically connected to the second substrate 343 by utilizing the second wires 345. The second molding compound 346 is used for encapsulating the second chip 344 and part of the top surface 3431 of the second substrate 343. It is to be noted that the second molding compound 346 does not cover the entire top surface 3431 of the second substrate 343. There are a plurality of pads (not shown) disposed on the portion of the top surface 3431 of the second substrate 343 that is not covered by the second molding compound 346 so as to be electrically connected to the third wires 35.
  • The sub-package 34 is selected from a group consisting of Land Grid Array (LGA) package, Quad Flat Non-leaded (QFN) package, Small Outline Non-leaded (SON) package and Chip On Film package. In this embodiment, the sub-package 34 is a Land Grid Array package whose bottom surface 3432 has a plurality of landing pads for testing. Therefore, the sub-package 34 is adhered to the first chip 32 after being tested so as to raise the yield rate of the multi-chip package structure 30A.
  • The third chip 38 is attached to the top surface 341 of the sub-package 34 and is electrically connected to the first substrate 31 by utilizing the fourth wires 39 or is electrically connected to the first chip 32 by utilizing the fifth wires 391.
  • The first molding compound 36 is used for encapsulating the first chip 32, the sub-package 34, the first wires 33, the third wires 35, the third chip 38, the fourth wires 39 and the top surface 311 of the first substrate 31. The solder balls 37 are formed on the bottom surface 312 of the first substrate 31 so as to be electrically connected to an outer circuit.
  • The first chip 32, the second chip 344 and the third chip 38 may be optical chip, logic chip, microprocessor chip or memory chip. In this embodiment, the first chip 32 is a microprocessor chip, the second chip 344 is a memory chip and the third chip 38 is another microprocessor chip.
  • FIG. 7 shows a cross sectional view of a multi-chip package structure according to the fifth embodiment of the present invention. The multi-chip package structure 30B of the embodiment is substantially equal to that of the fourth embodiment, except that the third chip 38 is disposed is between the first chip 32 and the sub-package 34. That is, the first chip 32 is attached to the top surface 311 of the first substrate 31, the third chip 38 is attached to the first chip 32, and the bottom surface 342 of the sub-package 34 is adhered to the third chip 38.
  • In this embodiment, the first wires 33 electrically connect the first chip 32 and the first substrate 31. The second wires 345 electrically connect the second chip 344 and the second substrate 343. The third wires 35 electrically connect the second substrate 343 and the first chip 32. The fourth wires 392 electrically connect the second substrate 343 and the third chip 38. The fifth wires 391 electrically connect the first chip 32 and the third chip 38.
  • FIG. 8 shows a cross sectional view of a multi-chip package structure according to the sixth embodiment of the present invention. The multi-chip package structure 30C of the embodiment is substantially equal to that of the fourth embodiment, except that the first chip 32 and the third chip 38 are both disposed above the sub-package 34. That is, the bottom surface 342 of the sub-package 34 is adhered to the top surface 311 of the first substrate 31, the first chip 32 is attached to the top surface 341 of the sub-package 34, and the third chip 38 is attached to the first chip 32.
  • In this embodiment, the first wires 33 electrically connect the first chip 32 and the first substrate 31. The second wires 345 electrically connect the second chip 344 and the second substrate 343. The third wires 35 electrically connect the first substrate 31 and the second substrate 343. The fourth wires 392 electrically connect the first substrate 31 and the third chip 38. The fifth wires 391 electrically connect the first chip 32 and the third chip 38.
  • FIG. 9 shows a cross sectional view of a second type of sub-package according to the present invention. In above-mentioned embodiment, the sub-packages 24 (FIG. 3), 34 (FIG. 6) are first type of sub-package, wherein the second chips 244 (FIG. 3), 344 (FIG. 6) are attached to the top surface of the second substrate 243 (FIG. 3), 343 (FIG. 6). In FIG. 9, the sub-package is a second type of sub-package 40A that has a top surface 401 and a bottom surface 402, and further comprises a second substrate 41, a second chip 42, a plurality of second wires 43 and a second molding compound 44.
  • The second substrate 41 has a top surface 411, a bottom surface 412 and an opening 45. The second chip 42 is disposed in the opening 45 and is electrically connected to the second substrate 41 by utilizing the second wires 43. The second molding compound 44 is used for encapsulating the second chip 42 and part of the top surface 411 of the second substrate 41. It is to be noted that the second molding compound 44 does not cover the entire top surface 411 of the second substrate 41. There are at least one finger pad 46 and at least one test pad 47 disposed on the portion of the second substrate 41 that is not covered by the second molding compound 44. The finger pad 46 is used for being electrically connected to a wire, and the test pad 47 is used for testing. In this embodiment, the finger pad 46 is disposed on the top surface 411 of the second substrate 41, and the test pad 47 is disposed on the bottom surface 412 of the second substrate 41.
  • FIG. 10 shows a cross sectional view of a third type of sub-package according to the present invention. The sub-package 40B of the embodiment is substantially equal to the second type of sub-package 40A of FIG. 9, except that the finger pad 46 and the test pad 47 are both disposed on the top surface 411 of the second substrate 41 in this embodiment.
  • FIG. 11 shows a cross sectional view of a multi-chip package structure according to the seventh embodiment of the present invention.
  • The multi-chip package structure 20D of the embodiment is substantially equal to that of the first embodiment of FIG. 3, except that the sub-package 24 of the embodiment is inverted. Accordingly, the top surface 2431 of the second substrate 243 is the top surface of the sub-package, the bottom surface of the second molding compound 346 is the bottom surface of the sub-package, and the second chip 244 is attached to the bottom surface 2432 of the second substrate 243. The sub-package 24 of the embodiment is defined as a fourth type of sub-package 24.
  • FIG. 12 shows a cross sectional view of a fifth type of sub-package according to the present invention. The fifth type of sub-package 50A has a top surface 501 and a bottom surface 502, and further comprises a second substrate 51, a second chip 52, a plurality of second wires 53 and a second molding compound 54.
  • The second substrate 51 has a top surface 511, a bottom surface 512 and an opening 55. The second chip 52 is disposed in the opening 55 and is electrically connected to the second substrate 51 by utilizing the second wires 53. The second molding compound 54 is used for encapsulating the second chip 52 and part of the bottom surface 512 of the second substrate 51. There are at least one finger pad 56 and at least one test pad 57 disposed on the portion of the second substrate 51 that is not covered by the second molding compound 54. The finger pad 56 is used for being electrically connected to a wire, and the test pad 57 is used for testing. In this embodiment, the finger pad 56 is disposed on the top surface 511 of the second substrate 51, and the test pad 57 is disposed on the bottom surface 512 of the second substrate 51.
  • FIG. 13 shows a cross sectional view of a sixth type of sub-package according to the present invention. The sub-package 50B of the embodiment is substantially equal to the fifth type of sub-package 50A of FIG. 12, except that the finger pad 56 and the test pad 57 are both disposed on the top surface 511 of the second substrate 51 in this embodiment.
  • FIG. 14 shows a cross sectional view of a seventh type of sub-package according to the present invention. The sub-package 50C of the embodiment is substantially equal to the sixth type of sub-package 50B of FIG. 13, except that the finger pad 56 is disposed on the bottom surface 512 of the second substrate 51, and the test pad 57 is disposed on the top surface 511 of the second substrate 51.
  • FIG. 15 shows a cross sectional view of a multi-chip package structure according to the eighth embodiment of the present invention. The multi-chip package structure 60 of the embodiment comprises a first sub-package 61, a second sub-package 62, a third substrate 63, a third molding compound 64, a plurality of third wires 65, a plurality of fourth wires 66 and a plurality of solder balls 67.
  • The third substrate 63 has a top surface 631 and a bottom surface 632. The third molding compound 64 is used for encapsulating the first sub-package 61, the second sub-package 62 and the top surface 631 of the third substrate 63. The third wires 65 electrically connect the third substrate 63 and the first sub-package 61. The fourth wires 66 electrically connect the third substrate 63 and the second sub-package 62. The solder balls 67 are formed on the bottom surface 632 of the third substrate 63.
  • The first sub-package 61 has a top surface 611 and a bottom surface 612, and further comprises a first substrate 613, a first chip 614, a first molding compound 615 and a plurality of first wires 616. The first substrate 613 has a top surface 6131 and a bottom surface 6132. The first chip 614 is electrically connected to the first substrate 613 by utilizing the first wires 616. The first molding compound 615 has a top surface and a second surface, and is used for encapsulating the first chip 614 and the first substrate 613.
  • The second sub-package 62 has a top surface 621 and a bottom surface 622, and further comprises a second substrate 623, a second chip 624, a second molding compound 625 and a plurality of second wires 626. The second substrate 623 has a top surface 6231 and a bottom surface 6232. The second chip 624 is electrically connected to the second substrate 623 by utilizing the second wires 626. The second molding compound 625 has a top surface and a second surface, and is used for encapsulating the second chip 624 and the second substrate 623.
  • In the first sub-package 61 of this embodiment, the first chip 614 is attached to the top surface 6131 of the first substrate 613 directly, and in the second sub-package 62, the second chip 624 is attached to the top surface 6231 of the second substrate 623 directly. However, it is understood that the first sub-package 61 or the second sub-package 62 can be replaced by the second type of sub-package 40A shown in FIG. 9 or the third type of sub-package 40B shown in FIG. 10.
  • In this embodiment, the first sub-package 61 and the second sub-package 62 are stacked. However, it is understood that the multi-chip package structure 60 can further comprise a third chip that may be disposed above the second sub-package 62, between the first sub-package 61 and the second sub-package 62, or between the first sub-package 61 and the third substrate 63.
  • FIG. 16 shows a cross sectional view of a multi-chip package structure according to the ninth embodiment of the present invention. The multi-chip package structure 60B of the embodiment is substantially equal to that of the eighth embodiment of FIG. 15, except that the sub-package 62 of this embodiment is inverted. It is understood that the first sub-package 61 may also be inverted.
  • In the second sub-package 62 of this embodiment, the second chip 624 is attached to the bottom surface 6232 of the second substrate 623 directly. However, it is understood that the inverse second sub-package 62 can be replaced by the fifth type of sub-package 50A shown in FIG. 12, the sixth type of sub-package 50B shown in FIG. 13, or the seventh type of sub-package 50C shown in FIG. 14.
  • In this embodiment, the first sub-package 61 and the second sub-package 62 are stacked. However, it is understood that the multi-chip package structure 60 can further comprise a third chip that may be disposed above the second sub-package 62, between the first sub-package 61 and the second sub-package 62, or between the first sub-package 61 and the third substrate 63.
  • FIG. 17 shows a cross sectional view of a multi-chip package structure according to the tenth embodiment of the present invention. The multi-chip package structure 30D of the embodiment is substantially the same as that of the sixth embodiment of FIG. 8, except that the sub-package 34 of this embodiment is inverted.
  • The multi-chip package structure 30D of the embodiment comprises a first substrate 31, a first chip 32, a plurality of first wires 33, a sub-package 34, a plurality of third wires 35, a first molding compound 36, a plurality of solder balls 37, a third chip 38, a plurality of fourth wires 39 and a plurality of fifth wires 391.
  • The first substrate 31 has a top-surface 311 and a bottom surface 312. The bottom surface 342 of the sub-package 34 is attached to the top surface 311 of the first substrate 31 by utilizing adhesive glue. The sub-package 34 includes a second substrate 343, a second chip 344, a plurality of second wires 345 and a second molding compound 346.
  • The second substrate 343 has a top surface 3431 and a bottom surface 3432 and is electrically connected to the first substrate 31 by utilizing the third wires 35. The second chip 344 is attached to the bottom surface 3433 of the second substrate 343 and is electrically connected to the second substrate 343 by utilizing the second wires 345. The second molding compound 346 is used for encapsulating the second chip 344 and part of the bottom surface 3432 of the second substrate 343.
  • The first chip 32 is attached to the top surface 3411 of the sub-package 34 and is electrically connected to the first substrate 31 by utilizing the first wires 33. The third chip 38 is attached to the first chip 32 and is electrically connected to the first substrate 31 by utilizing the fourth wires 392 or is electrically connected to the first chip 32 by utilizing the fifth wires 391.
  • The first molding compound 36 is used for encapsulating the first chip 32, the sub-package 34, the first wires 33, the third wires 35, the third chip 38, the fourth wires 39, the fifth wires 391 and the top surface 311 of the first substrate 31. The solder balls 37 are formed on the bottom surface 312 of the first substrate 31 so as to be electrically connected to an outer circuit.
  • While several embodiments of the present invention have been illustrated and described, various modifications and improvements can be made by those skilled in the art. The embodiments of the present invention are therefore described in an illustrative but not restrictive sense. It is intended that the present invention may not be limited to the particular forms as illustrated, and that all modifications which maintain the spirit and scope of the present invention are within the scope as defined in the appended claims.

Claims (19)

1. (canceled)
2. (canceled)
3. (canceled)
4. (canceled)
5. (canceled)
6. (canceled)
7. (canceled)
8. (canceled)
9. (canceled)
10. (canceled)
11. (canceled)
12. (canceled)
13. (canceled)
14. A multi-chip package structure comprising:
a first substrate having a top surface and a bottom surface;
a first chip attached to the top surface of the first substrate;
a plurality of first wires used for electrically connecting the first substrate and the first chip;
a sub-package having a top surface and a bottom surface, wherein the bottom surface of the sub-package is attached to the first chip, the sub-package including:
a second substrate having a top surface and a bottom surface, the second substrate being electrically connected to the first substrate;
a second chip attached to the top surface of the second substrate and electrically connected to the second substrate; and
a second molding compound used for encapsulating the second chip and part of the top surface of the second substrate; and
a first molding compound used for encapsulating the first chip, the sub-package and the top surface of the first substrate.
15. The package structure according to claim 1, further comprising a heat spreader having a heat spreader body and a supporting portion, wherein the supporting portion extends outwardly and downwardly from the heat spreader body so as to support the heat spreader body, and the top surface of the heat spreader body is exposed to the air.
16. The package structure according to claim 1, further comprising a third chip disposed on the top surface of the sub-package.
17. A multi-chip package structure comprising:
a first substrate having a top surface and a bottom surface;
a first chip attached to the top surface of the first substrate;
a plurality of first wires used for electrically connecting the first substrate and the first chip;
a third chip attached to the top surface of the first chip;
a sub-package having a top surface and a bottom surface, wherein the bottom surface of the sub-package is attached to the third chip, the sub-package including:
a second substrate having a top surface and a bottom surface, the second substrate being electrically connected to the first substrate;
a second chip attached to the top surface of the second substrate and electrically connected to the second substrate; and
a second molding compound used for encapsulating the second chip and part of the top surface of the second substrate; and
a first molding compound used for encapsulating the first chip, the third chip, the sub-package and the top surface of the first substrate.
18. The package structure according to claim 4, wherein the second substrate is electrically connected to the first chip.
19. The package structure according to claim 4, wherein the second substrate is electrically connected to the third chip.
US11/353,532 2003-12-31 2006-02-14 Multi-chip package structure Abandoned US20060131717A1 (en)

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US11/026,763 US7129583B2 (en) 2003-12-31 2004-12-31 Multi-chip package structure
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050140022A1 (en) * 2003-12-31 2005-06-30 Su Tao Multi-chip package structure

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6297548B1 (en) 1998-06-30 2001-10-02 Micron Technology, Inc. Stackable ceramic FBGA for high thermal applications
US20060138631A1 (en) * 2003-12-31 2006-06-29 Advanced Semiconductor Engineering, Inc. Multi-chip package structure
JP2006190972A (en) * 2004-12-08 2006-07-20 Mitsubishi Electric Corp Power semiconductor device
US7271496B2 (en) * 2005-02-04 2007-09-18 Stats Chippac Ltd. Integrated circuit package-in-package system
JP2006216911A (en) * 2005-02-07 2006-08-17 Renesas Technology Corp Semiconductor device and encapsulated semiconductor package
KR100651125B1 (en) * 2005-03-21 2006-12-01 삼성전자주식회사 Double molded multi chip package and manufacturing method thereof
US7582963B2 (en) * 2005-03-29 2009-09-01 Texas Instruments Incorporated Vertically integrated system-in-a-package
US7332808B2 (en) * 2005-03-30 2008-02-19 Sanyo Electric Co., Ltd. Semiconductor module and method of manufacturing the same
JP4748648B2 (en) * 2005-03-31 2011-08-17 ルネサスエレクトロニクス株式会社 Semiconductor device
US7589407B2 (en) * 2005-04-11 2009-09-15 Stats Chippac Ltd. Semiconductor multipackage module including tape substrate land grid array package stacked over ball grid array package
US7849441B2 (en) * 2005-06-27 2010-12-07 Ikoa Corporation Method for specifying stateful, transaction-oriented systems for flexible mapping to structurally configurable, in-memory processing semiconductor device
JP4871280B2 (en) 2005-08-30 2012-02-08 スパンション エルエルシー Semiconductor device and manufacturing method thereof
TWI263314B (en) * 2005-10-26 2006-10-01 Advanced Semiconductor Eng Multi-chip package structure
US7981702B2 (en) 2006-03-08 2011-07-19 Stats Chippac Ltd. Integrated circuit package in package system
US7986043B2 (en) * 2006-03-08 2011-07-26 Stats Chippac Ltd. Integrated circuit package on package system
TWI298198B (en) 2006-05-30 2008-06-21 Advanced Semiconductor Eng Stackable semiconductor package
DE102006026023A1 (en) * 2006-06-01 2007-12-06 Infineon Technologies Ag Semiconductor component, has plastic compound arranged between another plastic compound and edge sides of adhesive layer and chip and upper side of chip such that latter plastic compound does not have physical contact to chip and layer
US20080042265A1 (en) * 2006-08-15 2008-02-21 Merilo Leo A Chip scale module package in bga semiconductor package
TWI317993B (en) 2006-08-18 2009-12-01 Advanced Semiconductor Eng Stackable semiconductor package
US20080054431A1 (en) * 2006-08-31 2008-03-06 Tingqing Wang Embedded package in package
US7659609B2 (en) * 2007-08-31 2010-02-09 Stats Chippac Ltd. Integrated circuit package-in-package system with carrier interposer
US8120150B2 (en) * 2007-09-18 2012-02-21 Stats Chippac Ltd. Integrated circuit package system with dual connectivity
SG142321A1 (en) 2008-04-24 2009-11-26 Micron Technology Inc Pre-encapsulated cavity interposer
KR101490334B1 (en) * 2008-04-30 2015-02-06 삼성전자주식회사 Interposer chip and multi-chip package having the interposer chip
US8022539B2 (en) * 2008-11-17 2011-09-20 Stats Chippac Ltd. Integrated circuit packaging system with increased connectivity and method of manufacture thereof
US8743561B2 (en) * 2009-08-26 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level molded structure for package assembly
US8451014B2 (en) * 2009-09-09 2013-05-28 Advanced Micro Devices, Inc. Die stacking, testing and packaging for yield
TWM398646U (en) * 2010-08-13 2011-02-21 Orient Semiconductor Elect Ltd Micro projector module
KR20130110937A (en) * 2012-03-30 2013-10-10 삼성전자주식회사 Semiconductor package and method of manufacturing the semiconductor package
US9379034B1 (en) 2014-12-30 2016-06-28 Stmicroelectronics Pte Ltd Method of making an electronic device including two-step encapsulation and related devices
US9786623B2 (en) * 2015-03-17 2017-10-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming PoP semiconductor device with RDL over top package
TWI582916B (en) * 2015-04-27 2017-05-11 南茂科技股份有限公司 Multi chip package structure, wafer level chip package structure and manufacturing method thereof
TWI584428B (en) * 2016-06-08 2017-05-21 力成科技股份有限公司 Heat-dissipating semiconductor package for lessening package warpage

Citations (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6521881B2 (en) * 2001-04-16 2003-02-18 Kingpak Technology Inc. Stacked structure of an image sensor and method for manufacturing the same
US6583512B2 (en) * 2000-12-26 2003-06-24 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
US6607937B1 (en) * 2000-08-23 2003-08-19 Micron Technology, Inc. Stacked microelectronic dies and methods for stacking microelectronic dies
US6677672B2 (en) * 2002-04-26 2004-01-13 Semiconductor Components Industries Llc Structure and method of forming a multiple leadframe semiconductor device
US6700178B2 (en) * 2001-03-09 2004-03-02 Advanced Semiconductor Engineering, Inc. Package of a chip with beveled edges
US20040056227A1 (en) * 2002-09-25 2004-03-25 Karlheinz Mayr Proportional pressure-regulator valve
US20040061212A1 (en) * 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages
US20040063246A1 (en) * 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages
US20040061213A1 (en) * 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
US20040063242A1 (en) * 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages
US20040065963A1 (en) * 2002-09-17 2004-04-08 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield
US20040113275A1 (en) * 2002-10-08 2004-06-17 Chippac, Inc. Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package
US6753599B2 (en) * 2001-02-12 2004-06-22 Samsung Electronics Co., Ltd. Semiconductor package and mounting structure on substrate thereof and stack structure thereof
US6762488B2 (en) * 2002-03-19 2004-07-13 Nec Electronics Corporation Light thin stacked package semiconductor device and process for fabrication thereof
US6828665B2 (en) * 2002-10-18 2004-12-07 Siliconware Precision Industries Co., Ltd. Module device of stacked semiconductor packages and method for fabricating the same
US20050133916A1 (en) * 2003-12-17 2005-06-23 Stats Chippac, Inc Multiple chip package module having inverted package stacked over die
US6979895B2 (en) * 1997-03-10 2005-12-27 Micron Technology, Inc. Semiconductor assembly of stacked substrates and multiple semiconductor dice
US20060012018A1 (en) * 2004-07-13 2006-01-19 Chippac, Inc. Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package
US7129583B2 (en) * 2003-12-31 2006-10-31 Advanced Semiconductor Engineering, Inc. Multi-chip package structure
US20070018296A1 (en) * 2004-05-24 2007-01-25 Chippac, Inc Stacked Semiconductor Package having Adhesive/Spacer Structure and Insulation
US20070241442A1 (en) * 2006-04-18 2007-10-18 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
US20080032450A1 (en) * 2005-02-02 2008-02-07 Chien-Ping Huang Method for fabricating chip-stacked semiconductor package
US20080042251A1 (en) * 2006-08-18 2008-02-21 Gwo-Liang Weng Stackable semiconductor package

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5492586A (en) * 1993-10-29 1996-02-20 Martin Marietta Corporation Method for fabricating encased molded multi-chip module substrate
TW445612B (en) * 2000-08-03 2001-07-11 Siliconware Prec Ind Co Ltd Solder ball array structure to control the degree of collapsing
WO2002048259A2 (en) 2000-12-12 2002-06-20 Massachusetts General Hospital Selective, controlled manipulation of polymers
US20020127771A1 (en) * 2001-03-12 2002-09-12 Salman Akram Multiple die package
JP4126891B2 (en) * 2001-08-03 2008-07-30 セイコーエプソン株式会社 A method of manufacturing a semiconductor device
US6972481B2 (en) 2002-09-17 2005-12-06 Chippac, Inc. Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages
US6852259B2 (en) 2002-09-18 2005-02-08 Owens Corning Fiberglas Technology, Inc. Moldable preform with B-stage thermoset polymer powder binder
JP3680839B2 (en) * 2003-03-18 2005-08-10 セイコーエプソン株式会社 The method of manufacturing a semiconductor device and a semiconductor device
JP2004281920A (en) * 2003-03-18 2004-10-07 Seiko Epson Corp Semiconductor device, electronic device, electronic apparatus, process for producing semiconductor device, and process for producing electronic device
US7034387B2 (en) * 2003-04-04 2006-04-25 Chippac, Inc. Semiconductor multipackage module including processor and memory package assemblies
US20060138631A1 (en) * 2003-12-31 2006-06-29 Advanced Semiconductor Engineering, Inc. Multi-chip package structure
TWI239611B (en) * 2004-04-19 2005-09-11 Advanced Semiconductor Eng Multi chip module with embedded package configuration and method for manufacturing the same

Patent Citations (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6979895B2 (en) * 1997-03-10 2005-12-27 Micron Technology, Inc. Semiconductor assembly of stacked substrates and multiple semiconductor dice
US6607937B1 (en) * 2000-08-23 2003-08-19 Micron Technology, Inc. Stacked microelectronic dies and methods for stacking microelectronic dies
US6583512B2 (en) * 2000-12-26 2003-06-24 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for fabricating the same
US6753599B2 (en) * 2001-02-12 2004-06-22 Samsung Electronics Co., Ltd. Semiconductor package and mounting structure on substrate thereof and stack structure thereof
US6700178B2 (en) * 2001-03-09 2004-03-02 Advanced Semiconductor Engineering, Inc. Package of a chip with beveled edges
US6521881B2 (en) * 2001-04-16 2003-02-18 Kingpak Technology Inc. Stacked structure of an image sensor and method for manufacturing the same
US6762488B2 (en) * 2002-03-19 2004-07-13 Nec Electronics Corporation Light thin stacked package semiconductor device and process for fabrication thereof
US6677672B2 (en) * 2002-04-26 2004-01-13 Semiconductor Components Industries Llc Structure and method of forming a multiple leadframe semiconductor device
US20040063246A1 (en) * 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages
US20040061213A1 (en) * 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages
US20040063242A1 (en) * 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over ball grid array package and having wire bond interconnect between stacked packages
US20040065963A1 (en) * 2002-09-17 2004-04-08 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield
US20040061212A1 (en) * 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages
US7064426B2 (en) * 2002-09-17 2006-06-20 Chippac, Inc. Semiconductor multi-package module having wire bond interconnect between stacked packages
US20040056227A1 (en) * 2002-09-25 2004-03-25 Karlheinz Mayr Proportional pressure-regulator valve
US20040113253A1 (en) * 2002-10-08 2004-06-17 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package
US20040119152A1 (en) * 2002-10-08 2004-06-24 Chippac, Inc. Semiconductor multi-package module having inverted bump chip carrier second package
US20040119153A1 (en) * 2002-10-08 2004-06-24 Chippac, Inc. Semiconductor multi-package module having inverted land grid array (LGA) package stacked over ball grid array (BGA) package
US20040113254A1 (en) * 2002-10-08 2004-06-17 Chippac, Inc. Semiconductor multi-package module having inverted second package stacked over die-down flip-chip ball grid array (BGA) package
US20040113275A1 (en) * 2002-10-08 2004-06-17 Chippac, Inc. Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package
US20040113255A1 (en) * 2002-10-08 2004-06-17 Chippac, Inc. Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package
US20040124518A1 (en) * 2002-10-08 2004-07-01 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package and electrically shielded first package
US6828665B2 (en) * 2002-10-18 2004-12-07 Siliconware Precision Industries Co., Ltd. Module device of stacked semiconductor packages and method for fabricating the same
US20050133916A1 (en) * 2003-12-17 2005-06-23 Stats Chippac, Inc Multiple chip package module having inverted package stacked over die
US7129583B2 (en) * 2003-12-31 2006-10-31 Advanced Semiconductor Engineering, Inc. Multi-chip package structure
US20070018296A1 (en) * 2004-05-24 2007-01-25 Chippac, Inc Stacked Semiconductor Package having Adhesive/Spacer Structure and Insulation
US20060012018A1 (en) * 2004-07-13 2006-01-19 Chippac, Inc. Semiconductor multipackage module including die and inverted land grid array package stacked over ball grid array package
US20080032450A1 (en) * 2005-02-02 2008-02-07 Chien-Ping Huang Method for fabricating chip-stacked semiconductor package
US20070241442A1 (en) * 2006-04-18 2007-10-18 Stats Chippac Ltd. Stacked integrated circuit package-in-package system
US20080042251A1 (en) * 2006-08-18 2008-02-21 Gwo-Liang Weng Stackable semiconductor package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050140022A1 (en) * 2003-12-31 2005-06-30 Su Tao Multi-chip package structure
US20060055019A1 (en) * 2003-12-31 2006-03-16 Su Tao Multi-chip package structure
US7253529B2 (en) * 2003-12-31 2007-08-07 Advanced Semiconductor Engineering, Inc. Multi-chip package structure

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US20070290318A1 (en) 2007-12-20
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