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US20060122805A1 - Adaptive cache algorithm for temperature sensitive memory - Google Patents

Adaptive cache algorithm for temperature sensitive memory Download PDF

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Publication number
US20060122805A1
US20060122805A1 US11338232 US33823206A US2006122805A1 US 20060122805 A1 US20060122805 A1 US 20060122805A1 US 11338232 US11338232 US 11338232 US 33823206 A US33823206 A US 33823206A US 2006122805 A1 US2006122805 A1 US 2006122805A1
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Prior art keywords
cache
temperature
memory
system
operation
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Abandoned
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US11338232
Inventor
Richard Coulson
Brian Leete
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Coulson Richard L
Leete Brian A
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/16Constructional details or arrangements
    • G06F1/20Cooling means
    • G06F1/206Cooling means comprising thermal management
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache

Abstract

A temperature sensitive memory, such as a ferro-electric polymer memory, may be utilized as a disk cache memory in one embodiment. If the temperature begins to threaten shutdown, the memory may be transitioned from a write-back to a write-through cache memory. In such case, the system is ready for shutdown without the loss of critical data.

Description

  • [0001]
    This application is a continuation of U.S. patent application Ser. No. 10/660,310, filed on Sep. 11, 2003.
  • BACKGROUND
  • [0002]
    This invention relates generally to electronic memories which may be sensitive to higher temperature environments.
  • [0003]
    In many cases, electronic memories may be subjected to higher temperature operating environments. For example, within a notebook or mobile personal computer, elevated temperatures may be encountered. Some types of memory may cease to function correctly at extended temperatures.
  • [0004]
    Ferroelectric polymer memory uses a polymer between a pair of electrodes. Ferroelectric polymer memories may be subject to voltage based disturbs at higher temperatures. At higher temperatures, a ferroelectric polymer memory may slow down its operation in order to function correctly.
  • [0005]
    This tendency to reduce speed at extended temperatures may complicate the operation of the system which relies on the ferroelectric polymer memory or other temperature sensitive memories. The slower data transfer rate may be unexpected by the rest of the system, since the remainder of the system may not be aware of the higher temperature conditions. Thus, the unexpected speed reduction may create unexpected problems in processor-based systems that rely on these memories, for example for caching purposes.
  • [0006]
    Thus, there is a need for a way to adapt processor-based systems to temperature sensitive memories.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0007]
    FIG. 1 is a schematic depiction of one embodiment of the present invention;
  • [0008]
    FIG. 2 is a state diagram for a cache driver in accordance with one embodiment of the present invention; and
  • [0009]
    FIG. 3 is a flow chart for one embodiment of the present invention.
  • DETAILED DESCRIPTION
  • [0010]
    Referring to FIG. 1, a processor-based system 10 may be any conventional processor-based system, including mobile systems that operate on battery power. Examples of mobile systems include laptop computers, personal digital assistants, digital cameras, and cellular telephones. However, the present invention may be applicable to any of a wide range of processor-based systems.
  • [0011]
    The system 10 may include a processor 12 coupled in one architecture to a memory control hub 16. The hub 16 may in turn be coupled to an input/output control hub 18 in that architecture. The input/output control hub 18 may be coupled to a disk drive 20 and a cache memory 22. The cache memory 22 may be temperature sensitive. As examples, the temperature sensitive cache memory may be a ferroelectric polymer memory or a flash memory.
  • [0012]
    The memory 22 may include a temperature sensor 24 in one embodiment of the present invention. The temperature sensor 24 may be a silicon diode formed on or integrated into the memory 22 in one embodiment.
  • [0013]
    Although a particular architecture is illustrated in FIG. 1, the present invention is dependent on no particular architecture. Thus, a wide variety of other processor-based architectures may be utilized in other embodiments.
  • [0014]
    The processor 12 may include a storage 14 that stores a cache driver 14 that executes on the processor 12. The cache driver 14 adapts the processor-based system 10 to the vagaries of the cache memory 22 and, particularly, to its temperature sensitivity. For example, in one embodiment, when the temperature rises, and the memory 22 has a slower data transfer rate, the cache driver 14 may enable the system to adapt. The driver 14 itself may adapt to make more optimal decisions about what data to cache and not cache based on its knowledge of the cache's current data rate in view of the detected temperature.
  • [0015]
    Whenever the driver 14 makes a request to the cache memory 22, a status code is returned. This status code includes whether the operation succeeded or failed, whether error correction was applied, how much was applied, and the cache's temperature environment.
  • [0016]
    Referring to FIG. 2, normal operation is indicated at the state 26. In normal operation, the memory 22 may be a write-back cache. In a write-back cache, modifications to data in the cache are not copied to the disk drive 20 or other cache source and the cache simultaneously. In a write-through cache those changes may start to be written simultaneously, but since the disk drive is much slower, the operation takes longer, and thus the performance is lower.
  • [0017]
    The system 10 transitions from the normal operation state 26, to a reduced speed operation state 28, for example when the cache memory 22 is exposed to an elevated temperature environment called the throttle temperature range. In one embodiment, the temperature sensor 24 may detect that a higher temperature environment has been encountered. This higher or throttle temperature environment may be a temperature in the range of 60 to 80° C. in an embodiment where the cache memory 22 is a ferroelectric polymer memory.
  • [0018]
    In this throttle temperature range, the cache memory 22 may be exposed to voltage disturbs if it does not reduce its data transfer rate. A voltage disturb is a voltage that causes data to be written incorrectly. The use of the memory 22 may be adjusted for reduced speed operation, if any, at state 28. For example, in one embodiment, the cache driver 14 may avoid operations like pre-fetching or other speculative data acquisitions that may necessitate higher data transfer rates than the cache memory 22 can currently support. Also, the timing of the control logic on the memory 22 may be slowed down.
  • [0019]
    From the reduced speed operation state 28, the system may transition to an operation safe for sudden shutdown state 30. This may occur when the temperature becomes even more elevated. In one embodiment, using a cache memory 22 that is a ferroelectric polymer memory, the state 30 may be encountered at a critical temperature of 80 to 85° C.
  • [0020]
    In the state 30, the system 10 switches to a write-through caching algorithm and dirty cache lines (i.e., those that have not been written to system memory) are flushed. The system 10 may be close to the upper temperature or shutoff temperature of the cache memory 22. Thus, the cache driver 14 software or its hardware equivalent, changes algorithms so that it can shut off at any time without compromising data integrity. The driver 14 may cause the memory 22 to operate as a write-through cache rather than a write-back cache so that there is no dirty data in the cache.
  • [0021]
    The next transition, to the cache shutdown state 32, may occur at a shut-off temperature of about 85° C. in the embodiment in which the cache memory 22 is a ferroelectric polymer memory. In this transition, cache lines may be invalidated and the cache memory 22 may be shut off.
  • [0022]
    The system 10 then waits for a reduced or critical temperature range to introduce hysteresis in state 34. Alternatively, the system may wait until a reboot/resume before resuming reduced speed cache operations. From the hysteresis state 34, the system 10 may transition back to reduced speed operation state 28 by initializing a cache state, beginning the use of the cache, and using reduced speed algorithms. In the reduced speed operation state 28, with reduced temperature, the system 10 may adjust the algorithm for full speed operations, eventually returning, as indicated at F, to the normal operation state 26 at the normal temperature range.
  • [0023]
    Transitions may be spurred by the temperature sensor 24 that provides the temperature information to the cache driver 14 to appropriately control the operation of the system 10. For example, in the transition A, the temperature sensor 24 may indicate a throttle temperature range through the cache driver 14. The transition B may be initiated in response to a critical temperature range and the transition C may be indicated in response to the detection of a shutoff temperature. The transition D may be the result of a status indication of a critical temperature. The transition E may be the result of a status indication of a throttle temperature range, while the transition F may result from a status indication of a normal temperature range.
  • [0024]
    When the temperature sensed by the temperature sensor 24 is rising, the cache memory 22 is switched to write-through caching, so if the temperature rises further, and cache memory 22 shutdown is necessary, it can be done without loss of data integrity. The cache memory 22 operates in a shutdown safe mode without dirty data in the cache. The critical range is set sufficiently below the shutdown temperature to allow margin for writing the dirty data before the temperature rises to shutdown.
  • [0025]
    If the temperature reaches the shutdown temperature, the cache memory 22 is no longer used. The contents of the cache memory 22 are invalidated so that, in case of a crash and recovery, it is clear that the contents of a cache memory 22 are invalid. As the temperature cools, there are two choices in some embodiments. Under one choice, the system 10 can wait until a reboot or resume to start up the cache memory 22 again. Alternatively, the system 10 can wait until the temperature is below the critical temperature. In either case, the cache memory 22 may be reinitialized and started from empty.
  • [0026]
    Referring to FIG. 3, the cache driver 14, in one embodiment, may initially check to determine whether the throttle temperature was exceeded as indicated in diamond 36. If so, the operation of either the cache memory 22, the cache driver 14, or other components of the system 10 may be modified to adapt to the slower speed operation of the cache memory 22 as indicated in block 38.
  • [0027]
    Next, a check at diamond 40 determines whether or not a critical temperature has been exceeded. If so, the cache memory 22 may be switched to operate as a write-through cache as indicated in block 42. Also, any dirty lines may be flushed as indicated in block 44.
  • [0028]
    Thereafter, the driver 14 monitors for the occurrence of a shutoff temperature as determined in diamond 46. If it is detected, the cache memory 22 may be shutdown as indicated in block 48. Thereafter, the memory 22 may transition back through a hysteresis state 34 to a reduced speed operation state 28, back to normal operation as shown in FIG. 2.
  • [0029]
    Thus, despite temperature sensitivity, some memories can be used as cache memories, for disk caching purposes for example, when the operating range is less than the possible temperatures experienced in real life usage. In one such case, the cache memory 22 may be utilized as a disk cache to cache information read off the disk drive 20.
  • [0030]
    While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Claims (14)

  1. 1. A method comprising:
    monitoring a temperature; and
    in response to a detection of a temperature condition, operating a cache memory in one of two different modes depending on the temperature.
  2. 2. The method of claim 1 including monitoring the temperature of a ferroelectric polymer cache memory.
  3. 3. The method of claim 1 including adjusting the operation of a system using said memory at a first temperature and, in response to the detection of a higher, second temperature, transitioning the cache from a write-back cache to a write-through cache.
  4. 4. The method of claim 3, including slowing an operation of said system at said first temperature.
  5. 5. The method of claim 3 including reducing pre-fetching at said first temperature.
  6. 6. A computer readable medium storing instructions that, if executed, enable a processor-based system to:
    monitor a temperature of a cache memory; and
    in response to the detection of a temperature condition, operating a cache memory in one of two different modes depending on the temperature.
  7. 7. The medium of claim 6 further storing instructions that, if executed, enable a processor-based system to monitor the temperature of a ferroelectric polymer cache memory.
  8. 8. The medium of claim 6 further storing instructions that, if executed, enable a processor-based system to adjust the operation of a system using said memory at a first temperature and, in response to the detection of a higher, second temperature, transition the cache memory from a write-back to a write-through cache.
  9. 9. A circuit comprising:
    a cache memory; and
    a component to receive an indication of a temperature and to develop a signal to transition the cache memory from a first to a second operating mode in response to said temperature indication.
  10. 10. The circuit of claim 9 wherein said component to vary the operation of a system to adjust for the temperature affected operation of said cache memory.
  11. 11. The circuit of claim 10 wherein said component to adjust a caching operation of the system in response to a temperature indication from said memory.
  12. 12. The circuit of claim 10 wherein said component to shut off said cache in response to a temperature indication.
  13. 13. The circuit of claim 12 wherein said component to invalidate a cache line in said cache memory.
  14. 14. The circuit of claim 9 including a ferroelectric polymer memory.
US11338232 2003-09-11 2006-01-24 Adaptive cache algorithm for temperature sensitive memory Abandoned US20060122805A1 (en)

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US10660310 US7233880B2 (en) 2003-09-11 2003-09-11 Adaptive cache algorithm for temperature sensitive memory
US11338232 US20060122805A1 (en) 2003-09-11 2006-01-24 Adaptive cache algorithm for temperature sensitive memory

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US11338232 US20060122805A1 (en) 2003-09-11 2006-01-24 Adaptive cache algorithm for temperature sensitive memory

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US10660310 Continuation US7233880B2 (en) 2003-09-11 2003-09-11 Adaptive cache algorithm for temperature sensitive memory

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EP (1) EP1668514B1 (en)
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CN (1) CN100573475C (en)
DE (1) DE602004004414T2 (en)
WO (1) WO2005026965A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080010408A1 (en) * 2006-07-05 2008-01-10 International Business Machines Corporation Cache reconfiguration based on run-time performance data or software hint
US20130176170A1 (en) * 2012-01-05 2013-07-11 Cambridge Silicon Radio Ltd. Reverse frequency and time aiding
US8612677B1 (en) 2012-07-26 2013-12-17 Kabushiki Kaisha Toshiba Memory system and method of writing data in a memory system

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004102389A1 (en) * 2003-05-16 2004-11-25 Fujitsu Limited Initialization device, initialization method, initialization program, and information processing device
US8683139B2 (en) * 2006-10-31 2014-03-25 Hewlett-Packard Development Company, L.P. Cache and method for cache bypass functionality
KR100916550B1 (en) 2007-10-08 2009-09-14 고려대학교 산학협력단 method for proventing damage of instruction cache memory by malicious code
US20090138220A1 (en) * 2007-11-28 2009-05-28 Bell Jr Robert H Power-aware line intervention for a multiprocessor directory-based coherency protocol
US8706950B2 (en) 2008-03-01 2014-04-22 Kabushiki Kaisha Toshiba Memory system
JP4643671B2 (en) * 2008-03-11 2011-03-02 株式会社東芝 Memory system
US8364901B2 (en) * 2009-02-13 2013-01-29 Micron Technology, Inc. Memory prefetch systems and methods
US8782667B2 (en) * 2010-12-27 2014-07-15 International Business Machines Corporation Weather adaptive environmentally hardened appliances
US8719531B2 (en) * 2011-06-14 2014-05-06 Western Digital Technologies, Inc. System and method for performing data retention that incorporates environmental conditions
US20130080679A1 (en) * 2011-09-26 2013-03-28 Lsi Corporation System and method for optimizing thermal management for a storage controller cache
US9584617B2 (en) * 2013-12-31 2017-02-28 Successfactors, Inc. Allocating cache request in distributed cache system based upon cache object and marker identifying mission critical data

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5598395A (en) * 1993-11-02 1997-01-28 Olympus Optical Co., Ltd. Data loss prevention in a cache memory when the temperature of an optical recording medium is abnormal
US5737748A (en) * 1995-03-15 1998-04-07 Texas Instruments Incorporated Microprocessor unit having a first level write-through cache memory and a smaller second-level write-back cache memory
US5761705A (en) * 1996-04-04 1998-06-02 Symbios, Inc. Methods and structure for maintaining cache consistency in a RAID controller having redundant caches
US5815648A (en) * 1995-11-14 1998-09-29 Eccs, Inc. Apparatus and method for changing the cache mode dynamically in a storage array system
US5956289A (en) * 1997-06-17 1999-09-21 Micron Technology, Inc. Clock signal from an adjustable oscillator for an integrated circuit
US5996289A (en) * 1998-04-23 1999-12-07 Building Materials Corporation Of America Soffit vent
US6438647B1 (en) * 2000-06-23 2002-08-20 International Business Machines Corporation Method and apparatus for providing battery-backed immediate write back cache for an array of disk drives in a computer system
US6564288B2 (en) * 2000-11-30 2003-05-13 Hewlett-Packard Company Memory controller with temperature sensors
US20040260957A1 (en) * 2003-06-20 2004-12-23 Jeddeloh Joseph M. System and method for selective memory module power management

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5091846A (en) * 1986-10-03 1992-02-25 Intergraph Corporation Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
US5155843A (en) * 1990-06-29 1992-10-13 Digital Equipment Corporation Error transition mode for multi-processor system
US5524212A (en) * 1992-04-27 1996-06-04 University Of Washington Multiprocessor system with write generate method for updating cache
EP0600626A1 (en) * 1992-11-13 1994-06-08 Cyrix Corporation Coherency for write-back cache in a system designed for write-through cache
US5347559A (en) 1992-12-30 1994-09-13 Digital Equipment Corporation Apparatus and method of data transfer between systems using different clocks
US5608892A (en) * 1995-06-09 1997-03-04 Alantec Corporation Active cache for a microprocessor
US5719800A (en) * 1995-06-30 1998-02-17 Intel Corporation Performance throttling to reduce IC power consumption
US5870616A (en) * 1996-10-04 1999-02-09 International Business Machines Corporation System and method for reducing power consumption in an electronic circuit
US6029006A (en) * 1996-12-23 2000-02-22 Motorola, Inc. Data processor with circuit for regulating instruction throughput while powered and method of operation
US5974438A (en) * 1996-12-31 1999-10-26 Compaq Computer Corporation Scoreboard for cached multi-thread processes
US6088799A (en) * 1997-12-11 2000-07-11 International Business Machines Corporation Security method and system for persistent storage and communications on computer network systems and computer network systems employing the same
US6470289B1 (en) * 1999-08-05 2002-10-22 Compaq Information Technologies Group, L.P. Independently controlling passive and active cooling in a computer system
US6108266A (en) 1999-10-28 2000-08-22 Motorola, Inc. Memory utilizing a programmable delay to control address buffers
EP1182552A3 (en) 2000-08-21 2003-10-01 Texas Instruments France Dynamic hardware configuration for energy management systems using task attributes
US6725342B1 (en) * 2000-09-26 2004-04-20 Intel Corporation Non-volatile mass storage cache coherency apparatus
US6662136B2 (en) * 2001-04-10 2003-12-09 International Business Machines Corporation Digital temperature sensor (DTS) system to monitor temperature in a memory subsystem
US6711512B2 (en) 2001-08-07 2004-03-23 Korea Electric Power Data Network Co. Ltd. Pole transformer load monitoring system using wireless internet network
US6970985B2 (en) * 2002-07-09 2005-11-29 Bluerisc Inc. Statically speculative memory accessing
CN100585730C (en) * 2002-09-11 2010-01-27 薄膜电子有限公司 Method for operating a ferroelectric of electret memory device, and a device of this kind

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5598395A (en) * 1993-11-02 1997-01-28 Olympus Optical Co., Ltd. Data loss prevention in a cache memory when the temperature of an optical recording medium is abnormal
US5737748A (en) * 1995-03-15 1998-04-07 Texas Instruments Incorporated Microprocessor unit having a first level write-through cache memory and a smaller second-level write-back cache memory
US5815648A (en) * 1995-11-14 1998-09-29 Eccs, Inc. Apparatus and method for changing the cache mode dynamically in a storage array system
US5761705A (en) * 1996-04-04 1998-06-02 Symbios, Inc. Methods and structure for maintaining cache consistency in a RAID controller having redundant caches
US5956289A (en) * 1997-06-17 1999-09-21 Micron Technology, Inc. Clock signal from an adjustable oscillator for an integrated circuit
US5996289A (en) * 1998-04-23 1999-12-07 Building Materials Corporation Of America Soffit vent
US6438647B1 (en) * 2000-06-23 2002-08-20 International Business Machines Corporation Method and apparatus for providing battery-backed immediate write back cache for an array of disk drives in a computer system
US6564288B2 (en) * 2000-11-30 2003-05-13 Hewlett-Packard Company Memory controller with temperature sensors
US20040260957A1 (en) * 2003-06-20 2004-12-23 Jeddeloh Joseph M. System and method for selective memory module power management

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080010408A1 (en) * 2006-07-05 2008-01-10 International Business Machines Corporation Cache reconfiguration based on run-time performance data or software hint
US20080263278A1 (en) * 2006-07-05 2008-10-23 International Business Machines Corporation Cache reconfiguration based on run-time performance data or software hint
US7467280B2 (en) * 2006-07-05 2008-12-16 International Business Machines Corporation Method for reconfiguring cache memory based on at least analysis of heat generated during runtime, at least by associating an access bit with a cache line and associating a granularity bit with a cache line in level-2 cache
US7913041B2 (en) 2006-07-05 2011-03-22 International Business Machines Corporation Cache reconfiguration based on analyzing one or more characteristics of run-time performance data or software hint
US20110107032A1 (en) * 2006-07-05 2011-05-05 International Business Machines Corporation Cache reconfiguration based on run-time performance data or software hint
US8140764B2 (en) 2006-07-05 2012-03-20 International Business Machines Corporation System for reconfiguring cache memory having an access bit associated with a sector of a lower-level cache memory and a granularity bit associated with a sector of a higher-level cache memory
US20130176170A1 (en) * 2012-01-05 2013-07-11 Cambridge Silicon Radio Ltd. Reverse frequency and time aiding
US9151845B2 (en) * 2012-01-05 2015-10-06 Cambridge Silicon Radio Limited Reverse frequency and time aiding
US8612677B1 (en) 2012-07-26 2013-12-17 Kabushiki Kaisha Toshiba Memory system and method of writing data in a memory system

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JP3990439B2 (en) 2007-10-10 grant
US7233880B2 (en) 2007-06-19 grant
DE602004004414T2 (en) 2007-08-23 grant
US20050060126A1 (en) 2005-03-17 application
WO2005026965A1 (en) 2005-03-24 application
EP1668514B1 (en) 2007-01-17 grant
CN1849593A (en) 2006-10-18 application
KR20060063979A (en) 2006-06-12 application
KR100824476B1 (en) 2008-04-22 grant
DE602004004414D1 (en) 2007-03-08 grant
JP2007505406A (en) 2007-03-08 application
EP1668514A1 (en) 2006-06-14 application
CN100573475C (en) 2009-12-23 grant

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