US20060105572A1 - Via reactive ion etching process - Google Patents

Via reactive ion etching process Download PDF

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US20060105572A1
US20060105572A1 US10904533 US90453304A US2006105572A1 US 20060105572 A1 US20060105572 A1 US 20060105572A1 US 10904533 US10904533 US 10904533 US 90453304 A US90453304 A US 90453304A US 2006105572 A1 US2006105572 A1 US 2006105572A1
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sccm
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gas flow
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Peter Biolsi
Samuel Choi
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International Business Machines Corp
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International Business Machines Corp
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02057Cleaning during device manufacture
    • H01L21/0206Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching

Abstract

Methods of etching a dielectric layer and a cap layer over a conductor level to open a via to the conductor. The methods include the provision of tetrafluoro methane (CF4) in a photoresist strip. In addition, the methods may provide an increased amount of tetrafluoro methane (CF4) in a dielectric layer etch, and trifluoro methane (CHF3) in a cap layer etch. The invention provides higher yield, more predictable etch rates, faster processing, and removes the need for an ash step.

Description

    TECHNICAL FIELD
  • The present invention relates generally to semiconductor fabrication, and more particularly, to a via reactive ion etching process.
  • RELATED ART
  • In the semiconductor industry, reactive ion etching (RIE) is used to open pathways for circuitry within a semiconductor chip. One structure formed using RIE is a via, which electrically connects conductors within different layers. RIE is a variation of plasma (gas) etching in which a semiconductor wafer is placed on a radio frequency (RF) powered electrode, and etching species are extracted and accelerated from the plasma toward the surface to be etched. A chemical etching reaction occurs which removes parts of the surface. RIE is one of the most common etching techniques in semiconductor manufacturing.
  • Referring to FIG. 1, a semiconductor structure 10 including large-via pad dielectric layers 12 prior to etching is shown. Structure 10 includes a conductor level 14 including a dielectric layer 16 (e.g., of silicon dioxide SiO2) surrounding conductor 18 (e.g., of copper Cu); a cap layer 20 (e.g., of silicon nitride Si3N4) atop conductor level 14; a dielectric layer 22 (e.g., of silicon dioxide SiO2); another dielectric layer 24 (e.g., of silicon nitride Si3N4); and a patterned photoresist 26. A typical large-via RIE process is conducted in a single plasma chamber capable of two RF settings, e.g., 2 MHz and 27 MHz. One conventional RIE process includes the following steps: etching of dielectric layer 24, etching dielectric layer 22 and stopping on cap layer 20 so as to not expose conductor 18, stripping photoresist 26, etching cap layer 20 to expose conductor 18, and finally, performing a nitrogen-hydrogen (N2H2) plasma chemistry (ash) to remove residual RIE polymers from conductor 18. More specifically, dielectric layer 22 etching may occur, for example, using the following conditions: 80 mTorr (mT) of pressure, an RF energy of 1800 watts (W) at 27 MHz and 600 W at 2 MHz, and a gas flow of 10 standard cubic centimeters per minute (sccm) of tetrafluoro methane (CF4), 220 sccm of carbon monoxide (CO) and 400 sccm of argon (Ar), resulting in an approximately 45 Ångstrom/second (Å/s) etch rate. The photoresist strip may use, for example, the following conditions in two stages including: 800 mT of pressure, an RF energy of 800 W at 27 MHz, and a gas flow of 1000 sccm of oxygen (O2), followed by 450 mT of pressure, 1200 W at 27 MHz and 200 W at 2 MHz, and a gas flow including 1000 sccm of oxygen (O2). The dielectric layer 20 etch may occur, for example, using the following conditions: 150 mT of pressure, an RF energy of 1000 W at 2 MHz and 1500 W at 27 MHz, and a gas flow of 100 sccm of oxygen (O2), 190 sccm tetrafluoro methane (CF4) and 400 sccm argon (Ar). The ash step may occur, for example, using the following conditions: 200 mT of pressure, an RF energy of 1200 W at 27 MHz, and a gas flow including 600 sccm nitrogen (N2) and 200 sccm hydrogen (H2).
  • The conventional RIE process suffers from a number of problems. First, conventional RIE techniques suffer from a low etch rate because the gas flow for the process is typically centered at the minimum operating range of a mass flow controller, which reduces yields. Second, typical plasma processes are susceptible to gas flow fluctuations, e.g., within a process chamber or between different equipment, which results in widely varying etch rates. Finally, with the movement of wafer fabrication facilities from the conventional 200 mm wafer to the larger 300 mm wafer, process cycle times of conventional RIE processes are considered too long. For example, large via (LV) pads are the final level of 300 mm wafer fabrication connecting the transistors to the wire bonds for the final electrical test. The via RIE process for LV pads typically takes approximately 5 minutes per wafer, which makes this step a target for improvement.
  • In view of the foregoing, there is a need in the art for an improved via RIE process that does not suffer from the problems of the related art.
  • SUMMARY OF THE INVENTION
  • The invention includes methods of etching a dielectric layer and a cap layer over a conductor level to open a via to the conductor. The methods include the provision of tetrafluoro methane (CF4) in a photoresist strip. In addition, the methods may provide an increased amount of tetrafluoro methane (CF4) in a dielectric layer etch, and trifluoro methane (CHF3) in a cap layer etch. The invention provides higher yield, more predictable etch rates, faster processing, and removes the need for an ash step.
  • A first aspect of the invention is directed to a method of etching a dielectric layer and a cap layer over a conductor level to open a via to the conductor, a pattern for the via being provided by a photoresist, the method comprising the steps of: etching the via through the dielectric layer; stripping the photoresist using a plasma chemistry including tetrafluoro methane (CF4); and etching the cap layer to open the via to the conductor.
  • A second aspect of the invention includes a method of etching a dielectric layer and a cap layer over a conductor level to open a via to the conductor, a pattern for the via being provided by a photoresist, the method consisting of the steps of: etching the via through the dielectric layer; stripping the photoresist using a plasma chemistry including tetrafluoro methane (CF4); and etching the cap layer to open the via to the conductor.
  • A third aspect of the invention relates to a method of etching a dielectric layer and a cap layer over a conductor level to open a via to the conductor, a pattern for the via being provided by a photoresist, the method comprising of the steps of: etching the via through the dielectric layer using approximately 80 mT of pressure, an RF energy of approximately 1200 W at 27 MHz and approximately 2700 W at 2 MHz, and a gas flow including tetrafluoro methane (CF4) and carbon monoxide (CO) in a gas flow ratio of no less than approximately 0.104 and no greater than approximately 0.2; stripping the photoresist using a plasma chemistry including tetrafluoro methane (CF4) using a gas flow of no less than approximately 7 standard cubic centimeters per minute (sccm) and no greater than approximately 15 sccm of the tetrafluoro methane (CF4); and etching the cap layer to open the via to the conductor using approximately 150 mT of pressure, an RF energy of approximately 1000 W at 2 MHz and approximately 1500 W at 27 MHz, and a gas flow including tetrafluoro methane (CF4) and trifluoro methane (CHF3) in a gas flow ratio of no less than approximately 2.33 and no greater than approximately 3.96.
  • A fourth aspect of the invention relates to a method of etching a first dielectric layer, a second dielectric layer and a cap layer over a conductor level to open a via to the conductor, a pattern for the via being provided by a photoresist, the method comprising the steps of: etching the via through the first dielectric layer; etching the via through the second dielectric layer; stripping the photoresist using a plasma chemistry including tetrafluoro methane (CF4); and etching the cap layer to open the via to the conductor.
  • The foregoing and other features of the invention will be apparent from the following more particular description of embodiments of the invention.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The embodiments of this invention will be described in detail, with reference to the following figures, wherein like designations denote like elements, and wherein:
  • FIG. 1 shows a conventional semiconductor structure including large-via pad dielectric layers prior to etching.
  • FIGS. 2-5 show a method of etching a via according to the invention.
  • FIG. 6 shows a semiconductor structure illustrating some of the problems solved by the invention.
  • DETAILED DESCRIPTION OF THE INVENTION
  • With reference to the accompanying drawings, FIG. 2-5 show a method of etching a dielectric layer and a cap layer over a conductor level to open a via to the conductor according to the invention. The method modifies the conventional process such that the process results in improved yields, more predictable etch rates and greatly reduced processing time. The process begins with a conventional semiconductor structure 10 including large-via pad dielectric layers 12, similar to that shown in FIG. 1. Structure 10 includes a conductor level 14 including a dielectric layer 16 (e.g., of silicon dioxide SiO2 or any other appropriate dielectric material) surrounding conductor 18 (e.g., of copper Cu); a cap layer 20 atop conductor level 14; a dielectric layer 22; another dielectric layer 24 (e.g., of silicon nitride Si3N4 or any other dielectric material); and a patterned photoresist 26. Patterned photoresist 26 includes a pattern (opening) for the via to be formed. Dielectric layer 22 may include any silicon dioxide (SiO2) type material such as hydrogenated silicon oxycarbide (SiCOH), CORAL™ available from Novellus, tetraethyl orthosilicate (Si(OC2H5)4)(TEOS), fluorine doped TEOS (FTEOS), fluorine doped silicate glass (FSG), undoped silicate glass (USG), boro-phospho-silicate glass (BPSG), etc. Cap layer 20 may include any typical cap material such as: high density plasma (HDP) silicon nitride, ultraviolet light transparent silicon nitride (UVN), silicon carbide (SiC), etc.
  • An initial step of the method includes, as shown in FIG. 2, etching through dielectric (e.g., silicon nitride) layer 24. Since the etch conditions 100 used may be any conventional method, this step is not considered an integral part of the invention in all cases.
  • Next, as shown in FIG. 3, the via is etched through dielectric layer 22. In one embodiment, etching recipe 104 includes using approximately 80 mTorr (mT) of pressure, and an RF energy of approximately 1200 watts (W) at 27 MHz and approximately 2700 W at 2 MHz, which represents an increase in RF energy compared to the conventional process. A gas flow for this embodiment includes tetrafluoro methane (CF4) and carbon monoxide (CO) in a gas flow ratio of approximately 0.104-0.200, and preferably about 0.136. Tetrafluoro methane (CF4) (also known as carbon tetrafluoride) is an etchant that etches practically all dielectrics, and is available, for example, under the brand name Freon® 14 from Dupont. In one embodiment, the gas flow includes approximately 25-40 sccm of tetrafluoro methane (CF4) (preferably about 30 sccm), and approximately 200-240 sccm of carbon monoxide (CO) (preferably about 220 sccm). In addition, the gas flow includes approximately 400 sccm of argon (Ar). This etch recipe 102 provides more than twice as fast an etch rate (i.e., approximately 95 Ångstroms/second (Å/s)) as the conventional process due to an increased amount of tetrafluoro methane (CF4). In addition, this etch recipe 102 is highly selective to cap layer 20, and causes no changes in the etch profile compared to the conventional process.
  • Referring to FIG. 4, a next step includes stripping the photoresist using a plasma chemistry 102 including tetrafluoro methane (CF4), which is not used in conventional stripping processes. In one embodiment, the photoresist stripping step includes two stages. A first stage uses approximately 120 mT of pressure, and an RF energy of approximately 1000 W at 27 MHz and approximately 200 W at 2 MHz. In one embodiment, a gas flow of approximately 900-1100 sccm of oxygen (O2) (preferably about 1000 sccm) is used in the first stage. A second stage uses approximately 400 mT of pressure, and an RF energy of approximately 1600 W at 2 MHz. A gas flow of the second stage includes tetrafluoro methane (CF4) and oxygen (O2) in a gas flow ratio of approximately 0.006-0.016, and preferably about 0.010. During the second stage, the tetrafluoro methane (CF4) may be provided at approximately 7-15 sccm (preferably about 10 sccm), and the oxygen (O2) may be provided at approximately 900-1100 sccm (preferably about 1000 sccm).
  • The photoresist strip step according to the invention adds tetrafluoro methane (CF4) gas to remove photoresist polymer 134 (FIG. 6) left behind from the high RF energy used during the dielectric etching 100 (FIG. 3). Contrary to expectations, however, the addition of tetrafluoro methane (CF4) does not etch cap layer 20 sufficiently to cause exposure of conductor 18, and does not affect the etch profile. In particular, a low gas flow and duration provides enough tetrafluoro methane (CF4) to obtain a clean strip of the hardened photoresist polymer 134 (FIG. 6) while minimizing the etching of cap layer 20. More significantly, however, the addition of tetrafluoro methane (CF4) cuts the etching time in approximately half compared to the conventional process, which greatly increases the overall speed of the via RIE process. In particular, this stage may last approximately 10-15 seconds, which is significantly shorter than the conventional process, which typically lasts 20-30 seconds. Another advantage of the tetrafluoro methane (CF4) usage is that it removes residual polymer created by the oxygen (O2) etch (FIG. 3), and leaves a clean cap layer 20 surface after photoresist strip. As shown in FIG. 6, the oxygen (O2) etch with such a high RF energy tends leave photoresist 26 (FIG. 3) harder than in conventional RIE processes, which causes increased residual photoresist polymer 134, e.g., carbon mixed with oxide. However, the tetrafluoro methane (CF4) removes this residual polymer.
  • Referring to FIG. 5, the next step includes etching cap layer 20 to open the via to conductor 18. In one embodiment, the cap layer etching step includes an etch recipe 106 using approximately 150 mT of pressure, and an RF energy of approximately 1000 W at 2 MHz and approximately 1500 W at 27 MHz. A gas flow includes tetrafluoro methane (CF4) and trifluoro methane (CHF3) in a gas flow ratio of approximately 2.33-3.96. Trifluoro methane (CHF3) (also known as fluoroform) is available, for example, under trade name Freon® 23 from Dupont. The addition of trifluoro methane (CHF3) is presented in this step to improve sidewall profile striations, which would lead to higher contact resistance. In one embodiment, the gas flow includes approximately 80-110 sccm of oxygen (O2) (preferably about 100 sccm), approximately 170-210 sccm of the tetrafluoro methane (CF4) (preferably about 190 sccm), and approximately 53-73 sccm of the trifluoro methane (CHF3) (preferably about 63 sccm). The gas flow also includes approximately 400 sccm of argon (Ar).
  • With further regard to the cap layer etching step, for certain types of vias, the thickness of cap layer 20 may be thicker than in other via pad dielectric stacks. For instance, the above values are optimal for a cap layer 20 having a thickness of approximately 800-1200 Å, i.e., about 1000 Å, of, for example, silicon nitride. However, thicker cap layers 120 of, for example, silicon nitride, such as shown in FIG. 6, are subject to undercutting 130 and metal oxidation 132 that lead to higher contact resistance when the above-described amount of oxygen (O2) is used. To address this situation, in an alternative embodiment, the gas flow includes the same gases and rates as described above, except the amount of oxygen (O2) is reduced by a factor of approximately 10, which prevents the undercutting. In one embodiment, the amount of oxygen is approximately 7-13 sccm, and is preferably about 10 sccm. This amount of oxygen (O2) has been found sufficient for cap layers 120 (FIG. 6) having a thickness of approximately 2500-3500 Å, i.e., about 3000 Å, of, for example, silicon nitride. In particular, the given oxygen gas flow results in no lateral undercut 130 (FIG. 6), minimal metal oxidation 134 (FIG. 6), and does not compromise etching time. Further decrease in oxygen gas, however, results in a dramatic drop in etch rate.
  • The above-described method also reduces processing time by eliminating the need for a nitrogen-hydrogen plasma chemistry (ash) step as in conventional via RIE processing. This saves approximately 45 seconds per wafer. The invention also attains required wall profile angle, provides high selectivity of dielectric layer 22 etching chemistry 104 to cap layer 20, and minimal oxidation of a surface of metal 18. The invention can be applied to any large via pads requiring high etching selectivity to a cap layer 20, minimal cap layer 20 undercutting, and reduced metal oxidation. The invention provides higher yield, more predictable etch rates, and faster processing, and removes the need for an ash step.
  • The following table summarizes the RIE etch parameters for a preferred embodiment:
    Cap Layer Cap Layer
    Dielectric Photoresist Photoresist 20 120
    Layer 22 Stage 1 Stage 2 (˜1000 Å) (˜3000 Å)
    Pressure (mT) 80 120 400 150 150
    RF energy (W)
    27 MHz 1200 1000 0 1500 1500
    2 MHz 2700 200 1600 1000 1000
    Gas Flow (sccm)
    CH4 25-40 0 7-15 170-210 170-210
    CHF3 0 0 0 53-73 53-73
    CO 200-240 0 0 0 0
    O2 0 900-1100 900-1100  80-110  7-13
    Ar 400 0 0 400 400
    Gas Flow Ratios:
    CF4/CO 0.104-0.200
    CF4/O2 0.006-0.0160
    CF4/CHF3 2.33-3.96 2.33-3.96
  • While this invention has been described in conjunction with the specific embodiments outlined above, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, the embodiments of the invention as set forth above are intended to be illustrative, not limiting. Various changes may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims (28)

  1. 1. (canceled)
  2. 2. A method of etching a dielectric layer and a cap layer over a conductor level to open a via to a conductor, a pattern for the via being provided by a photoresist, the method comprising the steps of:
    etching the via through the dielectric layer;
    stripping the photoresist using a plasma chemistry including tetrafluoro methane (CF4); and
    etching the cap layer to open the via to the conductor;
    wherein the dielectric layer etching step includes using approximately 80 mT of pressure, an RF energy of approximately 1200 W at 27 MHz and approximately 2700 W at 2 MHz, and a gas flow including tetrafluoro methane (CF4) and carbon monoxide (CO) in a gas flow ratio of no less than approximately 0.104 and no greater than approximately 0.2.
  3. 3. The method of claim 2, wherein the gas flow during the dielectric layer etching step includes no less than approximately 25 and no greater than approximately 40 standard cubic centimeters per minute (sccm) of tetrafluoro methane (CF4), no less than approximately 200 and no greater than approximately 240 sccm of carbon monoxide (CO), and approximately 400 sccm of argon (Ar).
  4. 4. The method of claim 2, wherein the dielectric layer etching step has an etch rate of approximately 95 Ångstroms/second (Å/s).
  5. 5. The method of claim 2, wherein the photoresist stripping step includes using a gas flow of no less than approximately 7 standard cubic centimeters per minute (sccm) and no greater than approximately 15 scam of the tetrafluoro methane (CF4).
  6. 6. A method of etching a dielectric layer and a cap layer over a conductor level to open a via to a conductor, a pattern for the via being provided by a photoresist, the method comprising the steps of:
    etching the via through the dielectric layer;
    stripping the photoresist using a plasma chemistry including tetrafluoro methane (CF4); and
    etching the cap layer to open the via to die conductor;
    wherein the photoresist stripping step includes two stages including:
    a first stage using approximately 120 mT of pressure, an RF energy of approximately 1000 W at 27 MHz and approximately 200 W at 2 MHz, and a gas flow including oxygen (O2); and
    a second stage using approximately 400 mT of pressure, an RF energy of approximately 1600 W at 2 MHz, and a gas flow including the tetrafluoro methane (CF4) and oxygen (O2) in a gas flow ratio no less than approximately 0.006 and no greater than, approximately 0.016.
  7. 7. The method of claim 6, wherein the gas flow of the first stage includes no less than approximately 900 standard cubic centimeters per minute (sccm) and no greater than approximately 1100 sccm of the oxygen O2.
  8. 8. The method of claim 6, wherein the gas flow of the second stage includes no less than approximately 7 standard cubic centimeters per minute (sccm) and no greater than approximately 15 sccm of the tetrafluoro methane (CF4), and no less than approximately 900 sccm and no greater than approximately 1100 sccm of the oxygen (O2).
  9. 9. The method of claim 6, wherein the cap layer etching step includes using approximately 150 mT of pressure, an RF energy of approximately 1000 W at 2 MHz and approximately 1500 W at 27 MHz, and a gas flow including tetrafluoro methane (CF4) and trifluoro methane (CHF3) in a gas flow ratio of no less than approximately 2.33 and no greater than approximately 3.96.
  10. 10. The method of claim 9, wherein, in the case that the cap layer has a thickness of no less than approximately 800 Å and no greater than 1200 Å, the cap layer etching step gas flow includes no less than approximately 80 and no greater than approximately 110 standard cubic centimeters per minute (sccm) of oxygen (O2), no less than approximately 170 and no greater than approximately 210 sccm of tetrafluoro methane (CF4), no less than approximately 53 and no greater than approximately 73 scam of trifluoro methane (CHF3), and approximately 400 sccm of argon (Ar).
  11. 11. The method of claim 9, wherein, in the case that the cap layer has a thickness of no less than approximately 2500 Å and no greater than 3500 Å, the cap layer etching step gas flow includes no less than approximately 7 and no greater than approximately 13 standard cubic centimeters per minute (sccm) of oxygen (O2), no less than approximately 170 and no greater than approximately 210 sccm of tetrafluoro methane (CF4), no less than approximately 53 and no greater than approximately 73 sccm of trifluoro methane (CHF3), and approximately 400 sccm of argon (Ar).
  12. 12. (canceled)
  13. 13. A method of etching a dielectric layer and a cap layer over a conductor level to open a via to a conductor, a pattern for the via being provided by a photoresist, the method consisting of the steps of:
    etching the via through the dielectric layer;
    stripping the photoresist using a plasma chemistry including tetrafluoro methane (CF4); and
    etching the cap layer to open the via to the conductor;
    wherein the dielectric layer etching step includes using approximately 80 mT of pressure, an RF energy of approximately 1200 W at 27 MHz and approximately 2700 W at 2 MHz, and a gas flow including tetrafluoro methane (CF4) and carbon monoxide (CO) in a gas flow ratio of no less than approximately 0.104 and no greater than approximately 0.2.
  14. 14. The method of claim 13, wherein the gas flow during the dielectric layer etching step includes no less than approximately 25 and no greater than approximately 40 standard cubic centimeters per minute (sccm) of tetrafluoro methane (CF4), no less than approximately 200 and no greater than approximately 240 sccm of carbon monoxide (CO), and approximately 400 sccm of argon (Ar).
  15. 15. The method of claim 13, wherein the photoresist stripping step includes using a gas flow of no less than approximately 7 standard cubic centimeters per minute (scam) and no greater than approximately 15 sccm of the tetrafluoro methane (CF4).
  16. 16. The method of claim 13, wherein the photoresist stripping step includes two stages including:
    a first stage using approximately 120 mT of pressure, an RE energy of approximately 1000 W at 27 MHz and approximately 200 W at 2 MHz, and a gas flow including oxygen (O2); and
    a second stage using approximately 400 mT of pressure, an RF energy of approximately 1600 W at 2 MHz, and a gas flow including the tetrafluoro methane (CF4) and oxygen (O2) in a gas flow ratio no less than approximately 0.006 and no greater than approximately 0.016.
  17. 17. The method of claim 16, wherein the gas flow of the first stage includes no less than approximately 900 standard cubic centimeters per minute (sccm) and no greater than approximately 1100 sccm of the oxygen (O2).
  18. 18. The method of claim 16, wherein the gas flow of the second stage includes no less than approximately 7 sccm and no greater than approximately 15 sccm of the tetrafluoro methane (CF4), and no less than approximately 900 sccm and no greater than approximately 1100 scam of the oxygen (O2).
  19. 19. The method of claim 13, wherein the cap layer etching step includes using approximately 150 mT of pressure, an RF energy of approximately 1000 W at 2 MHz and approximately 1500 W at 27 MHz, and a gas flow including tetrafluoro methane (CF4) and trifluoro methane (CHF3) in a gas flow ratio of no less than approximately 2.33 and no greater than approximately 3.96.
  20. 20. The method of claim 19, wherein, in the case that the cap layer has a thickness of no less than approximately 800 Å and no greater than 1200 Å, the cap layer etching step gas flow includes no less than approximately 80 and no greater than approximately 110 standard cubic centimeters per minute (sccm) of oxygen (O2), no less than approximately 170 and no greater than approximately 210 sccm of tetrafluoro methane (CF4), no less than approximately 53 and no greater than approximately 73 sccm of trifluoro methane (CHF3), and approximately 400 sccm of argon (Ar).
  21. 21. The method of claim 19, wherein, in the case that the cap layer has a thickness of no less than approximately 2500 Å and no greater than 3500 Å, the cap layer etching step gas flow includes no less than approximately 7 and no greater than approximately 13 standard cubic centimeters per minute (sccm) of oxygen (O2), no less than approximately 170 and no greater than approximately 210 scan of tetrafluoro methane (CF4), no less than approximately 53 and no greater than approximately 73 sccm of trifluoro methane (CHF3), and approximately 400 sccm of argon (Ar).
  22. 22. A method of etching a dielectric layer and a cap layer over a conductor level to open a via to a conductor, a pattern for the via being provided by a photoresist, the method comprising of the steps of:
    etching the via through the dielectric layer using approximately 80 mT of pressure, an RF energy of approximately 1200 W at 27 MHz and approximately 2700 W at 2 MHz, and a gas flow including tetrafluoro methane (CF4) and carbon monoxide (CO) in a gas flow ratio of no less than approximately 0.104 and no greater than approximately 0.2;
    stripping the photoresist using a plasma chemistry including tetrafluoro methane (CF4) using a gas flow of no less than approximately 7 standard cubic centimeters per minute (sccm) and no greater than approximately 15 sccm of the tetrafluoro methane (CF4); and
    etching the cap layer to open the via to the conductor using approximately 150 mT of pressure, an RF energy of approximately 1000 W at 2 MHz and approximately 1500 W at 27 MHz, and a gas flow including tetrafluoro methane (CF4) and trifluoro methane (CHF3) in a gas flow ratio of no less than approximately 2.33 and no greater than approximately 3.96.
  23. 23. The method of claim 22, wherein the gas flow the dielectric layer etching step includes no less than approximately 25 and no greater than approximately 40 standard cubic centimeters per minute (sccm) of tetrafluoro methane (CF4), no less than approximately 200 and no greater than approximately 240 sccm of carbon monoxide (CO), and approximately 400 sccm of argon (Ar).
  24. 24. The method of claim 22, wherein die photoresist stripping step includes two stages including:
    a first stage using approximately 120 mT of pressure, an RF energy of approximately 1000 W at 27 MHz and approximately 200 W at 2 MHz, and a gas flow of no less than approximately 900 standard cubic centimeters per minute (sccm) and no greater than approximately 1100 sccm of oxygen (O2); and
    a second stage using approximately 400 mT of pressure, an RF energy of approximately 1600 W at 2 MHz, and a gas flow including the tetrafluoro methane (CF4) and oxygen (O2) in a gas flow ratio no less than approximately 0.006 and no greater than approximately 0.016.
  25. 25. The method of claim 24, wherein the gas flow of the second stage includes no less than approximately 900 sccm and no greater than approximately 1100 sccm of the oxygen (O2).
  26. 26. The method of claim 22, wherein, in the case that the cap layer has a thickness of no less than approximately 800 Å and no greater than 1200 Å, the cap layer etching step gas flow includes no less than approximately 80 and no greater than approximately 110 standard cubic centimeters per minute (sccm) of oxygen (O2), no less than approximately 170 and no greater than approximately 21.0 sccm of tetrafluoro methane (CF4), no less than approximately 53 and no greater than approximately 73 sccm of trifluoro methane (CHF3), and approximately 400 sccm of argon (Ar).
  27. 27. The method of claim 22, wherein, in the case that the cap layer has a thickness of no less than approximately 2500 Å and no greater than 3500 Å, the cap layer etching step gas flow includes no less than approximately 7 and no greater than approximately 13 standard cubic centimeters per minute (sccm) of oxygen (O2), no less than approximately 170 and no greater than approximately 210 sccm of tetrafluoro methane (CF4), no less than approximately 53 and no greater than approximately 73 sccm of trifluoro methane (CHF3), and approximately 400 sccm of argon (Ar).
  28. 28-30. (canceled)
US10904533 2004-11-15 2004-11-15 Via reactive ion etching process Expired - Fee Related US7045464B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7470616B1 (en) 2008-05-15 2008-12-30 International Business Machines Corporation Damascene wiring fabrication methods incorporating dielectric cap etch process with hard mask retention

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100617056B1 (en) * 2004-12-30 2006-08-30 동부일렉트로닉스 주식회사 The method for preventing attack during via etching
US7510965B2 (en) * 2006-11-30 2009-03-31 United Microelectronics Corp. Method for fabricating a dual damascene structure
CN100517604C (en) 2006-12-05 2009-07-22 中芯国际集成电路制造(上海)有限公司 Through hole etching method
CN103107090B (en) * 2011-11-14 2016-04-06 中芯国际集成电路制造(上海)有限公司 The method of manufacturing a semiconductor device
CN103681462B (en) * 2012-09-12 2017-08-01 中芯国际集成电路制造(上海)有限公司 A method of manufacturing a semiconductor device
US20170316981A1 (en) * 2016-04-28 2017-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Method of Manufacture

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5221424A (en) * 1991-11-21 1993-06-22 Applied Materials, Inc. Method for removal of photoresist over metal which also removes or inactivates corosion-forming materials remaining from previous metal etch
US5445710A (en) * 1991-01-22 1995-08-29 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US6325861B1 (en) * 1998-09-18 2001-12-04 Applied Materials, Inc. Method for etching and cleaning a substrate
US6376384B1 (en) * 2000-04-24 2002-04-23 Vanguard International Semiconductor Corporation Multiple etch contact etching method incorporating post contact etch etching
US20040198062A1 (en) * 2003-04-07 2004-10-07 Applied Materials, Inc. Method of fabricating a dual damascene interconnect structure
US6838300B2 (en) * 2003-02-04 2005-01-04 Texas Instruments Incorporated Chemical treatment of low-k dielectric films
US20050059234A1 (en) * 2003-09-16 2005-03-17 Applied Materials, Inc. Method of fabricating a dual damascene interconnect structure
US6893973B2 (en) * 1999-12-21 2005-05-17 Nec Electronics Corporation Method of etching silicon nitride film and method of producing semiconductor device
US6897159B1 (en) * 2003-11-28 2005-05-24 Hynix Semiconductor Inc. Method for fabricating semiconductor device

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5445710A (en) * 1991-01-22 1995-08-29 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US5221424A (en) * 1991-11-21 1993-06-22 Applied Materials, Inc. Method for removal of photoresist over metal which also removes or inactivates corosion-forming materials remaining from previous metal etch
US6325861B1 (en) * 1998-09-18 2001-12-04 Applied Materials, Inc. Method for etching and cleaning a substrate
US6893973B2 (en) * 1999-12-21 2005-05-17 Nec Electronics Corporation Method of etching silicon nitride film and method of producing semiconductor device
US6376384B1 (en) * 2000-04-24 2002-04-23 Vanguard International Semiconductor Corporation Multiple etch contact etching method incorporating post contact etch etching
US6838300B2 (en) * 2003-02-04 2005-01-04 Texas Instruments Incorporated Chemical treatment of low-k dielectric films
US20040198062A1 (en) * 2003-04-07 2004-10-07 Applied Materials, Inc. Method of fabricating a dual damascene interconnect structure
US20050059234A1 (en) * 2003-09-16 2005-03-17 Applied Materials, Inc. Method of fabricating a dual damascene interconnect structure
US6897159B1 (en) * 2003-11-28 2005-05-24 Hynix Semiconductor Inc. Method for fabricating semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7470616B1 (en) 2008-05-15 2008-12-30 International Business Machines Corporation Damascene wiring fabrication methods incorporating dielectric cap etch process with hard mask retention
US20090283912A1 (en) * 2008-05-15 2009-11-19 Akinmade-Yusuff Hakeem B S Damascene wiring fabrication methods incorporating dielectric cap etch process with hard mask retention

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