US20060094252A1 - Methods to form electronic devices and methods to form a material over a semiconductive substrate - Google Patents

Methods to form electronic devices and methods to form a material over a semiconductive substrate Download PDF

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US20060094252A1
US20060094252A1 US11304397 US30439705A US2006094252A1 US 20060094252 A1 US20060094252 A1 US 20060094252A1 US 11304397 US11304397 US 11304397 US 30439705 A US30439705 A US 30439705A US 2006094252 A1 US2006094252 A1 US 2006094252A1
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reactor
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chemical vapor
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Randhir Thakur
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Thakur Randhir P
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/314Inorganic layers
    • H01L21/3143Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3145Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers formed by deposition from a gas or vapour
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34Nitrides
    • C23C16/345Silicon nitride
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/314Inorganic layers
    • H01L21/3143Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3144Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/314Inorganic layers
    • H01L21/318Inorganic layers composed of nitrides
    • H01L21/3185Inorganic layers composed of nitrides of siliconnitrides
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/1085Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto
    • H01L27/10852Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor extending over the access transistor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors

Abstract

A first electrode and a doped oxide layer laterally proximate thereof are provided over a substrate. A silicon nitride layer is formed over both the doped oxide layer and the first electrode to a thickness of no greater than 80 Angstroms over at least the first electrode by low pressure chemical vapor deposition using feed gases comprising a silicon hydride, H2 and ammonia. The substrate with silicon nitride layer is exposed to oxidizing conditions comprising at least 700° C. to form a silicon dioxide layer over the silicon nitride layer, with the thickness of silicon nitride over the doped oxide layer being sufficient to shield oxidizable substrate material beneath the doped oxide layer from oxidizing during the exposing. A second electrode is formed over the silicon dioxide layer and the first electrode. In one implementation, the chemical vapor depositing comprises feed gases of a silicon hydride and ammonia, with the depositing comprising increasing internal reactor temperature from below 500° C. to a maximum deposition temperature above 600° C. and starting feed of the silicon hydride into the reactor at a temperature less than or equal to 600° C. In one implementation the depositing comprises increasing internal reactor temperature from below 500° C. to a maximum deposition temperature above 600° C. using a temperature ramp rate of at least 10° C./minute from at least 500° C. to at least 600° C. Other aspects and implementations are described.

Description

    TECHNICAL FIELD
  • This invention relates to methods to form electronic devices, for example capacitors, antifuses, transistor gate and other constructions, and to methods to form a material over a semiconductive substrate.
  • BACKGROUND OF THE INVENTION
  • As the density of DRAM cells increases, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area. One principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. Yet as feature sizes continue to become smaller and smaller, development of improved materials for cell dielectrics as well as the cell design and structure become important. The feature size of higher density DRAMS, for example 256 Mb, will be on the order of 0.25 micron and less. Such overall reduction in cell size drives the thickness of the capacitor dielectric layer to smaller values, and conventional capacitor dielectric materials such as SiO2 and Si3N4 might become unsuitable. However it would be desirable to utilize silicon oxides and nitrides in spite of the reduced thicknesses due to the ease of use and available thorough understanding to integrate these materials in DRAM process flows. Yet processing associated with chemical vapor deposition of thin silicon nitride films in certain environments has also created other problems not directly associated with the capacitors.
  • For example, one prior art technique is the fabrication of stacked capacitors in a container shape within a borophosphosilicate glass layer (BPSG) to form the storage capacitors in DRAM circuitry. Here, a container opening is formed in a planarized layer of BPSG over a desired node location, typically in the form of a conductive polysilicon plug. The conductive electrode material is deposited to less than completely fill the opening, and then is typically chemical-mechanically polished back to provide a storage node electrode inside of the BPSG opening in the shape of a cup or container. Capacitor dielectric material is then provided over the storage node container, followed by deposition of a conductive cell plate layer which is subsequently patterned.
  • As circuitry integration and density increases, the corresponding dimensions and thicknesses of the various components also decreases. A typical capacitor dielectric layer in the above construction comprises a silicon dioxide/silicon nitride/silicon dioxide composite (ONO). The first oxide layer formed over the storage node electrode is typically native oxide formed by exposure of the exposed storage node material to ambient air. Silicon nitride is next chemical vapor deposited, for example utilizing a silicon hydride such as dichlorosilane and ammonia. Typical deposition conditions are at sub-Torr pressures and temperatures at or above 680° C., more typically above 700° C. The deposition process and the very thin nature of the typically deposited silicon nitride layer results in pin holes or other defects in the deposited layer. This is typically cured by a dense re-oxidation process which forms the outer silicon dioxide layer of the ONO construction. The prior art re-oxidation conditions for forming this outer oxide layer are conducted wet or dry at a temperature of from 800° C. to 950° C. at atmospheric pressure for from 5 to 30 minutes. Subsequently, a conductive cell plate layer is deposited and patterned over the ONO dielectric layer(s).
  • However as the nitride thickness of the ONO construction over the storage node electrode fell to below 80 Angstroms, it was discovered that the underlying bulk silicon substrate was oxidizing to the point of circuit destruction. BPSG is known to be extremely diffusive to oxidizing components during the above-described re-oxidation conditions. Silicon nitride, on the other hand, is known to form a good barrier layer to diffusion of such oxidizing gases under such conditions. Yet, the silicon nitride deposited over the BPSG in conjunction with the capacitor dielectric layer formation was apparently inadequate in shielding oxidation of substrate material underlying the BPSG when the deposited silicon nitride layer thickness for the capacitors fell below 80 Angstroms.
  • The invention was principally motivated with respect to overcoming this problem to enable silicon nitride to continue to be utilized as a capacitor dielectric layer where its thickness fell to below 80 Angstroms in deposition also occurring over a doped oxide layer, such as BPSG.
  • SUMMARY OF THE INVENTION
  • The invention comprises forming electronic devices, such as capacitors, antifuses, transistor gate and other constructions, and to methods of forming a material over a semiconductive substrate. In but one implementation, a first electrode and a doped oxide layer laterally proximate thereof are provided over a substrate. A silicon nitride layer is formed over both the doped oxide layer and the first electrode to a thickness of no greater than 80 Angstroms over at least the first electrode by low pressure chemical vapor deposition using feed gases comprising a silicon hydride, H2 and ammonia. The substrate with silicon nitride layer is exposed to oxidizing conditions comprising at least 700° C. to form a silicon dioxide layer over the silicon nitride layer, with the thickness of silicon nitride over the doped oxide layer being sufficient to shield oxidizable substrate material beneath the doped oxide layer from oxidizing during the exposing. A second electrode is formed over the silicon dioxide layer and the first electrode.
  • In one implementation, the chemical vapor depositing comprises feed gases of a silicon hydride and ammonia, with the depositing comprising increasing internal reactor temperature from below 500° C. to a maximum deposition temperature above 600° C. and starting feed of the silicon hydride into the reactor at a temperature less than or equal to 600° C. In one implementation the depositing comprises increasing internal reactor temperature from below 500° C. to a maximum deposition temperature above 600° C. using a temperature ramp rate of at least 500° C./minute from at least 500° C. to at least 600° C. In preferred implementations, the substrate is rotating during deposition, with the depositing comprising increasing internal reactor temperature from below 500° C. to a maximum deposition temperature above 600° C. and starting the substrate to rotate prior to reaching the maximum deposition temperature. In one implementation, rotation rate of the substrate is reduced upon substantially ceasing flow of at least one reactant gas to the reactor. In one implementation, rotation rate of the substrate is reduced within 1 minute of substantially ceasing flow of the at least one reactant gas to the reactor.
  • In one implementation, an inert cooling gas is flowed through a chemical vapor deposition reactor to cool a substrate and deposited material after the deposition.
  • In one implementation, a doped oxide layer is provided over a substrate. The doped oxide layer is chemical-mechanical polished. After the chemical-mechanical polishing, the doped oxide layer is caused to flow in a process comprising at least two steps. A prior in time of the steps comprises an inert atmosphere at a temperature of at least about 700° C. A later in time of the steps comprises an ammonia comprising atmosphere at a temperature of at least about 700° C. and forms a silicon nitride layer over the doped oxide layer.
  • Other aspects and implementations are described below.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
  • FIG. 1 is a diagrammatic view of a semiconductor wafer fragment at one processing step in accordance with the invention.
  • FIG. 2 is a view of the FIG. 1 wafer at a processing step subsequent to that depicted by FIG. 1.
  • FIG. 3 is a view of the FIG. 1 wafer at a processing step subsequent to that depicted by FIG. 2.
  • FIG. 4 is a view of the FIG. 1 wafer at a processing step subsequent to that depicted by FIG. 3.
  • FIG. 5 is a view of the FIG. 1 wafer at a processing step subsequent to that depicted by FIG. 4.
  • FIG. 6 is a diagrammatic depiction of a hot wall, vertical chemical vapor deposition reactor usable in a process in accordance with the invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws to promote the progress of science and useful arts' (Article 1, Section 8).
  • It has been recognized that the chemical vapor deposition of silicon nitride utilizing silicon hydride gases and ammonia occurs at different rates over the storage node electrode of a DRAM capacitor (including any thin oxide formed thereover) and doped oxides. Specifically, such deposition of silicon nitride is largely selective to the storage node (typically polysilicon), and regardless is at a considerably greater growth rate than what occurs over the BPSG or other doped oxide layers. Accordingly, as the silicon nitride layer thickness over the storage node fell to below 80 Angstroms, an apparent lesser quantity growing over the doped oxide layer resulted in a layer too thin to achieve the barrier layer effect during the subsequent re-oxidation to form the outer oxide layer of the capacitor dielectric ONO composite. Several processing solutions in accordance with the invention have been developed.
  • Referring to FIG. 1, a semiconductor wafer fragment or substrate is indicated generally with reference numeral 10. To aid in interpretation of the claims that follow, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
  • Fragment 10 comprises a bulk monocrystalline silicon substrate 12 having a diffusion region 14 formed therein. Field oxide region 16 and a gate oxide layer 18 are formed over bulk substrate 12. A pair of word lines 20 and 22 are formed on opposing sides of diffusion region 14. A conductive polysilicon plug 24 is provided over and in electrical connection with diffusion region 14. A layer 26 of doped oxide, preferably BPSG, is provided over the illustrated component, and formed to have a container storage node opening 28 provided therein over plug 24. A conductively doped, and preferably hemispherical grain, polysilicon layer has been formed over the substrate to within container opening 28. Such has been planarized back to form the illustrated isolated first capacitor electrode 30, with doped oxide layer 26 being positioned laterally proximate thereof.
  • Referring to FIG. 2, a silicon dioxide layer 32 can be formed on first capacitor electrode 30, such as by exposing the substrate to ambient air to form a native oxide layer or by CVD or other deposition. Regardless, an exemplary thickness for layer 32 is 20 Angstroms. A silicon nitride layer will subsequently be formed, as described below.
  • Referring to FIG. 3, a silicon nitride layer 34 is formed over both doped oxide layer 26 and first capacitor electrode 30 to a thickness of no greater than 80 Angstroms over at least first capacitor electrode 30. Several aspects and implementations for forming layer 34 are possible as described below. Various of the implementations could be utilized alone or in any combination with other implementations as will be appreciated by the artisan. Further, such can incorporate any of the methods and implementations described in U.S. patent application Ser. No. ______ by Randhir P. S. Thakur, entitled “Methods of Forming Electronic Devices” and filed commensurate with the filing of this application, and which is hereby incorporated by reference.
  • Provision of layer 34 preferably comprises chemical vapor deposition using feed gases comprising a silicon hydride and ammonia, and more preferably low pressure chemical vapor deposition which is substantially void of plasma. In the context of this document, “low pressure chemical vapor deposition” is intended to define any chemical vapor deposition process occurring at or below 700 Torr. Processing in accordance with the above identified application filed on the same date as this application, and in accordance with this application, is intended to result in less selectivity of the deposition between exposed polysilicon (or thin oxide formed thereover) and undoped oxide of layer 26. Accordingly, a suitably thick layer 34 is intended to be deposited over the doped oxide to effectively preclude oxidation of oxidizable material beneath layer 26 during a subsequent oxidation of the silicon nitride layer. Layer 34 will also typically deposit to a thickness of less than 80 Angstroms over doped oxide layer 26, and still perhaps to a thickness lower than the thickness of the silicon nitride layer deposited over first capacitor electrode 30. Further, silicon nitride layer formation over first capacitor electrode 30 can be to a thickness of no greater than 60 Angstroms in accordance with a desired capacitor construction.
  • As shown, first capacitor electrode 30 is not outwardly exposed during the formation of silicon nitride layer 34 thereover, rather being covered by oxide layer 32. Alternately and perhaps more preferred, first capacitor electrode 30 is void of layer 32, and is outwardly exposed during the formation of the silicon nitride layer 34 thereover, with the silicon nitride layer being formed on doped first capacitor electrode 30. Also as shown and preferred, the silicon nitride layer forms on the doped oxide layer as opposed to on any intervening layer.
  • In but one implementation for depositing silicon nitride layer 34, internal reactor temperature is increased from below 500° C. to some maximum deposition temperature above 600° C., with the starting of the feed of the silicon hydride into the reactor occurring at some temperature less than or equal to 600° C. Preferred pressure during processing is from 1000 to 2000 Torr, with the preferred maximum deposition temperature being 600° C. Typical prior art processing achieves a maximum deposition temperature of between 640° C. and 700° C., where ammonia flow is initially provided with the flow of dichlorosilane and does not occur until maximum deposition temperature is reached. Starting the feed of silicon hydride into the reactor at a temperature of less than or equal to about 600° C. in accordance with an aspect of the invention facilitates nitride layer deposition and reduction in the selectivity of such deposition relative to polysilicon or undoped oxide as compared to doped oxide layer 26. More preferably, feed of the silicon hydride into the reactor is started at a temperature of less than or equal to 550° C., with less than or equal to 500° C. being even more preferred. Ammonia feed to the reactor also preferably occurs at a temperature of less than or equal to 600° C. The temperature then preferably ramps continuously upward to achieve the maximum deposition temperature.
  • In one implementation, the depositing comprises increasing internal reactor temperature from below 500° C. to a maximum deposition temperature above 600° C. using a temperature ramp rate of greater than 10° C./min from at least 500° C. to at least 600° C. The temperature ramp rate is preferably no greater than 100° C./min from at least 500° C. to at least 600° C. Preferably, the temperature ramp rate of greater than 10° C./min starts from a temperature below 500° C. and continues to a temperature above 600° C., and more preferably continues until reaching the maximum deposition temperature. Prior art processing achieves a temperature ramp rate up to the maximum deposition temperature of between 8° C. to 10° C. per minute. Increasing the ramp rate above 10° C. achieves an unexpected result of less selectivity in the silicon nitride layer deposition, and achieving better radial uniformity across a wafer surface during the deposition.
  • In another implementation, the substrate is rotating during deposition and is started to rotate prior to reaching a maximum deposition temperature above 600° C. Preferably, the substrate is started to rotate prior to the reactor temperature reaching 600° C., and upon commencing initial feed of the silicon hydride to the reactor at below 600° C. A preferred wafer rotation speed is from 5 to 10 rpm. In the prior art deposition, wafer rotation wasn't commenced until achieving a maximum deposition temperature of at least 640° C. and immediately prior to or commensurate with reactant gas injection. Commencing rotation in accordance with this implementation of the invention achieves less selectivity in the deposition and more radial uniformity in the deposition across the substrate.
  • In another implementation, rotation rate of the substrate is reduced upon substantially ceasing flow of at least one of the silicon hydride and ammonia to the reactor at the substantial conclusion of the deposition. An example rotation rate range during depositing and after a speed reduction is from about 3 rpm to 15 rpm. The rotation rate is preferably reduced by at least 50% to 70% of that rate immediately prior to substantially ceasing flow of the at least one of the silicon hydride and ammonia to the reactor. Also preferably, the reducing is to some constant layer rate which is maintained for at least 1 to 2 minutes, such as during initial wafer cooling. The rotation rate is preferably reduced upon substantially ceasing flow of the silicon hydride to the reactor, which is also preferably commensurate with ceasing flow of the ammonia to the reactor.
  • In one implementation, rotation rate of the substrate is reduced within 1-2 minutes of substantially ceasing flow of at least one of the silicon hydride and ammonia to the reactor. More preferably, such rotation reduction occurs within 30 to 60 seconds of the flow stoppage. Reducing can occur before or after substantially ceasing flow of at least one of the reactant gases, and preferably occurs upon/commensurate with ceasing flow of at least one of the reactant gases as described above. The prior is understood to maintain a constant rotation rate of about 5 rpm upon reaching maximum deposition temperature and continuing such rate after ceasing flow of the reactant gases and throughout cooling of the wafers. Processing in accordance with the immediately above-described preferred implementations has the effect of improving 17 the radial uniformity across the wafer during deposition. Rotation facilitates control of depletion of the reactant species across the wafer and across the load.
  • In accordance with another implementation, low pressure chemical vapor deposition of layer 34 utilizes feed gases comprising a silicon hydride, H2 and ammonia. The H2 is preferably injected to within the reactor during the deposition as an N2/H2 mix. The H2 is preferably added in addition to existing preferred flows of ammonia and silane at a preferred 3:1 or greater volumetric ratio. The prior art has not provided a separate feed of H2 gas to the reactor. Provision of such in accordance with this implementation achieves less selectivity in the silicon nitride layer deposition and more radial uniformity in the deposition across the wafer.
  • A further considered deposition process for layer 35 is described with reference to FIG. 6. This depicts a vertical, hot wall chemical vapor deposition reactor 50 having a plurality of substrates 10 oriented horizontally therein. Chemical vapor depositing in accordance with this aspect of the invention comprises injecting silicon hydride to within the reactor at multiple spaced locations 52, positioned proximate spaced wafers of the plurality of wafers being deposited upon. Ammonia and H2 can also be injected from multiple locations, but are preferably injected to within the reactor at only single respective locations, as shown. The prior art processing and provision of dichlorosilane to the reactor in conjunction with the silicon nitride layer deposition having the problems to which this invention is directed to overcoming only provides silane injection at/from a single location at the bottom of the reactor. Provision of the less mobile silicon hydride from multiple spaced locations positioned proximate spaced wafers within the reactor has the effect of achieving less selectivity in the nitride layer deposition, and potentially more radial uniformity in the deposition across the wafer.
  • In accordance with another implementation, the doped oxide layer is caused to flow in a process comprising at least two steps. The flowing is preferably conducted after all chemical-mechanical polishing or other removal processes has occurred relative to the outermost surface of layer 26. A prior in time of the flowing steps comprises an inert atmosphere at a temperature of at least about 700° C. Preferred conditions are flowing N2 and/or Ar at a temperature of from about 950° C. to 1050° C. at atmospheric pressure for from about 10 to 30 seconds. A later in time of the steps comprises feeding ammonia at a temperature of at least 700° C. which forms a silicon nitride layer at least over doped oxide layer 26. Preferred temperature, pressure and time of processing conditions are as immediately described above with respect to the inert atmosphere. Such flow/reflow processing in accordance with the invention will either form a suitably thick silicon nitride layer to preclude oxidation of substrate material beneath oxide layer 26 during later processing, or at least form a suitably thick initiating seed layer for achieving a suitably thick silicon nitride layer by subsequent deposition for complete fabrication of silicon nitride layer 34. Flowing of doped oxide layer 26 might also be conducted prior to chemical-mechanical polishing or any other planarizing of the outer surface thereof.
  • In accordance with another implementation and at the conclusion of the deposition, an inert cooling gas is flowed through the reactor to cool the substrate and deposited material. Preferably, pressure within the reactor during such cooling is greater than one atmosphere. Prior art processes for cooling the wafers flow cooling gas externally of the reactor to cool the reactor walls, which ultimately results in wafer cooling. Flowing an inert cooling gas directly through the reactor to cool the substrate and deposited silicon nitride layer achieves more radial uniformity in such layer across the wafer.
  • Referring again to FIG. 4, the substrate is exposed to oxidizing conditions comprising at least 700° C. to form a silicon dioxide comprising layer 36 over silicon nitride layer 34. The thickness of silicon nitride layer 34 over doped oxide layer 26 is sufficient to shield oxidizable substrate material beneath doped oxide layer 26 (i.e., bulk substrate material 12) from oxidizing during the re-oxidation exposure. An example and preferred thickness for layer 36 is from 10 to 15 Angstroms on the nitride surface. Example wet oxidation conditions (i.e., in the presence of steam) or dry oxidation conditions (i.e., in the presence of oxygen) include exposure at from 800° C.-950° C. in an atmospheric furnace for from 5 to 30 minutes.
  • Referring to FIG. 5, a second capacitor electrode layer 38 (i.e., conductively doped polysilicon) is deposited and patterned to form a second capacitor electrode over silicon dioxide layer 36 and first capacitor electrode 30. Such provides but one example method in accordance with the invention for producing an adequately thick layer of silicon nitride over BPSG layer 26 in spite of thickness of such layer at least over storage node layer 30 being less than 80 Angstroms thick.
  • Again, the invention was principally motivated from problems associated with capacitor fabrication where silicon nitride layer thickness in an ONO construction fell below 80 Angstroms, with the substrate also comprising outwardly exposed boron and/or phosphorus doped silicate glass. Aspects of the invention are also believed applicable in fabrication of other electronic devices and materials, with the invention only being limited by the accompanying claims appropriately interpreted in accordance with the Doctrine of Equivalents. By way of example only, example alternate constructions include antifuses and transistor gates. For example, the invention contemplates fabrication of silicon nitride layers, such as described above, to comprise at least a portion of a dielectric layer separating two antifuse electrodes. Further, methods in accordance with the invention could also be utilized to fabricate gate dielectric layers, such as layer 18 of the FIGS. 1-13 above-described embodiments. Further, the invention contemplates processing of dielectric layers in the context of floating gate fabrication, with the subject dielectric layer forming either the typical top and/or bottom dielectric layer(s) utilized in floating gate constructions.
  • Further, the invention contemplates methods of forming electronic devices incorporating a high K dielectric layer construction. In the context of this document, “high K” is intended to define a dielectric layer having a dielectric constant K of at least 15. By way of example only, such materials include (Ba, Sr)TiO3, SrTiO3, (Pb, Zr)TiO3, Ta2O5, and Nb2O 5. Nitride layers formed in accordance with the invention, such as described above, can form useful passivation and other purpose layers when formed on high K dielectric layers utilized in electronic devices incorporating high K dielectric layers and another conductive component, such as for example capacitors in antifuse constructions.
  • Aspects of the invention are also contemplated outside of formation of electronic devices as described in the preferred embodiments above. Specifically, reducing rotation rate of the substrate upon substantially ceasing flow of one reactant gas into the reactor, or within 1 to 2 minutes of doing so, is usable in formation of various materials over semiconductor substrates by chemical vapor deposition. The same is also applicable to flowing of an inert cooling gas through the chemical vapor deposition reactor at the conclusion of deposition. Further, doped oxide flow or reflow in a layer comprising at least two steps as described above and claimed after chemical-mechanical-polishing is also contemplated outside of fabrication of an electronic device comprising two conductive electrodes having a silicon nitride layer positioned therebetween.
  • In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.

Claims (23)

  1. 1-47. (canceled)
  2. 48. A method of forming a material over a semiconductive substrate comprising:
    chemical vapor depositing a material over a semiconductive substrate within a reactor using at least one reactant gas while the substrate is rotating; and
    reducing rotation rate of the substrate upon substantially ceasing flow of the at least one reactant gas to the reactor.
  3. 49. The method of claim 48 wherein the chemical vapor depositing comprises low pressure chemical vapor deposition.
  4. 50. The method of claim 48 wherein the chemical vapor depositing comprises low pressure chemical vapor deposition void of plasma.
  5. 51. The method of claim 48 wherein the rotation rate is reduced by at least 50% of that immediately prior to substantially ceasing flow of the at least one reactant gas to the reactor.
  6. 52. The method of claim 48 wherein said reducing is to some constant lower rate which is maintained for at least 1 minute.
  7. 53. The method of claim 48 wherein flow of all reactant gases fed to the reactor is ceased at substantially the same time.
  8. 54-59. (canceled)
  9. 60. A method of forming a material over a semiconductive substrate comprising:
    chemical vapor depositing a material over a semiconductive substrate within a reactor using at least one reactant gas while the substrate is rotating; and
    reducing rotation rate of the substrate within 2 minutes of substantially ceasing flow of the at least one reactant gas to the reactor.
  10. 61. The method of claim 60 wherein the reducing occurs within 60 seconds of substantially ceasing flow of the at least one reactant gas to the reactor.
  11. 62. The method of claim 60 wherein the reducing occurs commensurate with or after substantially ceasing flow of the at least one reactant gas to the reactor.
  12. 63. The method of claim 60 wherein the reducing occurs after substantially ceasing flow of the at least one reactant gas to the reactor.
  13. 64. The method of claim 60 wherein the reducing occurs before substantially ceasing flow of the at least one reactant gas to the reactor.
  14. 65. The method of claim 60 wherein the rotation rate is reduced by at least 50% of that immediately prior to starting said reducing.
  15. 66. The method of claim 60 wherein said reducing is to some constant lower rate which is maintained for at least 1 minute.
  16. 67. The method of claim 60 wherein the reducing occurs commensurate with or after substantially ceasing flow of the at least one reactant gas to the reactor, and the reducing is to some constant lower rate which is maintained for at least 1 minute.
  17. 68. The method of claim 60 wherein the reducing occurs after substantially ceasing flow of the at least one reactant gas to the reactor, and the reducing is to some constant lower rate which is maintained for at least 1 minute.
  18. 69-76. (canceled)
  19. 77. A method of forming a material over a semiconductive substrate comprising:
    chemical vapor depositing a material over a semiconductive substrate within a reactor using at least one reactant gas; and
    flowing an inert cooling gas through the reactor to cool the substrate and deposited material.
  20. 78. The method of claim 77 wherein pressure within the reactor during the cooling is greater than 1 atmosphere.
  21. 79. The method of claim 77 wherein the chemical vapor depositing is low pressure chemical vapor deposition.
  22. 80. The method of claim 77 wherein the chemical vapor depositing is low pressure chemical vapor deposition, and pressure within the reactor during the cooling is greater than 1 atmosphere.
  23. 81-89. (canceled)
US11304397 1998-08-24 2005-12-14 Methods to form electronic devices and methods to form a material over a semiconductive substrate Abandoned US20060094252A1 (en)

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US20030113968A1 (en) 2003-06-19 application

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