US20060039203A1 - Register file apparatus and method incorporating read-after-write blocking using detection cells - Google Patents
Register file apparatus and method incorporating read-after-write blocking using detection cells Download PDFInfo
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- US20060039203A1 US20060039203A1 US10/922,247 US92224704A US2006039203A1 US 20060039203 A1 US20060039203 A1 US 20060039203A1 US 92224704 A US92224704 A US 92224704A US 2006039203 A1 US2006039203 A1 US 2006039203A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
Definitions
- the present invention relates generally to register file access control circuits, and more particularly to a register file having automatic read-after-write blocking.
- Register files are commonly used building blocks in digital circuits, particularly in processing system components where fast access to a fairly small quantity of data is required with low access latency. Examples of register file uses include register arrays in processors, cache directories in cache memories.
- register file cells are often written to and then read from within the same clock cycle.
- register files are almost always read immediately after a write in the same clock cycle.
- Such register files are in the critical path that determines processor speed and as such, the write to read delays are finely tuned to provide the best performance possible within clock skew variation, voltage variation, and other factors that could cause the reading of false or unstable data.
- Typical design margins for register file read-after-write timing may waste up to 30% of the clock cycle time by waiting until the write cycle is complete. But such margins are necessary within the typical ranges of the operational variables mentioned above and with current circuits used to implement register file cells and control logic.
- the objectives of improving register file performance and processor performance are achieved in a register file apparatus and method for operating a register file.
- One or more cells within the register file are dedicated to use as a detection mechanism for determining when the end of a write cycle has occurred.
- One cell may be used for the entire array, one cell may be assigned for each row in the register file array, or cells may be assigned for groups of rows.
- the detection cells may be connected so that the value of the cells alternates at each write operation and the value of an active detection cell is used to control logic that blocks a read to the register file row until the active detection cell changes state.
- the detection cells may be configured so that a first state is set prior to the commencement of the write cycle and then the detection cells are written with a value corresponding to the opposite state by the write.
- the indication of a detection cell state change can be used to truncate the leading edge of a next read strobe to the storage cells affected by the write, or may be used within the access control logic to delay generation of a read strobe that causes a read to the affected cells.
- FIG. 1 is a block diagram of a register file in accordance with an embodiment of the invention.
- FIG. 2A is a block diagram of a detection cell and associated control logic as may be used in the register file of FIG. 1 .
- FIG. 2B is a block diagram of another detection cell and associated control logic as may be used in the register file of FIG. 1 .
- FIG. 3 is a timing diagram depicting the relationship of signals within the register file of FIG. 1 .
- FIG. 4 is a block diagram depicting control logic within the register file of FIG. 1 , in accordance with an alternative embodiment of the present invention.
- FIG. 5 is a schematic depicting details of dynamic control logic as may be used in the circuit of FIG. 2B .
- FIG. 6 is a schematic depicting details of dynamic control logic as may be used in the circuit of FIG. 2A .
- FIG. 1 there is depicted a block diagram of a register file circuit embodying a method and an apparatus in accordance with the present invention.
- An array of storage cells 12 provide storage for words in rows aligned across the figure. Each bit in the words forms a column running up and down the figure.
- the physical layout of storage cells 12 generally mimics the layout depicted, but may vary, for example the rows may be partitioned into two or more units, in which case the layout of a portion of the row may mimic that portion of the drawing, but the overall layout of the register file may be split.
- Storage cells 12 are coupled to a control logic 10 that provides strobe signals that control the individual storage cells 12 in order to perform read and write functions to the registers (rows) within the register file.
- Control logic 10 also may be coupled to a scan logic 16 that provides testing capability for the register file circuit via generating special functional/scan clock relations to storage cells 12 and detection cells 14 .
- Data input and output buffers/latches 18 provide for input and output of data from storage cells 12 .
- the detection cells are used to provide a signal that indicates when all of storage cells 12 implicated in a given write operation have assumed the state directed by the data written to storage cells 12 .
- the detection is performed by using cells having characteristics matched to storage cells 12 so that over operational variations such as clock skew, power supply voltage, temperature variations and process variations, the delay between a write strobe and the actual change of data in storage cells 12 will be matched by the delay to produce a state change in detection cell(s) 14 (and/or 14 A and 14 Z).
- Detection cells 14 represent a physical and logical arrangement wherein a detection cell is included for each row and located at the end of each row. It should be understood that the term “end” as used with respect to the term “row” indicates the distant end with respect to the clock (strobe) distribution network. In other words, the end cell in a row is the last to receive a strobe transition. Use of detection cells 14 thereby provides a signal to each row that can indicate when a write to that row should have resulted in a complete state change of any storage cells located in that row.
- a column of detection cells may be positioned at another location away from the ends of the rows, which is particularly useful in tuning the delay of the detection cell state change to read blocking delay.
- Other multiple detection cell arrangements are possible, such as providing a detection cell 14 for every other row.
- a single detection cell 14 A or 14 Z may be employed to provide a signal indicating completion of a write. (Or for split arrays, a single cell might be used for each portion of the array). Detection cell 14 Z indicates the location of a single cell that corresponds to the end of the last row in the array, wherein “last” is defined in a manner similar to the above for “end”, indicating the cell at the distant end of the clock distribution for both columns and rows. Therefore, detection cell 14 Z provides an indication that all other cells implicated by a write should have completed their state changes. To ensure that a state change has occurred, the control logic 10 provides some delay for providing a margin of confidence before enabling a read after a write has occurred. In addition, location of detection cells in other locations such as detection cell 14 A require that a delay be added to the write completion signal that compensates for the fact that other cells are expected to have state changes occurring later than the state change in detection cell 14 A.
- the present invention is directed toward a register file circuit that includes one or more detection cells that provide a write complete indication so that reads occurring earlier than the end of the write strobe cycle can be blocked or not generated until there is confidence that the data in storage cells 12 is stable.
- Detection cells can either provide such indication directly, wherein control circuit 10 only includes such additional delay as needed for confidence margin.
- detection cells such as detection cell 14 A can provide an early indication, with delay added either by control logic or the distribution of the indication(s) to control logic so that the confidence margin is achieved.
- read strobe timing and skew does not have to be controlled so that the write is known to be completed, which is typically accomplished in the prior art by delaying the read strobe until the write strobe is de-asserted.
- a fixed margin is added after the beginning of the write strobe and is used to enable the next read.
- the result of applying the techniques of the present invention is an increased performance in terms of throughput of a register file circuit. Further, the circuit achieves better delay scaling over operational parameters, permitting increased frequency of operation and a design in which the above-mentioned margin does not have to be evaluated extensively. A further result provides for asynchronous read operations so that a read strobe to the same row is not generated at all until the state changes due to the write cycle are complete.
- Detection cell 24 A is a modified storage cell having two inputs coupled through transmission gates TG 1 and TG 2 (or pass gates using one pass transistor) to a buffer B 1 with storage on the input of buffer B 1 .
- One transmission gate TG 1 input is connected to a logical high value and the other input (of TG 2 ) is connected to a logical low value.
- the output of detection cell 24 A is provided to control logic 10 A through an optional delay D 2 , which as mentioned above, may be tuned to compensate for the location of detection cell 24 A and may also provide the desired margin of confidence in conjunction with the path delay to control logic 10 A and control logic 10 A internal delays.
- logical AND gate 27 qualifies the row read strobe signal Row Read Stb to produce the Read Row signals provided to the read inputs of storage cells 12 , so that no read can be asserted to row storage cells 12 prior to the indication from detection cell 24 A that the write state change has occurred.
- the Write Comp signal at an input of AND gate 27 is provided by a logic circuit having a combined static and dynamic function. A specific circuit having the static function incorporated within the dynamic AND gate will be illustrated in detail below in FIG.
- the summing node of a dynamic domino circuit represented by inverter I 1 is connected to an input of a static logical NAND gate 29 .
- the precharge input of inverter I 1 is connected to the Write Row signal, so that prior to the commencement of a write to the row, the output of inverter I 1 is in a logical high state. Therefore, when the Write Row signal is asserted, both inputs of logical NAND gate 29 assume a logical high value that disables the Row Read Stb signal via AND gate 27 until the inherent clock-to-state-change delay of detection cell 24 A has elapsed plus any additional delay due to delay D 2 .
- inverter I 1 evaluates, providing a logical low value at the input of NAND gate 29 .
- the output of NAND gate 29 will then assume a logical high state, enabling the Row Read Stb signal via AND gate 27 .
- Inverter I 1 will continue to provide a logical low value at the input of NAND gate 29 until the Write Row signal is de-asserted.
- control logic 10 A (as part of control logic 10 of FIG. 1 ) it should be understood that the physical location of the gating function can be provided locally at each row cell or by one gate located in the row, with a distribution of the detection cells 14 outputs along the row lines.
- detection cell 24 B is connected to a scan latch 22 that normally is used to store the value in detection cell 24 B for scan testing.
- scan latch 22 attached to detection cell 24 B is used for another purpose when in functional (operational) mode.
- the Write Row signal is connected to the enable input of detection cell 24 B (which is a standard storage cell) and an inverted version provided to scan latch 22 via an inverter 12 .
- An inverted output of scan latch 22 is provided to the write data input of storage cell 24 B, so that the logical value stored in detection cell 24 B alternates at each write strobe.
- Control logic 10 B detects when the outputs of detection cell 24 B and scan latch 22 are different, providing an indication as described above for the circuit of FIG. 2A , optionally delayed by delay D 2 that delays the detection cell 24 B output change and thereby provides a write complete (WriteComp) signal via a dynamic XNOR gate and static NAND gate 29 .
- a dynamic XNOR circuit having an incorporated static NAND function are shown in detail below in FIG. 5 and the associated description.
- the preset input of dynamic XNOR gate 25 is connected to the Write Row signal so that the output of XNOR gate 25 remains in the precharge state except after the Write Row signal has been asserted and before the optionally delayed output of detection cell 24 B has changed state due to the write cycle.
- both inputs of NAND gate 29 assume a logical high value, as the inputs of XNOR gate 25 are equal at this time, preventing XNOR gate 25 from evaluating.
- the output of NAND gate 29 will thus be at a logical low level, blocking any Row Read Stb assertion that has arrived before the state change due to the write cycle has occurred.
- dynamic XNOR gate 25 evaluates, providing a logical low value at the input of NAND gate 29 that is connected to XNOR gate 29 .
- the output of AND gate 29 will then assume a logical high state, enabling the Row Read Stb signal via AND gate 27 .
- Dynamic XNOR gate 25 will continue to provide a logical low value at the input of NAND gate 29 until the Write Row signal is de-asserted and XNOR gate 25 is precharged.
- the Write Row signal is provided to the other input of NAND gate 29 so that the output of NAND gate 29 continues to be held until the next write cycle to the row, which prevents the Read Row cycle from being truncated by de-assertion of the Write Row signal when the output of scan latch 22 changes state.
- FIG. 3 a timing diagram illustrating the operation of the circuit of FIG. 2B within the register file circuit of FIG. 1 is depicted.
- the detection cell output (DetStorageCell) matches the scan latch output (DetScanrLatch) and the WriteComp signal is low.
- DetStorageCell assumes a value opposite that of DetScanLatch (due to the connection of scan latch 22 inverting output to detection cell 24 B input) and XOR gate 25 transitions to a logical high value, providing the WriteComp signal that qualifies the row read strobe RowRead to provide the ReadRow signal that drives the row read strobes to storage cells 12 .
- the ReadRow signal is truncated from the RowRead signal until the delay has expired.
- a cell delay i.e., the inherent detection cell write strobe to state change delay
- a tuned delay which includes the confidence margin and any delay needed to tune for a detection cell that is not guaranteed to be the last cell to transition on a write operation.
- Control logic 10 C receives the Write Comp signal(s) at an address unit 44 that compares a next read address to the previous write address in order to determine whether or not read access to a row needs to be blocked until detection cell(s) 14 have detected that the state changes due to the previous write have occurred. If not, the generation of the Row Read Stb signal is postponed until the WriteComp indication is received. At that time, Strobe generators /line buffers 42 provides the appropriate read strobe.
- FIG. 5 a specific circuit that may be used to implement control logic 10 B of FIG. 2B is shown.
- the illustrated circuit has advantages in that only a few devices need be added over a standard dynamic XOR gate in order to provide the NAND function, thus implementing the combination of dynamic XNOR 25 and NAND 29 .
- a logical exclusive-NOR function is provided at an internal summing node Node 0 by two N-device trees, transistors N 60 and N 61 forming the first tree and transistors N 62 and N 63 forming the second tree.
- the gates of transistors N 61 and N 63 are driven by scan latch 22 output and a complement provided by inverter I 61 , respectively.
- transistors N 60 and N 62 are driven by detection cell 24 B output and a complement provided by inverter I 60 .
- the resulting function is a dynamic exclusive-NOR at Node 0 , with precharge transistor P 60 and foot transistor N 64 completing the dynamic circuit function.
- a half-latch HL 60 provides that the state of internal node Node 0 will be maintained in the absence of the precharge signal both before and after an evaluation has occurred.
- Inverter I 62 transforms the internal node signal Node 0 to provide what would be a traditional exclusive-OR function at output Write Compl, but for the presence of output foot transistor N 65 and output pull-up transistor P 61 .
- the output state change is made upon de-assertion of the /Precharge signal and remains until the circuit has evaluated.
- the illustrated circuit is especially suitable for the operation of the present invention, where it is desirable to generate a signal indicative of the time between the initiation of the row write and the change at the control logic input(s) due to the expiration of the inherent detection cell delay.
- FIG. 6 a specific circuit that may be used to implement control logic 10 A of FIG. 2A is shown.
- the illustrated circuit is a simplification of the circuit of FIG. 5 and thus only differences will be described.
- the illustrated circuit provides the combined operation of dynamic inverter I 1 and NAND gate 29 in the circuit of FIG. 2A .
- the internal summing node represents a dynamic-logic invert of the detection cell output (i.e., the summing node will be at a logical low value only if the circuit is not in the precharge condition and the detection cell output is in a logical high condition).
- the balance of the circuit operates as described for the circuit of FIG. 5 , with a logical NAND function imposed on the state of the internal summing node where one of the NAND inputs is the /Precharge signal.
- the precharged state of the internal summing node will cause the output of the illustrated circuit to transition to a logical low state (after being held up by transistor P 61 during the precharge cycle).
- the detection cell output transitions to a logical high state, the output of the illustrated circuit will return to a logical high state.
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Abstract
Description
- The present application is related to co-pending U.S. Patent Application “DYNAMIC-STATIC LOGICAL CONTROL ELEMENT FOR SIGNALING AN INTERVAL BETWEEN THE END OF A CONTROL SIGNAL AND A LOGICAL EVALUATION”, Ser. No. 10/______, filed concurrently with this application by the same inventors and assigned to the same Assignee. The specification of the above-referenced application is incorporated herein by reference.
- 1. Technical Field
- The present invention relates generally to register file access control circuits, and more particularly to a register file having automatic read-after-write blocking.
- 2. Description of the Related Art
- Register files are commonly used building blocks in digital circuits, particularly in processing system components where fast access to a fairly small quantity of data is required with low access latency. Examples of register file uses include register arrays in processors, cache directories in cache memories.
- In contrast to static random access memory (SRAM) cells, register file cells are often written to and then read from within the same clock cycle. For processor core elements where register files are storing machine state information, register files are almost always read immediately after a write in the same clock cycle. Such register files are in the critical path that determines processor speed and as such, the write to read delays are finely tuned to provide the best performance possible within clock skew variation, voltage variation, and other factors that could cause the reading of false or unstable data.
- Typical design margins for register file read-after-write timing may waste up to 30% of the clock cycle time by waiting until the write cycle is complete. But such margins are necessary within the typical ranges of the operational variables mentioned above and with current circuits used to implement register file cells and control logic.
- Therefore, it would be desirable to further reduce the read-after-write margins to improve register file performance and the performance of processors using register files for storage of values and state information.
- The objectives of improving register file performance and processor performance are achieved in a register file apparatus and method for operating a register file.
- One or more cells within the register file are dedicated to use as a detection mechanism for determining when the end of a write cycle has occurred. One cell may be used for the entire array, one cell may be assigned for each row in the register file array, or cells may be assigned for groups of rows.
- The detection cells may be connected so that the value of the cells alternates at each write operation and the value of an active detection cell is used to control logic that blocks a read to the register file row until the active detection cell changes state. Alternatively, the detection cells may be configured so that a first state is set prior to the commencement of the write cycle and then the detection cells are written with a value corresponding to the opposite state by the write.
- The indication of a detection cell state change can be used to truncate the leading edge of a next read strobe to the storage cells affected by the write, or may be used within the access control logic to delay generation of a read strobe that causes a read to the affected cells.
- The foregoing and other objectives, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiment of the invention, as illustrated in the accompanying drawings.
- The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objectives, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein like reference numerals indicate like components, and:
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FIG. 1 is a block diagram of a register file in accordance with an embodiment of the invention. -
FIG. 2A is a block diagram of a detection cell and associated control logic as may be used in the register file ofFIG. 1 . -
FIG. 2B is a block diagram of another detection cell and associated control logic as may be used in the register file ofFIG. 1 . -
FIG. 3 is a timing diagram depicting the relationship of signals within the register file ofFIG. 1 . -
FIG. 4 is a block diagram depicting control logic within the register file ofFIG. 1 , in accordance with an alternative embodiment of the present invention. -
FIG. 5 is a schematic depicting details of dynamic control logic as may be used in the circuit ofFIG. 2B . -
FIG. 6 is a schematic depicting details of dynamic control logic as may be used in the circuit ofFIG. 2A . - With reference now to the figures, and in particular with reference to
FIG. 1 , there is depicted a block diagram of a register file circuit embodying a method and an apparatus in accordance with the present invention. - An array of
storage cells 12 provide storage for words in rows aligned across the figure. Each bit in the words forms a column running up and down the figure. The physical layout ofstorage cells 12 generally mimics the layout depicted, but may vary, for example the rows may be partitioned into two or more units, in which case the layout of a portion of the row may mimic that portion of the drawing, but the overall layout of the register file may be split.Storage cells 12 are coupled to acontrol logic 10 that provides strobe signals that control theindividual storage cells 12 in order to perform read and write functions to the registers (rows) within the register file. It should be understood that rows and columns may be interchanged in a particular register file design and that the term “rows” is used herein and in the claims to indicate the group of storage cells corresponding to an individual storage “word”, which may be of any bit-width.Control logic 10 also may be coupled to ascan logic 16 that provides testing capability for the register file circuit via generating special functional/scan clock relations tostorage cells 12 anddetection cells 14. Data input and output buffers/latches 18 provide for input and output of data fromstorage cells 12. - Unique to the register file disclosed in
FIG. 1 , is the addition of one or more detection cells 14 (and/ordetection cells storage cells 12 implicated in a given write operation have assumed the state directed by the data written tostorage cells 12. The detection is performed by using cells having characteristics matched tostorage cells 12 so that over operational variations such as clock skew, power supply voltage, temperature variations and process variations, the delay between a write strobe and the actual change of data instorage cells 12 will be matched by the delay to produce a state change in detection cell(s) 14 (and/or 14A and 14Z). - The number and location of detection cells can vary in accordance with embodiment of the present invention.
Detection cells 14 represent a physical and logical arrangement wherein a detection cell is included for each row and located at the end of each row. It should be understood that the term “end” as used with respect to the term “row” indicates the distant end with respect to the clock (strobe) distribution network. In other words, the end cell in a row is the last to receive a strobe transition. Use ofdetection cells 14 thereby provides a signal to each row that can indicate when a write to that row should have resulted in a complete state change of any storage cells located in that row. Alternatively, a column of detection cells may be positioned at another location away from the ends of the rows, which is particularly useful in tuning the delay of the detection cell state change to read blocking delay. Other multiple detection cell arrangements are possible, such as providing adetection cell 14 for every other row. - Alternatively, a
single detection cell Detection cell 14Z indicates the location of a single cell that corresponds to the end of the last row in the array, wherein “last” is defined in a manner similar to the above for “end”, indicating the cell at the distant end of the clock distribution for both columns and rows. Therefore,detection cell 14Z provides an indication that all other cells implicated by a write should have completed their state changes. To ensure that a state change has occurred, thecontrol logic 10 provides some delay for providing a margin of confidence before enabling a read after a write has occurred. In addition, location of detection cells in other locations such asdetection cell 14A require that a delay be added to the write completion signal that compensates for the fact that other cells are expected to have state changes occurring later than the state change indetection cell 14A. - In general, the present invention is directed toward a register file circuit that includes one or more detection cells that provide a write complete indication so that reads occurring earlier than the end of the write strobe cycle can be blocked or not generated until there is confidence that the data in
storage cells 12 is stable. Detection cells (14, 14Z) can either provide such indication directly, whereincontrol circuit 10 only includes such additional delay as needed for confidence margin. Or, detection cells such asdetection cell 14A can provide an early indication, with delay added either by control logic or the distribution of the indication(s) to control logic so that the confidence margin is achieved. The advantage of the above-described operation is that read strobe timing and skew does not have to be controlled so that the write is known to be completed, which is typically accomplished in the prior art by delaying the read strobe until the write strobe is de-asserted. In some dynamic circuit designs, a fixed margin is added after the beginning of the write strobe and is used to enable the next read. - The result of applying the techniques of the present invention is an increased performance in terms of throughput of a register file circuit. Further, the circuit achieves better delay scaling over operational parameters, permitting increased frequency of operation and a design in which the above-mentioned margin does not have to be evaluated extensively. A further result provides for asynchronous read operations so that a read strobe to the same row is not generated at all until the state changes due to the write cycle are complete.
- Referring now to
FIG. 2A , an example of adetection cell 24A connected to anexemplary control logic 10A that may be used within thecontrol logic 10 circuit ofFIG. 1 .Detection cell 24A is a modified storage cell having two inputs coupled through transmission gates TG1 and TG2 (or pass gates using one pass transistor) to a buffer B1 with storage on the input of buffer B1. One transmission gate TG1 input is connected to a logical high value and the other input (of TG2) is connected to a logical low value. When Write Row becomes active (logic high),storage cell 24A was previously in logical low state due to the connection of an active low enable input of transmission gate TG2 to the Write Row signal and only transitions to a logical high state after Write Row is asserted and the inherent clock-to-state-change delay ofdetection cell 24A has elapsed. The logical high state ofdetection cell 24A is set by activation of transmission gate TG1 upon assertion of Write Row signal. - The output of
detection cell 24A is provided to controllogic 10A through an optional delay D2, which as mentioned above, may be tuned to compensate for the location ofdetection cell 24A and may also provide the desired margin of confidence in conjunction with the path delay to controllogic 10A and controllogic 10A internal delays. Withincontrol logic 10A, logical ANDgate 27 qualifies the row read strobe signal Row Read Stb to produce the Read Row signals provided to the read inputs ofstorage cells 12, so that no read can be asserted to rowstorage cells 12 prior to the indication fromdetection cell 24A that the write state change has occurred. The Write Comp signal at an input of ANDgate 27 is provided by a logic circuit having a combined static and dynamic function. A specific circuit having the static function incorporated within the dynamic AND gate will be illustrated in detail below inFIG. 6 and the associated description. The summing node of a dynamic domino circuit represented by inverter I1 is connected to an input of a staticlogical NAND gate 29. The precharge input of inverter I1 is connected to the Write Row signal, so that prior to the commencement of a write to the row, the output of inverter I1 is in a logical high state. Therefore, when the Write Row signal is asserted, both inputs oflogical NAND gate 29 assume a logical high value that disables the Row Read Stb signal via ANDgate 27 until the inherent clock-to-state-change delay ofdetection cell 24A has elapsed plus any additional delay due to delay D2. - When the inherent clock-to-state-change delay of
detection cell 24A has elapsed plus any additional delay due to delay D2, inverter I1 evaluates, providing a logical low value at the input ofNAND gate 29. The output ofNAND gate 29 will then assume a logical high state, enabling the Row Read Stb signal via ANDgate 27. Inverter I1 will continue to provide a logical low value at the input ofNAND gate 29 until the Write Row signal is de-asserted. When Write Row is deasserted, inverter I1 is precharged for the next evaluation, but the connection of the Write Row signal toNAND gate 29 ensures that the output ofNAND gate 29 will continue to enable the Row Read Stb signal until the next write to the row begins, which prevents the Read Row cycle from being truncated by de-assertion of the Write Row signal. - While the illustration shows the gating function present in
separate control logic 10A (as part ofcontrol logic 10 ofFIG. 1 ) it should be understood that the physical location of the gating function can be provided locally at each row cell or by one gate located in the row, with a distribution of thedetection cells 14 outputs along the row lines. - Referring now to
FIG. 2B , another detection cell circuit and associatedcontrol logic 10B is shown that is particularly advantageous in register file circuits having scannable architecture. In the depicted circuit,detection cell 24B is connected to ascan latch 22 that normally is used to store the value indetection cell 24B for scan testing. However, scanlatch 22 attached todetection cell 24B is used for another purpose when in functional (operational) mode. The Write Row signal is connected to the enable input ofdetection cell 24B (which is a standard storage cell) and an inverted version provided to scanlatch 22 via aninverter 12. An inverted output ofscan latch 22 is provided to the write data input ofstorage cell 24B, so that the logical value stored indetection cell 24B alternates at each write strobe. Since the value inscan latch 22 is not updated until after the Write Row signal is de-asserted, initially the values ofscan latch 22 andstorage cell 24B will be the same and will continue to be the same until the Write Row signal is asserted and the inherent clock-to-state-change delay ofdetection cell 24B has elapsed. -
Control logic 10B detects when the outputs ofdetection cell 24B and scanlatch 22 are different, providing an indication as described above for the circuit ofFIG. 2A , optionally delayed by delay D2 that delays thedetection cell 24B output change and thereby provides a write complete (WriteComp) signal via a dynamic XNOR gate andstatic NAND gate 29. A dynamic XNOR circuit having an incorporated static NAND function are shown in detail below inFIG. 5 and the associated description. - The preset input of
dynamic XNOR gate 25 is connected to the Write Row signal so that the output ofXNOR gate 25 remains in the precharge state except after the Write Row signal has been asserted and before the optionally delayed output ofdetection cell 24B has changed state due to the write cycle. When the Write Row signal is asserted, both inputs ofNAND gate 29 assume a logical high value, as the inputs ofXNOR gate 25 are equal at this time, preventingXNOR gate 25 from evaluating. The output ofNAND gate 29 will thus be at a logical low level, blocking any Row Read Stb assertion that has arrived before the state change due to the write cycle has occurred. When the inherent clock-to-state-change delay ofdetection cell 24B has elapsed plus any additional delay due to delay D2,dynamic XNOR gate 25 evaluates, providing a logical low value at the input ofNAND gate 29 that is connected toXNOR gate 29. The output of ANDgate 29 will then assume a logical high state, enabling the Row Read Stb signal via ANDgate 27.Dynamic XNOR gate 25 will continue to provide a logical low value at the input ofNAND gate 29 until the Write Row signal is de-asserted andXNOR gate 25 is precharged. The Write Row signal is provided to the other input ofNAND gate 29 so that the output ofNAND gate 29 continues to be held until the next write cycle to the row, which prevents the Read Row cycle from being truncated by de-assertion of the Write Row signal when the output ofscan latch 22 changes state. - Referring now to
FIG. 3 a timing diagram illustrating the operation of the circuit ofFIG. 2B within the register file circuit ofFIG. 1 is depicted. For the circuit ofFIG. 2A operation for each cycle is similar to the first cycle (left hand side) shown inFIG. 3 , as the initial value of the detection cell inFIG. 2A does not alternate between cycles. Upon and prior to receiving a WriteRow signal, the detection cell output (DetStorageCell) matches the scan latch output (DetScanrLatch) and the WriteComp signal is low. When the inherent clock-to-state-change delay ofdetection cell 24B has elapsed, DetStorageCell assumes a value opposite that of DetScanLatch (due to the connection ofscan latch 22 inverting output todetection cell 24B input) andXOR gate 25 transitions to a logical high value, providing the WriteComp signal that qualifies the row read strobe RowRead to provide the ReadRow signal that drives the row read strobes tostorage cells 12. Thus, as can be seen fromFIG. 3 the ReadRow signal is truncated from the RowRead signal until the delay has expired. Also illustrated in the figure is the provision of a cell delay (i.e., the inherent detection cell write strobe to state change delay) added to a tuned delay, which includes the confidence margin and any delay needed to tune for a detection cell that is not guaranteed to be the last cell to transition on a write operation. - Referring now to
FIG. 4 , an alternative blocking mechanism is depicted in the form of analternative control logic 10C as may be employed within the register file circuit ofFIG. 1 .Control logic 10C receives the Write Comp signal(s) at anaddress unit 44 that compares a next read address to the previous write address in order to determine whether or not read access to a row needs to be blocked until detection cell(s) 14 have detected that the state changes due to the previous write have occurred. If not, the generation of the Row Read Stb signal is postponed until the WriteComp indication is received. At that time, Strobe generators /line buffers 42 provides the appropriate read strobe. - Referring now to
FIG. 5 , a specific circuit that may be used to implementcontrol logic 10B ofFIG. 2B is shown. The illustrated circuit has advantages in that only a few devices need be added over a standard dynamic XOR gate in order to provide the NAND function, thus implementing the combination ofdynamic XNOR 25 andNAND 29. A logical exclusive-NOR function is provided at an internal summing node Node0 by two N-device trees, transistors N60 and N61 forming the first tree and transistors N62 and N63 forming the second tree. The gates of transistors N61 and N63 are driven byscan latch 22 output and a complement provided by inverter I61, respectively. Similarly, transistors N60 and N62 are driven bydetection cell 24B output and a complement provided by inverter I60. The resulting function is a dynamic exclusive-NOR at Node 0, with precharge transistor P60 and foot transistor N64 completing the dynamic circuit function. A half-latch HL60 provides that the state of internal node Node0 will be maintained in the absence of the precharge signal both before and after an evaluation has occurred. Inverter I62 transforms the internal node signal Node0 to provide what would be a traditional exclusive-OR function at output Write Compl, but for the presence of output foot transistor N65 and output pull-up transistor P61. When the /Precharge input (in this case the Write Row) signal is in a logic low state (during the absence of the write strobe), foot transistor N65 is turned off, disabling the action of the exclusive-OR by disabling inverter I62. Also, transistor P61 is turned on, causing the output of the circuit to be forced to a logic high value while the /Precharge input is active (thus transistor N65 is necessary in order to prevent shorting the pulled-up output through inverter I62). The operation of the above-described circuit is counter-intuitive in that in typical dynamic logic gates, an output state change from the precharged state is reflective of an evaluated state of the internal summing node. However, in the illustrated circuit, the output state change is made upon de-assertion of the /Precharge signal and remains until the circuit has evaluated. Thus the illustrated circuit is especially suitable for the operation of the present invention, where it is desirable to generate a signal indicative of the time between the initiation of the row write and the change at the control logic input(s) due to the expiration of the inherent detection cell delay. - Referring now to
FIG. 6 a specific circuit that may be used to implementcontrol logic 10A ofFIG. 2A is shown. The illustrated circuit is a simplification of the circuit ofFIG. 5 and thus only differences will be described. The illustrated circuit provides the combined operation of dynamic inverter I1 andNAND gate 29 in the circuit ofFIG. 2A . Since only the detection cell output is needed to provide the state change for generating the Write Compl signal along with the Write Row signal used as a precharge signal, only transistor N62 is needed for the evaluation tree and the internal summing node represents a dynamic-logic invert of the detection cell output (i.e., the summing node will be at a logical low value only if the circuit is not in the precharge condition and the detection cell output is in a logical high condition). The balance of the circuit operates as described for the circuit ofFIG. 5 , with a logical NAND function imposed on the state of the internal summing node where one of the NAND inputs is the /Precharge signal. When the /Precharge signal is de-asserted, the precharged state of the internal summing node will cause the output of the illustrated circuit to transition to a logical low state (after being held up by transistor P61 during the precharge cycle). When the detection cell output transitions to a logical high state, the output of the illustrated circuit will return to a logical high state. - While the invention has been particularly shown and described with reference to the preferred embodiment thereof, it will be understood by those skilled in the art that the foregoing and other changes in form, and details may be made therein without departing from the spirit and scope of the invention.
Claims (22)
Priority Applications (13)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/922,247 US7012839B1 (en) | 2004-08-19 | 2004-08-19 | Register file apparatus and method incorporating read-after-write blocking using detection cells |
TW094126253A TWI349941B (en) | 2004-08-19 | 2005-08-02 | Register file apparatus and method incorporating read-after-write blocking using detection cells |
AT05779156T ATE436073T1 (en) | 2004-08-19 | 2005-08-19 | REGISTER FILE APPARATUS AND METHOD FOR INTEGRATING READ-POST-WRITE BLOCKING USING DETECTION CELLS |
DE602005015336T DE602005015336D1 (en) | 2004-08-19 | 2005-08-19 | REGISTER FILE DEVICE AND METHOD FOR INTEGRATING READ-POST-WRITE BLOCKING USING DETECTION CELLS |
MX2007002013A MX2007002013A (en) | 2004-08-19 | 2005-08-19 | Register file apparatus and method incorporating read-after-write blocking using detection cells. |
KR1020077002554A KR100901235B1 (en) | 2004-08-19 | 2005-08-19 | Register file apparatus and method incorporating read-after-write blocking using detection cells |
CN200580023208A CN100594553C (en) | 2004-08-19 | 2005-08-19 | Register file apparatus and method incorporating read-after-write blocking using detection cells |
EP05779156A EP1784834B1 (en) | 2004-08-19 | 2005-08-19 | Register file apparatus and method incorporating read-after-write blocking using detection cells |
CA002577272A CA2577272A1 (en) | 2004-08-19 | 2005-08-19 | Register file apparatus and method incorporating read-after-write blocking using detection cells |
PCT/EP2005/054103 WO2006018452A1 (en) | 2004-08-19 | 2005-08-19 | Register file apparatus and method incorporating read-after-write blocking using detection cells |
JP2007526468A JP4392041B2 (en) | 2004-08-19 | 2005-08-19 | Register file apparatus and method for incorporating read-after-write block function using detection cell |
US11/242,376 US7142463B2 (en) | 2004-08-19 | 2005-10-03 | Register file method incorporating read-after-write blocking using detection cells |
IL181245A IL181245A (en) | 2004-08-19 | 2007-02-08 | Register file apparatus and method incorporating read-after-write blocking using detection cells |
Applications Claiming Priority (1)
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US10/922,247 US7012839B1 (en) | 2004-08-19 | 2004-08-19 | Register file apparatus and method incorporating read-after-write blocking using detection cells |
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US11/242,376 Division US7142463B2 (en) | 2004-08-19 | 2005-10-03 | Register file method incorporating read-after-write blocking using detection cells |
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US20060039203A1 true US20060039203A1 (en) | 2006-02-23 |
US7012839B1 US7012839B1 (en) | 2006-03-14 |
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US10/922,247 Expired - Fee Related US7012839B1 (en) | 2004-08-19 | 2004-08-19 | Register file apparatus and method incorporating read-after-write blocking using detection cells |
US11/242,376 Expired - Fee Related US7142463B2 (en) | 2004-08-19 | 2005-10-03 | Register file method incorporating read-after-write blocking using detection cells |
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US11/242,376 Expired - Fee Related US7142463B2 (en) | 2004-08-19 | 2005-10-03 | Register file method incorporating read-after-write blocking using detection cells |
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US (2) | US7012839B1 (en) |
EP (1) | EP1784834B1 (en) |
JP (1) | JP4392041B2 (en) |
KR (1) | KR100901235B1 (en) |
CN (1) | CN100594553C (en) |
AT (1) | ATE436073T1 (en) |
CA (1) | CA2577272A1 (en) |
DE (1) | DE602005015336D1 (en) |
IL (1) | IL181245A (en) |
MX (1) | MX2007002013A (en) |
TW (1) | TWI349941B (en) |
WO (1) | WO2006018452A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060171214A1 (en) * | 2005-02-03 | 2006-08-03 | Hynix Semiconductor Inc. | Internal voltage generation control circuit and internal voltage generation circuit using the same |
US20140223101A1 (en) * | 2013-01-24 | 2014-08-07 | Imagination Technologies, Ltd. | Register file having a plurality of sub-register files |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US7610571B2 (en) * | 2006-04-14 | 2009-10-27 | Cadence Design Systems, Inc. | Method and system for simulating state retention of an RTL design |
US9105328B2 (en) | 2012-07-31 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tracking signals in memory write or read operation |
US11269777B2 (en) * | 2019-09-25 | 2022-03-08 | Facebook Technologies, Llc. | Systems and methods for efficient data buffering |
CN114528019A (en) * | 2020-11-23 | 2022-05-24 | 深圳比特微电子科技有限公司 | Multi-bit register, chip and computing device |
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US6701484B1 (en) * | 2000-08-11 | 2004-03-02 | International Business Machines Corporation | Register file with delayed parity check |
-
2004
- 2004-08-19 US US10/922,247 patent/US7012839B1/en not_active Expired - Fee Related
-
2005
- 2005-08-02 TW TW094126253A patent/TWI349941B/en not_active IP Right Cessation
- 2005-08-19 AT AT05779156T patent/ATE436073T1/en not_active IP Right Cessation
- 2005-08-19 WO PCT/EP2005/054103 patent/WO2006018452A1/en active Application Filing
- 2005-08-19 DE DE602005015336T patent/DE602005015336D1/en active Active
- 2005-08-19 KR KR1020077002554A patent/KR100901235B1/en not_active IP Right Cessation
- 2005-08-19 CA CA002577272A patent/CA2577272A1/en not_active Abandoned
- 2005-08-19 MX MX2007002013A patent/MX2007002013A/en active IP Right Grant
- 2005-08-19 JP JP2007526468A patent/JP4392041B2/en not_active Expired - Fee Related
- 2005-08-19 EP EP05779156A patent/EP1784834B1/en not_active Not-in-force
- 2005-08-19 CN CN200580023208A patent/CN100594553C/en not_active Expired - Fee Related
- 2005-10-03 US US11/242,376 patent/US7142463B2/en not_active Expired - Fee Related
-
2007
- 2007-02-08 IL IL181245A patent/IL181245A/en not_active IP Right Cessation
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US5825689A (en) * | 1996-09-05 | 1998-10-20 | Nec Corporation | Nonvolatile semiconductor memory device having data detecting circuit for memory cells block |
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US20060171214A1 (en) * | 2005-02-03 | 2006-08-03 | Hynix Semiconductor Inc. | Internal voltage generation control circuit and internal voltage generation circuit using the same |
US7102938B2 (en) * | 2005-02-03 | 2006-09-05 | Hynix Semiconductor Inc. | Internal voltage generation control circuit and internal voltage generation circuit using the same |
US20070064503A1 (en) * | 2005-02-03 | 2007-03-22 | Hynix Semiconductor Inc. | Internal Voltage Generation Control Circuit and Internal Voltage Generation Circuit Using the Same |
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US20140223101A1 (en) * | 2013-01-24 | 2014-08-07 | Imagination Technologies, Ltd. | Register file having a plurality of sub-register files |
US9304934B2 (en) * | 2013-01-24 | 2016-04-05 | Imagination Technologies Limited | Register file having a plurality of sub-register files |
US9672039B2 (en) | 2013-01-24 | 2017-06-06 | Imagination Technologies Limited | Register file having a plurality of sub-register files |
Also Published As
Publication number | Publication date |
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EP1784834B1 (en) | 2009-07-08 |
US7142463B2 (en) | 2006-11-28 |
US7012839B1 (en) | 2006-03-14 |
CN100594553C (en) | 2010-03-17 |
EP1784834A1 (en) | 2007-05-16 |
ATE436073T1 (en) | 2009-07-15 |
KR20070042541A (en) | 2007-04-23 |
JP2008510241A (en) | 2008-04-03 |
IL181245A (en) | 2010-04-15 |
CN1998051A (en) | 2007-07-11 |
KR100901235B1 (en) | 2009-06-08 |
DE602005015336D1 (en) | 2009-08-20 |
IL181245A0 (en) | 2007-07-04 |
TW200627470A (en) | 2006-08-01 |
MX2007002013A (en) | 2007-03-28 |
TWI349941B (en) | 2011-10-01 |
US20060039202A1 (en) | 2006-02-23 |
CA2577272A1 (en) | 2006-02-23 |
JP4392041B2 (en) | 2009-12-24 |
WO2006018452A1 (en) | 2006-02-23 |
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